URL
https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
Subversion Repositories ram_wb
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- from Rev 5 to Rev 6
- ↔ Reverse comparison
Rev 5 → Rev 6
/ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v
33,7 → 33,7
endmodule |
|
// wrapper for the above dual port RAM |
module ram (dat_i, dat_o, adr_i, we_i, rst, clk ); |
module ram (dat_i, dat_o, adr_i, we_i, clk ); |
|
parameter dat_width = 32; |
parameter adr_width = 11; |
43,40 → 43,25
input [adr_width-1:0] adr_i; |
input we_i; |
output [dat_width-1:0] dat_o; |
input rst; |
input clk; |
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reg sel; |
wire [dat_width-1:0] q_a, q_b; |
|
// when adr_i[adr_width-1] = 0 => use a side |
// when adr_i[adr_width-1] = 1 => use b side |
// delay one clock cycle since read has one pipeline stage |
always @ (posedge clk or posedge rst) |
if (rst) |
sel <= 1'b0; |
else |
sel <= adr_i[adr_width-1]; |
|
assign dat_o = !sel ? q_a : q_b; |
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ram_sc_dw |
# |
( |
.dat_width(dat_width), |
.adr_width(adr_width-1), |
.mem_size(mem_size/2) |
.adr_width(adr_width), |
.mem_size(mem_size) |
) |
ram0 |
( |
.d_a(dat_i), |
.q_a(q_a), |
.adr_a(adr_i[adr_width-2:0]), |
.we_a(we_i & !adr_i[adr_width-1]), |
.q_b(q_b), |
.adr_b(adr_i[adr_width-2:0]), |
.d_b(dat_i), |
.we_b(we_i & adr_i[adr_width-1]), |
.q_a(), |
.adr_a(adr_i), |
.we_a(we_i), |
.q_b(dat_o), |
.adr_b(adr_i), |
.d_b({dat_width{1'b0}}), |
.we_b(1'b0), |
.clk(clk) |
); |
|