URL
https://opencores.org/ocsvn/ram_wb/ram_wb/trunk
Subversion Repositories ram_wb
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/ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_32x2048.vm
0,0 → 1,1387
// |
// Written by Synplify |
// Product Version "Version 9.6A" |
// Program "Synplify", Mapper "9.4.2, Build 069R" |
// Wed Apr 29 11:28:25 2009 |
// |
// Source file index table: |
// Object locations will have the form <file>:<line> |
// file 0 "noname" |
// file 1 "\c:\actel\libero_v8.5\synplify\synplify_96a\lib\proasic\proasic3.v " |
// file 2 "\l:\work\ocsvn\ram_wb\trunk\rtl\verilog\ram_wb_sc_dw.v " |
|
`timescale 100 ps/100 ps |
module ram_sc_dw ( |
d_a, |
q_a, |
adr_a, |
we_a, |
q_b, |
adr_b, |
d_b, |
we_b, |
clk |
) |
; |
input [31:0] d_a ; |
output [31:0] q_a ; |
input [10:0] adr_a ; |
input we_a ; |
output [31:0] q_b ; |
input [10:0] adr_b ; |
input [31:0] d_b ; |
input we_b ; |
input clk ; |
wire we_a ; |
wire we_b ; |
wire clk ; |
wire [8:2] \ram_tile_14.DOUT0_SIG ; |
wire [8:2] \ram_tile_14.DOUT1_SIG ; |
wire [8:2] \ram_tile_13.DOUT0_SIG ; |
wire [8:2] \ram_tile_13.DOUT1_SIG ; |
wire [8:2] \ram_tile_12.DOUT0_SIG ; |
wire [8:2] \ram_tile_12.DOUT1_SIG ; |
wire [8:2] \ram_tile_11.DOUT0_SIG ; |
wire [8:2] \ram_tile_11.DOUT1_SIG ; |
wire [8:2] \ram_tile_10.DOUT0_SIG ; |
wire [8:2] \ram_tile_10.DOUT1_SIG ; |
wire [8:2] \ram_tile_9.DOUT0_SIG ; |
wire [8:2] \ram_tile_9.DOUT1_SIG ; |
wire [8:2] \ram_tile_8.DOUT0_SIG ; |
wire [8:2] \ram_tile_8.DOUT1_SIG ; |
wire [8:2] \ram_tile_7.DOUT0_SIG ; |
wire [8:2] \ram_tile_7.DOUT1_SIG ; |
wire [8:2] \ram_tile_6.DOUT0_SIG ; |
wire [8:2] \ram_tile_6.DOUT1_SIG ; |
wire [8:2] \ram_tile_5.DOUT0_SIG ; |
wire [8:2] \ram_tile_5.DOUT1_SIG ; |
wire [8:2] \ram_tile_4.DOUT0_SIG ; |
wire [8:2] \ram_tile_4.DOUT1_SIG ; |
wire [8:2] \ram_tile_3.DOUT0_SIG ; |
wire [8:2] \ram_tile_3.DOUT1_SIG ; |
wire [8:2] \ram_tile_2.DOUT0_SIG ; |
wire [8:2] \ram_tile_2.DOUT1_SIG ; |
wire [8:2] \ram_tile_1.DOUT0_SIG ; |
wire [8:2] \ram_tile_1.DOUT1_SIG ; |
wire [8:2] \ram_tile_0.DOUT0_SIG ; |
wire [8:2] \ram_tile_0.DOUT1_SIG ; |
wire [8:2] \ram_tile.DOUT0_SIG ; |
wire [8:2] \ram_tile.DOUT1_SIG ; |
wire VCC ; |
wire N_1 ; |
wire N_2 ; |
wire N_3 ; |
wire N_4 ; |
wire N_5 ; |
wire N_6 ; |
wire N_7 ; |
wire N_8 ; |
wire N_9 ; |
wire N_10 ; |
wire N_11 ; |
wire N_12 ; |
wire N_13 ; |
wire N_14 ; |
wire N_15 ; |
wire N_16 ; |
wire N_17 ; |
wire N_18 ; |
wire N_19 ; |
wire N_20 ; |
wire N_21 ; |
wire N_22 ; |
wire GND ; |
wire we_b_i ; |
wire we_a_i ; |
wire GND_Z ; |
wire VCC_Z ; |
INV we_a_RNIA08 ( |
.Y(we_a_i), |
.A(we_a) |
); |
INV we_b_RNIB08 ( |
.Y(we_b_i), |
.A(we_b) |
); |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
// @2:26 |
RAM4K9 \ram_tile_14.I_1 ( |
.DOUTA0(q_b[30]), |
.DOUTA1(q_b[31]), |
.DOUTA2(\ram_tile_14.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_14.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_14.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_14.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_14.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_14.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_14.DOUT0_SIG [8]), |
.DOUTB0(q_a[30]), |
.DOUTB1(q_a[31]), |
.DOUTB2(\ram_tile_14.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_14.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_14.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_14.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_14.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_14.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_14.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[30]), |
.DINA1(d_b[31]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[30]), |
.DINB1(d_a[31]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_13.I_1 ( |
.DOUTA0(q_b[28]), |
.DOUTA1(q_b[29]), |
.DOUTA2(\ram_tile_13.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_13.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_13.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_13.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_13.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_13.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_13.DOUT0_SIG [8]), |
.DOUTB0(q_a[28]), |
.DOUTB1(q_a[29]), |
.DOUTB2(\ram_tile_13.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_13.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_13.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_13.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_13.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_13.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_13.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[28]), |
.DINA1(d_b[29]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[28]), |
.DINB1(d_a[29]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_12.I_1 ( |
.DOUTA0(q_b[26]), |
.DOUTA1(q_b[27]), |
.DOUTA2(\ram_tile_12.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_12.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_12.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_12.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_12.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_12.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_12.DOUT0_SIG [8]), |
.DOUTB0(q_a[26]), |
.DOUTB1(q_a[27]), |
.DOUTB2(\ram_tile_12.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_12.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_12.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_12.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_12.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_12.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_12.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[26]), |
.DINA1(d_b[27]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[26]), |
.DINB1(d_a[27]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_11.I_1 ( |
.DOUTA0(q_b[24]), |
.DOUTA1(q_b[25]), |
.DOUTA2(\ram_tile_11.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_11.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_11.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_11.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_11.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_11.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_11.DOUT0_SIG [8]), |
.DOUTB0(q_a[24]), |
.DOUTB1(q_a[25]), |
.DOUTB2(\ram_tile_11.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_11.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_11.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_11.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_11.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_11.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_11.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[24]), |
.DINA1(d_b[25]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[24]), |
.DINB1(d_a[25]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_10.I_1 ( |
.DOUTA0(q_b[22]), |
.DOUTA1(q_b[23]), |
.DOUTA2(\ram_tile_10.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_10.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_10.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_10.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_10.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_10.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_10.DOUT0_SIG [8]), |
.DOUTB0(q_a[22]), |
.DOUTB1(q_a[23]), |
.DOUTB2(\ram_tile_10.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_10.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_10.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_10.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_10.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_10.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_10.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[22]), |
.DINA1(d_b[23]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[22]), |
.DINB1(d_a[23]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_9.I_1 ( |
.DOUTA0(q_b[20]), |
.DOUTA1(q_b[21]), |
.DOUTA2(\ram_tile_9.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_9.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_9.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_9.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_9.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_9.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_9.DOUT0_SIG [8]), |
.DOUTB0(q_a[20]), |
.DOUTB1(q_a[21]), |
.DOUTB2(\ram_tile_9.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_9.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_9.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_9.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_9.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_9.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_9.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[20]), |
.DINA1(d_b[21]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[20]), |
.DINB1(d_a[21]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_8.I_1 ( |
.DOUTA0(q_b[18]), |
.DOUTA1(q_b[19]), |
.DOUTA2(\ram_tile_8.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_8.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_8.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_8.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_8.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_8.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_8.DOUT0_SIG [8]), |
.DOUTB0(q_a[18]), |
.DOUTB1(q_a[19]), |
.DOUTB2(\ram_tile_8.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_8.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_8.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_8.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_8.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_8.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_8.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[18]), |
.DINA1(d_b[19]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[18]), |
.DINB1(d_a[19]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_7.I_1 ( |
.DOUTA0(q_b[16]), |
.DOUTA1(q_b[17]), |
.DOUTA2(\ram_tile_7.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_7.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_7.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_7.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_7.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_7.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_7.DOUT0_SIG [8]), |
.DOUTB0(q_a[16]), |
.DOUTB1(q_a[17]), |
.DOUTB2(\ram_tile_7.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_7.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_7.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_7.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_7.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_7.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_7.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[16]), |
.DINA1(d_b[17]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[16]), |
.DINB1(d_a[17]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_6.I_1 ( |
.DOUTA0(q_b[14]), |
.DOUTA1(q_b[15]), |
.DOUTA2(\ram_tile_6.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_6.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_6.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_6.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_6.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_6.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_6.DOUT0_SIG [8]), |
.DOUTB0(q_a[14]), |
.DOUTB1(q_a[15]), |
.DOUTB2(\ram_tile_6.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_6.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_6.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_6.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_6.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_6.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_6.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[14]), |
.DINA1(d_b[15]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[14]), |
.DINB1(d_a[15]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_5.I_1 ( |
.DOUTA0(q_b[12]), |
.DOUTA1(q_b[13]), |
.DOUTA2(\ram_tile_5.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_5.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_5.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_5.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_5.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_5.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_5.DOUT0_SIG [8]), |
.DOUTB0(q_a[12]), |
.DOUTB1(q_a[13]), |
.DOUTB2(\ram_tile_5.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_5.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_5.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_5.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_5.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_5.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_5.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[12]), |
.DINA1(d_b[13]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[12]), |
.DINB1(d_a[13]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_4.I_1 ( |
.DOUTA0(q_b[10]), |
.DOUTA1(q_b[11]), |
.DOUTA2(\ram_tile_4.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_4.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_4.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_4.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_4.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_4.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_4.DOUT0_SIG [8]), |
.DOUTB0(q_a[10]), |
.DOUTB1(q_a[11]), |
.DOUTB2(\ram_tile_4.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_4.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_4.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_4.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_4.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_4.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_4.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[10]), |
.DINA1(d_b[11]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[10]), |
.DINB1(d_a[11]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_3.I_1 ( |
.DOUTA0(q_b[8]), |
.DOUTA1(q_b[9]), |
.DOUTA2(\ram_tile_3.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_3.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_3.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_3.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_3.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_3.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_3.DOUT0_SIG [8]), |
.DOUTB0(q_a[8]), |
.DOUTB1(q_a[9]), |
.DOUTB2(\ram_tile_3.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_3.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_3.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_3.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_3.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_3.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_3.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[8]), |
.DINA1(d_b[9]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[8]), |
.DINB1(d_a[9]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_2.I_1 ( |
.DOUTA0(q_b[6]), |
.DOUTA1(q_b[7]), |
.DOUTA2(\ram_tile_2.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_2.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_2.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_2.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_2.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_2.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_2.DOUT0_SIG [8]), |
.DOUTB0(q_a[6]), |
.DOUTB1(q_a[7]), |
.DOUTB2(\ram_tile_2.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_2.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_2.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_2.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_2.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_2.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_2.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[6]), |
.DINA1(d_b[7]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[6]), |
.DINB1(d_a[7]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_1.I_1 ( |
.DOUTA0(q_b[4]), |
.DOUTA1(q_b[5]), |
.DOUTA2(\ram_tile_1.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_1.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_1.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_1.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_1.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_1.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_1.DOUT0_SIG [8]), |
.DOUTB0(q_a[4]), |
.DOUTB1(q_a[5]), |
.DOUTB2(\ram_tile_1.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_1.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_1.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_1.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_1.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_1.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_1.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[4]), |
.DINA1(d_b[5]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[4]), |
.DINB1(d_a[5]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_0.I_1 ( |
.DOUTA0(q_b[2]), |
.DOUTA1(q_b[3]), |
.DOUTA2(\ram_tile_0.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_0.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_0.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_0.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_0.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_0.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_0.DOUT0_SIG [8]), |
.DOUTB0(q_a[2]), |
.DOUTB1(q_a[3]), |
.DOUTB2(\ram_tile_0.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_0.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_0.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_0.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_0.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_0.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_0.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[2]), |
.DINA1(d_b[3]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[2]), |
.DINB1(d_a[3]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile.I_1 ( |
.DOUTA0(q_b[0]), |
.DOUTA1(q_b[1]), |
.DOUTA2(\ram_tile.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile.DOUT0_SIG [8]), |
.DOUTB0(q_a[0]), |
.DOUTB1(q_a[1]), |
.DOUTB2(\ram_tile.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[0]), |
.DINA1(d_b[1]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[0]), |
.DINB1(d_a[1]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
VCC VCC_i ( |
.Y(VCC) |
); |
// @2:26 |
GND GND_i ( |
.Y(GND) |
); |
assign GND_Z = 1'b0; |
assign VCC_Z = 1'b1; |
endmodule /* ram_sc_dw */ |
|
ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_32x2048.vm
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ram_wb/trunk/rtl/verilog/wb_ram_sc_sw.v
===================================================================
--- ram_wb/trunk/rtl/verilog/wb_ram_sc_sw.v (nonexistent)
+++ ram_wb/trunk/rtl/verilog/wb_ram_sc_sw.v (revision 7)
@@ -0,0 +1,22 @@
+module ram (dat_i, dat_o, adr_i, we_i, clk );
+
+ parameter dat_width = 32;
+ parameter adr_width = 11;
+ parameter mem_size = 2048;
+
+ input [dat_width-1:0] dat_i;
+ input [adr_width-1:0] adr_i;
+ input we_i;
+ output reg [dat_width-1:0] dat_o;
+ input clk;
+
+ reg [dat_width-1:0] ram [0:mem_size - 1] /* synthesis ram_style = no_rw_check */;
+
+ always @ (posedge clk)
+ begin
+ dat_o <= ram[adr_i];
+ if (we_i)
+ ram[adr_i] <= dat_i;
+ end
+
+endmodule // ram
ram_wb/trunk/rtl/verilog/wb_ram_sc_sw.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v
===================================================================
--- ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v (revision 6)
+++ ram_wb/trunk/rtl/verilog/ram_wb_sc_dw.v (revision 7)
@@ -1,9 +1,9 @@
// True dual port RAM as found in ACTEL proasic3 devices
module ram_sc_dw (d_a, q_a, adr_a, we_a, q_b, adr_b, d_b, we_b, clk);
- parameter dat_width = 32;
- parameter adr_width = 11;
- parameter mem_size = 2048;
+ parameter dat_width = `RAM_WB_DAT_WIDTH;
+ parameter adr_width = `RAM_WB_ADR_WIDTH;
+ parameter mem_size = `RAM_WB_MEM_SIZE;
input [dat_width-1:0] d_a;
input [adr_width-1:0] adr_a;
@@ -15,7 +15,7 @@
input we_b;
input clk;
- reg [dat_width-1:0] ram [0:mem_size - 1] ;
+ reg [dat_width-1:0] ram [0:mem_size - 1] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk)
begin
@@ -22,7 +22,8 @@
q_a <= ram[adr_a];
if (we_a)
ram[adr_a] <= d_a;
- end
+ end
+
always @ (posedge clk)
begin
q_b <= ram[adr_b];
@@ -31,38 +32,3 @@
end
endmodule
-
-// wrapper for the above dual port RAM
-module ram (dat_i, dat_o, adr_i, we_i, clk );
-
- parameter dat_width = 32;
- parameter adr_width = 11;
- parameter mem_size = 2048;
-
- input [dat_width-1:0] dat_i;
- input [adr_width-1:0] adr_i;
- input we_i;
- output [dat_width-1:0] dat_o;
- input clk;
-
- ram_sc_dw
- #
- (
- .dat_width(dat_width),
- .adr_width(adr_width),
- .mem_size(mem_size)
- )
- ram0
- (
- .d_a(dat_i),
- .q_a(),
- .adr_a(adr_i),
- .we_a(we_i),
- .q_b(dat_o),
- .adr_b(adr_i),
- .d_b({dat_width{1'b0}}),
- .we_b(1'b0),
- .clk(clk)
- );
-
-endmodule // ram
/ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_32x1024.vm
0,0 → 1,1387
// |
// Written by Synplify |
// Product Version "Version 9.6A" |
// Program "Synplify", Mapper "9.4.2, Build 069R" |
// Wed Apr 29 11:28:25 2009 |
// |
// Source file index table: |
// Object locations will have the form <file>:<line> |
// file 0 "noname" |
// file 1 "\c:\actel\libero_v8.5\synplify\synplify_96a\lib\proasic\proasic3.v " |
// file 2 "\l:\work\ocsvn\ram_wb\trunk\rtl\verilog\ram_wb_sc_dw.v " |
|
`timescale 100 ps/100 ps |
module ram_sc_dw ( |
d_a, |
q_a, |
adr_a, |
we_a, |
q_b, |
adr_b, |
d_b, |
we_b, |
clk |
) |
; |
input [31:0] d_a ; |
output [31:0] q_a ; |
input [10:0] adr_a ; |
input we_a ; |
output [31:0] q_b ; |
input [10:0] adr_b ; |
input [31:0] d_b ; |
input we_b ; |
input clk ; |
wire we_a ; |
wire we_b ; |
wire clk ; |
wire [8:2] \ram_tile_14.DOUT0_SIG ; |
wire [8:2] \ram_tile_14.DOUT1_SIG ; |
wire [8:2] \ram_tile_13.DOUT0_SIG ; |
wire [8:2] \ram_tile_13.DOUT1_SIG ; |
wire [8:2] \ram_tile_12.DOUT0_SIG ; |
wire [8:2] \ram_tile_12.DOUT1_SIG ; |
wire [8:2] \ram_tile_11.DOUT0_SIG ; |
wire [8:2] \ram_tile_11.DOUT1_SIG ; |
wire [8:2] \ram_tile_10.DOUT0_SIG ; |
wire [8:2] \ram_tile_10.DOUT1_SIG ; |
wire [8:2] \ram_tile_9.DOUT0_SIG ; |
wire [8:2] \ram_tile_9.DOUT1_SIG ; |
wire [8:2] \ram_tile_8.DOUT0_SIG ; |
wire [8:2] \ram_tile_8.DOUT1_SIG ; |
wire [8:2] \ram_tile_7.DOUT0_SIG ; |
wire [8:2] \ram_tile_7.DOUT1_SIG ; |
wire [8:2] \ram_tile_6.DOUT0_SIG ; |
wire [8:2] \ram_tile_6.DOUT1_SIG ; |
wire [8:2] \ram_tile_5.DOUT0_SIG ; |
wire [8:2] \ram_tile_5.DOUT1_SIG ; |
wire [8:2] \ram_tile_4.DOUT0_SIG ; |
wire [8:2] \ram_tile_4.DOUT1_SIG ; |
wire [8:2] \ram_tile_3.DOUT0_SIG ; |
wire [8:2] \ram_tile_3.DOUT1_SIG ; |
wire [8:2] \ram_tile_2.DOUT0_SIG ; |
wire [8:2] \ram_tile_2.DOUT1_SIG ; |
wire [8:2] \ram_tile_1.DOUT0_SIG ; |
wire [8:2] \ram_tile_1.DOUT1_SIG ; |
wire [8:2] \ram_tile_0.DOUT0_SIG ; |
wire [8:2] \ram_tile_0.DOUT1_SIG ; |
wire [8:2] \ram_tile.DOUT0_SIG ; |
wire [8:2] \ram_tile.DOUT1_SIG ; |
wire VCC ; |
wire N_1 ; |
wire N_2 ; |
wire N_3 ; |
wire N_4 ; |
wire N_5 ; |
wire N_6 ; |
wire N_7 ; |
wire N_8 ; |
wire N_9 ; |
wire N_10 ; |
wire N_11 ; |
wire N_12 ; |
wire N_13 ; |
wire N_14 ; |
wire N_15 ; |
wire N_16 ; |
wire N_17 ; |
wire N_18 ; |
wire N_19 ; |
wire N_20 ; |
wire N_21 ; |
wire N_22 ; |
wire GND ; |
wire we_b_i ; |
wire we_a_i ; |
wire GND_Z ; |
wire VCC_Z ; |
INV we_a_RNIA08 ( |
.Y(we_a_i), |
.A(we_a) |
); |
INV we_b_RNIB08 ( |
.Y(we_b_i), |
.A(we_b) |
); |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
//@2:26 |
// @2:26 |
RAM4K9 \ram_tile_14.I_1 ( |
.DOUTA0(q_b[30]), |
.DOUTA1(q_b[31]), |
.DOUTA2(\ram_tile_14.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_14.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_14.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_14.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_14.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_14.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_14.DOUT0_SIG [8]), |
.DOUTB0(q_a[30]), |
.DOUTB1(q_a[31]), |
.DOUTB2(\ram_tile_14.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_14.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_14.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_14.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_14.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_14.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_14.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[30]), |
.DINA1(d_b[31]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[30]), |
.DINB1(d_a[31]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_13.I_1 ( |
.DOUTA0(q_b[28]), |
.DOUTA1(q_b[29]), |
.DOUTA2(\ram_tile_13.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_13.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_13.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_13.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_13.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_13.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_13.DOUT0_SIG [8]), |
.DOUTB0(q_a[28]), |
.DOUTB1(q_a[29]), |
.DOUTB2(\ram_tile_13.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_13.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_13.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_13.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_13.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_13.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_13.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[28]), |
.DINA1(d_b[29]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[28]), |
.DINB1(d_a[29]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_12.I_1 ( |
.DOUTA0(q_b[26]), |
.DOUTA1(q_b[27]), |
.DOUTA2(\ram_tile_12.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_12.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_12.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_12.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_12.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_12.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_12.DOUT0_SIG [8]), |
.DOUTB0(q_a[26]), |
.DOUTB1(q_a[27]), |
.DOUTB2(\ram_tile_12.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_12.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_12.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_12.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_12.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_12.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_12.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[26]), |
.DINA1(d_b[27]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[26]), |
.DINB1(d_a[27]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_11.I_1 ( |
.DOUTA0(q_b[24]), |
.DOUTA1(q_b[25]), |
.DOUTA2(\ram_tile_11.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_11.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_11.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_11.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_11.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_11.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_11.DOUT0_SIG [8]), |
.DOUTB0(q_a[24]), |
.DOUTB1(q_a[25]), |
.DOUTB2(\ram_tile_11.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_11.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_11.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_11.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_11.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_11.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_11.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[24]), |
.DINA1(d_b[25]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[24]), |
.DINB1(d_a[25]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_10.I_1 ( |
.DOUTA0(q_b[22]), |
.DOUTA1(q_b[23]), |
.DOUTA2(\ram_tile_10.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_10.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_10.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_10.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_10.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_10.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_10.DOUT0_SIG [8]), |
.DOUTB0(q_a[22]), |
.DOUTB1(q_a[23]), |
.DOUTB2(\ram_tile_10.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_10.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_10.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_10.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_10.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_10.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_10.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[22]), |
.DINA1(d_b[23]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[22]), |
.DINB1(d_a[23]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_9.I_1 ( |
.DOUTA0(q_b[20]), |
.DOUTA1(q_b[21]), |
.DOUTA2(\ram_tile_9.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_9.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_9.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_9.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_9.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_9.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_9.DOUT0_SIG [8]), |
.DOUTB0(q_a[20]), |
.DOUTB1(q_a[21]), |
.DOUTB2(\ram_tile_9.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_9.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_9.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_9.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_9.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_9.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_9.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[20]), |
.DINA1(d_b[21]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[20]), |
.DINB1(d_a[21]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_8.I_1 ( |
.DOUTA0(q_b[18]), |
.DOUTA1(q_b[19]), |
.DOUTA2(\ram_tile_8.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_8.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_8.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_8.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_8.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_8.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_8.DOUT0_SIG [8]), |
.DOUTB0(q_a[18]), |
.DOUTB1(q_a[19]), |
.DOUTB2(\ram_tile_8.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_8.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_8.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_8.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_8.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_8.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_8.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[18]), |
.DINA1(d_b[19]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[18]), |
.DINB1(d_a[19]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_7.I_1 ( |
.DOUTA0(q_b[16]), |
.DOUTA1(q_b[17]), |
.DOUTA2(\ram_tile_7.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_7.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_7.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_7.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_7.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_7.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_7.DOUT0_SIG [8]), |
.DOUTB0(q_a[16]), |
.DOUTB1(q_a[17]), |
.DOUTB2(\ram_tile_7.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_7.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_7.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_7.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_7.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_7.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_7.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[16]), |
.DINA1(d_b[17]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[16]), |
.DINB1(d_a[17]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_6.I_1 ( |
.DOUTA0(q_b[14]), |
.DOUTA1(q_b[15]), |
.DOUTA2(\ram_tile_6.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_6.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_6.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_6.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_6.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_6.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_6.DOUT0_SIG [8]), |
.DOUTB0(q_a[14]), |
.DOUTB1(q_a[15]), |
.DOUTB2(\ram_tile_6.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_6.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_6.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_6.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_6.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_6.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_6.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[14]), |
.DINA1(d_b[15]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[14]), |
.DINB1(d_a[15]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_5.I_1 ( |
.DOUTA0(q_b[12]), |
.DOUTA1(q_b[13]), |
.DOUTA2(\ram_tile_5.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_5.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_5.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_5.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_5.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_5.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_5.DOUT0_SIG [8]), |
.DOUTB0(q_a[12]), |
.DOUTB1(q_a[13]), |
.DOUTB2(\ram_tile_5.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_5.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_5.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_5.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_5.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_5.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_5.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[12]), |
.DINA1(d_b[13]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[12]), |
.DINB1(d_a[13]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_4.I_1 ( |
.DOUTA0(q_b[10]), |
.DOUTA1(q_b[11]), |
.DOUTA2(\ram_tile_4.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_4.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_4.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_4.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_4.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_4.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_4.DOUT0_SIG [8]), |
.DOUTB0(q_a[10]), |
.DOUTB1(q_a[11]), |
.DOUTB2(\ram_tile_4.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_4.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_4.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_4.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_4.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_4.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_4.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[10]), |
.DINA1(d_b[11]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[10]), |
.DINB1(d_a[11]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_3.I_1 ( |
.DOUTA0(q_b[8]), |
.DOUTA1(q_b[9]), |
.DOUTA2(\ram_tile_3.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_3.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_3.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_3.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_3.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_3.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_3.DOUT0_SIG [8]), |
.DOUTB0(q_a[8]), |
.DOUTB1(q_a[9]), |
.DOUTB2(\ram_tile_3.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_3.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_3.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_3.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_3.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_3.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_3.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[8]), |
.DINA1(d_b[9]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[8]), |
.DINB1(d_a[9]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_2.I_1 ( |
.DOUTA0(q_b[6]), |
.DOUTA1(q_b[7]), |
.DOUTA2(\ram_tile_2.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_2.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_2.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_2.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_2.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_2.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_2.DOUT0_SIG [8]), |
.DOUTB0(q_a[6]), |
.DOUTB1(q_a[7]), |
.DOUTB2(\ram_tile_2.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_2.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_2.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_2.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_2.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_2.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_2.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[6]), |
.DINA1(d_b[7]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[6]), |
.DINB1(d_a[7]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_1.I_1 ( |
.DOUTA0(q_b[4]), |
.DOUTA1(q_b[5]), |
.DOUTA2(\ram_tile_1.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_1.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_1.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_1.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_1.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_1.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_1.DOUT0_SIG [8]), |
.DOUTB0(q_a[4]), |
.DOUTB1(q_a[5]), |
.DOUTB2(\ram_tile_1.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_1.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_1.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_1.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_1.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_1.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_1.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[4]), |
.DINA1(d_b[5]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[4]), |
.DINB1(d_a[5]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile_0.I_1 ( |
.DOUTA0(q_b[2]), |
.DOUTA1(q_b[3]), |
.DOUTA2(\ram_tile_0.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile_0.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile_0.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile_0.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile_0.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile_0.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile_0.DOUT0_SIG [8]), |
.DOUTB0(q_a[2]), |
.DOUTB1(q_a[3]), |
.DOUTB2(\ram_tile_0.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile_0.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile_0.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile_0.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile_0.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile_0.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile_0.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[2]), |
.DINA1(d_b[3]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[2]), |
.DINB1(d_a[3]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
RAM4K9 \ram_tile.I_1 ( |
.DOUTA0(q_b[0]), |
.DOUTA1(q_b[1]), |
.DOUTA2(\ram_tile.DOUT0_SIG [2]), |
.DOUTA3(\ram_tile.DOUT0_SIG [3]), |
.DOUTA4(\ram_tile.DOUT0_SIG [4]), |
.DOUTA5(\ram_tile.DOUT0_SIG [5]), |
.DOUTA6(\ram_tile.DOUT0_SIG [6]), |
.DOUTA7(\ram_tile.DOUT0_SIG [7]), |
.DOUTA8(\ram_tile.DOUT0_SIG [8]), |
.DOUTB0(q_a[0]), |
.DOUTB1(q_a[1]), |
.DOUTB2(\ram_tile.DOUT1_SIG [2]), |
.DOUTB3(\ram_tile.DOUT1_SIG [3]), |
.DOUTB4(\ram_tile.DOUT1_SIG [4]), |
.DOUTB5(\ram_tile.DOUT1_SIG [5]), |
.DOUTB6(\ram_tile.DOUT1_SIG [6]), |
.DOUTB7(\ram_tile.DOUT1_SIG [7]), |
.DOUTB8(\ram_tile.DOUT1_SIG [8]), |
.ADDRA0(adr_b[0]), |
.ADDRA1(adr_b[1]), |
.ADDRA2(adr_b[2]), |
.ADDRA3(adr_b[3]), |
.ADDRA4(adr_b[4]), |
.ADDRA5(adr_b[5]), |
.ADDRA6(adr_b[6]), |
.ADDRA7(adr_b[7]), |
.ADDRA8(adr_b[8]), |
.ADDRA9(adr_b[9]), |
.ADDRA10(adr_b[10]), |
.ADDRA11(GND), |
.ADDRB0(adr_a[0]), |
.ADDRB1(adr_a[1]), |
.ADDRB2(adr_a[2]), |
.ADDRB3(adr_a[3]), |
.ADDRB4(adr_a[4]), |
.ADDRB5(adr_a[5]), |
.ADDRB6(adr_a[6]), |
.ADDRB7(adr_a[7]), |
.ADDRB8(adr_a[8]), |
.ADDRB9(adr_a[9]), |
.ADDRB10(adr_a[10]), |
.ADDRB11(GND), |
.BLKA(GND), |
.BLKB(GND), |
.CLKA(clk), |
.CLKB(clk), |
.DINA0(d_b[0]), |
.DINA1(d_b[1]), |
.DINA2(GND), |
.DINA3(GND), |
.DINA4(GND), |
.DINA5(GND), |
.DINA6(GND), |
.DINA7(GND), |
.DINA8(GND), |
.DINB0(d_a[0]), |
.DINB1(d_a[1]), |
.DINB2(GND), |
.DINB3(GND), |
.DINB4(GND), |
.DINB5(GND), |
.DINB6(GND), |
.DINB7(GND), |
.DINB8(GND), |
.PIPEA(GND), |
.PIPEB(GND), |
.RESET(VCC), |
.WENA(we_b_i), |
.WENB(we_a_i), |
.WIDTHA1(GND), |
.WIDTHA0(VCC), |
.WIDTHB1(GND), |
.WIDTHB0(VCC), |
.WMODEA(GND), |
.WMODEB(GND) |
); |
// @2:26 |
VCC VCC_i ( |
.Y(VCC) |
); |
// @2:26 |
GND GND_i ( |
.Y(GND) |
); |
assign GND_Z = 1'b0; |
assign VCC_Z = 1'b1; |
endmodule /* ram_sc_dw */ |
|
ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_32x1024.vm
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_wrapper.v
===================================================================
--- ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_wrapper.v (nonexistent)
+++ ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_wrapper.v (revision 7)
@@ -0,0 +1,38 @@
+// wrapper for the above dual port RAM
+module ram (dat_i, dat_o, adr_i, we_i, clk );
+
+ parameter dat_width = 32;
+ parameter adr_width = 11;
+ parameter mem_size = 2048;
+
+ input [dat_width-1:0] dat_i;
+ input [adr_width-1:0] adr_i;
+ input we_i;
+ output [dat_width-1:0] dat_o;
+ input clk;
+
+ wire [dat_width-1:0] q_b;
+
+ ram_sc_dw
+ /*
+ #
+ (
+ .dat_width(dat_width),
+ .adr_width(adr_width),
+ .mem_size(mem_size)
+ )
+ */
+ ram0
+ (
+ .d_a(dat_i),
+ .q_a(dat_o),
+ .adr_a(adr_i),
+ .we_a(we_i),
+ .q_b(q_b),
+ .adr_b({adr_width{1'b0}}),
+ .d_b({dat_width{1'b0}}),
+ .we_b(1'b0),
+ .clk(clk)
+ );
+
+endmodule // ram
ram_wb/trunk/rtl/verilog/ram_wb_sc_dw_wrapper.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: ram_wb/trunk/rtl/verilog/Makefile
===================================================================
--- ram_wb/trunk/rtl/verilog/Makefile (nonexistent)
+++ ram_wb/trunk/rtl/verilog/Makefile (revision 7)
@@ -0,0 +1,5 @@
+ACTEL:
+ vppp +define+RAM_WB_DAT_WIDTH+32 +define+RAM_WB_ADR_WIDTH+11 +define+RAM_WB_MEM_SIZE+2048 --simple ram_wb_sc_dw.v > ram_wb_sc_dw_32x2048.v
+ vppp +define+RAM_WB_DAT_WIDTH+32 +define+RAM_WB_ADR_WIDTH+10 +define+RAM_WB_MEM_SIZE+1024 --simple ram_wb_sc_dw.v > ram_wb_sc_dw_32x1024.v
+
+all: ACTEL
ram_wb/trunk/rtl/verilog/Makefile
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property