Subversion Repositories ram_wb

/trunk/rtl/verilog/ram_wb_defines.v

trunk/rtl/verilog/ram_wb_defines.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/RAM_wb_sc_dw.v =================================================================== --- trunk/rtl/verilog/RAM_wb_sc_dw.v (nonexistent) +++ trunk/rtl/verilog/RAM_wb_sc_dw.v (revision 2) @@ -0,0 +1,40 @@ +module RAM_wb_sc_dw + ( + d_a, + q_a, + adr_a, + we_a, + q_b, + adr_b, + d_b, + we_b, + clk + ); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 11; + parameter MEM_SIZE = 2048; + + input [(DATA_WIDTH-1):0] d_a; + input [(ADDR_WIDTH-1):0] adr_a; + input [(ADDR_WIDTH-1):0] adr_b; + input we_a; + output [(DATA_WIDTH-1):0] q_b; + input [(DATA_WIDTH-1):0] d_b; + output reg [(DATA_WIDTH-1):0] q_a; + input we_b; + input clk; + reg [(DATA_WIDTH-1):0] q_b; + reg [DATA_WIDTH-1:0] ram [0:MEM_SIZE - 1] ; + always @ (posedge clk) + begin + q_a <= ram[adr_a]; + if (we_a) + ram[adr_a] <= d_a; + end + always @ (posedge clk) + begin + q_b <= ram[adr_b]; + if (we_b) + ram[adr_b] <= d_b; + end +endmodule

trunk/rtl/verilog/RAM_wb_sc_dw.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/RAM_wb.v =================================================================== --- trunk/rtl/verilog/RAM_wb.v (nonexistent) +++ trunk/rtl/verilog/RAM_wb.v (revision 2) @@ -0,0 +1,64 @@ + + +module RAM_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i); + + parameter ram_wb_adr_width = `RAM_WB_ADR_WIDTH; + parameter ram_wb_mem_size = `RAM_WB_MEM_SIZE; + parameter ram_wb_dat_width = `RAM_WB_DAT_WIDTH; + + // wishbone signals + input [31:0] dat_i; + output [31:0] dat_o; + input [ram_wb_adr_width-1:2] adr_i; + input we_i; + input [3:0] sel_i; + input cyc_i; + input stb_i; + output reg ack_o; + input [2:0] cti_i; + + // clock + input clk_i; + // async reset + input rst_i; + + wire [31:0] wr_data; + + // mux for data to ram + assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24]; + assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16]; + assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8]; + assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0]; + + + //vfifo_dual_port_ram_sc_dw + RAM_wb_sc_dw + /* # + ( + .DATA_WIDTH(32), + .ADDR_WIDTH(11) + )*/ + ram + ( + .d_a(wr_data), + .q_a(), + .adr_a(adr_i), + .we_a(we_i & ack_o), + .q_b(dat_o), + .adr_b(adr_i), + .d_b(32'h0), + .we_b(1'b0), + .clk(clk_i) + ); + + + // ack_o + always @ (posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + ack_o <= cyc_i & stb_i & !ack_o; + +endmodule + + \ No newline at end of file

trunk/rtl/verilog/RAM_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/rtl/verilog/ram_wb.v =================================================================== --- trunk/rtl/verilog/ram_wb.v (nonexistent) +++ trunk/rtl/verilog/ram_wb.v (revision 2) @@ -0,0 +1,69 @@ + + +module RAM_wb ( dat_i, dat_o, adr_i, we_i, sel_i, cyc_i, stb_i, ack_o, cti_i, clk_i, rst_i); + + parameter ram_wb_adr_width = `RAM_WB_ADR_WIDTH; + parameter ram_wb_mem_size = `RAM_WB_MEM_SIZE; + parameter ram_wb_dat_width = `RAM_WB_DAT_WIDTH; + + // wishbone signals + input [31:0] dat_i; + output [31:0] dat_o; + input [ram_wb_adr_width-1:2] adr_i; + input we_i; + input [3:0] sel_i; + input cyc_i; + input stb_i; + output reg ack_o; + input [2:0] cti_i; + + // clock + input clk_i; + // async reset + input rst_i; + + wire [31:0] wr_data; + + // mux for data to ram + assign wr_data[31:24] = sel_i[3] ? dat_i[31:24] : dat_o[31:24]; + assign wr_data[23:16] = sel_i[2] ? dat_i[23:16] : dat_o[23:16]; + assign wr_data[15: 8] = sel_i[1] ? dat_i[15: 8] : dat_o[15: 8]; + assign wr_data[ 7: 0] = sel_i[0] ? dat_i[ 7: 0] : dat_o[ 7: 0]; + + + //vfifo_dual_port_ram_sc_dw + ram_wb_sc_dw + /* # + ( + .DATA_WIDTH(32), + .ADDR_WIDTH(11) + )*/ + ram + ( + .d_a(wr_data), + .q_a(), + .adr_a(adr_i), + .we_a(we_i & ack_o), + .q_b(dat_o), + .adr_b(adr_i), + .d_b(32'h0), + .we_b(1'b0), + .clk(clk_i) + ); + + + // ack_o + always @ (posedge clk_i or posedge rst_i) + if (rst_i) + ack_o <= 1'b0; + else + if (!ack_o) + if (cyc_i & stb_i) + ack_o <= 1'b1; + else + if ((sel_i != 4'b1111) | (ct_i == 3'b000) | (cti_i == 3'b111)) + ack_o <= 1'b0; + +endmodule + + \ No newline at end of file

trunk/rtl/verilog/ram_wb.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/doc/src/block.dia =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/block.dia =================================================================== --- trunk/doc/src/block.dia (nonexistent) +++ trunk/doc/src/block.dia (revision 2)

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trunk/doc/src/block.png Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property