OpenCores
URL https://opencores.org/ocsvn/reed_solomon_codec_generator/reed_solomon_codec_generator/trunk

Subversion Repositories reed_solomon_codec_generator

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /reed_solomon_codec_generator
    from Rev 3 to Rev 4
    ↔ Reverse comparison
  •

Rev 3 → Rev 4

/trunk/example/rtl/RsDecodeTop.v
0,0 → 1,1745
//===================================================================
// Module Name : RsDecodeTop
// File Name : RsDecodeTop.v
// Function : Rs Decoder Top Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeTop(
// Inputs
CLK, // system clock
RESET, // system reset
enable, // system enable
startPls, // sync signal
erasureIn, // erasure input
dataIn, // data input
// Outputs
outEnable, // data out valid signal
outStartPls, // first decoded symbol trigger
outDone, // last symbol decoded trigger
errorNum, // number of errors corrected
erasureNum, // number of erasure corrected
fail, // decoding failure signal
delayedData, // decoding failure signal
outData // data output
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // system enable
input startPls; // sync signal
input erasureIn; // erasure input
input [7:0] dataIn; // data input
output outEnable; // data out valid signal
output outStartPls; // first decoded symbol trigger
output outDone; // last symbol decoded trigger
output [7:0] errorNum; // number of errors corrected
output [7:0] erasureNum; // number of erasure corrected
output fail; // decoding failure signal
output [7:0] delayedData; // delayed input data
output [7:0] outData; // data output
 
 
 
//------------------------------------------------------------------------
// + dataInCheck
//- assign to 0 if Erasure
//------------------------------------------------------------------------
wire [7:0] dataInCheck;
 
assign dataInCheck = (erasureIn == 1'b0) ? dataIn : 8'd0;
 
 
 
//------------------------------------------------------------------
// + syndrome_0,...,syndrome_21
// + doneSyndrome
//- RS Syndrome calculation
//------------------------------------------------------------------
wire [7:0] syndrome_0;
wire [7:0] syndrome_1;
wire [7:0] syndrome_2;
wire [7:0] syndrome_3;
wire [7:0] syndrome_4;
wire [7:0] syndrome_5;
wire [7:0] syndrome_6;
wire [7:0] syndrome_7;
wire [7:0] syndrome_8;
wire [7:0] syndrome_9;
wire [7:0] syndrome_10;
wire [7:0] syndrome_11;
wire [7:0] syndrome_12;
wire [7:0] syndrome_13;
wire [7:0] syndrome_14;
wire [7:0] syndrome_15;
wire [7:0] syndrome_16;
wire [7:0] syndrome_17;
wire [7:0] syndrome_18;
wire [7:0] syndrome_19;
wire [7:0] syndrome_20;
wire [7:0] syndrome_21;
wire doneSyndrome;
 
 
RsDecodeSyndrome RsDecodeSyndrome(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.sync (startPls),
.dataIn (dataInCheck),
// Outputs
.syndrome_0 (syndrome_0),
.syndrome_1 (syndrome_1),
.syndrome_2 (syndrome_2),
.syndrome_3 (syndrome_3),
.syndrome_4 (syndrome_4),
.syndrome_5 (syndrome_5),
.syndrome_6 (syndrome_6),
.syndrome_7 (syndrome_7),
.syndrome_8 (syndrome_8),
.syndrome_9 (syndrome_9),
.syndrome_10 (syndrome_10),
.syndrome_11 (syndrome_11),
.syndrome_12 (syndrome_12),
.syndrome_13 (syndrome_13),
.syndrome_14 (syndrome_14),
.syndrome_15 (syndrome_15),
.syndrome_16 (syndrome_16),
.syndrome_17 (syndrome_17),
.syndrome_18 (syndrome_18),
.syndrome_19 (syndrome_19),
.syndrome_20 (syndrome_20),
.syndrome_21 (syndrome_21),
.done (doneSyndrome)
);
 
 
 
//------------------------------------------------------------------
// + epsilon_0,..., epsilon_22
// + degreeEpsilon, failErasure, doneErasure
//- RS Erasure calculation
//------------------------------------------------------------------
wire [7:0] epsilon_0;
wire [7:0] epsilon_1;
wire [7:0] epsilon_2;
wire [7:0] epsilon_3;
wire [7:0] epsilon_4;
wire [7:0] epsilon_5;
wire [7:0] epsilon_6;
wire [7:0] epsilon_7;
wire [7:0] epsilon_8;
wire [7:0] epsilon_9;
wire [7:0] epsilon_10;
wire [7:0] epsilon_11;
wire [7:0] epsilon_12;
wire [7:0] epsilon_13;
wire [7:0] epsilon_14;
wire [7:0] epsilon_15;
wire [7:0] epsilon_16;
wire [7:0] epsilon_17;
wire [7:0] epsilon_18;
wire [7:0] epsilon_19;
wire [7:0] epsilon_20;
wire [7:0] epsilon_21;
wire [7:0] epsilon_22;
wire [4:0] degreeEpsilon;
wire failErasure;
wire doneErasure;
 
 
RsDecodeErasure RsDecodeErasure(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.sync (startPls),
.erasureIn (erasureIn),
// Outputs
.epsilon_0 (epsilon_0),
.epsilon_1 (epsilon_1),
.epsilon_2 (epsilon_2),
.epsilon_3 (epsilon_3),
.epsilon_4 (epsilon_4),
.epsilon_5 (epsilon_5),
.epsilon_6 (epsilon_6),
.epsilon_7 (epsilon_7),
.epsilon_8 (epsilon_8),
.epsilon_9 (epsilon_9),
.epsilon_10 (epsilon_10),
.epsilon_11 (epsilon_11),
.epsilon_12 (epsilon_12),
.epsilon_13 (epsilon_13),
.epsilon_14 (epsilon_14),
.epsilon_15 (epsilon_15),
.epsilon_16 (epsilon_16),
.epsilon_17 (epsilon_17),
.epsilon_18 (epsilon_18),
.epsilon_19 (epsilon_19),
.epsilon_20 (epsilon_20),
.epsilon_21 (epsilon_21),
.epsilon_22 (epsilon_22),
.numErasure (degreeEpsilon),
.fail (failErasure),
.done (doneErasure)
);
 
 
 
//------------------------------------------------------------------
// + polymulSyndrome_0,..., polymulSyndrome_21
// + donePolymul
//- RS Polymul calculation
//------------------------------------------------------------------
wire [7:0] polymulSyndrome_0;
wire [7:0] polymulSyndrome_1;
wire [7:0] polymulSyndrome_2;
wire [7:0] polymulSyndrome_3;
wire [7:0] polymulSyndrome_4;
wire [7:0] polymulSyndrome_5;
wire [7:0] polymulSyndrome_6;
wire [7:0] polymulSyndrome_7;
wire [7:0] polymulSyndrome_8;
wire [7:0] polymulSyndrome_9;
wire [7:0] polymulSyndrome_10;
wire [7:0] polymulSyndrome_11;
wire [7:0] polymulSyndrome_12;
wire [7:0] polymulSyndrome_13;
wire [7:0] polymulSyndrome_14;
wire [7:0] polymulSyndrome_15;
wire [7:0] polymulSyndrome_16;
wire [7:0] polymulSyndrome_17;
wire [7:0] polymulSyndrome_18;
wire [7:0] polymulSyndrome_19;
wire [7:0] polymulSyndrome_20;
wire [7:0] polymulSyndrome_21;
wire donePolymul;
 
 
RsDecodePolymul RsDecodePolymul(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.sync (doneSyndrome),
.syndromeIn_0 (syndrome_0),
.syndromeIn_1 (syndrome_1),
.syndromeIn_2 (syndrome_2),
.syndromeIn_3 (syndrome_3),
.syndromeIn_4 (syndrome_4),
.syndromeIn_5 (syndrome_5),
.syndromeIn_6 (syndrome_6),
.syndromeIn_7 (syndrome_7),
.syndromeIn_8 (syndrome_8),
.syndromeIn_9 (syndrome_9),
.syndromeIn_10 (syndrome_10),
.syndromeIn_11 (syndrome_11),
.syndromeIn_12 (syndrome_12),
.syndromeIn_13 (syndrome_13),
.syndromeIn_14 (syndrome_14),
.syndromeIn_15 (syndrome_15),
.syndromeIn_16 (syndrome_16),
.syndromeIn_17 (syndrome_17),
.syndromeIn_18 (syndrome_18),
.syndromeIn_19 (syndrome_19),
.syndromeIn_20 (syndrome_20),
.syndromeIn_21 (syndrome_21),
.epsilon_0 (epsilon_0),
.epsilon_1 (epsilon_1),
.epsilon_2 (epsilon_2),
.epsilon_3 (epsilon_3),
.epsilon_4 (epsilon_4),
.epsilon_5 (epsilon_5),
.epsilon_6 (epsilon_6),
.epsilon_7 (epsilon_7),
.epsilon_8 (epsilon_8),
.epsilon_9 (epsilon_9),
.epsilon_10 (epsilon_10),
.epsilon_11 (epsilon_11),
.epsilon_12 (epsilon_12),
.epsilon_13 (epsilon_13),
.epsilon_14 (epsilon_14),
.epsilon_15 (epsilon_15),
.epsilon_16 (epsilon_16),
.epsilon_17 (epsilon_17),
.epsilon_18 (epsilon_18),
.epsilon_19 (epsilon_19),
.epsilon_20 (epsilon_20),
.epsilon_21 (epsilon_21),
.epsilon_22 (epsilon_22),
// Outputs
.syndromeOut_0 (polymulSyndrome_0),
.syndromeOut_1 (polymulSyndrome_1),
.syndromeOut_2 (polymulSyndrome_2),
.syndromeOut_3 (polymulSyndrome_3),
.syndromeOut_4 (polymulSyndrome_4),
.syndromeOut_5 (polymulSyndrome_5),
.syndromeOut_6 (polymulSyndrome_6),
.syndromeOut_7 (polymulSyndrome_7),
.syndromeOut_8 (polymulSyndrome_8),
.syndromeOut_9 (polymulSyndrome_9),
.syndromeOut_10 (polymulSyndrome_10),
.syndromeOut_11 (polymulSyndrome_11),
.syndromeOut_12 (polymulSyndrome_12),
.syndromeOut_13 (polymulSyndrome_13),
.syndromeOut_14 (polymulSyndrome_14),
.syndromeOut_15 (polymulSyndrome_15),
.syndromeOut_16 (polymulSyndrome_16),
.syndromeOut_17 (polymulSyndrome_17),
.syndromeOut_18 (polymulSyndrome_18),
.syndromeOut_19 (polymulSyndrome_19),
.syndromeOut_20 (polymulSyndrome_20),
.syndromeOut_21 (polymulSyndrome_21),
.done (donePolymul)
);
 
 
 
//------------------------------------------------------------------
// + lambda_0,..., lambda_21
// + omega_0,..., omega_21
// + numShifted, doneEuclide
//- RS EUCLIDE
//------------------------------------------------------------------
wire [7:0] lambda_0;
wire [7:0] lambda_1;
wire [7:0] lambda_2;
wire [7:0] lambda_3;
wire [7:0] lambda_4;
wire [7:0] lambda_5;
wire [7:0] lambda_6;
wire [7:0] lambda_7;
wire [7:0] lambda_8;
wire [7:0] lambda_9;
wire [7:0] lambda_10;
wire [7:0] lambda_11;
wire [7:0] lambda_12;
wire [7:0] lambda_13;
wire [7:0] lambda_14;
wire [7:0] lambda_15;
wire [7:0] lambda_16;
wire [7:0] lambda_17;
wire [7:0] lambda_18;
wire [7:0] lambda_19;
wire [7:0] lambda_20;
wire [7:0] lambda_21;
wire [7:0] omega_0;
wire [7:0] omega_1;
wire [7:0] omega_2;
wire [7:0] omega_3;
wire [7:0] omega_4;
wire [7:0] omega_5;
wire [7:0] omega_6;
wire [7:0] omega_7;
wire [7:0] omega_8;
wire [7:0] omega_9;
wire [7:0] omega_10;
wire [7:0] omega_11;
wire [7:0] omega_12;
wire [7:0] omega_13;
wire [7:0] omega_14;
wire [7:0] omega_15;
wire [7:0] omega_16;
wire [7:0] omega_17;
wire [7:0] omega_18;
wire [7:0] omega_19;
wire [7:0] omega_20;
wire [7:0] omega_21;
wire doneEuclide;
wire [4:0] numShifted;
reg [4:0] degreeEpsilonReg;
 
 
RsDecodeEuclide RsDecodeEuclide(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.sync (donePolymul),
.syndrome_0 (polymulSyndrome_0),
.syndrome_1 (polymulSyndrome_1),
.syndrome_2 (polymulSyndrome_2),
.syndrome_3 (polymulSyndrome_3),
.syndrome_4 (polymulSyndrome_4),
.syndrome_5 (polymulSyndrome_5),
.syndrome_6 (polymulSyndrome_6),
.syndrome_7 (polymulSyndrome_7),
.syndrome_8 (polymulSyndrome_8),
.syndrome_9 (polymulSyndrome_9),
.syndrome_10 (polymulSyndrome_10),
.syndrome_11 (polymulSyndrome_11),
.syndrome_12 (polymulSyndrome_12),
.syndrome_13 (polymulSyndrome_13),
.syndrome_14 (polymulSyndrome_14),
.syndrome_15 (polymulSyndrome_15),
.syndrome_16 (polymulSyndrome_16),
.syndrome_17 (polymulSyndrome_17),
.syndrome_18 (polymulSyndrome_18),
.syndrome_19 (polymulSyndrome_19),
.syndrome_20 (polymulSyndrome_20),
.syndrome_21 (polymulSyndrome_21),
.numErasure (degreeEpsilonReg),
// Outputs
.lambda_0 (lambda_0),
.lambda_1 (lambda_1),
.lambda_2 (lambda_2),
.lambda_3 (lambda_3),
.lambda_4 (lambda_4),
.lambda_5 (lambda_5),
.lambda_6 (lambda_6),
.lambda_7 (lambda_7),
.lambda_8 (lambda_8),
.lambda_9 (lambda_9),
.lambda_10 (lambda_10),
.lambda_11 (lambda_11),
.lambda_12 (lambda_12),
.lambda_13 (lambda_13),
.lambda_14 (lambda_14),
.lambda_15 (lambda_15),
.lambda_16 (lambda_16),
.lambda_17 (lambda_17),
.lambda_18 (lambda_18),
.lambda_19 (lambda_19),
.lambda_20 (lambda_20),
.lambda_21 (lambda_21),
.omega_0 (omega_0),
.omega_1 (omega_1),
.omega_2 (omega_2),
.omega_3 (omega_3),
.omega_4 (omega_4),
.omega_5 (omega_5),
.omega_6 (omega_6),
.omega_7 (omega_7),
.omega_8 (omega_8),
.omega_9 (omega_9),
.omega_10 (omega_10),
.omega_11 (omega_11),
.omega_12 (omega_12),
.omega_13 (omega_13),
.omega_14 (omega_14),
.omega_15 (omega_15),
.omega_16 (omega_16),
.omega_17 (omega_17),
.omega_18 (omega_18),
.omega_19 (omega_19),
.omega_20 (omega_20),
.omega_21 (omega_21),
.numShifted (numShifted),
.done (doneEuclide)
);
 
 
 
//------------------------------------------------------------------
// + epsilonReg_0, ..., epsilonReg_22
//-
//------------------------------------------------------------------
reg [7:0] epsilonReg_0;
reg [7:0] epsilonReg_1;
reg [7:0] epsilonReg_2;
reg [7:0] epsilonReg_3;
reg [7:0] epsilonReg_4;
reg [7:0] epsilonReg_5;
reg [7:0] epsilonReg_6;
reg [7:0] epsilonReg_7;
reg [7:0] epsilonReg_8;
reg [7:0] epsilonReg_9;
reg [7:0] epsilonReg_10;
reg [7:0] epsilonReg_11;
reg [7:0] epsilonReg_12;
reg [7:0] epsilonReg_13;
reg [7:0] epsilonReg_14;
reg [7:0] epsilonReg_15;
reg [7:0] epsilonReg_16;
reg [7:0] epsilonReg_17;
reg [7:0] epsilonReg_18;
reg [7:0] epsilonReg_19;
reg [7:0] epsilonReg_20;
reg [7:0] epsilonReg_21;
reg [7:0] epsilonReg_22;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= 8'd0;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
epsilonReg_0 [7:0] <= epsilon_0 [7:0];
epsilonReg_1 [7:0] <= epsilon_1 [7:0];
epsilonReg_2 [7:0] <= epsilon_2 [7:0];
epsilonReg_3 [7:0] <= epsilon_3 [7:0];
epsilonReg_4 [7:0] <= epsilon_4 [7:0];
epsilonReg_5 [7:0] <= epsilon_5 [7:0];
epsilonReg_6 [7:0] <= epsilon_6 [7:0];
epsilonReg_7 [7:0] <= epsilon_7 [7:0];
epsilonReg_8 [7:0] <= epsilon_8 [7:0];
epsilonReg_9 [7:0] <= epsilon_9 [7:0];
epsilonReg_10 [7:0] <= epsilon_10 [7:0];
epsilonReg_11 [7:0] <= epsilon_11 [7:0];
epsilonReg_12 [7:0] <= epsilon_12 [7:0];
epsilonReg_13 [7:0] <= epsilon_13 [7:0];
epsilonReg_14 [7:0] <= epsilon_14 [7:0];
epsilonReg_15 [7:0] <= epsilon_15 [7:0];
epsilonReg_16 [7:0] <= epsilon_16 [7:0];
epsilonReg_17 [7:0] <= epsilon_17 [7:0];
epsilonReg_18 [7:0] <= epsilon_18 [7:0];
epsilonReg_19 [7:0] <= epsilon_19 [7:0];
epsilonReg_20 [7:0] <= epsilon_20 [7:0];
epsilonReg_21 [7:0] <= epsilon_21 [7:0];
epsilonReg_22 [7:0] <= epsilon_22 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + epsilonReg2_0,..., epsilonReg2_22
//-
//------------------------------------------------------------------
reg [7:0] epsilonReg2_0;
reg [7:0] epsilonReg2_1;
reg [7:0] epsilonReg2_2;
reg [7:0] epsilonReg2_3;
reg [7:0] epsilonReg2_4;
reg [7:0] epsilonReg2_5;
reg [7:0] epsilonReg2_6;
reg [7:0] epsilonReg2_7;
reg [7:0] epsilonReg2_8;
reg [7:0] epsilonReg2_9;
reg [7:0] epsilonReg2_10;
reg [7:0] epsilonReg2_11;
reg [7:0] epsilonReg2_12;
reg [7:0] epsilonReg2_13;
reg [7:0] epsilonReg2_14;
reg [7:0] epsilonReg2_15;
reg [7:0] epsilonReg2_16;
reg [7:0] epsilonReg2_17;
reg [7:0] epsilonReg2_18;
reg [7:0] epsilonReg2_19;
reg [7:0] epsilonReg2_20;
reg [7:0] epsilonReg2_21;
reg [7:0] epsilonReg2_22;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg2_0 [7:0] <= 8'd0;
epsilonReg2_1 [7:0] <= 8'd0;
epsilonReg2_2 [7:0] <= 8'd0;
epsilonReg2_3 [7:0] <= 8'd0;
epsilonReg2_4 [7:0] <= 8'd0;
epsilonReg2_5 [7:0] <= 8'd0;
epsilonReg2_6 [7:0] <= 8'd0;
epsilonReg2_7 [7:0] <= 8'd0;
epsilonReg2_8 [7:0] <= 8'd0;
epsilonReg2_9 [7:0] <= 8'd0;
epsilonReg2_10 [7:0] <= 8'd0;
epsilonReg2_11 [7:0] <= 8'd0;
epsilonReg2_12 [7:0] <= 8'd0;
epsilonReg2_13 [7:0] <= 8'd0;
epsilonReg2_14 [7:0] <= 8'd0;
epsilonReg2_15 [7:0] <= 8'd0;
epsilonReg2_16 [7:0] <= 8'd0;
epsilonReg2_17 [7:0] <= 8'd0;
epsilonReg2_18 [7:0] <= 8'd0;
epsilonReg2_19 [7:0] <= 8'd0;
epsilonReg2_20 [7:0] <= 8'd0;
epsilonReg2_21 [7:0] <= 8'd0;
epsilonReg2_22 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
epsilonReg2_0 [7:0] <= epsilonReg_0 [7:0];
epsilonReg2_1 [7:0] <= epsilonReg_1 [7:0];
epsilonReg2_2 [7:0] <= epsilonReg_2 [7:0];
epsilonReg2_3 [7:0] <= epsilonReg_3 [7:0];
epsilonReg2_4 [7:0] <= epsilonReg_4 [7:0];
epsilonReg2_5 [7:0] <= epsilonReg_5 [7:0];
epsilonReg2_6 [7:0] <= epsilonReg_6 [7:0];
epsilonReg2_7 [7:0] <= epsilonReg_7 [7:0];
epsilonReg2_8 [7:0] <= epsilonReg_8 [7:0];
epsilonReg2_9 [7:0] <= epsilonReg_9 [7:0];
epsilonReg2_10 [7:0] <= epsilonReg_10 [7:0];
epsilonReg2_11 [7:0] <= epsilonReg_11 [7:0];
epsilonReg2_12 [7:0] <= epsilonReg_12 [7:0];
epsilonReg2_13 [7:0] <= epsilonReg_13 [7:0];
epsilonReg2_14 [7:0] <= epsilonReg_14 [7:0];
epsilonReg2_15 [7:0] <= epsilonReg_15 [7:0];
epsilonReg2_16 [7:0] <= epsilonReg_16 [7:0];
epsilonReg2_17 [7:0] <= epsilonReg_17 [7:0];
epsilonReg2_18 [7:0] <= epsilonReg_18 [7:0];
epsilonReg2_19 [7:0] <= epsilonReg_19 [7:0];
epsilonReg2_20 [7:0] <= epsilonReg_20 [7:0];
epsilonReg2_21 [7:0] <= epsilonReg_21 [7:0];
epsilonReg2_22 [7:0] <= epsilonReg_22 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + epsilonReg3_0, ..., epsilonReg3_22
//-
//------------------------------------------------------------------
reg [7:0] epsilonReg3_0;
reg [7:0] epsilonReg3_1;
reg [7:0] epsilonReg3_2;
reg [7:0] epsilonReg3_3;
reg [7:0] epsilonReg3_4;
reg [7:0] epsilonReg3_5;
reg [7:0] epsilonReg3_6;
reg [7:0] epsilonReg3_7;
reg [7:0] epsilonReg3_8;
reg [7:0] epsilonReg3_9;
reg [7:0] epsilonReg3_10;
reg [7:0] epsilonReg3_11;
reg [7:0] epsilonReg3_12;
reg [7:0] epsilonReg3_13;
reg [7:0] epsilonReg3_14;
reg [7:0] epsilonReg3_15;
reg [7:0] epsilonReg3_16;
reg [7:0] epsilonReg3_17;
reg [7:0] epsilonReg3_18;
reg [7:0] epsilonReg3_19;
reg [7:0] epsilonReg3_20;
reg [7:0] epsilonReg3_21;
reg [7:0] epsilonReg3_22;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg3_0 [7:0] <= 8'd0;
epsilonReg3_1 [7:0] <= 8'd0;
epsilonReg3_2 [7:0] <= 8'd0;
epsilonReg3_3 [7:0] <= 8'd0;
epsilonReg3_4 [7:0] <= 8'd0;
epsilonReg3_5 [7:0] <= 8'd0;
epsilonReg3_6 [7:0] <= 8'd0;
epsilonReg3_7 [7:0] <= 8'd0;
epsilonReg3_8 [7:0] <= 8'd0;
epsilonReg3_9 [7:0] <= 8'd0;
epsilonReg3_10 [7:0] <= 8'd0;
epsilonReg3_11 [7:0] <= 8'd0;
epsilonReg3_12 [7:0] <= 8'd0;
epsilonReg3_13 [7:0] <= 8'd0;
epsilonReg3_14 [7:0] <= 8'd0;
epsilonReg3_15 [7:0] <= 8'd0;
epsilonReg3_16 [7:0] <= 8'd0;
epsilonReg3_17 [7:0] <= 8'd0;
epsilonReg3_18 [7:0] <= 8'd0;
epsilonReg3_19 [7:0] <= 8'd0;
epsilonReg3_20 [7:0] <= 8'd0;
epsilonReg3_21 [7:0] <= 8'd0;
epsilonReg3_22 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
epsilonReg3_0 [7:0] <= epsilonReg2_0 [7:0];
epsilonReg3_1 [7:0] <= epsilonReg2_1 [7:0];
epsilonReg3_2 [7:0] <= epsilonReg2_2 [7:0];
epsilonReg3_3 [7:0] <= epsilonReg2_3 [7:0];
epsilonReg3_4 [7:0] <= epsilonReg2_4 [7:0];
epsilonReg3_5 [7:0] <= epsilonReg2_5 [7:0];
epsilonReg3_6 [7:0] <= epsilonReg2_6 [7:0];
epsilonReg3_7 [7:0] <= epsilonReg2_7 [7:0];
epsilonReg3_8 [7:0] <= epsilonReg2_8 [7:0];
epsilonReg3_9 [7:0] <= epsilonReg2_9 [7:0];
epsilonReg3_10 [7:0] <= epsilonReg2_10 [7:0];
epsilonReg3_11 [7:0] <= epsilonReg2_11 [7:0];
epsilonReg3_12 [7:0] <= epsilonReg2_12 [7:0];
epsilonReg3_13 [7:0] <= epsilonReg2_13 [7:0];
epsilonReg3_14 [7:0] <= epsilonReg2_14 [7:0];
epsilonReg3_15 [7:0] <= epsilonReg2_15 [7:0];
epsilonReg3_16 [7:0] <= epsilonReg2_16 [7:0];
epsilonReg3_17 [7:0] <= epsilonReg2_17 [7:0];
epsilonReg3_18 [7:0] <= epsilonReg2_18 [7:0];
epsilonReg3_19 [7:0] <= epsilonReg2_19 [7:0];
epsilonReg3_20 [7:0] <= epsilonReg2_20 [7:0];
epsilonReg3_21 [7:0] <= epsilonReg2_21 [7:0];
epsilonReg3_22 [7:0] <= epsilonReg2_22 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + degreeEpsilonReg
//-
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeEpsilonReg [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
degreeEpsilonReg <= degreeEpsilon;
end
end
 
 
 
//------------------------------------------------------------------
// + degreeEpsilonReg2
//-
//------------------------------------------------------------------
reg [4:0] degreeEpsilonReg2;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeEpsilonReg2 [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
degreeEpsilonReg2 <= degreeEpsilonReg;
end
end
 
 
 
//------------------------------------------------------------------
// + degreeEpsilonReg3
//-
//------------------------------------------------------------------
reg [4:0] degreeEpsilonReg3;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeEpsilonReg3 [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
degreeEpsilonReg3 <= degreeEpsilonReg2;
end
end
 
 
 
reg doneShiftReg;
//------------------------------------------------------------------
// + degreeEpsilonReg4
//-
//------------------------------------------------------------------
reg [4:0] degreeEpsilonReg4;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeEpsilonReg4 [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
degreeEpsilonReg4 <= degreeEpsilonReg3;
end
end
 
 
 
wire doneChien;
//------------------------------------------------------------------
// + degreeEpsilonReg5
//-
//------------------------------------------------------------------
reg [4:0] degreeEpsilonReg5;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeEpsilonReg5 [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (doneChien == 1'b1)) begin
degreeEpsilonReg5 <= degreeEpsilonReg4;
end
end
 
 
 
reg [2:0] doneReg;
//------------------------------------------------------------------
// + numErasureReg
//-
//------------------------------------------------------------------
reg [4:0] numErasureReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numErasureReg <= 5'd0;
end
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
numErasureReg <= degreeEpsilonReg5;
end
end
 
 
 
//------------------------------------------------------------------------
// + doneShift
//------------------------------------------------------------------------
reg doneShift;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
doneShift <= 1'b0;
end
else if (enable == 1'b1) begin
doneShift <= doneEuclide;
end
end
 
 
 
//------------------------------------------------------------------
// + numShiftedReg
//------------------------------------------------------------------
reg [4:0] numShiftedReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numShiftedReg <= 5'd0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
numShiftedReg <= numShifted;
end
end
 
 
 
//------------------------------------------------------------------
// + lambdaReg_0,..., lambdaReg_21
//------------------------------------------------------------------
reg [7:0] lambdaReg_0;
reg [7:0] lambdaReg_1;
reg [7:0] lambdaReg_2;
reg [7:0] lambdaReg_3;
reg [7:0] lambdaReg_4;
reg [7:0] lambdaReg_5;
reg [7:0] lambdaReg_6;
reg [7:0] lambdaReg_7;
reg [7:0] lambdaReg_8;
reg [7:0] lambdaReg_9;
reg [7:0] lambdaReg_10;
reg [7:0] lambdaReg_11;
reg [7:0] lambdaReg_12;
reg [7:0] lambdaReg_13;
reg [7:0] lambdaReg_14;
reg [7:0] lambdaReg_15;
reg [7:0] lambdaReg_16;
reg [7:0] lambdaReg_17;
reg [7:0] lambdaReg_18;
reg [7:0] lambdaReg_19;
reg [7:0] lambdaReg_20;
reg [7:0] lambdaReg_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaReg_0 [7:0] <= 8'd0;
lambdaReg_1 [7:0] <= 8'd0;
lambdaReg_2 [7:0] <= 8'd0;
lambdaReg_3 [7:0] <= 8'd0;
lambdaReg_4 [7:0] <= 8'd0;
lambdaReg_5 [7:0] <= 8'd0;
lambdaReg_6 [7:0] <= 8'd0;
lambdaReg_7 [7:0] <= 8'd0;
lambdaReg_8 [7:0] <= 8'd0;
lambdaReg_9 [7:0] <= 8'd0;
lambdaReg_10 [7:0] <= 8'd0;
lambdaReg_11 [7:0] <= 8'd0;
lambdaReg_12 [7:0] <= 8'd0;
lambdaReg_13 [7:0] <= 8'd0;
lambdaReg_14 [7:0] <= 8'd0;
lambdaReg_15 [7:0] <= 8'd0;
lambdaReg_16 [7:0] <= 8'd0;
lambdaReg_17 [7:0] <= 8'd0;
lambdaReg_18 [7:0] <= 8'd0;
lambdaReg_19 [7:0] <= 8'd0;
lambdaReg_20 [7:0] <= 8'd0;
lambdaReg_21 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
lambdaReg_0 [7:0] <= lambda_0 [7:0];
lambdaReg_1 [7:0] <= lambda_1 [7:0];
lambdaReg_2 [7:0] <= lambda_2 [7:0];
lambdaReg_3 [7:0] <= lambda_3 [7:0];
lambdaReg_4 [7:0] <= lambda_4 [7:0];
lambdaReg_5 [7:0] <= lambda_5 [7:0];
lambdaReg_6 [7:0] <= lambda_6 [7:0];
lambdaReg_7 [7:0] <= lambda_7 [7:0];
lambdaReg_8 [7:0] <= lambda_8 [7:0];
lambdaReg_9 [7:0] <= lambda_9 [7:0];
lambdaReg_10 [7:0] <= lambda_10 [7:0];
lambdaReg_11 [7:0] <= lambda_11 [7:0];
lambdaReg_12 [7:0] <= lambda_12 [7:0];
lambdaReg_13 [7:0] <= lambda_13 [7:0];
lambdaReg_14 [7:0] <= lambda_14 [7:0];
lambdaReg_15 [7:0] <= lambda_15 [7:0];
lambdaReg_16 [7:0] <= lambda_16 [7:0];
lambdaReg_17 [7:0] <= lambda_17 [7:0];
lambdaReg_18 [7:0] <= lambda_18 [7:0];
lambdaReg_19 [7:0] <= lambda_19 [7:0];
lambdaReg_20 [7:0] <= lambda_20 [7:0];
lambdaReg_21 [7:0] <= lambda_21 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + omegaReg_0,..., omegaReg_21
//------------------------------------------------------------------
reg [7:0] omegaReg_0;
reg [7:0] omegaReg_1;
reg [7:0] omegaReg_2;
reg [7:0] omegaReg_3;
reg [7:0] omegaReg_4;
reg [7:0] omegaReg_5;
reg [7:0] omegaReg_6;
reg [7:0] omegaReg_7;
reg [7:0] omegaReg_8;
reg [7:0] omegaReg_9;
reg [7:0] omegaReg_10;
reg [7:0] omegaReg_11;
reg [7:0] omegaReg_12;
reg [7:0] omegaReg_13;
reg [7:0] omegaReg_14;
reg [7:0] omegaReg_15;
reg [7:0] omegaReg_16;
reg [7:0] omegaReg_17;
reg [7:0] omegaReg_18;
reg [7:0] omegaReg_19;
reg [7:0] omegaReg_20;
reg [7:0] omegaReg_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaReg_0 [7:0] <= 8'd0;
omegaReg_1 [7:0] <= 8'd0;
omegaReg_2 [7:0] <= 8'd0;
omegaReg_3 [7:0] <= 8'd0;
omegaReg_4 [7:0] <= 8'd0;
omegaReg_5 [7:0] <= 8'd0;
omegaReg_6 [7:0] <= 8'd0;
omegaReg_7 [7:0] <= 8'd0;
omegaReg_8 [7:0] <= 8'd0;
omegaReg_9 [7:0] <= 8'd0;
omegaReg_10 [7:0] <= 8'd0;
omegaReg_11 [7:0] <= 8'd0;
omegaReg_12 [7:0] <= 8'd0;
omegaReg_13 [7:0] <= 8'd0;
omegaReg_14 [7:0] <= 8'd0;
omegaReg_15 [7:0] <= 8'd0;
omegaReg_16 [7:0] <= 8'd0;
omegaReg_17 [7:0] <= 8'd0;
omegaReg_18 [7:0] <= 8'd0;
omegaReg_19 [7:0] <= 8'd0;
omegaReg_20 [7:0] <= 8'd0;
omegaReg_21 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
omegaReg_0 [7:0] <= omega_0 [7:0];
omegaReg_1 [7:0] <= omega_1 [7:0];
omegaReg_2 [7:0] <= omega_2 [7:0];
omegaReg_3 [7:0] <= omega_3 [7:0];
omegaReg_4 [7:0] <= omega_4 [7:0];
omegaReg_5 [7:0] <= omega_5 [7:0];
omegaReg_6 [7:0] <= omega_6 [7:0];
omegaReg_7 [7:0] <= omega_7 [7:0];
omegaReg_8 [7:0] <= omega_8 [7:0];
omegaReg_9 [7:0] <= omega_9 [7:0];
omegaReg_10 [7:0] <= omega_10 [7:0];
omegaReg_11 [7:0] <= omega_11 [7:0];
omegaReg_12 [7:0] <= omega_12 [7:0];
omegaReg_13 [7:0] <= omega_13 [7:0];
omegaReg_14 [7:0] <= omega_14 [7:0];
omegaReg_15 [7:0] <= omega_15 [7:0];
omegaReg_16 [7:0] <= omega_16 [7:0];
omegaReg_17 [7:0] <= omega_17 [7:0];
omegaReg_18 [7:0] <= omega_18 [7:0];
omegaReg_19 [7:0] <= omega_19 [7:0];
omegaReg_20 [7:0] <= omega_20 [7:0];
omegaReg_21 [7:0] <= omega_21 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + omegaShifted_0, ..., omegaShifted_21
//- Rs Shift Omega
//------------------------------------------------------------------
wire [7:0] omegaShifted_0;
wire [7:0] omegaShifted_1;
wire [7:0] omegaShifted_2;
wire [7:0] omegaShifted_3;
wire [7:0] omegaShifted_4;
wire [7:0] omegaShifted_5;
wire [7:0] omegaShifted_6;
wire [7:0] omegaShifted_7;
wire [7:0] omegaShifted_8;
wire [7:0] omegaShifted_9;
wire [7:0] omegaShifted_10;
wire [7:0] omegaShifted_11;
wire [7:0] omegaShifted_12;
wire [7:0] omegaShifted_13;
wire [7:0] omegaShifted_14;
wire [7:0] omegaShifted_15;
wire [7:0] omegaShifted_16;
wire [7:0] omegaShifted_17;
wire [7:0] omegaShifted_18;
wire [7:0] omegaShifted_19;
wire [7:0] omegaShifted_20;
wire [7:0] omegaShifted_21;
 
 
RsDecodeShiftOmega RsDecodeShiftOmega(
// Inputs
.omega_0 (omegaReg_0),
.omega_1 (omegaReg_1),
.omega_2 (omegaReg_2),
.omega_3 (omegaReg_3),
.omega_4 (omegaReg_4),
.omega_5 (omegaReg_5),
.omega_6 (omegaReg_6),
.omega_7 (omegaReg_7),
.omega_8 (omegaReg_8),
.omega_9 (omegaReg_9),
.omega_10 (omegaReg_10),
.omega_11 (omegaReg_11),
.omega_12 (omegaReg_12),
.omega_13 (omegaReg_13),
.omega_14 (omegaReg_14),
.omega_15 (omegaReg_15),
.omega_16 (omegaReg_16),
.omega_17 (omegaReg_17),
.omega_18 (omegaReg_18),
.omega_19 (omegaReg_19),
.omega_20 (omegaReg_20),
.omega_21 (omegaReg_21),
// Outputs
.omegaShifted_0 (omegaShifted_0),
.omegaShifted_1 (omegaShifted_1),
.omegaShifted_2 (omegaShifted_2),
.omegaShifted_3 (omegaShifted_3),
.omegaShifted_4 (omegaShifted_4),
.omegaShifted_5 (omegaShifted_5),
.omegaShifted_6 (omegaShifted_6),
.omegaShifted_7 (omegaShifted_7),
.omegaShifted_8 (omegaShifted_8),
.omegaShifted_9 (omegaShifted_9),
.omegaShifted_10 (omegaShifted_10),
.omegaShifted_11 (omegaShifted_11),
.omegaShifted_12 (omegaShifted_12),
.omegaShifted_13 (omegaShifted_13),
.omegaShifted_14 (omegaShifted_14),
.omegaShifted_15 (omegaShifted_15),
.omegaShifted_16 (omegaShifted_16),
.omegaShifted_17 (omegaShifted_17),
.omegaShifted_18 (omegaShifted_18),
.omegaShifted_19 (omegaShifted_19),
.omegaShifted_20 (omegaShifted_20),
.omegaShifted_21 (omegaShifted_21),
// Inputs
.numShifted (numShiftedReg)
);
 
 
 
//------------------------------------------------------------------
// + omegaShiftedReg_0,.., omegaShiftedReg_21
//------------------------------------------------------------------
reg [7:0] omegaShiftedReg_0;
reg [7:0] omegaShiftedReg_1;
reg [7:0] omegaShiftedReg_2;
reg [7:0] omegaShiftedReg_3;
reg [7:0] omegaShiftedReg_4;
reg [7:0] omegaShiftedReg_5;
reg [7:0] omegaShiftedReg_6;
reg [7:0] omegaShiftedReg_7;
reg [7:0] omegaShiftedReg_8;
reg [7:0] omegaShiftedReg_9;
reg [7:0] omegaShiftedReg_10;
reg [7:0] omegaShiftedReg_11;
reg [7:0] omegaShiftedReg_12;
reg [7:0] omegaShiftedReg_13;
reg [7:0] omegaShiftedReg_14;
reg [7:0] omegaShiftedReg_15;
reg [7:0] omegaShiftedReg_16;
reg [7:0] omegaShiftedReg_17;
reg [7:0] omegaShiftedReg_18;
reg [7:0] omegaShiftedReg_19;
reg [7:0] omegaShiftedReg_20;
reg [7:0] omegaShiftedReg_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaShiftedReg_0 [7:0] <= 8'd0;
omegaShiftedReg_1 [7:0] <= 8'd0;
omegaShiftedReg_2 [7:0] <= 8'd0;
omegaShiftedReg_3 [7:0] <= 8'd0;
omegaShiftedReg_4 [7:0] <= 8'd0;
omegaShiftedReg_5 [7:0] <= 8'd0;
omegaShiftedReg_6 [7:0] <= 8'd0;
omegaShiftedReg_7 [7:0] <= 8'd0;
omegaShiftedReg_8 [7:0] <= 8'd0;
omegaShiftedReg_9 [7:0] <= 8'd0;
omegaShiftedReg_10 [7:0] <= 8'd0;
omegaShiftedReg_11 [7:0] <= 8'd0;
omegaShiftedReg_12 [7:0] <= 8'd0;
omegaShiftedReg_13 [7:0] <= 8'd0;
omegaShiftedReg_14 [7:0] <= 8'd0;
omegaShiftedReg_15 [7:0] <= 8'd0;
omegaShiftedReg_16 [7:0] <= 8'd0;
omegaShiftedReg_17 [7:0] <= 8'd0;
omegaShiftedReg_18 [7:0] <= 8'd0;
omegaShiftedReg_19 [7:0] <= 8'd0;
omegaShiftedReg_20 [7:0] <= 8'd0;
omegaShiftedReg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
omegaShiftedReg_0 [7:0] <= omegaShifted_0 [7:0];
omegaShiftedReg_1 [7:0] <= omegaShifted_1 [7:0];
omegaShiftedReg_2 [7:0] <= omegaShifted_2 [7:0];
omegaShiftedReg_3 [7:0] <= omegaShifted_3 [7:0];
omegaShiftedReg_4 [7:0] <= omegaShifted_4 [7:0];
omegaShiftedReg_5 [7:0] <= omegaShifted_5 [7:0];
omegaShiftedReg_6 [7:0] <= omegaShifted_6 [7:0];
omegaShiftedReg_7 [7:0] <= omegaShifted_7 [7:0];
omegaShiftedReg_8 [7:0] <= omegaShifted_8 [7:0];
omegaShiftedReg_9 [7:0] <= omegaShifted_9 [7:0];
omegaShiftedReg_10 [7:0] <= omegaShifted_10 [7:0];
omegaShiftedReg_11 [7:0] <= omegaShifted_11 [7:0];
omegaShiftedReg_12 [7:0] <= omegaShifted_12 [7:0];
omegaShiftedReg_13 [7:0] <= omegaShifted_13 [7:0];
omegaShiftedReg_14 [7:0] <= omegaShifted_14 [7:0];
omegaShiftedReg_15 [7:0] <= omegaShifted_15 [7:0];
omegaShiftedReg_16 [7:0] <= omegaShifted_16 [7:0];
omegaShiftedReg_17 [7:0] <= omegaShifted_17 [7:0];
omegaShiftedReg_18 [7:0] <= omegaShifted_18 [7:0];
omegaShiftedReg_19 [7:0] <= omegaShifted_19 [7:0];
omegaShiftedReg_20 [7:0] <= omegaShifted_20 [7:0];
omegaShiftedReg_21 [7:0] <= omegaShifted_21 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + degreeOmega
//------------------------------------------------------------------
wire [4:0] degreeOmega;
 
 
RsDecodeDegree RsDecodeDegree_1(
// Inputs
.polynom_0 (omegaShiftedReg_0),
.polynom_1 (omegaShiftedReg_1),
.polynom_2 (omegaShiftedReg_2),
.polynom_3 (omegaShiftedReg_3),
.polynom_4 (omegaShiftedReg_4),
.polynom_5 (omegaShiftedReg_5),
.polynom_6 (omegaShiftedReg_6),
.polynom_7 (omegaShiftedReg_7),
.polynom_8 (omegaShiftedReg_8),
.polynom_9 (omegaShiftedReg_9),
.polynom_10 (omegaShiftedReg_10),
.polynom_11 (omegaShiftedReg_11),
.polynom_12 (omegaShiftedReg_12),
.polynom_13 (omegaShiftedReg_13),
.polynom_14 (omegaShiftedReg_14),
.polynom_15 (omegaShiftedReg_15),
.polynom_16 (omegaShiftedReg_16),
.polynom_17 (omegaShiftedReg_17),
.polynom_18 (omegaShiftedReg_18),
.polynom_19 (omegaShiftedReg_19),
.polynom_20 (omegaShiftedReg_20),
.polynom_21 (omegaShiftedReg_21),
// Outputs
.degree (degreeOmega)
);
 
 
 
//------------------------------------------------------------------
// + lambdaReg2_0,.., lambdaReg2_21
//------------------------------------------------------------------
reg [7:0] lambdaReg2_0;
reg [7:0] lambdaReg2_1;
reg [7:0] lambdaReg2_2;
reg [7:0] lambdaReg2_3;
reg [7:0] lambdaReg2_4;
reg [7:0] lambdaReg2_5;
reg [7:0] lambdaReg2_6;
reg [7:0] lambdaReg2_7;
reg [7:0] lambdaReg2_8;
reg [7:0] lambdaReg2_9;
reg [7:0] lambdaReg2_10;
reg [7:0] lambdaReg2_11;
reg [7:0] lambdaReg2_12;
reg [7:0] lambdaReg2_13;
reg [7:0] lambdaReg2_14;
reg [7:0] lambdaReg2_15;
reg [7:0] lambdaReg2_16;
reg [7:0] lambdaReg2_17;
reg [7:0] lambdaReg2_18;
reg [7:0] lambdaReg2_19;
reg [7:0] lambdaReg2_20;
reg [7:0] lambdaReg2_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaReg2_0 [7:0] <= 8'd0;
lambdaReg2_1 [7:0] <= 8'd0;
lambdaReg2_2 [7:0] <= 8'd0;
lambdaReg2_3 [7:0] <= 8'd0;
lambdaReg2_4 [7:0] <= 8'd0;
lambdaReg2_5 [7:0] <= 8'd0;
lambdaReg2_6 [7:0] <= 8'd0;
lambdaReg2_7 [7:0] <= 8'd0;
lambdaReg2_8 [7:0] <= 8'd0;
lambdaReg2_9 [7:0] <= 8'd0;
lambdaReg2_10 [7:0] <= 8'd0;
lambdaReg2_11 [7:0] <= 8'd0;
lambdaReg2_12 [7:0] <= 8'd0;
lambdaReg2_13 [7:0] <= 8'd0;
lambdaReg2_14 [7:0] <= 8'd0;
lambdaReg2_15 [7:0] <= 8'd0;
lambdaReg2_16 [7:0] <= 8'd0;
lambdaReg2_17 [7:0] <= 8'd0;
lambdaReg2_18 [7:0] <= 8'd0;
lambdaReg2_19 [7:0] <= 8'd0;
lambdaReg2_20 [7:0] <= 8'd0;
lambdaReg2_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
lambdaReg2_0 [7:0] <= lambdaReg_0 [7:0];
lambdaReg2_1 [7:0] <= lambdaReg_1 [7:0];
lambdaReg2_2 [7:0] <= lambdaReg_2 [7:0];
lambdaReg2_3 [7:0] <= lambdaReg_3 [7:0];
lambdaReg2_4 [7:0] <= lambdaReg_4 [7:0];
lambdaReg2_5 [7:0] <= lambdaReg_5 [7:0];
lambdaReg2_6 [7:0] <= lambdaReg_6 [7:0];
lambdaReg2_7 [7:0] <= lambdaReg_7 [7:0];
lambdaReg2_8 [7:0] <= lambdaReg_8 [7:0];
lambdaReg2_9 [7:0] <= lambdaReg_9 [7:0];
lambdaReg2_10 [7:0] <= lambdaReg_10 [7:0];
lambdaReg2_11 [7:0] <= lambdaReg_11 [7:0];
lambdaReg2_12 [7:0] <= lambdaReg_12 [7:0];
lambdaReg2_13 [7:0] <= lambdaReg_13 [7:0];
lambdaReg2_14 [7:0] <= lambdaReg_14 [7:0];
lambdaReg2_15 [7:0] <= lambdaReg_15 [7:0];
lambdaReg2_16 [7:0] <= lambdaReg_16 [7:0];
lambdaReg2_17 [7:0] <= lambdaReg_17 [7:0];
lambdaReg2_18 [7:0] <= lambdaReg_18 [7:0];
lambdaReg2_19 [7:0] <= lambdaReg_19 [7:0];
lambdaReg2_20 [7:0] <= lambdaReg_20 [7:0];
lambdaReg2_21 [7:0] <= lambdaReg_21 [7:0];
end
end
 
 
 
//------------------------------------------------------------------
// + degreeLambda
//------------------------------------------------------------------
wire [4:0] degreeLambda;
RsDecodeDegree RsDecodeDegree_2(
// Inputs
.polynom_0 (lambdaReg2_0),
.polynom_1 (lambdaReg2_1),
.polynom_2 (lambdaReg2_2),
.polynom_3 (lambdaReg2_3),
.polynom_4 (lambdaReg2_4),
.polynom_5 (lambdaReg2_5),
.polynom_6 (lambdaReg2_6),
.polynom_7 (lambdaReg2_7),
.polynom_8 (lambdaReg2_8),
.polynom_9 (lambdaReg2_9),
.polynom_10 (lambdaReg2_10),
.polynom_11 (lambdaReg2_11),
.polynom_12 (lambdaReg2_12),
.polynom_13 (lambdaReg2_13),
.polynom_14 (lambdaReg2_14),
.polynom_15 (lambdaReg2_15),
.polynom_16 (lambdaReg2_16),
.polynom_17 (lambdaReg2_17),
.polynom_18 (lambdaReg2_18),
.polynom_19 (lambdaReg2_19),
.polynom_20 (lambdaReg2_20),
.polynom_21 (lambdaReg2_21),
// Outputs
.degree (degreeLambda)
);
 
 
 
//------------------------------------------------------------------
// + degreeOmegaReg
// + degreeLambdaReg
//------------------------------------------------------------------
reg [4:0] degreeOmegaReg;
reg [4:0] degreeLambdaReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeOmegaReg <= 5'd0;
degreeLambdaReg <= 5'd0;
end
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
degreeOmegaReg <= degreeOmega;
degreeLambdaReg <= degreeLambda;
end
end
 
 
 
//------------------------------------------------------------------
// + doneShiftReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
doneShiftReg <= 1'b0;
end
else if (enable == 1'b1) begin
doneShiftReg <= doneShift;
end
end
 
 
 
//------------------------------------------------------------------
// +
//- RS Chien Search Algorithm
//------------------------------------------------------------------
wire [4:0] numErrorChien;
wire [7:0] error;
wire delayedErasureIn;
 
 
RsDecodeChien RsDecodeChien(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.sync (doneShiftReg),
.erasureIn (delayedErasureIn),
.lambdaIn_0 (lambdaReg2_0),
.lambdaIn_1 (lambdaReg2_1),
.lambdaIn_2 (lambdaReg2_2),
.lambdaIn_3 (lambdaReg2_3),
.lambdaIn_4 (lambdaReg2_4),
.lambdaIn_5 (lambdaReg2_5),
.lambdaIn_6 (lambdaReg2_6),
.lambdaIn_7 (lambdaReg2_7),
.lambdaIn_8 (lambdaReg2_8),
.lambdaIn_9 (lambdaReg2_9),
.lambdaIn_10 (lambdaReg2_10),
.lambdaIn_11 (lambdaReg2_11),
.lambdaIn_12 (lambdaReg2_12),
.lambdaIn_13 (lambdaReg2_13),
.lambdaIn_14 (lambdaReg2_14),
.lambdaIn_15 (lambdaReg2_15),
.lambdaIn_16 (lambdaReg2_16),
.lambdaIn_17 (lambdaReg2_17),
.lambdaIn_18 (lambdaReg2_18),
.lambdaIn_19 (lambdaReg2_19),
.lambdaIn_20 (lambdaReg2_20),
.lambdaIn_21 (lambdaReg2_21),
.omegaIn_0 (omegaShiftedReg_0),
.omegaIn_1 (omegaShiftedReg_1),
.omegaIn_2 (omegaShiftedReg_2),
.omegaIn_3 (omegaShiftedReg_3),
.omegaIn_4 (omegaShiftedReg_4),
.omegaIn_5 (omegaShiftedReg_5),
.omegaIn_6 (omegaShiftedReg_6),
.omegaIn_7 (omegaShiftedReg_7),
.omegaIn_8 (omegaShiftedReg_8),
.omegaIn_9 (omegaShiftedReg_9),
.omegaIn_10 (omegaShiftedReg_10),
.omegaIn_11 (omegaShiftedReg_11),
.omegaIn_12 (omegaShiftedReg_12),
.omegaIn_13 (omegaShiftedReg_13),
.omegaIn_14 (omegaShiftedReg_14),
.omegaIn_15 (omegaShiftedReg_15),
.omegaIn_16 (omegaShiftedReg_16),
.omegaIn_17 (omegaShiftedReg_17),
.omegaIn_18 (omegaShiftedReg_18),
.omegaIn_19 (omegaShiftedReg_19),
.omegaIn_20 (omegaShiftedReg_20),
.omegaIn_21 (omegaShiftedReg_21),
.epsilonIn_0 (epsilonReg3_0),
.epsilonIn_1 (epsilonReg3_1),
.epsilonIn_2 (epsilonReg3_2),
.epsilonIn_3 (epsilonReg3_3),
.epsilonIn_4 (epsilonReg3_4),
.epsilonIn_5 (epsilonReg3_5),
.epsilonIn_6 (epsilonReg3_6),
.epsilonIn_7 (epsilonReg3_7),
.epsilonIn_8 (epsilonReg3_8),
.epsilonIn_9 (epsilonReg3_9),
.epsilonIn_10 (epsilonReg3_10),
.epsilonIn_11 (epsilonReg3_11),
.epsilonIn_12 (epsilonReg3_12),
.epsilonIn_13 (epsilonReg3_13),
.epsilonIn_14 (epsilonReg3_14),
.epsilonIn_15 (epsilonReg3_15),
.epsilonIn_16 (epsilonReg3_16),
.epsilonIn_17 (epsilonReg3_17),
.epsilonIn_18 (epsilonReg3_18),
.epsilonIn_19 (epsilonReg3_19),
.epsilonIn_20 (epsilonReg3_20),
.epsilonIn_21 (epsilonReg3_21),
.epsilonIn_22 (epsilonReg3_22),
// Outputs
.errorOut (error),
.numError (numErrorChien),
.done (doneChien)
);
 
 
 
//------------------------------------------------------------------
// + delayOut
//- Rs Decode Delay
//------------------------------------------------------------------
wire [8:0] delayOut;
wire [8:0] delayIn;
 
 
RsDecodeDelay RsDecodeDelay(
// Inputs
.CLK (CLK),
.RESET (RESET),
.enable (enable),
.dataIn (delayIn),
// Outputs
.dataOut (delayOut)
);
 
 
 
//------------------------------------------------------------------
// + delayIn, delayedErasureIn, delayedDataIn
//------------------------------------------------------------------
wire [7:0] delayedDataIn;
assign delayIn = {erasureIn, dataInCheck};
assign delayedErasureIn = delayOut[8];
assign delayedDataIn = delayOut[7:0];
 
 
 
//------------------------------------------------------------------------
// + OutputValidReg
//------------------------------------------------------------------------
reg OutputValidReg;
reg [3:0] startReg;
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
OutputValidReg <= 1'b0;
end
else if (enable == 1'b1) begin
if (startReg[1] == 1'b1) begin
OutputValidReg <= 1'b1;
end
else if (doneReg[0] == 1'b1) begin
OutputValidReg <= 1'b0;
end
end
end
 
 
 
//------------------------------------------------------------------
// + startReg, doneReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
startReg [3:0] <= 4'd0;
doneReg [2:0] <= 3'd0;
end
else if (enable == 1'b1) begin
startReg [3:0] <= {doneShiftReg, startReg[3:1]};
doneReg [2:0] <= {doneChien, doneReg[2:1]};
end
end
 
 
 
//------------------------------------------------------------------
// + numErrorLambdaReg
//------------------------------------------------------------------
reg [4:0] numErrorLambdaReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numErrorLambdaReg [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
numErrorLambdaReg <= degreeLambdaReg;
end
end
 
 
 
//------------------------------------------------------------------
// + degreeErrorReg
//------------------------------------------------------------------
reg degreeErrorReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
degreeErrorReg <= 1'b0;
end
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
if (({1'b0, degreeOmegaReg}) <= ({1'b0, degreeLambdaReg}) + ({1'b0, degreeEpsilonReg4})) begin
degreeErrorReg <= 1'b0;
end
else begin
degreeErrorReg <= 1'b1;
end
end
end
 
 
 
//------------------------------------------------------------------
// + numErrorReg
//------------------------------------------------------------------
reg [4:0] numErrorReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numErrorReg [4:0] <= 5'd0;
end
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
numErrorReg [4:0] <= numErrorChien[4:0];
end
end
 
 
 
//------------------------------------------------------------------
// + failErasureReg
//-
//------------------------------------------------------------------
reg failErasureReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failErasureReg <= 1'b0;
end
else if ((enable == 1'b1) && (doneErasure == 1'b1)) begin
failErasureReg <= failErasure;
end
end
 
 
 
//------------------------------------------------------------------
// + failErasureReg2
//-
//------------------------------------------------------------------
reg failErasureReg2;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failErasureReg2 <= 1'b0;
end
else if ((enable == 1'b1) && (donePolymul == 1'b1)) begin
failErasureReg2 <= failErasureReg;
end
end
 
 
 
//------------------------------------------------------------------
// + failErasureReg3
//-
//------------------------------------------------------------------
reg failErasureReg3;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failErasureReg3 <= 1'b0;
end
else if ((enable == 1'b1) && (doneEuclide == 1'b1)) begin
failErasureReg3 <= failErasureReg2;
end
end
 
 
 
//------------------------------------------------------------------
// + failErasureReg4
//-
//------------------------------------------------------------------
reg failErasureReg4;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failErasureReg4 <= 1'b0;
end
else if ((enable == 1'b1) && (doneShiftReg == 1'b1)) begin
failErasureReg4 <= failErasureReg3;
end
end
 
 
 
//------------------------------------------------------------------
// + failErasureReg5
//-
//------------------------------------------------------------------
reg failErasureReg5;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failErasureReg5 <= 1'b0;
end
else if ((enable == 1'b1) && (startReg[1] == 1'b1)) begin
failErasureReg5 <= failErasureReg4;
end
end
 
 
 
//------------------------------------------------------------------
// + failReg
//------------------------------------------------------------------
reg failReg;
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
failReg <= 1'b0;
end
else if ((enable == 1'b1) && (doneReg[0] == 1'b1)) begin
if ((numErrorLambdaReg == numErrorChien) && (degreeErrorReg == 1'b0) && (failErasureReg5 == 1'b0)) begin
failReg <= 1'b0;
end
else begin
failReg <= 1'b1;
end
end
end
 
 
 
//------------------------------------------------------------------
// + DataOutInner
//------------------------------------------------------------------
reg [7:0] DataOutInner;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
DataOutInner <= 8'd0;
end
else begin
DataOutInner <= delayedDataIn ^ error;
end
end
 
 
 
//------------------------------------------------------------------
// + DelayedDataOutInner
//------------------------------------------------------------------
reg [7:0] DelayedDataOutInner;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
DelayedDataOutInner <= 8'd0;
end
else begin
DelayedDataOutInner <= delayedDataIn;
end
end
 
 
 
//------------------------------------------------------------------
// - enableFF
//------------------------------------------------------------------
reg enableFF;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
enableFF <= 1'b0;
end
else begin
enableFF <= enable;
end
end
 
 
 
//------------------------------------------------------------------
// - FF for Outputs
//------------------------------------------------------------------
reg startRegInner;
reg doneRegInner;
reg [7:0] numErrorRegInner;
reg [7:0] numErasureRegInner;
reg failRegInner;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
startRegInner <= 1'b0;
doneRegInner <= 1'b0;
numErrorRegInner <= 8'd0;
numErasureRegInner <= 8'd0;
failRegInner <= 1'b0;
end
else begin
startRegInner <= startReg[0];
doneRegInner <= doneReg[0];
numErrorRegInner <= { 3'd0, numErrorReg[4:0]};
numErasureRegInner <= { 3'd0, numErasureReg[4:0]};
failRegInner <= failReg;
end
end
 
 
 
//------------------------------------------------------------------
// - OutputValidRegInner
//------------------------------------------------------------------
reg OutputValidRegInner;
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
OutputValidRegInner <= 1'b0;
end
else if (enableFF == 1'b1) begin
OutputValidRegInner <= OutputValidReg;
end
else begin
OutputValidRegInner <= 1'b0;
end
end
 
 
 
//------------------------------------------------------------------
// - Output Ports
//------------------------------------------------------------------
assign outEnable = OutputValidRegInner;
assign outStartPls = startRegInner;
assign outDone = doneRegInner;
assign outData = DataOutInner;
assign errorNum = numErrorRegInner;
assign erasureNum = numErasureRegInner;
assign delayedData = DelayedDataOutInner;
assign fail = failRegInner;
 
 
endmodule
/trunk/example/rtl/RsDecodeDpRam.v
0,0 → 1,84
//===================================================================
// Module Name : RsDecodeDpRam
// File Name : RsDecodeDpRam.v
// Function : Rs Decoder DpRam Memory Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeDpRam (/*AUTOARG*/
// Outputs
q,
// Inputs
clock,
data,
rdaddress,
rden,
wraddress,
wren
);
 
output [8:0] q;
input clock;
input [8:0] data;
input [8:0] rdaddress;
input [8:0] wraddress;
input rden;
input wren;
 
 
 
//------------------------------------------------------------------
// + mem
// - DpRam Memory
//------------------------------------------------------------------
reg [8:0] mem[0:351];
always@(posedge clock) begin
if (wren)
mem[wraddress] <= data;
end
 
 
 
//------------------------------------------------------------------
// + rRdAddr
// - Read Address register
//------------------------------------------------------------------
reg [8:0] rRdAddr;
always@(posedge clock) begin
rRdAddr <= rdaddress;
end
 
 
 
//------------------------------------------------------------------
// + rRdEn
 
//------------------------------------------------------------------
reg rRdEn;
always@(posedge clock) begin
rRdEn <= rden;
end
 
 
 
//------------------------------------------------------------------
// + q
 
//------------------------------------------------------------------
reg [8:0] q;
always@(posedge clock) begin
if (rRdEn)
q <= mem[rRdAddr];
end
 
 
 
endmodule
/trunk/example/rtl/RsDecodeErasure.v
0,0 → 1,430
//===================================================================
// Module Name : RsDecodeErasure
// File Name : RsDecodeErasure.v
// Function : Rs Decoder Erasure polynomial calculation Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeErasure(
CLK, // system clock
RESET, // system reset
enable, // enable signal
sync, // sync signal
erasureIn, // erasure input
epsilon_0, // epsilon polynom 0
epsilon_1, // epsilon polynom 1
epsilon_2, // epsilon polynom 2
epsilon_3, // epsilon polynom 3
epsilon_4, // epsilon polynom 4
epsilon_5, // epsilon polynom 5
epsilon_6, // epsilon polynom 6
epsilon_7, // epsilon polynom 7
epsilon_8, // epsilon polynom 8
epsilon_9, // epsilon polynom 9
epsilon_10, // epsilon polynom 10
epsilon_11, // epsilon polynom 11
epsilon_12, // epsilon polynom 12
epsilon_13, // epsilon polynom 13
epsilon_14, // epsilon polynom 14
epsilon_15, // epsilon polynom 15
epsilon_16, // epsilon polynom 16
epsilon_17, // epsilon polynom 17
epsilon_18, // epsilon polynom 18
epsilon_19, // epsilon polynom 19
epsilon_20, // epsilon polynom 20
epsilon_21, // epsilon polynom 21
epsilon_22, // epsilon polynom 22
numErasure, // erasure amount
fail, // decoder failure signal
done // done signal
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input sync; // sync signal
input erasureIn; // erasure input
output [7:0] epsilon_0; // syndrome polynom 0
output [7:0] epsilon_1; // syndrome polynom 1
output [7:0] epsilon_2; // syndrome polynom 2
output [7:0] epsilon_3; // syndrome polynom 3
output [7:0] epsilon_4; // syndrome polynom 4
output [7:0] epsilon_5; // syndrome polynom 5
output [7:0] epsilon_6; // syndrome polynom 6
output [7:0] epsilon_7; // syndrome polynom 7
output [7:0] epsilon_8; // syndrome polynom 8
output [7:0] epsilon_9; // syndrome polynom 9
output [7:0] epsilon_10; // syndrome polynom 10
output [7:0] epsilon_11; // syndrome polynom 11
output [7:0] epsilon_12; // syndrome polynom 12
output [7:0] epsilon_13; // syndrome polynom 13
output [7:0] epsilon_14; // syndrome polynom 14
output [7:0] epsilon_15; // syndrome polynom 15
output [7:0] epsilon_16; // syndrome polynom 16
output [7:0] epsilon_17; // syndrome polynom 17
output [7:0] epsilon_18; // syndrome polynom 18
output [7:0] epsilon_19; // syndrome polynom 19
output [7:0] epsilon_20; // syndrome polynom 20
output [7:0] epsilon_21; // syndrome polynom 21
output [7:0] epsilon_22; // syndrome polynom 22
output [4:0] numErasure; // erasure amount
output fail; // decoder failure signal
output done; // done signal
//------------------------------------------------------------------
// - parameters
//------------------------------------------------------------------
parameter erasureInitialPower = 8'd2;
 
 
 
//------------------------------------------------------------------------
// + count
//- Counter
//------------------------------------------------------------------------
reg [7:0] count;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
count[7:0] <= 8'd1;
end
else if ( (count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
count[7:0] <= 8'd0;
end
else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
 
 
 
//------------------------------------------------------------------------
// + done
//------------------------------------------------------------------------
reg done;
always @(count) begin
if (count ==8'd255) begin
done = 1'b1;
end
else begin
done = 1'b0;
end
end
 
 
//------------------------------------------------------------------------
// + erasureCount
//- Erasure Counter
//------------------------------------------------------------------------
reg [7:0] erasureCount;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
erasureCount [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
if (erasureIn == 1'b1) begin
erasureCount [7:0] <= 8'd1;
end
else begin
erasureCount [7:0] <= 8'd0;
end
end
else if (erasureIn == 1'b1) begin
erasureCount [7:0] <= erasureCount [7:0] + 8'd1;
end
end
end
 
 
//------------------------------------------------------------------------
// + fail
//- If Erasure amount > 22 -> fail is ON
//------------------------------------------------------------------------
reg fail;
always @(erasureCount) begin
if (erasureCount [7:0]> 8'd22) begin
fail = 1'b1;
end
else begin
fail = 1'b0;
end
end
 
 
//------------------------------------------------------------------------
// Erasure Polynominal Generator
//------------------------------------------------------------------------
reg [7:0] powerReg;
wire [7:0] powerNew;
wire [7:0] powerInitialNew;
 
assign powerInitialNew [0] = erasureInitialPower[7];
assign powerInitialNew [1] = erasureInitialPower[0];
assign powerInitialNew [2] = erasureInitialPower[1] ^ erasureInitialPower[7];
assign powerInitialNew [3] = erasureInitialPower[2] ^ erasureInitialPower[7];
assign powerInitialNew [4] = erasureInitialPower[3] ^ erasureInitialPower[7];
assign powerInitialNew [5] = erasureInitialPower[4];
assign powerInitialNew [6] = erasureInitialPower[5];
assign powerInitialNew [7] = erasureInitialPower[6];
assign powerNew [0] = powerReg[7];
assign powerNew [1] = powerReg[0];
assign powerNew [2] = powerReg[1] ^ powerReg[7];
assign powerNew [3] = powerReg[2] ^ powerReg[7];
assign powerNew [4] = powerReg[3] ^ powerReg[7];
assign powerNew [5] = powerReg[4];
assign powerNew [6] = powerReg[5];
assign powerNew [7] = powerReg[6];
 
 
//------------------------------------------------------------------
// + powerReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
powerReg [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
powerReg[7:0] <= powerInitialNew[7:0];
end
else begin
powerReg[7:0] <= powerNew[7:0];
end
end
end
 
 
//------------------------------------------------------------------------
// + product_0,..., product_22
//- Erasure Polynominal Generator
//------------------------------------------------------------------------
wire [7:0] product_0;
wire [7:0] product_1;
wire [7:0] product_2;
wire [7:0] product_3;
wire [7:0] product_4;
wire [7:0] product_5;
wire [7:0] product_6;
wire [7:0] product_7;
wire [7:0] product_8;
wire [7:0] product_9;
wire [7:0] product_10;
wire [7:0] product_11;
wire [7:0] product_12;
wire [7:0] product_13;
wire [7:0] product_14;
wire [7:0] product_15;
wire [7:0] product_16;
wire [7:0] product_17;
wire [7:0] product_18;
wire [7:0] product_19;
wire [7:0] product_20;
wire [7:0] product_21;
wire [7:0] product_22;
 
reg [7:0] epsilonReg_0;
reg [7:0] epsilonReg_1;
reg [7:0] epsilonReg_2;
reg [7:0] epsilonReg_3;
reg [7:0] epsilonReg_4;
reg [7:0] epsilonReg_5;
reg [7:0] epsilonReg_6;
reg [7:0] epsilonReg_7;
reg [7:0] epsilonReg_8;
reg [7:0] epsilonReg_9;
reg [7:0] epsilonReg_10;
reg [7:0] epsilonReg_11;
reg [7:0] epsilonReg_12;
reg [7:0] epsilonReg_13;
reg [7:0] epsilonReg_14;
reg [7:0] epsilonReg_15;
reg [7:0] epsilonReg_16;
reg [7:0] epsilonReg_17;
reg [7:0] epsilonReg_18;
reg [7:0] epsilonReg_19;
reg [7:0] epsilonReg_20;
reg [7:0] epsilonReg_21;
reg [7:0] epsilonReg_22;
 
 
RsDecodeMult RsDecodeMult_0 (.A(powerReg[7:0]), .B(epsilonReg_0[7:0]), .P(product_0[7:0]));
RsDecodeMult RsDecodeMult_1 (.A(powerReg[7:0]), .B(epsilonReg_1[7:0]), .P(product_1[7:0]));
RsDecodeMult RsDecodeMult_2 (.A(powerReg[7:0]), .B(epsilonReg_2[7:0]), .P(product_2[7:0]));
RsDecodeMult RsDecodeMult_3 (.A(powerReg[7:0]), .B(epsilonReg_3[7:0]), .P(product_3[7:0]));
RsDecodeMult RsDecodeMult_4 (.A(powerReg[7:0]), .B(epsilonReg_4[7:0]), .P(product_4[7:0]));
RsDecodeMult RsDecodeMult_5 (.A(powerReg[7:0]), .B(epsilonReg_5[7:0]), .P(product_5[7:0]));
RsDecodeMult RsDecodeMult_6 (.A(powerReg[7:0]), .B(epsilonReg_6[7:0]), .P(product_6[7:0]));
RsDecodeMult RsDecodeMult_7 (.A(powerReg[7:0]), .B(epsilonReg_7[7:0]), .P(product_7[7:0]));
RsDecodeMult RsDecodeMult_8 (.A(powerReg[7:0]), .B(epsilonReg_8[7:0]), .P(product_8[7:0]));
RsDecodeMult RsDecodeMult_9 (.A(powerReg[7:0]), .B(epsilonReg_9[7:0]), .P(product_9[7:0]));
RsDecodeMult RsDecodeMult_10 (.A(powerReg[7:0]), .B(epsilonReg_10[7:0]), .P(product_10[7:0]));
RsDecodeMult RsDecodeMult_11 (.A(powerReg[7:0]), .B(epsilonReg_11[7:0]), .P(product_11[7:0]));
RsDecodeMult RsDecodeMult_12 (.A(powerReg[7:0]), .B(epsilonReg_12[7:0]), .P(product_12[7:0]));
RsDecodeMult RsDecodeMult_13 (.A(powerReg[7:0]), .B(epsilonReg_13[7:0]), .P(product_13[7:0]));
RsDecodeMult RsDecodeMult_14 (.A(powerReg[7:0]), .B(epsilonReg_14[7:0]), .P(product_14[7:0]));
RsDecodeMult RsDecodeMult_15 (.A(powerReg[7:0]), .B(epsilonReg_15[7:0]), .P(product_15[7:0]));
RsDecodeMult RsDecodeMult_16 (.A(powerReg[7:0]), .B(epsilonReg_16[7:0]), .P(product_16[7:0]));
RsDecodeMult RsDecodeMult_17 (.A(powerReg[7:0]), .B(epsilonReg_17[7:0]), .P(product_17[7:0]));
RsDecodeMult RsDecodeMult_18 (.A(powerReg[7:0]), .B(epsilonReg_18[7:0]), .P(product_18[7:0]));
RsDecodeMult RsDecodeMult_19 (.A(powerReg[7:0]), .B(epsilonReg_19[7:0]), .P(product_19[7:0]));
RsDecodeMult RsDecodeMult_20 (.A(powerReg[7:0]), .B(epsilonReg_20[7:0]), .P(product_20[7:0]));
RsDecodeMult RsDecodeMult_21 (.A(powerReg[7:0]), .B(epsilonReg_21[7:0]), .P(product_21[7:0]));
RsDecodeMult RsDecodeMult_22 (.A(powerReg[7:0]), .B(epsilonReg_22[7:0]), .P(product_22[7:0]));
 
 
 
//------------------------------------------------------------------------
// + epsilonReg_0,..., epsilonReg_21
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= 8'd0;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
if (erasureIn == 1'b1) begin
epsilonReg_0 [7:0] <= erasureInitialPower[7:0];
epsilonReg_1 [7:0] <= 8'd1;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
else begin
epsilonReg_0 [7:0] <= 8'd1;
epsilonReg_1 [7:0] <= 8'd0;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
end
else if (erasureIn == 1'b1) begin
epsilonReg_0 [7:0] <= product_0[7:0];
epsilonReg_1 [7:0] <= epsilonReg_0 [7:0] ^ product_1[7:0];
epsilonReg_2 [7:0] <= epsilonReg_1 [7:0] ^ product_2[7:0];
epsilonReg_3 [7:0] <= epsilonReg_2 [7:0] ^ product_3[7:0];
epsilonReg_4 [7:0] <= epsilonReg_3 [7:0] ^ product_4[7:0];
epsilonReg_5 [7:0] <= epsilonReg_4 [7:0] ^ product_5[7:0];
epsilonReg_6 [7:0] <= epsilonReg_5 [7:0] ^ product_6[7:0];
epsilonReg_7 [7:0] <= epsilonReg_6 [7:0] ^ product_7[7:0];
epsilonReg_8 [7:0] <= epsilonReg_7 [7:0] ^ product_8[7:0];
epsilonReg_9 [7:0] <= epsilonReg_8 [7:0] ^ product_9[7:0];
epsilonReg_10 [7:0] <= epsilonReg_9 [7:0] ^ product_10[7:0];
epsilonReg_11 [7:0] <= epsilonReg_10 [7:0] ^ product_11[7:0];
epsilonReg_12 [7:0] <= epsilonReg_11 [7:0] ^ product_12[7:0];
epsilonReg_13 [7:0] <= epsilonReg_12 [7:0] ^ product_13[7:0];
epsilonReg_14 [7:0] <= epsilonReg_13 [7:0] ^ product_14[7:0];
epsilonReg_15 [7:0] <= epsilonReg_14 [7:0] ^ product_15[7:0];
epsilonReg_16 [7:0] <= epsilonReg_15 [7:0] ^ product_16[7:0];
epsilonReg_17 [7:0] <= epsilonReg_16 [7:0] ^ product_17[7:0];
epsilonReg_18 [7:0] <= epsilonReg_17 [7:0] ^ product_18[7:0];
epsilonReg_19 [7:0] <= epsilonReg_18 [7:0] ^ product_19[7:0];
epsilonReg_20 [7:0] <= epsilonReg_19 [7:0] ^ product_20[7:0];
epsilonReg_21 [7:0] <= epsilonReg_20 [7:0] ^ product_21[7:0];
epsilonReg_22 [7:0] <= epsilonReg_21 [7:0] ^ product_22[7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
//- Output Ports
//------------------------------------------------------------------------
assign epsilon_0 [7:0] = epsilonReg_0[7:0];
assign epsilon_1 [7:0] = epsilonReg_1[7:0];
assign epsilon_2 [7:0] = epsilonReg_2[7:0];
assign epsilon_3 [7:0] = epsilonReg_3[7:0];
assign epsilon_4 [7:0] = epsilonReg_4[7:0];
assign epsilon_5 [7:0] = epsilonReg_5[7:0];
assign epsilon_6 [7:0] = epsilonReg_6[7:0];
assign epsilon_7 [7:0] = epsilonReg_7[7:0];
assign epsilon_8 [7:0] = epsilonReg_8[7:0];
assign epsilon_9 [7:0] = epsilonReg_9[7:0];
assign epsilon_10 [7:0] = epsilonReg_10[7:0];
assign epsilon_11 [7:0] = epsilonReg_11[7:0];
assign epsilon_12 [7:0] = epsilonReg_12[7:0];
assign epsilon_13 [7:0] = epsilonReg_13[7:0];
assign epsilon_14 [7:0] = epsilonReg_14[7:0];
assign epsilon_15 [7:0] = epsilonReg_15[7:0];
assign epsilon_16 [7:0] = epsilonReg_16[7:0];
assign epsilon_17 [7:0] = epsilonReg_17[7:0];
assign epsilon_18 [7:0] = epsilonReg_18[7:0];
assign epsilon_19 [7:0] = epsilonReg_19[7:0];
assign epsilon_20 [7:0] = epsilonReg_20[7:0];
assign epsilon_21 [7:0] = epsilonReg_21[7:0];
assign epsilon_22 [7:0] = epsilonReg_22[7:0];
 
assign numErasure = erasureCount[4:0];
 
endmodule
/trunk/example/rtl/RsDecodeShiftOmega.v
0,0 → 1,729
//===================================================================
// Module Name : RsDecodeShiftOmega
// File Name : RsDecodeShiftOmega.v
// Function : Rs Decoder Shift Omega Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeShiftOmega(
omega_0, // omega polynom 0
omega_1, // omega polynom 1
omega_2, // omega polynom 2
omega_3, // omega polynom 3
omega_4, // omega polynom 4
omega_5, // omega polynom 5
omega_6, // omega polynom 6
omega_7, // omega polynom 7
omega_8, // omega polynom 8
omega_9, // omega polynom 9
omega_10, // omega polynom 10
omega_11, // omega polynom 11
omega_12, // omega polynom 12
omega_13, // omega polynom 13
omega_14, // omega polynom 14
omega_15, // omega polynom 15
omega_16, // omega polynom 16
omega_17, // omega polynom 17
omega_18, // omega polynom 18
omega_19, // omega polynom 19
omega_20, // omega polynom 20
omega_21, // omega polynom 21
omegaShifted_0, // omega shifted polynom 0
omegaShifted_1, // omega shifted polynom 1
omegaShifted_2, // omega shifted polynom 2
omegaShifted_3, // omega shifted polynom 3
omegaShifted_4, // omega shifted polynom 4
omegaShifted_5, // omega shifted polynom 5
omegaShifted_6, // omega shifted polynom 6
omegaShifted_7, // omega shifted polynom 7
omegaShifted_8, // omega shifted polynom 8
omegaShifted_9, // omega shifted polynom 9
omegaShifted_10, // omega shifted polynom 10
omegaShifted_11, // omega shifted polynom 11
omegaShifted_12, // omega shifted polynom 12
omegaShifted_13, // omega shifted polynom 13
omegaShifted_14, // omega shifted polynom 14
omegaShifted_15, // omega shifted polynom 15
omegaShifted_16, // omega shifted polynom 16
omegaShifted_17, // omega shifted polynom 17
omegaShifted_18, // omega shifted polynom 18
omegaShifted_19, // omega shifted polynom 19
omegaShifted_20, // omega shifted polynom 20
omegaShifted_21, // omega shifted polynom 21
numShifted // shift amount
);
 
 
input [7:0] omega_0; // omega polynom 0
input [7:0] omega_1; // omega polynom 1
input [7:0] omega_2; // omega polynom 2
input [7:0] omega_3; // omega polynom 3
input [7:0] omega_4; // omega polynom 4
input [7:0] omega_5; // omega polynom 5
input [7:0] omega_6; // omega polynom 6
input [7:0] omega_7; // omega polynom 7
input [7:0] omega_8; // omega polynom 8
input [7:0] omega_9; // omega polynom 9
input [7:0] omega_10; // omega polynom 10
input [7:0] omega_11; // omega polynom 11
input [7:0] omega_12; // omega polynom 12
input [7:0] omega_13; // omega polynom 13
input [7:0] omega_14; // omega polynom 14
input [7:0] omega_15; // omega polynom 15
input [7:0] omega_16; // omega polynom 16
input [7:0] omega_17; // omega polynom 17
input [7:0] omega_18; // omega polynom 18
input [7:0] omega_19; // omega polynom 19
input [7:0] omega_20; // omega polynom 20
input [7:0] omega_21; // omega polynom 21
input [4:0] numShifted; // shift amount
 
output [7:0] omegaShifted_0; // omega shifted polynom 0
output [7:0] omegaShifted_1; // omega shifted polynom 1
output [7:0] omegaShifted_2; // omega shifted polynom 2
output [7:0] omegaShifted_3; // omega shifted polynom 3
output [7:0] omegaShifted_4; // omega shifted polynom 4
output [7:0] omegaShifted_5; // omega shifted polynom 5
output [7:0] omegaShifted_6; // omega shifted polynom 6
output [7:0] omegaShifted_7; // omega shifted polynom 7
output [7:0] omegaShifted_8; // omega shifted polynom 8
output [7:0] omegaShifted_9; // omega shifted polynom 9
output [7:0] omegaShifted_10; // omega shifted polynom 10
output [7:0] omegaShifted_11; // omega shifted polynom 11
output [7:0] omegaShifted_12; // omega shifted polynom 12
output [7:0] omegaShifted_13; // omega shifted polynom 13
output [7:0] omegaShifted_14; // omega shifted polynom 14
output [7:0] omegaShifted_15; // omega shifted polynom 15
output [7:0] omegaShifted_16; // omega shifted polynom 16
output [7:0] omegaShifted_17; // omega shifted polynom 17
output [7:0] omegaShifted_18; // omega shifted polynom 18
output [7:0] omegaShifted_19; // omega shifted polynom 19
output [7:0] omegaShifted_20; // omega shifted polynom 20
output [7:0] omegaShifted_21; // omega shifted polynom 21
 
 
 
//------------------------------------------------------------------------
//+ omegaShifted_0,..., omegaShifted_21
//- omegaShifted registers
//------------------------------------------------------------------------
reg [7:0] omegaShiftedInner_0;
reg [7:0] omegaShiftedInner_1;
reg [7:0] omegaShiftedInner_2;
reg [7:0] omegaShiftedInner_3;
reg [7:0] omegaShiftedInner_4;
reg [7:0] omegaShiftedInner_5;
reg [7:0] omegaShiftedInner_6;
reg [7:0] omegaShiftedInner_7;
reg [7:0] omegaShiftedInner_8;
reg [7:0] omegaShiftedInner_9;
reg [7:0] omegaShiftedInner_10;
reg [7:0] omegaShiftedInner_11;
reg [7:0] omegaShiftedInner_12;
reg [7:0] omegaShiftedInner_13;
reg [7:0] omegaShiftedInner_14;
reg [7:0] omegaShiftedInner_15;
reg [7:0] omegaShiftedInner_16;
reg [7:0] omegaShiftedInner_17;
reg [7:0] omegaShiftedInner_18;
reg [7:0] omegaShiftedInner_19;
reg [7:0] omegaShiftedInner_20;
reg [7:0] omegaShiftedInner_21;
 
 
always @ (numShifted or omega_0 or omega_1 or omega_2 or omega_3 or omega_4 or omega_5 or omega_6 or omega_7 or omega_8 or omega_9 or omega_10 or omega_11 or omega_12 or omega_13 or omega_14 or omega_15 or omega_16 or omega_17 or omega_18 or omega_19 or omega_20 or omega_21 ) begin
case (numShifted)
(5'd0): begin
omegaShiftedInner_0 [7:0] = omega_0 [7:0];
omegaShiftedInner_1 [7:0] = omega_1 [7:0];
omegaShiftedInner_2 [7:0] = omega_2 [7:0];
omegaShiftedInner_3 [7:0] = omega_3 [7:0];
omegaShiftedInner_4 [7:0] = omega_4 [7:0];
omegaShiftedInner_5 [7:0] = omega_5 [7:0];
omegaShiftedInner_6 [7:0] = omega_6 [7:0];
omegaShiftedInner_7 [7:0] = omega_7 [7:0];
omegaShiftedInner_8 [7:0] = omega_8 [7:0];
omegaShiftedInner_9 [7:0] = omega_9 [7:0];
omegaShiftedInner_10 [7:0] = omega_10 [7:0];
omegaShiftedInner_11 [7:0] = omega_11 [7:0];
omegaShiftedInner_12 [7:0] = omega_12 [7:0];
omegaShiftedInner_13 [7:0] = omega_13 [7:0];
omegaShiftedInner_14 [7:0] = omega_14 [7:0];
omegaShiftedInner_15 [7:0] = omega_15 [7:0];
omegaShiftedInner_16 [7:0] = omega_16 [7:0];
omegaShiftedInner_17 [7:0] = omega_17 [7:0];
omegaShiftedInner_18 [7:0] = omega_18 [7:0];
omegaShiftedInner_19 [7:0] = omega_19 [7:0];
omegaShiftedInner_20 [7:0] = omega_20 [7:0];
omegaShiftedInner_21 [7:0] = omega_21 [7:0];
end
(5'd1): begin
omegaShiftedInner_0 [7:0] = omega_1 [7:0];
omegaShiftedInner_1 [7:0] = omega_2 [7:0];
omegaShiftedInner_2 [7:0] = omega_3 [7:0];
omegaShiftedInner_3 [7:0] = omega_4 [7:0];
omegaShiftedInner_4 [7:0] = omega_5 [7:0];
omegaShiftedInner_5 [7:0] = omega_6 [7:0];
omegaShiftedInner_6 [7:0] = omega_7 [7:0];
omegaShiftedInner_7 [7:0] = omega_8 [7:0];
omegaShiftedInner_8 [7:0] = omega_9 [7:0];
omegaShiftedInner_9 [7:0] = omega_10 [7:0];
omegaShiftedInner_10 [7:0] = omega_11 [7:0];
omegaShiftedInner_11 [7:0] = omega_12 [7:0];
omegaShiftedInner_12 [7:0] = omega_13 [7:0];
omegaShiftedInner_13 [7:0] = omega_14 [7:0];
omegaShiftedInner_14 [7:0] = omega_15 [7:0];
omegaShiftedInner_15 [7:0] = omega_16 [7:0];
omegaShiftedInner_16 [7:0] = omega_17 [7:0];
omegaShiftedInner_17 [7:0] = omega_18 [7:0];
omegaShiftedInner_18 [7:0] = omega_19 [7:0];
omegaShiftedInner_19 [7:0] = omega_20 [7:0];
omegaShiftedInner_20 [7:0] = omega_21 [7:0];
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd2): begin
omegaShiftedInner_0 [7:0] = omega_2 [7:0];
omegaShiftedInner_1 [7:0] = omega_3 [7:0];
omegaShiftedInner_2 [7:0] = omega_4 [7:0];
omegaShiftedInner_3 [7:0] = omega_5 [7:0];
omegaShiftedInner_4 [7:0] = omega_6 [7:0];
omegaShiftedInner_5 [7:0] = omega_7 [7:0];
omegaShiftedInner_6 [7:0] = omega_8 [7:0];
omegaShiftedInner_7 [7:0] = omega_9 [7:0];
omegaShiftedInner_8 [7:0] = omega_10 [7:0];
omegaShiftedInner_9 [7:0] = omega_11 [7:0];
omegaShiftedInner_10 [7:0] = omega_12 [7:0];
omegaShiftedInner_11 [7:0] = omega_13 [7:0];
omegaShiftedInner_12 [7:0] = omega_14 [7:0];
omegaShiftedInner_13 [7:0] = omega_15 [7:0];
omegaShiftedInner_14 [7:0] = omega_16 [7:0];
omegaShiftedInner_15 [7:0] = omega_17 [7:0];
omegaShiftedInner_16 [7:0] = omega_18 [7:0];
omegaShiftedInner_17 [7:0] = omega_19 [7:0];
omegaShiftedInner_18 [7:0] = omega_20 [7:0];
omegaShiftedInner_19 [7:0] = omega_21 [7:0];
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd3): begin
omegaShiftedInner_0 [7:0] = omega_3 [7:0];
omegaShiftedInner_1 [7:0] = omega_4 [7:0];
omegaShiftedInner_2 [7:0] = omega_5 [7:0];
omegaShiftedInner_3 [7:0] = omega_6 [7:0];
omegaShiftedInner_4 [7:0] = omega_7 [7:0];
omegaShiftedInner_5 [7:0] = omega_8 [7:0];
omegaShiftedInner_6 [7:0] = omega_9 [7:0];
omegaShiftedInner_7 [7:0] = omega_10 [7:0];
omegaShiftedInner_8 [7:0] = omega_11 [7:0];
omegaShiftedInner_9 [7:0] = omega_12 [7:0];
omegaShiftedInner_10 [7:0] = omega_13 [7:0];
omegaShiftedInner_11 [7:0] = omega_14 [7:0];
omegaShiftedInner_12 [7:0] = omega_15 [7:0];
omegaShiftedInner_13 [7:0] = omega_16 [7:0];
omegaShiftedInner_14 [7:0] = omega_17 [7:0];
omegaShiftedInner_15 [7:0] = omega_18 [7:0];
omegaShiftedInner_16 [7:0] = omega_19 [7:0];
omegaShiftedInner_17 [7:0] = omega_20 [7:0];
omegaShiftedInner_18 [7:0] = omega_21 [7:0];
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd4): begin
omegaShiftedInner_0 [7:0] = omega_4 [7:0];
omegaShiftedInner_1 [7:0] = omega_5 [7:0];
omegaShiftedInner_2 [7:0] = omega_6 [7:0];
omegaShiftedInner_3 [7:0] = omega_7 [7:0];
omegaShiftedInner_4 [7:0] = omega_8 [7:0];
omegaShiftedInner_5 [7:0] = omega_9 [7:0];
omegaShiftedInner_6 [7:0] = omega_10 [7:0];
omegaShiftedInner_7 [7:0] = omega_11 [7:0];
omegaShiftedInner_8 [7:0] = omega_12 [7:0];
omegaShiftedInner_9 [7:0] = omega_13 [7:0];
omegaShiftedInner_10 [7:0] = omega_14 [7:0];
omegaShiftedInner_11 [7:0] = omega_15 [7:0];
omegaShiftedInner_12 [7:0] = omega_16 [7:0];
omegaShiftedInner_13 [7:0] = omega_17 [7:0];
omegaShiftedInner_14 [7:0] = omega_18 [7:0];
omegaShiftedInner_15 [7:0] = omega_19 [7:0];
omegaShiftedInner_16 [7:0] = omega_20 [7:0];
omegaShiftedInner_17 [7:0] = omega_21 [7:0];
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd5): begin
omegaShiftedInner_0 [7:0] = omega_5 [7:0];
omegaShiftedInner_1 [7:0] = omega_6 [7:0];
omegaShiftedInner_2 [7:0] = omega_7 [7:0];
omegaShiftedInner_3 [7:0] = omega_8 [7:0];
omegaShiftedInner_4 [7:0] = omega_9 [7:0];
omegaShiftedInner_5 [7:0] = omega_10 [7:0];
omegaShiftedInner_6 [7:0] = omega_11 [7:0];
omegaShiftedInner_7 [7:0] = omega_12 [7:0];
omegaShiftedInner_8 [7:0] = omega_13 [7:0];
omegaShiftedInner_9 [7:0] = omega_14 [7:0];
omegaShiftedInner_10 [7:0] = omega_15 [7:0];
omegaShiftedInner_11 [7:0] = omega_16 [7:0];
omegaShiftedInner_12 [7:0] = omega_17 [7:0];
omegaShiftedInner_13 [7:0] = omega_18 [7:0];
omegaShiftedInner_14 [7:0] = omega_19 [7:0];
omegaShiftedInner_15 [7:0] = omega_20 [7:0];
omegaShiftedInner_16 [7:0] = omega_21 [7:0];
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd6): begin
omegaShiftedInner_0 [7:0] = omega_6 [7:0];
omegaShiftedInner_1 [7:0] = omega_7 [7:0];
omegaShiftedInner_2 [7:0] = omega_8 [7:0];
omegaShiftedInner_3 [7:0] = omega_9 [7:0];
omegaShiftedInner_4 [7:0] = omega_10 [7:0];
omegaShiftedInner_5 [7:0] = omega_11 [7:0];
omegaShiftedInner_6 [7:0] = omega_12 [7:0];
omegaShiftedInner_7 [7:0] = omega_13 [7:0];
omegaShiftedInner_8 [7:0] = omega_14 [7:0];
omegaShiftedInner_9 [7:0] = omega_15 [7:0];
omegaShiftedInner_10 [7:0] = omega_16 [7:0];
omegaShiftedInner_11 [7:0] = omega_17 [7:0];
omegaShiftedInner_12 [7:0] = omega_18 [7:0];
omegaShiftedInner_13 [7:0] = omega_19 [7:0];
omegaShiftedInner_14 [7:0] = omega_20 [7:0];
omegaShiftedInner_15 [7:0] = omega_21 [7:0];
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd7): begin
omegaShiftedInner_0 [7:0] = omega_7 [7:0];
omegaShiftedInner_1 [7:0] = omega_8 [7:0];
omegaShiftedInner_2 [7:0] = omega_9 [7:0];
omegaShiftedInner_3 [7:0] = omega_10 [7:0];
omegaShiftedInner_4 [7:0] = omega_11 [7:0];
omegaShiftedInner_5 [7:0] = omega_12 [7:0];
omegaShiftedInner_6 [7:0] = omega_13 [7:0];
omegaShiftedInner_7 [7:0] = omega_14 [7:0];
omegaShiftedInner_8 [7:0] = omega_15 [7:0];
omegaShiftedInner_9 [7:0] = omega_16 [7:0];
omegaShiftedInner_10 [7:0] = omega_17 [7:0];
omegaShiftedInner_11 [7:0] = omega_18 [7:0];
omegaShiftedInner_12 [7:0] = omega_19 [7:0];
omegaShiftedInner_13 [7:0] = omega_20 [7:0];
omegaShiftedInner_14 [7:0] = omega_21 [7:0];
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd8): begin
omegaShiftedInner_0 [7:0] = omega_8 [7:0];
omegaShiftedInner_1 [7:0] = omega_9 [7:0];
omegaShiftedInner_2 [7:0] = omega_10 [7:0];
omegaShiftedInner_3 [7:0] = omega_11 [7:0];
omegaShiftedInner_4 [7:0] = omega_12 [7:0];
omegaShiftedInner_5 [7:0] = omega_13 [7:0];
omegaShiftedInner_6 [7:0] = omega_14 [7:0];
omegaShiftedInner_7 [7:0] = omega_15 [7:0];
omegaShiftedInner_8 [7:0] = omega_16 [7:0];
omegaShiftedInner_9 [7:0] = omega_17 [7:0];
omegaShiftedInner_10 [7:0] = omega_18 [7:0];
omegaShiftedInner_11 [7:0] = omega_19 [7:0];
omegaShiftedInner_12 [7:0] = omega_20 [7:0];
omegaShiftedInner_13 [7:0] = omega_21 [7:0];
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd9): begin
omegaShiftedInner_0 [7:0] = omega_9 [7:0];
omegaShiftedInner_1 [7:0] = omega_10 [7:0];
omegaShiftedInner_2 [7:0] = omega_11 [7:0];
omegaShiftedInner_3 [7:0] = omega_12 [7:0];
omegaShiftedInner_4 [7:0] = omega_13 [7:0];
omegaShiftedInner_5 [7:0] = omega_14 [7:0];
omegaShiftedInner_6 [7:0] = omega_15 [7:0];
omegaShiftedInner_7 [7:0] = omega_16 [7:0];
omegaShiftedInner_8 [7:0] = omega_17 [7:0];
omegaShiftedInner_9 [7:0] = omega_18 [7:0];
omegaShiftedInner_10 [7:0] = omega_19 [7:0];
omegaShiftedInner_11 [7:0] = omega_20 [7:0];
omegaShiftedInner_12 [7:0] = omega_21 [7:0];
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd10): begin
omegaShiftedInner_0 [7:0] = omega_10 [7:0];
omegaShiftedInner_1 [7:0] = omega_11 [7:0];
omegaShiftedInner_2 [7:0] = omega_12 [7:0];
omegaShiftedInner_3 [7:0] = omega_13 [7:0];
omegaShiftedInner_4 [7:0] = omega_14 [7:0];
omegaShiftedInner_5 [7:0] = omega_15 [7:0];
omegaShiftedInner_6 [7:0] = omega_16 [7:0];
omegaShiftedInner_7 [7:0] = omega_17 [7:0];
omegaShiftedInner_8 [7:0] = omega_18 [7:0];
omegaShiftedInner_9 [7:0] = omega_19 [7:0];
omegaShiftedInner_10 [7:0] = omega_20 [7:0];
omegaShiftedInner_11 [7:0] = omega_21 [7:0];
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd11): begin
omegaShiftedInner_0 [7:0] = omega_11 [7:0];
omegaShiftedInner_1 [7:0] = omega_12 [7:0];
omegaShiftedInner_2 [7:0] = omega_13 [7:0];
omegaShiftedInner_3 [7:0] = omega_14 [7:0];
omegaShiftedInner_4 [7:0] = omega_15 [7:0];
omegaShiftedInner_5 [7:0] = omega_16 [7:0];
omegaShiftedInner_6 [7:0] = omega_17 [7:0];
omegaShiftedInner_7 [7:0] = omega_18 [7:0];
omegaShiftedInner_8 [7:0] = omega_19 [7:0];
omegaShiftedInner_9 [7:0] = omega_20 [7:0];
omegaShiftedInner_10 [7:0] = omega_21 [7:0];
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd12): begin
omegaShiftedInner_0 [7:0] = omega_12 [7:0];
omegaShiftedInner_1 [7:0] = omega_13 [7:0];
omegaShiftedInner_2 [7:0] = omega_14 [7:0];
omegaShiftedInner_3 [7:0] = omega_15 [7:0];
omegaShiftedInner_4 [7:0] = omega_16 [7:0];
omegaShiftedInner_5 [7:0] = omega_17 [7:0];
omegaShiftedInner_6 [7:0] = omega_18 [7:0];
omegaShiftedInner_7 [7:0] = omega_19 [7:0];
omegaShiftedInner_8 [7:0] = omega_20 [7:0];
omegaShiftedInner_9 [7:0] = omega_21 [7:0];
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd13): begin
omegaShiftedInner_0 [7:0] = omega_13 [7:0];
omegaShiftedInner_1 [7:0] = omega_14 [7:0];
omegaShiftedInner_2 [7:0] = omega_15 [7:0];
omegaShiftedInner_3 [7:0] = omega_16 [7:0];
omegaShiftedInner_4 [7:0] = omega_17 [7:0];
omegaShiftedInner_5 [7:0] = omega_18 [7:0];
omegaShiftedInner_6 [7:0] = omega_19 [7:0];
omegaShiftedInner_7 [7:0] = omega_20 [7:0];
omegaShiftedInner_8 [7:0] = omega_21 [7:0];
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd14): begin
omegaShiftedInner_0 [7:0] = omega_14 [7:0];
omegaShiftedInner_1 [7:0] = omega_15 [7:0];
omegaShiftedInner_2 [7:0] = omega_16 [7:0];
omegaShiftedInner_3 [7:0] = omega_17 [7:0];
omegaShiftedInner_4 [7:0] = omega_18 [7:0];
omegaShiftedInner_5 [7:0] = omega_19 [7:0];
omegaShiftedInner_6 [7:0] = omega_20 [7:0];
omegaShiftedInner_7 [7:0] = omega_21 [7:0];
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd15): begin
omegaShiftedInner_0 [7:0] = omega_15 [7:0];
omegaShiftedInner_1 [7:0] = omega_16 [7:0];
omegaShiftedInner_2 [7:0] = omega_17 [7:0];
omegaShiftedInner_3 [7:0] = omega_18 [7:0];
omegaShiftedInner_4 [7:0] = omega_19 [7:0];
omegaShiftedInner_5 [7:0] = omega_20 [7:0];
omegaShiftedInner_6 [7:0] = omega_21 [7:0];
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd16): begin
omegaShiftedInner_0 [7:0] = omega_16 [7:0];
omegaShiftedInner_1 [7:0] = omega_17 [7:0];
omegaShiftedInner_2 [7:0] = omega_18 [7:0];
omegaShiftedInner_3 [7:0] = omega_19 [7:0];
omegaShiftedInner_4 [7:0] = omega_20 [7:0];
omegaShiftedInner_5 [7:0] = omega_21 [7:0];
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd17): begin
omegaShiftedInner_0 [7:0] = omega_17 [7:0];
omegaShiftedInner_1 [7:0] = omega_18 [7:0];
omegaShiftedInner_2 [7:0] = omega_19 [7:0];
omegaShiftedInner_3 [7:0] = omega_20 [7:0];
omegaShiftedInner_4 [7:0] = omega_21 [7:0];
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd18): begin
omegaShiftedInner_0 [7:0] = omega_18 [7:0];
omegaShiftedInner_1 [7:0] = omega_19 [7:0];
omegaShiftedInner_2 [7:0] = omega_20 [7:0];
omegaShiftedInner_3 [7:0] = omega_21 [7:0];
omegaShiftedInner_4 [7:0] = 8'd0;
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd19): begin
omegaShiftedInner_0 [7:0] = omega_19 [7:0];
omegaShiftedInner_1 [7:0] = omega_20 [7:0];
omegaShiftedInner_2 [7:0] = omega_21 [7:0];
omegaShiftedInner_3 [7:0] = 8'd0;
omegaShiftedInner_4 [7:0] = 8'd0;
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd20): begin
omegaShiftedInner_0 [7:0] = omega_20 [7:0];
omegaShiftedInner_1 [7:0] = omega_21 [7:0];
omegaShiftedInner_2 [7:0] = 8'd0;
omegaShiftedInner_3 [7:0] = 8'd0;
omegaShiftedInner_4 [7:0] = 8'd0;
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
(5'd21): begin
omegaShiftedInner_0 [7:0] = omega_21 [7:0];
omegaShiftedInner_1 [7:0] = 8'd0;
omegaShiftedInner_2 [7:0] = 8'd0;
omegaShiftedInner_3 [7:0] = 8'd0;
omegaShiftedInner_4 [7:0] = 8'd0;
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
default: begin
omegaShiftedInner_0 [7:0] = 8'd0;
omegaShiftedInner_1 [7:0] = 8'd0;
omegaShiftedInner_2 [7:0] = 8'd0;
omegaShiftedInner_3 [7:0] = 8'd0;
omegaShiftedInner_4 [7:0] = 8'd0;
omegaShiftedInner_5 [7:0] = 8'd0;
omegaShiftedInner_6 [7:0] = 8'd0;
omegaShiftedInner_7 [7:0] = 8'd0;
omegaShiftedInner_8 [7:0] = 8'd0;
omegaShiftedInner_9 [7:0] = 8'd0;
omegaShiftedInner_10 [7:0] = 8'd0;
omegaShiftedInner_11 [7:0] = 8'd0;
omegaShiftedInner_12 [7:0] = 8'd0;
omegaShiftedInner_13 [7:0] = 8'd0;
omegaShiftedInner_14 [7:0] = 8'd0;
omegaShiftedInner_15 [7:0] = 8'd0;
omegaShiftedInner_16 [7:0] = 8'd0;
omegaShiftedInner_17 [7:0] = 8'd0;
omegaShiftedInner_18 [7:0] = 8'd0;
omegaShiftedInner_19 [7:0] = 8'd0;
omegaShiftedInner_20 [7:0] = 8'd0;
omegaShiftedInner_21 [7:0] = 8'd0;
end
endcase
end
 
 
 
//------------------------------------------------------------------------
//- Output Ports
//------------------------------------------------------------------------
assign omegaShifted_0 = omegaShiftedInner_0;
assign omegaShifted_1 = omegaShiftedInner_1;
assign omegaShifted_2 = omegaShiftedInner_2;
assign omegaShifted_3 = omegaShiftedInner_3;
assign omegaShifted_4 = omegaShiftedInner_4;
assign omegaShifted_5 = omegaShiftedInner_5;
assign omegaShifted_6 = omegaShiftedInner_6;
assign omegaShifted_7 = omegaShiftedInner_7;
assign omegaShifted_8 = omegaShiftedInner_8;
assign omegaShifted_9 = omegaShiftedInner_9;
assign omegaShifted_10 = omegaShiftedInner_10;
assign omegaShifted_11 = omegaShiftedInner_11;
assign omegaShifted_12 = omegaShiftedInner_12;
assign omegaShifted_13 = omegaShiftedInner_13;
assign omegaShifted_14 = omegaShiftedInner_14;
assign omegaShifted_15 = omegaShiftedInner_15;
assign omegaShifted_16 = omegaShiftedInner_16;
assign omegaShifted_17 = omegaShiftedInner_17;
assign omegaShifted_18 = omegaShiftedInner_18;
assign omegaShifted_19 = omegaShiftedInner_19;
assign omegaShifted_20 = omegaShiftedInner_20;
assign omegaShifted_21 = omegaShiftedInner_21;
 
 
 
endmodule
/trunk/example/rtl/RsDecodeChien.v
0,0 → 1,1985
//===================================================================
// Module Name : RsDecodeChien
// File Name : RsDecodeChien.v
// Function : Rs Decoder Chien search algorithm Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeChien(
CLK, // system clock
RESET, // system reset
enable, // enable signal
sync, // sync signal
erasureIn, // erasure input
lambdaIn_0, // lambda polynom 0
lambdaIn_1, // lambda polynom 1
lambdaIn_2, // lambda polynom 2
lambdaIn_3, // lambda polynom 3
lambdaIn_4, // lambda polynom 4
lambdaIn_5, // lambda polynom 5
lambdaIn_6, // lambda polynom 6
lambdaIn_7, // lambda polynom 7
lambdaIn_8, // lambda polynom 8
lambdaIn_9, // lambda polynom 9
lambdaIn_10, // lambda polynom 10
lambdaIn_11, // lambda polynom 11
lambdaIn_12, // lambda polynom 12
lambdaIn_13, // lambda polynom 13
lambdaIn_14, // lambda polynom 14
lambdaIn_15, // lambda polynom 15
lambdaIn_16, // lambda polynom 16
lambdaIn_17, // lambda polynom 17
lambdaIn_18, // lambda polynom 18
lambdaIn_19, // lambda polynom 19
lambdaIn_20, // lambda polynom 20
lambdaIn_21, // lambda polynom 21
omegaIn_0, // omega polynom 0
omegaIn_1, // omega polynom 1
omegaIn_2, // omega polynom 2
omegaIn_3, // omega polynom 3
omegaIn_4, // omega polynom 4
omegaIn_5, // omega polynom 5
omegaIn_6, // omega polynom 6
omegaIn_7, // omega polynom 7
omegaIn_8, // omega polynom 8
omegaIn_9, // omega polynom 9
omegaIn_10, // omega polynom 10
omegaIn_11, // omega polynom 11
omegaIn_12, // omega polynom 12
omegaIn_13, // omega polynom 13
omegaIn_14, // omega polynom 14
omegaIn_15, // omega polynom 15
omegaIn_16, // omega polynom 16
omegaIn_17, // omega polynom 17
omegaIn_18, // omega polynom 18
omegaIn_19, // omega polynom 19
omegaIn_20, // omega polynom 20
omegaIn_21, // omega polynom 21
epsilonIn_0, // epsilon polynom 0
epsilonIn_1, // epsilon polynom 1
epsilonIn_2, // epsilon polynom 2
epsilonIn_3, // epsilon polynom 3
epsilonIn_4, // epsilon polynom 4
epsilonIn_5, // epsilon polynom 5
epsilonIn_6, // epsilon polynom 6
epsilonIn_7, // epsilon polynom 7
epsilonIn_8, // epsilon polynom 8
epsilonIn_9, // epsilon polynom 9
epsilonIn_10, // epsilon polynom 10
epsilonIn_11, // epsilon polynom 11
epsilonIn_12, // epsilon polynom 12
epsilonIn_13, // epsilon polynom 13
epsilonIn_14, // epsilon polynom 14
epsilonIn_15, // epsilon polynom 15
epsilonIn_16, // epsilon polynom 16
epsilonIn_17, // epsilon polynom 17
epsilonIn_18, // epsilon polynom 18
epsilonIn_19, // epsilon polynom 19
epsilonIn_20, // epsilon polynom 20
epsilonIn_21, // epsilon polynom 21
epsilonIn_22, // epsilon polynom 22
errorOut, // error output
numError, // error amount
done // done signal
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input sync; // sync signal
input erasureIn; // erasure input
input [7:0] lambdaIn_0; // lambda polynom 0
input [7:0] lambdaIn_1; // lambda polynom 1
input [7:0] lambdaIn_2; // lambda polynom 2
input [7:0] lambdaIn_3; // lambda polynom 3
input [7:0] lambdaIn_4; // lambda polynom 4
input [7:0] lambdaIn_5; // lambda polynom 5
input [7:0] lambdaIn_6; // lambda polynom 6
input [7:0] lambdaIn_7; // lambda polynom 7
input [7:0] lambdaIn_8; // lambda polynom 8
input [7:0] lambdaIn_9; // lambda polynom 9
input [7:0] lambdaIn_10; // lambda polynom 10
input [7:0] lambdaIn_11; // lambda polynom 11
input [7:0] lambdaIn_12; // lambda polynom 12
input [7:0] lambdaIn_13; // lambda polynom 13
input [7:0] lambdaIn_14; // lambda polynom 14
input [7:0] lambdaIn_15; // lambda polynom 15
input [7:0] lambdaIn_16; // lambda polynom 16
input [7:0] lambdaIn_17; // lambda polynom 17
input [7:0] lambdaIn_18; // lambda polynom 18
input [7:0] lambdaIn_19; // lambda polynom 19
input [7:0] lambdaIn_20; // lambda polynom 20
input [7:0] lambdaIn_21; // lambda polynom 21
input [7:0] omegaIn_0; // omega polynom 0
input [7:0] omegaIn_1; // omega polynom 1
input [7:0] omegaIn_2; // omega polynom 2
input [7:0] omegaIn_3; // omega polynom 3
input [7:0] omegaIn_4; // omega polynom 4
input [7:0] omegaIn_5; // omega polynom 5
input [7:0] omegaIn_6; // omega polynom 6
input [7:0] omegaIn_7; // omega polynom 7
input [7:0] omegaIn_8; // omega polynom 8
input [7:0] omegaIn_9; // omega polynom 9
input [7:0] omegaIn_10; // omega polynom 10
input [7:0] omegaIn_11; // omega polynom 11
input [7:0] omegaIn_12; // omega polynom 12
input [7:0] omegaIn_13; // omega polynom 13
input [7:0] omegaIn_14; // omega polynom 14
input [7:0] omegaIn_15; // omega polynom 15
input [7:0] omegaIn_16; // omega polynom 16
input [7:0] omegaIn_17; // omega polynom 17
input [7:0] omegaIn_18; // omega polynom 18
input [7:0] omegaIn_19; // omega polynom 19
input [7:0] omegaIn_20; // omega polynom 20
input [7:0] omegaIn_21; // omega polynom 21
 
input [7:0] epsilonIn_0; // epsilon polynom 0
input [7:0] epsilonIn_1; // epsilon polynom 1
input [7:0] epsilonIn_2; // epsilon polynom 2
input [7:0] epsilonIn_3; // epsilon polynom 3
input [7:0] epsilonIn_4; // epsilon polynom 4
input [7:0] epsilonIn_5; // epsilon polynom 5
input [7:0] epsilonIn_6; // epsilon polynom 6
input [7:0] epsilonIn_7; // epsilon polynom 7
input [7:0] epsilonIn_8; // epsilon polynom 8
input [7:0] epsilonIn_9; // epsilon polynom 9
input [7:0] epsilonIn_10; // epsilon polynom 10
input [7:0] epsilonIn_11; // epsilon polynom 11
input [7:0] epsilonIn_12; // epsilon polynom 12
input [7:0] epsilonIn_13; // epsilon polynom 13
input [7:0] epsilonIn_14; // epsilon polynom 14
input [7:0] epsilonIn_15; // epsilon polynom 15
input [7:0] epsilonIn_16; // epsilon polynom 16
input [7:0] epsilonIn_17; // epsilon polynom 17
input [7:0] epsilonIn_18; // epsilon polynom 18
input [7:0] epsilonIn_19; // epsilon polynom 19
input [7:0] epsilonIn_20; // epsilon polynom 20
input [7:0] epsilonIn_21; // epsilon polynom 21
input [7:0] epsilonIn_22; // epsilon polynom 22
output [7:0] errorOut; // error output
output [4:0] numError; // error amount
output done; // done signal
 
 
 
//------------------------------------------------------------------------
// +
//- registers
//------------------------------------------------------------------------
reg [7:0] lambdaSum;
reg [7:0] lambdaSumReg;
reg [7:0] lambdaEven;
reg [7:0] lambdaEvenReg;
reg [7:0] lambdaEvenReg2;
reg [7:0] lambdaEvenReg3;
reg [7:0] lambdaOdd;
reg [7:0] lambdaOddReg;
reg [7:0] lambdaOddReg2;
reg [7:0] lambdaOddReg3;
wire [7:0] denomE0;
wire [7:0] denomE1;
reg [7:0] denomE0Reg;
reg [7:0] denomE1Reg;
wire [7:0] denomE0Inv;
wire [7:0] denomE1Inv;
reg [7:0] denomE0InvReg;
reg [7:0] denomE1InvReg;
reg [7:0] omegaSum;
reg [7:0] omegaSumReg;
reg [7:0] numeReg;
reg [7:0] numeReg2;
reg [7:0] epsilonSum;
reg [7:0] epsilonSumReg;
reg [7:0] epsilonOdd;
reg [7:0] epsilonOddReg;
wire [7:0] errorValueE0;
wire [7:0] errorValueE1;
reg [7:0] count;
reg doneOrg;
 
 
 
 
 
//------------------------------------------------------------------
// + count
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
count[7:0] <= 8'd1;
end
else if ((count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
count[7:0] <= 8'd0;
end
else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
 
 
 
//------------------------------------------------------------------
// + doneOrg
//------------------------------------------------------------------
always @(count) begin
if (count[7:0] == 8'd255) begin
doneOrg = 1'b1;
end else begin
doneOrg = 1'b0;
end
end
 
assign done = doneOrg;
 
 
 
//------------------------------------------------------------------------
//- lambdaIni
//------------------------------------------------------------------------
wire [7:0] lambdaIni_0;
wire [7:0] lambdaIni_1;
wire [7:0] lambdaIni_2;
wire [7:0] lambdaIni_3;
wire [7:0] lambdaIni_4;
wire [7:0] lambdaIni_5;
wire [7:0] lambdaIni_6;
wire [7:0] lambdaIni_7;
wire [7:0] lambdaIni_8;
wire [7:0] lambdaIni_9;
wire [7:0] lambdaIni_10;
wire [7:0] lambdaIni_11;
wire [7:0] lambdaIni_12;
wire [7:0] lambdaIni_13;
wire [7:0] lambdaIni_14;
wire [7:0] lambdaIni_15;
wire [7:0] lambdaIni_16;
wire [7:0] lambdaIni_17;
wire [7:0] lambdaIni_18;
wire [7:0] lambdaIni_19;
wire [7:0] lambdaIni_20;
wire [7:0] lambdaIni_21;
 
 
assign lambdaIni_0 [0] = lambdaIn_0[0];
assign lambdaIni_0 [1] = lambdaIn_0[1];
assign lambdaIni_0 [2] = lambdaIn_0[2];
assign lambdaIni_0 [3] = lambdaIn_0[3];
assign lambdaIni_0 [4] = lambdaIn_0[4];
assign lambdaIni_0 [5] = lambdaIn_0[5];
assign lambdaIni_0 [6] = lambdaIn_0[6];
assign lambdaIni_0 [7] = lambdaIn_0[7];
assign lambdaIni_1 [0] = lambdaIn_1[7];
assign lambdaIni_1 [1] = lambdaIn_1[0];
assign lambdaIni_1 [2] = lambdaIn_1[1] ^ lambdaIn_1[7];
assign lambdaIni_1 [3] = lambdaIn_1[2] ^ lambdaIn_1[7];
assign lambdaIni_1 [4] = lambdaIn_1[3] ^ lambdaIn_1[7];
assign lambdaIni_1 [5] = lambdaIn_1[4];
assign lambdaIni_1 [6] = lambdaIn_1[5];
assign lambdaIni_1 [7] = lambdaIn_1[6];
assign lambdaIni_2 [0] = lambdaIn_2[6];
assign lambdaIni_2 [1] = lambdaIn_2[7];
assign lambdaIni_2 [2] = lambdaIn_2[0] ^ lambdaIn_2[6];
assign lambdaIni_2 [3] = lambdaIn_2[1] ^ lambdaIn_2[6] ^ lambdaIn_2[7];
assign lambdaIni_2 [4] = lambdaIn_2[2] ^ lambdaIn_2[6] ^ lambdaIn_2[7];
assign lambdaIni_2 [5] = lambdaIn_2[3] ^ lambdaIn_2[7];
assign lambdaIni_2 [6] = lambdaIn_2[4];
assign lambdaIni_2 [7] = lambdaIn_2[5];
assign lambdaIni_3 [0] = lambdaIn_3[5];
assign lambdaIni_3 [1] = lambdaIn_3[6];
assign lambdaIni_3 [2] = lambdaIn_3[5] ^ lambdaIn_3[7];
assign lambdaIni_3 [3] = lambdaIn_3[0] ^ lambdaIn_3[5] ^ lambdaIn_3[6];
assign lambdaIni_3 [4] = lambdaIn_3[1] ^ lambdaIn_3[5] ^ lambdaIn_3[6] ^ lambdaIn_3[7];
assign lambdaIni_3 [5] = lambdaIn_3[2] ^ lambdaIn_3[6] ^ lambdaIn_3[7];
assign lambdaIni_3 [6] = lambdaIn_3[3] ^ lambdaIn_3[7];
assign lambdaIni_3 [7] = lambdaIn_3[4];
assign lambdaIni_4 [0] = lambdaIn_4[4];
assign lambdaIni_4 [1] = lambdaIn_4[5];
assign lambdaIni_4 [2] = lambdaIn_4[4] ^ lambdaIn_4[6];
assign lambdaIni_4 [3] = lambdaIn_4[4] ^ lambdaIn_4[5] ^ lambdaIn_4[7];
assign lambdaIni_4 [4] = lambdaIn_4[0] ^ lambdaIn_4[4] ^ lambdaIn_4[5] ^ lambdaIn_4[6];
assign lambdaIni_4 [5] = lambdaIn_4[1] ^ lambdaIn_4[5] ^ lambdaIn_4[6] ^ lambdaIn_4[7];
assign lambdaIni_4 [6] = lambdaIn_4[2] ^ lambdaIn_4[6] ^ lambdaIn_4[7];
assign lambdaIni_4 [7] = lambdaIn_4[3] ^ lambdaIn_4[7];
assign lambdaIni_5 [0] = lambdaIn_5[3] ^ lambdaIn_5[7];
assign lambdaIni_5 [1] = lambdaIn_5[4];
assign lambdaIni_5 [2] = lambdaIn_5[3] ^ lambdaIn_5[5] ^ lambdaIn_5[7];
assign lambdaIni_5 [3] = lambdaIn_5[3] ^ lambdaIn_5[4] ^ lambdaIn_5[6] ^ lambdaIn_5[7];
assign lambdaIni_5 [4] = lambdaIn_5[3] ^ lambdaIn_5[4] ^ lambdaIn_5[5];
assign lambdaIni_5 [5] = lambdaIn_5[0] ^ lambdaIn_5[4] ^ lambdaIn_5[5] ^ lambdaIn_5[6];
assign lambdaIni_5 [6] = lambdaIn_5[1] ^ lambdaIn_5[5] ^ lambdaIn_5[6] ^ lambdaIn_5[7];
assign lambdaIni_5 [7] = lambdaIn_5[2] ^ lambdaIn_5[6] ^ lambdaIn_5[7];
assign lambdaIni_6 [0] = lambdaIn_6[2] ^ lambdaIn_6[6] ^ lambdaIn_6[7];
assign lambdaIni_6 [1] = lambdaIn_6[3] ^ lambdaIn_6[7];
assign lambdaIni_6 [2] = lambdaIn_6[2] ^ lambdaIn_6[4] ^ lambdaIn_6[6] ^ lambdaIn_6[7];
assign lambdaIni_6 [3] = lambdaIn_6[2] ^ lambdaIn_6[3] ^ lambdaIn_6[5] ^ lambdaIn_6[6];
assign lambdaIni_6 [4] = lambdaIn_6[2] ^ lambdaIn_6[3] ^ lambdaIn_6[4];
assign lambdaIni_6 [5] = lambdaIn_6[3] ^ lambdaIn_6[4] ^ lambdaIn_6[5];
assign lambdaIni_6 [6] = lambdaIn_6[0] ^ lambdaIn_6[4] ^ lambdaIn_6[5] ^ lambdaIn_6[6];
assign lambdaIni_6 [7] = lambdaIn_6[1] ^ lambdaIn_6[5] ^ lambdaIn_6[6] ^ lambdaIn_6[7];
assign lambdaIni_7 [0] = lambdaIn_7[1] ^ lambdaIn_7[5] ^ lambdaIn_7[6] ^ lambdaIn_7[7];
assign lambdaIni_7 [1] = lambdaIn_7[2] ^ lambdaIn_7[6] ^ lambdaIn_7[7];
assign lambdaIni_7 [2] = lambdaIn_7[1] ^ lambdaIn_7[3] ^ lambdaIn_7[5] ^ lambdaIn_7[6];
assign lambdaIni_7 [3] = lambdaIn_7[1] ^ lambdaIn_7[2] ^ lambdaIn_7[4] ^ lambdaIn_7[5];
assign lambdaIni_7 [4] = lambdaIn_7[1] ^ lambdaIn_7[2] ^ lambdaIn_7[3] ^ lambdaIn_7[7];
assign lambdaIni_7 [5] = lambdaIn_7[2] ^ lambdaIn_7[3] ^ lambdaIn_7[4];
assign lambdaIni_7 [6] = lambdaIn_7[3] ^ lambdaIn_7[4] ^ lambdaIn_7[5];
assign lambdaIni_7 [7] = lambdaIn_7[0] ^ lambdaIn_7[4] ^ lambdaIn_7[5] ^ lambdaIn_7[6];
assign lambdaIni_8 [0] = lambdaIn_8[0] ^ lambdaIn_8[4] ^ lambdaIn_8[5] ^ lambdaIn_8[6];
assign lambdaIni_8 [1] = lambdaIn_8[1] ^ lambdaIn_8[5] ^ lambdaIn_8[6] ^ lambdaIn_8[7];
assign lambdaIni_8 [2] = lambdaIn_8[0] ^ lambdaIn_8[2] ^ lambdaIn_8[4] ^ lambdaIn_8[5] ^ lambdaIn_8[7];
assign lambdaIni_8 [3] = lambdaIn_8[0] ^ lambdaIn_8[1] ^ lambdaIn_8[3] ^ lambdaIn_8[4];
assign lambdaIni_8 [4] = lambdaIn_8[0] ^ lambdaIn_8[1] ^ lambdaIn_8[2] ^ lambdaIn_8[6];
assign lambdaIni_8 [5] = lambdaIn_8[1] ^ lambdaIn_8[2] ^ lambdaIn_8[3] ^ lambdaIn_8[7];
assign lambdaIni_8 [6] = lambdaIn_8[2] ^ lambdaIn_8[3] ^ lambdaIn_8[4];
assign lambdaIni_8 [7] = lambdaIn_8[3] ^ lambdaIn_8[4] ^ lambdaIn_8[5];
assign lambdaIni_9 [0] = lambdaIn_9[3] ^ lambdaIn_9[4] ^ lambdaIn_9[5];
assign lambdaIni_9 [1] = lambdaIn_9[0] ^ lambdaIn_9[4] ^ lambdaIn_9[5] ^ lambdaIn_9[6];
assign lambdaIni_9 [2] = lambdaIn_9[1] ^ lambdaIn_9[3] ^ lambdaIn_9[4] ^ lambdaIn_9[6] ^ lambdaIn_9[7];
assign lambdaIni_9 [3] = lambdaIn_9[0] ^ lambdaIn_9[2] ^ lambdaIn_9[3] ^ lambdaIn_9[7];
assign lambdaIni_9 [4] = lambdaIn_9[0] ^ lambdaIn_9[1] ^ lambdaIn_9[5];
assign lambdaIni_9 [5] = lambdaIn_9[0] ^ lambdaIn_9[1] ^ lambdaIn_9[2] ^ lambdaIn_9[6];
assign lambdaIni_9 [6] = lambdaIn_9[1] ^ lambdaIn_9[2] ^ lambdaIn_9[3] ^ lambdaIn_9[7];
assign lambdaIni_9 [7] = lambdaIn_9[2] ^ lambdaIn_9[3] ^ lambdaIn_9[4];
assign lambdaIni_10 [0] = lambdaIn_10[2] ^ lambdaIn_10[3] ^ lambdaIn_10[4];
assign lambdaIni_10 [1] = lambdaIn_10[3] ^ lambdaIn_10[4] ^ lambdaIn_10[5];
assign lambdaIni_10 [2] = lambdaIn_10[0] ^ lambdaIn_10[2] ^ lambdaIn_10[3] ^ lambdaIn_10[5] ^ lambdaIn_10[6];
assign lambdaIni_10 [3] = lambdaIn_10[1] ^ lambdaIn_10[2] ^ lambdaIn_10[6] ^ lambdaIn_10[7];
assign lambdaIni_10 [4] = lambdaIn_10[0] ^ lambdaIn_10[4] ^ lambdaIn_10[7];
assign lambdaIni_10 [5] = lambdaIn_10[0] ^ lambdaIn_10[1] ^ lambdaIn_10[5];
assign lambdaIni_10 [6] = lambdaIn_10[0] ^ lambdaIn_10[1] ^ lambdaIn_10[2] ^ lambdaIn_10[6];
assign lambdaIni_10 [7] = lambdaIn_10[1] ^ lambdaIn_10[2] ^ lambdaIn_10[3] ^ lambdaIn_10[7];
assign lambdaIni_11 [0] = lambdaIn_11[1] ^ lambdaIn_11[2] ^ lambdaIn_11[3] ^ lambdaIn_11[7];
assign lambdaIni_11 [1] = lambdaIn_11[2] ^ lambdaIn_11[3] ^ lambdaIn_11[4];
assign lambdaIni_11 [2] = lambdaIn_11[1] ^ lambdaIn_11[2] ^ lambdaIn_11[4] ^ lambdaIn_11[5] ^ lambdaIn_11[7];
assign lambdaIni_11 [3] = lambdaIn_11[0] ^ lambdaIn_11[1] ^ lambdaIn_11[5] ^ lambdaIn_11[6] ^ lambdaIn_11[7];
assign lambdaIni_11 [4] = lambdaIn_11[3] ^ lambdaIn_11[6];
assign lambdaIni_11 [5] = lambdaIn_11[0] ^ lambdaIn_11[4] ^ lambdaIn_11[7];
assign lambdaIni_11 [6] = lambdaIn_11[0] ^ lambdaIn_11[1] ^ lambdaIn_11[5];
assign lambdaIni_11 [7] = lambdaIn_11[0] ^ lambdaIn_11[1] ^ lambdaIn_11[2] ^ lambdaIn_11[6];
assign lambdaIni_12 [0] = lambdaIn_12[0] ^ lambdaIn_12[1] ^ lambdaIn_12[2] ^ lambdaIn_12[6];
assign lambdaIni_12 [1] = lambdaIn_12[1] ^ lambdaIn_12[2] ^ lambdaIn_12[3] ^ lambdaIn_12[7];
assign lambdaIni_12 [2] = lambdaIn_12[0] ^ lambdaIn_12[1] ^ lambdaIn_12[3] ^ lambdaIn_12[4] ^ lambdaIn_12[6];
assign lambdaIni_12 [3] = lambdaIn_12[0] ^ lambdaIn_12[4] ^ lambdaIn_12[5] ^ lambdaIn_12[6] ^ lambdaIn_12[7];
assign lambdaIni_12 [4] = lambdaIn_12[2] ^ lambdaIn_12[5] ^ lambdaIn_12[7];
assign lambdaIni_12 [5] = lambdaIn_12[3] ^ lambdaIn_12[6];
assign lambdaIni_12 [6] = lambdaIn_12[0] ^ lambdaIn_12[4] ^ lambdaIn_12[7];
assign lambdaIni_12 [7] = lambdaIn_12[0] ^ lambdaIn_12[1] ^ lambdaIn_12[5];
assign lambdaIni_13 [0] = lambdaIn_13[0] ^ lambdaIn_13[1] ^ lambdaIn_13[5];
assign lambdaIni_13 [1] = lambdaIn_13[0] ^ lambdaIn_13[1] ^ lambdaIn_13[2] ^ lambdaIn_13[6];
assign lambdaIni_13 [2] = lambdaIn_13[0] ^ lambdaIn_13[2] ^ lambdaIn_13[3] ^ lambdaIn_13[5] ^ lambdaIn_13[7];
assign lambdaIni_13 [3] = lambdaIn_13[3] ^ lambdaIn_13[4] ^ lambdaIn_13[5] ^ lambdaIn_13[6];
assign lambdaIni_13 [4] = lambdaIn_13[1] ^ lambdaIn_13[4] ^ lambdaIn_13[6] ^ lambdaIn_13[7];
assign lambdaIni_13 [5] = lambdaIn_13[2] ^ lambdaIn_13[5] ^ lambdaIn_13[7];
assign lambdaIni_13 [6] = lambdaIn_13[3] ^ lambdaIn_13[6];
assign lambdaIni_13 [7] = lambdaIn_13[0] ^ lambdaIn_13[4] ^ lambdaIn_13[7];
assign lambdaIni_14 [0] = lambdaIn_14[0] ^ lambdaIn_14[4] ^ lambdaIn_14[7];
assign lambdaIni_14 [1] = lambdaIn_14[0] ^ lambdaIn_14[1] ^ lambdaIn_14[5];
assign lambdaIni_14 [2] = lambdaIn_14[1] ^ lambdaIn_14[2] ^ lambdaIn_14[4] ^ lambdaIn_14[6] ^ lambdaIn_14[7];
assign lambdaIni_14 [3] = lambdaIn_14[2] ^ lambdaIn_14[3] ^ lambdaIn_14[4] ^ lambdaIn_14[5];
assign lambdaIni_14 [4] = lambdaIn_14[0] ^ lambdaIn_14[3] ^ lambdaIn_14[5] ^ lambdaIn_14[6] ^ lambdaIn_14[7];
assign lambdaIni_14 [5] = lambdaIn_14[1] ^ lambdaIn_14[4] ^ lambdaIn_14[6] ^ lambdaIn_14[7];
assign lambdaIni_14 [6] = lambdaIn_14[2] ^ lambdaIn_14[5] ^ lambdaIn_14[7];
assign lambdaIni_14 [7] = lambdaIn_14[3] ^ lambdaIn_14[6];
assign lambdaIni_15 [0] = lambdaIn_15[3] ^ lambdaIn_15[6];
assign lambdaIni_15 [1] = lambdaIn_15[0] ^ lambdaIn_15[4] ^ lambdaIn_15[7];
assign lambdaIni_15 [2] = lambdaIn_15[0] ^ lambdaIn_15[1] ^ lambdaIn_15[3] ^ lambdaIn_15[5] ^ lambdaIn_15[6];
assign lambdaIni_15 [3] = lambdaIn_15[1] ^ lambdaIn_15[2] ^ lambdaIn_15[3] ^ lambdaIn_15[4] ^ lambdaIn_15[7];
assign lambdaIni_15 [4] = lambdaIn_15[2] ^ lambdaIn_15[4] ^ lambdaIn_15[5] ^ lambdaIn_15[6];
assign lambdaIni_15 [5] = lambdaIn_15[0] ^ lambdaIn_15[3] ^ lambdaIn_15[5] ^ lambdaIn_15[6] ^ lambdaIn_15[7];
assign lambdaIni_15 [6] = lambdaIn_15[1] ^ lambdaIn_15[4] ^ lambdaIn_15[6] ^ lambdaIn_15[7];
assign lambdaIni_15 [7] = lambdaIn_15[2] ^ lambdaIn_15[5] ^ lambdaIn_15[7];
assign lambdaIni_16 [0] = lambdaIn_16[2] ^ lambdaIn_16[5] ^ lambdaIn_16[7];
assign lambdaIni_16 [1] = lambdaIn_16[3] ^ lambdaIn_16[6];
assign lambdaIni_16 [2] = lambdaIn_16[0] ^ lambdaIn_16[2] ^ lambdaIn_16[4] ^ lambdaIn_16[5];
assign lambdaIni_16 [3] = lambdaIn_16[0] ^ lambdaIn_16[1] ^ lambdaIn_16[2] ^ lambdaIn_16[3] ^ lambdaIn_16[6] ^ lambdaIn_16[7];
assign lambdaIni_16 [4] = lambdaIn_16[1] ^ lambdaIn_16[3] ^ lambdaIn_16[4] ^ lambdaIn_16[5];
assign lambdaIni_16 [5] = lambdaIn_16[2] ^ lambdaIn_16[4] ^ lambdaIn_16[5] ^ lambdaIn_16[6];
assign lambdaIni_16 [6] = lambdaIn_16[0] ^ lambdaIn_16[3] ^ lambdaIn_16[5] ^ lambdaIn_16[6] ^ lambdaIn_16[7];
assign lambdaIni_16 [7] = lambdaIn_16[1] ^ lambdaIn_16[4] ^ lambdaIn_16[6] ^ lambdaIn_16[7];
assign lambdaIni_17 [0] = lambdaIn_17[1] ^ lambdaIn_17[4] ^ lambdaIn_17[6] ^ lambdaIn_17[7];
assign lambdaIni_17 [1] = lambdaIn_17[2] ^ lambdaIn_17[5] ^ lambdaIn_17[7];
assign lambdaIni_17 [2] = lambdaIn_17[1] ^ lambdaIn_17[3] ^ lambdaIn_17[4] ^ lambdaIn_17[7];
assign lambdaIni_17 [3] = lambdaIn_17[0] ^ lambdaIn_17[1] ^ lambdaIn_17[2] ^ lambdaIn_17[5] ^ lambdaIn_17[6] ^ lambdaIn_17[7];
assign lambdaIni_17 [4] = lambdaIn_17[0] ^ lambdaIn_17[2] ^ lambdaIn_17[3] ^ lambdaIn_17[4];
assign lambdaIni_17 [5] = lambdaIn_17[1] ^ lambdaIn_17[3] ^ lambdaIn_17[4] ^ lambdaIn_17[5];
assign lambdaIni_17 [6] = lambdaIn_17[2] ^ lambdaIn_17[4] ^ lambdaIn_17[5] ^ lambdaIn_17[6];
assign lambdaIni_17 [7] = lambdaIn_17[0] ^ lambdaIn_17[3] ^ lambdaIn_17[5] ^ lambdaIn_17[6] ^ lambdaIn_17[7];
assign lambdaIni_18 [0] = lambdaIn_18[0] ^ lambdaIn_18[3] ^ lambdaIn_18[5] ^ lambdaIn_18[6] ^ lambdaIn_18[7];
assign lambdaIni_18 [1] = lambdaIn_18[1] ^ lambdaIn_18[4] ^ lambdaIn_18[6] ^ lambdaIn_18[7];
assign lambdaIni_18 [2] = lambdaIn_18[0] ^ lambdaIn_18[2] ^ lambdaIn_18[3] ^ lambdaIn_18[6];
assign lambdaIni_18 [3] = lambdaIn_18[0] ^ lambdaIn_18[1] ^ lambdaIn_18[4] ^ lambdaIn_18[5] ^ lambdaIn_18[6];
assign lambdaIni_18 [4] = lambdaIn_18[1] ^ lambdaIn_18[2] ^ lambdaIn_18[3];
assign lambdaIni_18 [5] = lambdaIn_18[0] ^ lambdaIn_18[2] ^ lambdaIn_18[3] ^ lambdaIn_18[4];
assign lambdaIni_18 [6] = lambdaIn_18[1] ^ lambdaIn_18[3] ^ lambdaIn_18[4] ^ lambdaIn_18[5];
assign lambdaIni_18 [7] = lambdaIn_18[2] ^ lambdaIn_18[4] ^ lambdaIn_18[5] ^ lambdaIn_18[6];
assign lambdaIni_19 [0] = lambdaIn_19[2] ^ lambdaIn_19[4] ^ lambdaIn_19[5] ^ lambdaIn_19[6];
assign lambdaIni_19 [1] = lambdaIn_19[0] ^ lambdaIn_19[3] ^ lambdaIn_19[5] ^ lambdaIn_19[6] ^ lambdaIn_19[7];
assign lambdaIni_19 [2] = lambdaIn_19[1] ^ lambdaIn_19[2] ^ lambdaIn_19[5] ^ lambdaIn_19[7];
assign lambdaIni_19 [3] = lambdaIn_19[0] ^ lambdaIn_19[3] ^ lambdaIn_19[4] ^ lambdaIn_19[5];
assign lambdaIni_19 [4] = lambdaIn_19[0] ^ lambdaIn_19[1] ^ lambdaIn_19[2];
assign lambdaIni_19 [5] = lambdaIn_19[1] ^ lambdaIn_19[2] ^ lambdaIn_19[3];
assign lambdaIni_19 [6] = lambdaIn_19[0] ^ lambdaIn_19[2] ^ lambdaIn_19[3] ^ lambdaIn_19[4];
assign lambdaIni_19 [7] = lambdaIn_19[1] ^ lambdaIn_19[3] ^ lambdaIn_19[4] ^ lambdaIn_19[5];
assign lambdaIni_20 [0] = lambdaIn_20[1] ^ lambdaIn_20[3] ^ lambdaIn_20[4] ^ lambdaIn_20[5];
assign lambdaIni_20 [1] = lambdaIn_20[2] ^ lambdaIn_20[4] ^ lambdaIn_20[5] ^ lambdaIn_20[6];
assign lambdaIni_20 [2] = lambdaIn_20[0] ^ lambdaIn_20[1] ^ lambdaIn_20[4] ^ lambdaIn_20[6] ^ lambdaIn_20[7];
assign lambdaIni_20 [3] = lambdaIn_20[2] ^ lambdaIn_20[3] ^ lambdaIn_20[4] ^ lambdaIn_20[7];
assign lambdaIni_20 [4] = lambdaIn_20[0] ^ lambdaIn_20[1];
assign lambdaIni_20 [5] = lambdaIn_20[0] ^ lambdaIn_20[1] ^ lambdaIn_20[2];
assign lambdaIni_20 [6] = lambdaIn_20[1] ^ lambdaIn_20[2] ^ lambdaIn_20[3];
assign lambdaIni_20 [7] = lambdaIn_20[0] ^ lambdaIn_20[2] ^ lambdaIn_20[3] ^ lambdaIn_20[4];
assign lambdaIni_21 [0] = lambdaIn_21[0] ^ lambdaIn_21[2] ^ lambdaIn_21[3] ^ lambdaIn_21[4];
assign lambdaIni_21 [1] = lambdaIn_21[1] ^ lambdaIn_21[3] ^ lambdaIn_21[4] ^ lambdaIn_21[5];
assign lambdaIni_21 [2] = lambdaIn_21[0] ^ lambdaIn_21[3] ^ lambdaIn_21[5] ^ lambdaIn_21[6];
assign lambdaIni_21 [3] = lambdaIn_21[1] ^ lambdaIn_21[2] ^ lambdaIn_21[3] ^ lambdaIn_21[6] ^ lambdaIn_21[7];
assign lambdaIni_21 [4] = lambdaIn_21[0] ^ lambdaIn_21[7];
assign lambdaIni_21 [5] = lambdaIn_21[0] ^ lambdaIn_21[1];
assign lambdaIni_21 [6] = lambdaIn_21[0] ^ lambdaIn_21[1] ^ lambdaIn_21[2];
assign lambdaIni_21 [7] = lambdaIn_21[1] ^ lambdaIn_21[2] ^ lambdaIn_21[3];
 
 
 
//------------------------------------------------------------------------
//- lambdaNew
//------------------------------------------------------------------------
reg [7:0] lambdaReg_0;
reg [7:0] lambdaReg_1;
reg [7:0] lambdaReg_2;
reg [7:0] lambdaReg_3;
reg [7:0] lambdaReg_4;
reg [7:0] lambdaReg_5;
reg [7:0] lambdaReg_6;
reg [7:0] lambdaReg_7;
reg [7:0] lambdaReg_8;
reg [7:0] lambdaReg_9;
reg [7:0] lambdaReg_10;
reg [7:0] lambdaReg_11;
reg [7:0] lambdaReg_12;
reg [7:0] lambdaReg_13;
reg [7:0] lambdaReg_14;
reg [7:0] lambdaReg_15;
reg [7:0] lambdaReg_16;
reg [7:0] lambdaReg_17;
reg [7:0] lambdaReg_18;
reg [7:0] lambdaReg_19;
reg [7:0] lambdaReg_20;
reg [7:0] lambdaReg_21;
wire [7:0] lambdaUp_0;
wire [7:0] lambdaUp_1;
wire [7:0] lambdaUp_2;
wire [7:0] lambdaUp_3;
wire [7:0] lambdaUp_4;
wire [7:0] lambdaUp_5;
wire [7:0] lambdaUp_6;
wire [7:0] lambdaUp_7;
wire [7:0] lambdaUp_8;
wire [7:0] lambdaUp_9;
wire [7:0] lambdaUp_10;
wire [7:0] lambdaUp_11;
wire [7:0] lambdaUp_12;
wire [7:0] lambdaUp_13;
wire [7:0] lambdaUp_14;
wire [7:0] lambdaUp_15;
wire [7:0] lambdaUp_16;
wire [7:0] lambdaUp_17;
wire [7:0] lambdaUp_18;
wire [7:0] lambdaUp_19;
wire [7:0] lambdaUp_20;
wire [7:0] lambdaUp_21;
 
 
assign lambdaUp_0 [0] = lambdaReg_0[0];
assign lambdaUp_0 [1] = lambdaReg_0[1];
assign lambdaUp_0 [2] = lambdaReg_0[2];
assign lambdaUp_0 [3] = lambdaReg_0[3];
assign lambdaUp_0 [4] = lambdaReg_0[4];
assign lambdaUp_0 [5] = lambdaReg_0[5];
assign lambdaUp_0 [6] = lambdaReg_0[6];
assign lambdaUp_0 [7] = lambdaReg_0[7];
assign lambdaUp_1 [0] = lambdaReg_1[7];
assign lambdaUp_1 [1] = lambdaReg_1[0];
assign lambdaUp_1 [2] = lambdaReg_1[1] ^ lambdaReg_1[7];
assign lambdaUp_1 [3] = lambdaReg_1[2] ^ lambdaReg_1[7];
assign lambdaUp_1 [4] = lambdaReg_1[3] ^ lambdaReg_1[7];
assign lambdaUp_1 [5] = lambdaReg_1[4];
assign lambdaUp_1 [6] = lambdaReg_1[5];
assign lambdaUp_1 [7] = lambdaReg_1[6];
assign lambdaUp_2 [0] = lambdaReg_2[6];
assign lambdaUp_2 [1] = lambdaReg_2[7];
assign lambdaUp_2 [2] = lambdaReg_2[0] ^ lambdaReg_2[6];
assign lambdaUp_2 [3] = lambdaReg_2[1] ^ lambdaReg_2[6] ^ lambdaReg_2[7];
assign lambdaUp_2 [4] = lambdaReg_2[2] ^ lambdaReg_2[6] ^ lambdaReg_2[7];
assign lambdaUp_2 [5] = lambdaReg_2[3] ^ lambdaReg_2[7];
assign lambdaUp_2 [6] = lambdaReg_2[4];
assign lambdaUp_2 [7] = lambdaReg_2[5];
assign lambdaUp_3 [0] = lambdaReg_3[5];
assign lambdaUp_3 [1] = lambdaReg_3[6];
assign lambdaUp_3 [2] = lambdaReg_3[5] ^ lambdaReg_3[7];
assign lambdaUp_3 [3] = lambdaReg_3[0] ^ lambdaReg_3[5] ^ lambdaReg_3[6];
assign lambdaUp_3 [4] = lambdaReg_3[1] ^ lambdaReg_3[5] ^ lambdaReg_3[6] ^ lambdaReg_3[7];
assign lambdaUp_3 [5] = lambdaReg_3[2] ^ lambdaReg_3[6] ^ lambdaReg_3[7];
assign lambdaUp_3 [6] = lambdaReg_3[3] ^ lambdaReg_3[7];
assign lambdaUp_3 [7] = lambdaReg_3[4];
assign lambdaUp_4 [0] = lambdaReg_4[4];
assign lambdaUp_4 [1] = lambdaReg_4[5];
assign lambdaUp_4 [2] = lambdaReg_4[4] ^ lambdaReg_4[6];
assign lambdaUp_4 [3] = lambdaReg_4[4] ^ lambdaReg_4[5] ^ lambdaReg_4[7];
assign lambdaUp_4 [4] = lambdaReg_4[0] ^ lambdaReg_4[4] ^ lambdaReg_4[5] ^ lambdaReg_4[6];
assign lambdaUp_4 [5] = lambdaReg_4[1] ^ lambdaReg_4[5] ^ lambdaReg_4[6] ^ lambdaReg_4[7];
assign lambdaUp_4 [6] = lambdaReg_4[2] ^ lambdaReg_4[6] ^ lambdaReg_4[7];
assign lambdaUp_4 [7] = lambdaReg_4[3] ^ lambdaReg_4[7];
assign lambdaUp_5 [0] = lambdaReg_5[3] ^ lambdaReg_5[7];
assign lambdaUp_5 [1] = lambdaReg_5[4];
assign lambdaUp_5 [2] = lambdaReg_5[3] ^ lambdaReg_5[5] ^ lambdaReg_5[7];
assign lambdaUp_5 [3] = lambdaReg_5[3] ^ lambdaReg_5[4] ^ lambdaReg_5[6] ^ lambdaReg_5[7];
assign lambdaUp_5 [4] = lambdaReg_5[3] ^ lambdaReg_5[4] ^ lambdaReg_5[5];
assign lambdaUp_5 [5] = lambdaReg_5[0] ^ lambdaReg_5[4] ^ lambdaReg_5[5] ^ lambdaReg_5[6];
assign lambdaUp_5 [6] = lambdaReg_5[1] ^ lambdaReg_5[5] ^ lambdaReg_5[6] ^ lambdaReg_5[7];
assign lambdaUp_5 [7] = lambdaReg_5[2] ^ lambdaReg_5[6] ^ lambdaReg_5[7];
assign lambdaUp_6 [0] = lambdaReg_6[2] ^ lambdaReg_6[6] ^ lambdaReg_6[7];
assign lambdaUp_6 [1] = lambdaReg_6[3] ^ lambdaReg_6[7];
assign lambdaUp_6 [2] = lambdaReg_6[2] ^ lambdaReg_6[4] ^ lambdaReg_6[6] ^ lambdaReg_6[7];
assign lambdaUp_6 [3] = lambdaReg_6[2] ^ lambdaReg_6[3] ^ lambdaReg_6[5] ^ lambdaReg_6[6];
assign lambdaUp_6 [4] = lambdaReg_6[2] ^ lambdaReg_6[3] ^ lambdaReg_6[4];
assign lambdaUp_6 [5] = lambdaReg_6[3] ^ lambdaReg_6[4] ^ lambdaReg_6[5];
assign lambdaUp_6 [6] = lambdaReg_6[0] ^ lambdaReg_6[4] ^ lambdaReg_6[5] ^ lambdaReg_6[6];
assign lambdaUp_6 [7] = lambdaReg_6[1] ^ lambdaReg_6[5] ^ lambdaReg_6[6] ^ lambdaReg_6[7];
assign lambdaUp_7 [0] = lambdaReg_7[1] ^ lambdaReg_7[5] ^ lambdaReg_7[6] ^ lambdaReg_7[7];
assign lambdaUp_7 [1] = lambdaReg_7[2] ^ lambdaReg_7[6] ^ lambdaReg_7[7];
assign lambdaUp_7 [2] = lambdaReg_7[1] ^ lambdaReg_7[3] ^ lambdaReg_7[5] ^ lambdaReg_7[6];
assign lambdaUp_7 [3] = lambdaReg_7[1] ^ lambdaReg_7[2] ^ lambdaReg_7[4] ^ lambdaReg_7[5];
assign lambdaUp_7 [4] = lambdaReg_7[1] ^ lambdaReg_7[2] ^ lambdaReg_7[3] ^ lambdaReg_7[7];
assign lambdaUp_7 [5] = lambdaReg_7[2] ^ lambdaReg_7[3] ^ lambdaReg_7[4];
assign lambdaUp_7 [6] = lambdaReg_7[3] ^ lambdaReg_7[4] ^ lambdaReg_7[5];
assign lambdaUp_7 [7] = lambdaReg_7[0] ^ lambdaReg_7[4] ^ lambdaReg_7[5] ^ lambdaReg_7[6];
assign lambdaUp_8 [0] = lambdaReg_8[0] ^ lambdaReg_8[4] ^ lambdaReg_8[5] ^ lambdaReg_8[6];
assign lambdaUp_8 [1] = lambdaReg_8[1] ^ lambdaReg_8[5] ^ lambdaReg_8[6] ^ lambdaReg_8[7];
assign lambdaUp_8 [2] = lambdaReg_8[0] ^ lambdaReg_8[2] ^ lambdaReg_8[4] ^ lambdaReg_8[5] ^ lambdaReg_8[7];
assign lambdaUp_8 [3] = lambdaReg_8[0] ^ lambdaReg_8[1] ^ lambdaReg_8[3] ^ lambdaReg_8[4];
assign lambdaUp_8 [4] = lambdaReg_8[0] ^ lambdaReg_8[1] ^ lambdaReg_8[2] ^ lambdaReg_8[6];
assign lambdaUp_8 [5] = lambdaReg_8[1] ^ lambdaReg_8[2] ^ lambdaReg_8[3] ^ lambdaReg_8[7];
assign lambdaUp_8 [6] = lambdaReg_8[2] ^ lambdaReg_8[3] ^ lambdaReg_8[4];
assign lambdaUp_8 [7] = lambdaReg_8[3] ^ lambdaReg_8[4] ^ lambdaReg_8[5];
assign lambdaUp_9 [0] = lambdaReg_9[3] ^ lambdaReg_9[4] ^ lambdaReg_9[5];
assign lambdaUp_9 [1] = lambdaReg_9[0] ^ lambdaReg_9[4] ^ lambdaReg_9[5] ^ lambdaReg_9[6];
assign lambdaUp_9 [2] = lambdaReg_9[1] ^ lambdaReg_9[3] ^ lambdaReg_9[4] ^ lambdaReg_9[6] ^ lambdaReg_9[7];
assign lambdaUp_9 [3] = lambdaReg_9[0] ^ lambdaReg_9[2] ^ lambdaReg_9[3] ^ lambdaReg_9[7];
assign lambdaUp_9 [4] = lambdaReg_9[0] ^ lambdaReg_9[1] ^ lambdaReg_9[5];
assign lambdaUp_9 [5] = lambdaReg_9[0] ^ lambdaReg_9[1] ^ lambdaReg_9[2] ^ lambdaReg_9[6];
assign lambdaUp_9 [6] = lambdaReg_9[1] ^ lambdaReg_9[2] ^ lambdaReg_9[3] ^ lambdaReg_9[7];
assign lambdaUp_9 [7] = lambdaReg_9[2] ^ lambdaReg_9[3] ^ lambdaReg_9[4];
assign lambdaUp_10 [0] = lambdaReg_10[2] ^ lambdaReg_10[3] ^ lambdaReg_10[4];
assign lambdaUp_10 [1] = lambdaReg_10[3] ^ lambdaReg_10[4] ^ lambdaReg_10[5];
assign lambdaUp_10 [2] = lambdaReg_10[0] ^ lambdaReg_10[2] ^ lambdaReg_10[3] ^ lambdaReg_10[5] ^ lambdaReg_10[6];
assign lambdaUp_10 [3] = lambdaReg_10[1] ^ lambdaReg_10[2] ^ lambdaReg_10[6] ^ lambdaReg_10[7];
assign lambdaUp_10 [4] = lambdaReg_10[0] ^ lambdaReg_10[4] ^ lambdaReg_10[7];
assign lambdaUp_10 [5] = lambdaReg_10[0] ^ lambdaReg_10[1] ^ lambdaReg_10[5];
assign lambdaUp_10 [6] = lambdaReg_10[0] ^ lambdaReg_10[1] ^ lambdaReg_10[2] ^ lambdaReg_10[6];
assign lambdaUp_10 [7] = lambdaReg_10[1] ^ lambdaReg_10[2] ^ lambdaReg_10[3] ^ lambdaReg_10[7];
assign lambdaUp_11 [0] = lambdaReg_11[1] ^ lambdaReg_11[2] ^ lambdaReg_11[3] ^ lambdaReg_11[7];
assign lambdaUp_11 [1] = lambdaReg_11[2] ^ lambdaReg_11[3] ^ lambdaReg_11[4];
assign lambdaUp_11 [2] = lambdaReg_11[1] ^ lambdaReg_11[2] ^ lambdaReg_11[4] ^ lambdaReg_11[5] ^ lambdaReg_11[7];
assign lambdaUp_11 [3] = lambdaReg_11[0] ^ lambdaReg_11[1] ^ lambdaReg_11[5] ^ lambdaReg_11[6] ^ lambdaReg_11[7];
assign lambdaUp_11 [4] = lambdaReg_11[3] ^ lambdaReg_11[6];
assign lambdaUp_11 [5] = lambdaReg_11[0] ^ lambdaReg_11[4] ^ lambdaReg_11[7];
assign lambdaUp_11 [6] = lambdaReg_11[0] ^ lambdaReg_11[1] ^ lambdaReg_11[5];
assign lambdaUp_11 [7] = lambdaReg_11[0] ^ lambdaReg_11[1] ^ lambdaReg_11[2] ^ lambdaReg_11[6];
assign lambdaUp_12 [0] = lambdaReg_12[0] ^ lambdaReg_12[1] ^ lambdaReg_12[2] ^ lambdaReg_12[6];
assign lambdaUp_12 [1] = lambdaReg_12[1] ^ lambdaReg_12[2] ^ lambdaReg_12[3] ^ lambdaReg_12[7];
assign lambdaUp_12 [2] = lambdaReg_12[0] ^ lambdaReg_12[1] ^ lambdaReg_12[3] ^ lambdaReg_12[4] ^ lambdaReg_12[6];
assign lambdaUp_12 [3] = lambdaReg_12[0] ^ lambdaReg_12[4] ^ lambdaReg_12[5] ^ lambdaReg_12[6] ^ lambdaReg_12[7];
assign lambdaUp_12 [4] = lambdaReg_12[2] ^ lambdaReg_12[5] ^ lambdaReg_12[7];
assign lambdaUp_12 [5] = lambdaReg_12[3] ^ lambdaReg_12[6];
assign lambdaUp_12 [6] = lambdaReg_12[0] ^ lambdaReg_12[4] ^ lambdaReg_12[7];
assign lambdaUp_12 [7] = lambdaReg_12[0] ^ lambdaReg_12[1] ^ lambdaReg_12[5];
assign lambdaUp_13 [0] = lambdaReg_13[0] ^ lambdaReg_13[1] ^ lambdaReg_13[5];
assign lambdaUp_13 [1] = lambdaReg_13[0] ^ lambdaReg_13[1] ^ lambdaReg_13[2] ^ lambdaReg_13[6];
assign lambdaUp_13 [2] = lambdaReg_13[0] ^ lambdaReg_13[2] ^ lambdaReg_13[3] ^ lambdaReg_13[5] ^ lambdaReg_13[7];
assign lambdaUp_13 [3] = lambdaReg_13[3] ^ lambdaReg_13[4] ^ lambdaReg_13[5] ^ lambdaReg_13[6];
assign lambdaUp_13 [4] = lambdaReg_13[1] ^ lambdaReg_13[4] ^ lambdaReg_13[6] ^ lambdaReg_13[7];
assign lambdaUp_13 [5] = lambdaReg_13[2] ^ lambdaReg_13[5] ^ lambdaReg_13[7];
assign lambdaUp_13 [6] = lambdaReg_13[3] ^ lambdaReg_13[6];
assign lambdaUp_13 [7] = lambdaReg_13[0] ^ lambdaReg_13[4] ^ lambdaReg_13[7];
assign lambdaUp_14 [0] = lambdaReg_14[0] ^ lambdaReg_14[4] ^ lambdaReg_14[7];
assign lambdaUp_14 [1] = lambdaReg_14[0] ^ lambdaReg_14[1] ^ lambdaReg_14[5];
assign lambdaUp_14 [2] = lambdaReg_14[1] ^ lambdaReg_14[2] ^ lambdaReg_14[4] ^ lambdaReg_14[6] ^ lambdaReg_14[7];
assign lambdaUp_14 [3] = lambdaReg_14[2] ^ lambdaReg_14[3] ^ lambdaReg_14[4] ^ lambdaReg_14[5];
assign lambdaUp_14 [4] = lambdaReg_14[0] ^ lambdaReg_14[3] ^ lambdaReg_14[5] ^ lambdaReg_14[6] ^ lambdaReg_14[7];
assign lambdaUp_14 [5] = lambdaReg_14[1] ^ lambdaReg_14[4] ^ lambdaReg_14[6] ^ lambdaReg_14[7];
assign lambdaUp_14 [6] = lambdaReg_14[2] ^ lambdaReg_14[5] ^ lambdaReg_14[7];
assign lambdaUp_14 [7] = lambdaReg_14[3] ^ lambdaReg_14[6];
assign lambdaUp_15 [0] = lambdaReg_15[3] ^ lambdaReg_15[6];
assign lambdaUp_15 [1] = lambdaReg_15[0] ^ lambdaReg_15[4] ^ lambdaReg_15[7];
assign lambdaUp_15 [2] = lambdaReg_15[0] ^ lambdaReg_15[1] ^ lambdaReg_15[3] ^ lambdaReg_15[5] ^ lambdaReg_15[6];
assign lambdaUp_15 [3] = lambdaReg_15[1] ^ lambdaReg_15[2] ^ lambdaReg_15[3] ^ lambdaReg_15[4] ^ lambdaReg_15[7];
assign lambdaUp_15 [4] = lambdaReg_15[2] ^ lambdaReg_15[4] ^ lambdaReg_15[5] ^ lambdaReg_15[6];
assign lambdaUp_15 [5] = lambdaReg_15[0] ^ lambdaReg_15[3] ^ lambdaReg_15[5] ^ lambdaReg_15[6] ^ lambdaReg_15[7];
assign lambdaUp_15 [6] = lambdaReg_15[1] ^ lambdaReg_15[4] ^ lambdaReg_15[6] ^ lambdaReg_15[7];
assign lambdaUp_15 [7] = lambdaReg_15[2] ^ lambdaReg_15[5] ^ lambdaReg_15[7];
assign lambdaUp_16 [0] = lambdaReg_16[2] ^ lambdaReg_16[5] ^ lambdaReg_16[7];
assign lambdaUp_16 [1] = lambdaReg_16[3] ^ lambdaReg_16[6];
assign lambdaUp_16 [2] = lambdaReg_16[0] ^ lambdaReg_16[2] ^ lambdaReg_16[4] ^ lambdaReg_16[5];
assign lambdaUp_16 [3] = lambdaReg_16[0] ^ lambdaReg_16[1] ^ lambdaReg_16[2] ^ lambdaReg_16[3] ^ lambdaReg_16[6] ^ lambdaReg_16[7];
assign lambdaUp_16 [4] = lambdaReg_16[1] ^ lambdaReg_16[3] ^ lambdaReg_16[4] ^ lambdaReg_16[5];
assign lambdaUp_16 [5] = lambdaReg_16[2] ^ lambdaReg_16[4] ^ lambdaReg_16[5] ^ lambdaReg_16[6];
assign lambdaUp_16 [6] = lambdaReg_16[0] ^ lambdaReg_16[3] ^ lambdaReg_16[5] ^ lambdaReg_16[6] ^ lambdaReg_16[7];
assign lambdaUp_16 [7] = lambdaReg_16[1] ^ lambdaReg_16[4] ^ lambdaReg_16[6] ^ lambdaReg_16[7];
assign lambdaUp_17 [0] = lambdaReg_17[1] ^ lambdaReg_17[4] ^ lambdaReg_17[6] ^ lambdaReg_17[7];
assign lambdaUp_17 [1] = lambdaReg_17[2] ^ lambdaReg_17[5] ^ lambdaReg_17[7];
assign lambdaUp_17 [2] = lambdaReg_17[1] ^ lambdaReg_17[3] ^ lambdaReg_17[4] ^ lambdaReg_17[7];
assign lambdaUp_17 [3] = lambdaReg_17[0] ^ lambdaReg_17[1] ^ lambdaReg_17[2] ^ lambdaReg_17[5] ^ lambdaReg_17[6] ^ lambdaReg_17[7];
assign lambdaUp_17 [4] = lambdaReg_17[0] ^ lambdaReg_17[2] ^ lambdaReg_17[3] ^ lambdaReg_17[4];
assign lambdaUp_17 [5] = lambdaReg_17[1] ^ lambdaReg_17[3] ^ lambdaReg_17[4] ^ lambdaReg_17[5];
assign lambdaUp_17 [6] = lambdaReg_17[2] ^ lambdaReg_17[4] ^ lambdaReg_17[5] ^ lambdaReg_17[6];
assign lambdaUp_17 [7] = lambdaReg_17[0] ^ lambdaReg_17[3] ^ lambdaReg_17[5] ^ lambdaReg_17[6] ^ lambdaReg_17[7];
assign lambdaUp_18 [0] = lambdaReg_18[0] ^ lambdaReg_18[3] ^ lambdaReg_18[5] ^ lambdaReg_18[6] ^ lambdaReg_18[7];
assign lambdaUp_18 [1] = lambdaReg_18[1] ^ lambdaReg_18[4] ^ lambdaReg_18[6] ^ lambdaReg_18[7];
assign lambdaUp_18 [2] = lambdaReg_18[0] ^ lambdaReg_18[2] ^ lambdaReg_18[3] ^ lambdaReg_18[6];
assign lambdaUp_18 [3] = lambdaReg_18[0] ^ lambdaReg_18[1] ^ lambdaReg_18[4] ^ lambdaReg_18[5] ^ lambdaReg_18[6];
assign lambdaUp_18 [4] = lambdaReg_18[1] ^ lambdaReg_18[2] ^ lambdaReg_18[3];
assign lambdaUp_18 [5] = lambdaReg_18[0] ^ lambdaReg_18[2] ^ lambdaReg_18[3] ^ lambdaReg_18[4];
assign lambdaUp_18 [6] = lambdaReg_18[1] ^ lambdaReg_18[3] ^ lambdaReg_18[4] ^ lambdaReg_18[5];
assign lambdaUp_18 [7] = lambdaReg_18[2] ^ lambdaReg_18[4] ^ lambdaReg_18[5] ^ lambdaReg_18[6];
assign lambdaUp_19 [0] = lambdaReg_19[2] ^ lambdaReg_19[4] ^ lambdaReg_19[5] ^ lambdaReg_19[6];
assign lambdaUp_19 [1] = lambdaReg_19[0] ^ lambdaReg_19[3] ^ lambdaReg_19[5] ^ lambdaReg_19[6] ^ lambdaReg_19[7];
assign lambdaUp_19 [2] = lambdaReg_19[1] ^ lambdaReg_19[2] ^ lambdaReg_19[5] ^ lambdaReg_19[7];
assign lambdaUp_19 [3] = lambdaReg_19[0] ^ lambdaReg_19[3] ^ lambdaReg_19[4] ^ lambdaReg_19[5];
assign lambdaUp_19 [4] = lambdaReg_19[0] ^ lambdaReg_19[1] ^ lambdaReg_19[2];
assign lambdaUp_19 [5] = lambdaReg_19[1] ^ lambdaReg_19[2] ^ lambdaReg_19[3];
assign lambdaUp_19 [6] = lambdaReg_19[0] ^ lambdaReg_19[2] ^ lambdaReg_19[3] ^ lambdaReg_19[4];
assign lambdaUp_19 [7] = lambdaReg_19[1] ^ lambdaReg_19[3] ^ lambdaReg_19[4] ^ lambdaReg_19[5];
assign lambdaUp_20 [0] = lambdaReg_20[1] ^ lambdaReg_20[3] ^ lambdaReg_20[4] ^ lambdaReg_20[5];
assign lambdaUp_20 [1] = lambdaReg_20[2] ^ lambdaReg_20[4] ^ lambdaReg_20[5] ^ lambdaReg_20[6];
assign lambdaUp_20 [2] = lambdaReg_20[0] ^ lambdaReg_20[1] ^ lambdaReg_20[4] ^ lambdaReg_20[6] ^ lambdaReg_20[7];
assign lambdaUp_20 [3] = lambdaReg_20[2] ^ lambdaReg_20[3] ^ lambdaReg_20[4] ^ lambdaReg_20[7];
assign lambdaUp_20 [4] = lambdaReg_20[0] ^ lambdaReg_20[1];
assign lambdaUp_20 [5] = lambdaReg_20[0] ^ lambdaReg_20[1] ^ lambdaReg_20[2];
assign lambdaUp_20 [6] = lambdaReg_20[1] ^ lambdaReg_20[2] ^ lambdaReg_20[3];
assign lambdaUp_20 [7] = lambdaReg_20[0] ^ lambdaReg_20[2] ^ lambdaReg_20[3] ^ lambdaReg_20[4];
assign lambdaUp_21 [0] = lambdaReg_21[0] ^ lambdaReg_21[2] ^ lambdaReg_21[3] ^ lambdaReg_21[4];
assign lambdaUp_21 [1] = lambdaReg_21[1] ^ lambdaReg_21[3] ^ lambdaReg_21[4] ^ lambdaReg_21[5];
assign lambdaUp_21 [2] = lambdaReg_21[0] ^ lambdaReg_21[3] ^ lambdaReg_21[5] ^ lambdaReg_21[6];
assign lambdaUp_21 [3] = lambdaReg_21[1] ^ lambdaReg_21[2] ^ lambdaReg_21[3] ^ lambdaReg_21[6] ^ lambdaReg_21[7];
assign lambdaUp_21 [4] = lambdaReg_21[0] ^ lambdaReg_21[7];
assign lambdaUp_21 [5] = lambdaReg_21[0] ^ lambdaReg_21[1];
assign lambdaUp_21 [6] = lambdaReg_21[0] ^ lambdaReg_21[1] ^ lambdaReg_21[2];
assign lambdaUp_21 [7] = lambdaReg_21[1] ^ lambdaReg_21[2] ^ lambdaReg_21[3];
 
 
 
//------------------------------------------------------------------------
// + lambdaReg_0,...,lambdaReg_21
//- registers
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaReg_0 [7:0] <= 8'd0;
lambdaReg_1 [7:0] <= 8'd0;
lambdaReg_2 [7:0] <= 8'd0;
lambdaReg_3 [7:0] <= 8'd0;
lambdaReg_4 [7:0] <= 8'd0;
lambdaReg_5 [7:0] <= 8'd0;
lambdaReg_6 [7:0] <= 8'd0;
lambdaReg_7 [7:0] <= 8'd0;
lambdaReg_8 [7:0] <= 8'd0;
lambdaReg_9 [7:0] <= 8'd0;
lambdaReg_10 [7:0] <= 8'd0;
lambdaReg_11 [7:0] <= 8'd0;
lambdaReg_12 [7:0] <= 8'd0;
lambdaReg_13 [7:0] <= 8'd0;
lambdaReg_14 [7:0] <= 8'd0;
lambdaReg_15 [7:0] <= 8'd0;
lambdaReg_16 [7:0] <= 8'd0;
lambdaReg_17 [7:0] <= 8'd0;
lambdaReg_18 [7:0] <= 8'd0;
lambdaReg_19 [7:0] <= 8'd0;
lambdaReg_20 [7:0] <= 8'd0;
lambdaReg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
lambdaReg_0 [7:0] <= lambdaIni_0 [7:0];
lambdaReg_1 [7:0] <= lambdaIni_1 [7:0];
lambdaReg_2 [7:0] <= lambdaIni_2 [7:0];
lambdaReg_3 [7:0] <= lambdaIni_3 [7:0];
lambdaReg_4 [7:0] <= lambdaIni_4 [7:0];
lambdaReg_5 [7:0] <= lambdaIni_5 [7:0];
lambdaReg_6 [7:0] <= lambdaIni_6 [7:0];
lambdaReg_7 [7:0] <= lambdaIni_7 [7:0];
lambdaReg_8 [7:0] <= lambdaIni_8 [7:0];
lambdaReg_9 [7:0] <= lambdaIni_9 [7:0];
lambdaReg_10 [7:0] <= lambdaIni_10 [7:0];
lambdaReg_11 [7:0] <= lambdaIni_11 [7:0];
lambdaReg_12 [7:0] <= lambdaIni_12 [7:0];
lambdaReg_13 [7:0] <= lambdaIni_13 [7:0];
lambdaReg_14 [7:0] <= lambdaIni_14 [7:0];
lambdaReg_15 [7:0] <= lambdaIni_15 [7:0];
lambdaReg_16 [7:0] <= lambdaIni_16 [7:0];
lambdaReg_17 [7:0] <= lambdaIni_17 [7:0];
lambdaReg_18 [7:0] <= lambdaIni_18 [7:0];
lambdaReg_19 [7:0] <= lambdaIni_19 [7:0];
lambdaReg_20 [7:0] <= lambdaIni_20 [7:0];
lambdaReg_21 [7:0] <= lambdaIni_21 [7:0];
end
else begin
lambdaReg_0 [7:0] <= lambdaUp_0 [7:0];
lambdaReg_1 [7:0] <= lambdaUp_1 [7:0];
lambdaReg_2 [7:0] <= lambdaUp_2 [7:0];
lambdaReg_3 [7:0] <= lambdaUp_3 [7:0];
lambdaReg_4 [7:0] <= lambdaUp_4 [7:0];
lambdaReg_5 [7:0] <= lambdaUp_5 [7:0];
lambdaReg_6 [7:0] <= lambdaUp_6 [7:0];
lambdaReg_7 [7:0] <= lambdaUp_7 [7:0];
lambdaReg_8 [7:0] <= lambdaUp_8 [7:0];
lambdaReg_9 [7:0] <= lambdaUp_9 [7:0];
lambdaReg_10 [7:0] <= lambdaUp_10 [7:0];
lambdaReg_11 [7:0] <= lambdaUp_11 [7:0];
lambdaReg_12 [7:0] <= lambdaUp_12 [7:0];
lambdaReg_13 [7:0] <= lambdaUp_13 [7:0];
lambdaReg_14 [7:0] <= lambdaUp_14 [7:0];
lambdaReg_15 [7:0] <= lambdaUp_15 [7:0];
lambdaReg_16 [7:0] <= lambdaUp_16 [7:0];
lambdaReg_17 [7:0] <= lambdaUp_17 [7:0];
lambdaReg_18 [7:0] <= lambdaUp_18 [7:0];
lambdaReg_19 [7:0] <= lambdaUp_19 [7:0];
lambdaReg_20 [7:0] <= lambdaUp_20 [7:0];
lambdaReg_21 [7:0] <= lambdaUp_21 [7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
//- omegaIni
//------------------------------------------------------------------------
wire [7:0] omegaIni_0;
wire [7:0] omegaIni_1;
wire [7:0] omegaIni_2;
wire [7:0] omegaIni_3;
wire [7:0] omegaIni_4;
wire [7:0] omegaIni_5;
wire [7:0] omegaIni_6;
wire [7:0] omegaIni_7;
wire [7:0] omegaIni_8;
wire [7:0] omegaIni_9;
wire [7:0] omegaIni_10;
wire [7:0] omegaIni_11;
wire [7:0] omegaIni_12;
wire [7:0] omegaIni_13;
wire [7:0] omegaIni_14;
wire [7:0] omegaIni_15;
wire [7:0] omegaIni_16;
wire [7:0] omegaIni_17;
wire [7:0] omegaIni_18;
wire [7:0] omegaIni_19;
wire [7:0] omegaIni_20;
wire [7:0] omegaIni_21;
 
 
assign omegaIni_0 [0] = omegaIn_0[0];
assign omegaIni_0 [1] = omegaIn_0[1];
assign omegaIni_0 [2] = omegaIn_0[2];
assign omegaIni_0 [3] = omegaIn_0[3];
assign omegaIni_0 [4] = omegaIn_0[4];
assign omegaIni_0 [5] = omegaIn_0[5];
assign omegaIni_0 [6] = omegaIn_0[6];
assign omegaIni_0 [7] = omegaIn_0[7];
assign omegaIni_1 [0] = omegaIn_1[7];
assign omegaIni_1 [1] = omegaIn_1[0];
assign omegaIni_1 [2] = omegaIn_1[1] ^ omegaIn_1[7];
assign omegaIni_1 [3] = omegaIn_1[2] ^ omegaIn_1[7];
assign omegaIni_1 [4] = omegaIn_1[3] ^ omegaIn_1[7];
assign omegaIni_1 [5] = omegaIn_1[4];
assign omegaIni_1 [6] = omegaIn_1[5];
assign omegaIni_1 [7] = omegaIn_1[6];
assign omegaIni_2 [0] = omegaIn_2[6];
assign omegaIni_2 [1] = omegaIn_2[7];
assign omegaIni_2 [2] = omegaIn_2[0] ^ omegaIn_2[6];
assign omegaIni_2 [3] = omegaIn_2[1] ^ omegaIn_2[6] ^ omegaIn_2[7];
assign omegaIni_2 [4] = omegaIn_2[2] ^ omegaIn_2[6] ^ omegaIn_2[7];
assign omegaIni_2 [5] = omegaIn_2[3] ^ omegaIn_2[7];
assign omegaIni_2 [6] = omegaIn_2[4];
assign omegaIni_2 [7] = omegaIn_2[5];
assign omegaIni_3 [0] = omegaIn_3[5];
assign omegaIni_3 [1] = omegaIn_3[6];
assign omegaIni_3 [2] = omegaIn_3[5] ^ omegaIn_3[7];
assign omegaIni_3 [3] = omegaIn_3[0] ^ omegaIn_3[5] ^ omegaIn_3[6];
assign omegaIni_3 [4] = omegaIn_3[1] ^ omegaIn_3[5] ^ omegaIn_3[6] ^ omegaIn_3[7];
assign omegaIni_3 [5] = omegaIn_3[2] ^ omegaIn_3[6] ^ omegaIn_3[7];
assign omegaIni_3 [6] = omegaIn_3[3] ^ omegaIn_3[7];
assign omegaIni_3 [7] = omegaIn_3[4];
assign omegaIni_4 [0] = omegaIn_4[4];
assign omegaIni_4 [1] = omegaIn_4[5];
assign omegaIni_4 [2] = omegaIn_4[4] ^ omegaIn_4[6];
assign omegaIni_4 [3] = omegaIn_4[4] ^ omegaIn_4[5] ^ omegaIn_4[7];
assign omegaIni_4 [4] = omegaIn_4[0] ^ omegaIn_4[4] ^ omegaIn_4[5] ^ omegaIn_4[6];
assign omegaIni_4 [5] = omegaIn_4[1] ^ omegaIn_4[5] ^ omegaIn_4[6] ^ omegaIn_4[7];
assign omegaIni_4 [6] = omegaIn_4[2] ^ omegaIn_4[6] ^ omegaIn_4[7];
assign omegaIni_4 [7] = omegaIn_4[3] ^ omegaIn_4[7];
assign omegaIni_5 [0] = omegaIn_5[3] ^ omegaIn_5[7];
assign omegaIni_5 [1] = omegaIn_5[4];
assign omegaIni_5 [2] = omegaIn_5[3] ^ omegaIn_5[5] ^ omegaIn_5[7];
assign omegaIni_5 [3] = omegaIn_5[3] ^ omegaIn_5[4] ^ omegaIn_5[6] ^ omegaIn_5[7];
assign omegaIni_5 [4] = omegaIn_5[3] ^ omegaIn_5[4] ^ omegaIn_5[5];
assign omegaIni_5 [5] = omegaIn_5[0] ^ omegaIn_5[4] ^ omegaIn_5[5] ^ omegaIn_5[6];
assign omegaIni_5 [6] = omegaIn_5[1] ^ omegaIn_5[5] ^ omegaIn_5[6] ^ omegaIn_5[7];
assign omegaIni_5 [7] = omegaIn_5[2] ^ omegaIn_5[6] ^ omegaIn_5[7];
assign omegaIni_6 [0] = omegaIn_6[2] ^ omegaIn_6[6] ^ omegaIn_6[7];
assign omegaIni_6 [1] = omegaIn_6[3] ^ omegaIn_6[7];
assign omegaIni_6 [2] = omegaIn_6[2] ^ omegaIn_6[4] ^ omegaIn_6[6] ^ omegaIn_6[7];
assign omegaIni_6 [3] = omegaIn_6[2] ^ omegaIn_6[3] ^ omegaIn_6[5] ^ omegaIn_6[6];
assign omegaIni_6 [4] = omegaIn_6[2] ^ omegaIn_6[3] ^ omegaIn_6[4];
assign omegaIni_6 [5] = omegaIn_6[3] ^ omegaIn_6[4] ^ omegaIn_6[5];
assign omegaIni_6 [6] = omegaIn_6[0] ^ omegaIn_6[4] ^ omegaIn_6[5] ^ omegaIn_6[6];
assign omegaIni_6 [7] = omegaIn_6[1] ^ omegaIn_6[5] ^ omegaIn_6[6] ^ omegaIn_6[7];
assign omegaIni_7 [0] = omegaIn_7[1] ^ omegaIn_7[5] ^ omegaIn_7[6] ^ omegaIn_7[7];
assign omegaIni_7 [1] = omegaIn_7[2] ^ omegaIn_7[6] ^ omegaIn_7[7];
assign omegaIni_7 [2] = omegaIn_7[1] ^ omegaIn_7[3] ^ omegaIn_7[5] ^ omegaIn_7[6];
assign omegaIni_7 [3] = omegaIn_7[1] ^ omegaIn_7[2] ^ omegaIn_7[4] ^ omegaIn_7[5];
assign omegaIni_7 [4] = omegaIn_7[1] ^ omegaIn_7[2] ^ omegaIn_7[3] ^ omegaIn_7[7];
assign omegaIni_7 [5] = omegaIn_7[2] ^ omegaIn_7[3] ^ omegaIn_7[4];
assign omegaIni_7 [6] = omegaIn_7[3] ^ omegaIn_7[4] ^ omegaIn_7[5];
assign omegaIni_7 [7] = omegaIn_7[0] ^ omegaIn_7[4] ^ omegaIn_7[5] ^ omegaIn_7[6];
assign omegaIni_8 [0] = omegaIn_8[0] ^ omegaIn_8[4] ^ omegaIn_8[5] ^ omegaIn_8[6];
assign omegaIni_8 [1] = omegaIn_8[1] ^ omegaIn_8[5] ^ omegaIn_8[6] ^ omegaIn_8[7];
assign omegaIni_8 [2] = omegaIn_8[0] ^ omegaIn_8[2] ^ omegaIn_8[4] ^ omegaIn_8[5] ^ omegaIn_8[7];
assign omegaIni_8 [3] = omegaIn_8[0] ^ omegaIn_8[1] ^ omegaIn_8[3] ^ omegaIn_8[4];
assign omegaIni_8 [4] = omegaIn_8[0] ^ omegaIn_8[1] ^ omegaIn_8[2] ^ omegaIn_8[6];
assign omegaIni_8 [5] = omegaIn_8[1] ^ omegaIn_8[2] ^ omegaIn_8[3] ^ omegaIn_8[7];
assign omegaIni_8 [6] = omegaIn_8[2] ^ omegaIn_8[3] ^ omegaIn_8[4];
assign omegaIni_8 [7] = omegaIn_8[3] ^ omegaIn_8[4] ^ omegaIn_8[5];
assign omegaIni_9 [0] = omegaIn_9[3] ^ omegaIn_9[4] ^ omegaIn_9[5];
assign omegaIni_9 [1] = omegaIn_9[0] ^ omegaIn_9[4] ^ omegaIn_9[5] ^ omegaIn_9[6];
assign omegaIni_9 [2] = omegaIn_9[1] ^ omegaIn_9[3] ^ omegaIn_9[4] ^ omegaIn_9[6] ^ omegaIn_9[7];
assign omegaIni_9 [3] = omegaIn_9[0] ^ omegaIn_9[2] ^ omegaIn_9[3] ^ omegaIn_9[7];
assign omegaIni_9 [4] = omegaIn_9[0] ^ omegaIn_9[1] ^ omegaIn_9[5];
assign omegaIni_9 [5] = omegaIn_9[0] ^ omegaIn_9[1] ^ omegaIn_9[2] ^ omegaIn_9[6];
assign omegaIni_9 [6] = omegaIn_9[1] ^ omegaIn_9[2] ^ omegaIn_9[3] ^ omegaIn_9[7];
assign omegaIni_9 [7] = omegaIn_9[2] ^ omegaIn_9[3] ^ omegaIn_9[4];
assign omegaIni_10 [0] = omegaIn_10[2] ^ omegaIn_10[3] ^ omegaIn_10[4];
assign omegaIni_10 [1] = omegaIn_10[3] ^ omegaIn_10[4] ^ omegaIn_10[5];
assign omegaIni_10 [2] = omegaIn_10[0] ^ omegaIn_10[2] ^ omegaIn_10[3] ^ omegaIn_10[5] ^ omegaIn_10[6];
assign omegaIni_10 [3] = omegaIn_10[1] ^ omegaIn_10[2] ^ omegaIn_10[6] ^ omegaIn_10[7];
assign omegaIni_10 [4] = omegaIn_10[0] ^ omegaIn_10[4] ^ omegaIn_10[7];
assign omegaIni_10 [5] = omegaIn_10[0] ^ omegaIn_10[1] ^ omegaIn_10[5];
assign omegaIni_10 [6] = omegaIn_10[0] ^ omegaIn_10[1] ^ omegaIn_10[2] ^ omegaIn_10[6];
assign omegaIni_10 [7] = omegaIn_10[1] ^ omegaIn_10[2] ^ omegaIn_10[3] ^ omegaIn_10[7];
assign omegaIni_11 [0] = omegaIn_11[1] ^ omegaIn_11[2] ^ omegaIn_11[3] ^ omegaIn_11[7];
assign omegaIni_11 [1] = omegaIn_11[2] ^ omegaIn_11[3] ^ omegaIn_11[4];
assign omegaIni_11 [2] = omegaIn_11[1] ^ omegaIn_11[2] ^ omegaIn_11[4] ^ omegaIn_11[5] ^ omegaIn_11[7];
assign omegaIni_11 [3] = omegaIn_11[0] ^ omegaIn_11[1] ^ omegaIn_11[5] ^ omegaIn_11[6] ^ omegaIn_11[7];
assign omegaIni_11 [4] = omegaIn_11[3] ^ omegaIn_11[6];
assign omegaIni_11 [5] = omegaIn_11[0] ^ omegaIn_11[4] ^ omegaIn_11[7];
assign omegaIni_11 [6] = omegaIn_11[0] ^ omegaIn_11[1] ^ omegaIn_11[5];
assign omegaIni_11 [7] = omegaIn_11[0] ^ omegaIn_11[1] ^ omegaIn_11[2] ^ omegaIn_11[6];
assign omegaIni_12 [0] = omegaIn_12[0] ^ omegaIn_12[1] ^ omegaIn_12[2] ^ omegaIn_12[6];
assign omegaIni_12 [1] = omegaIn_12[1] ^ omegaIn_12[2] ^ omegaIn_12[3] ^ omegaIn_12[7];
assign omegaIni_12 [2] = omegaIn_12[0] ^ omegaIn_12[1] ^ omegaIn_12[3] ^ omegaIn_12[4] ^ omegaIn_12[6];
assign omegaIni_12 [3] = omegaIn_12[0] ^ omegaIn_12[4] ^ omegaIn_12[5] ^ omegaIn_12[6] ^ omegaIn_12[7];
assign omegaIni_12 [4] = omegaIn_12[2] ^ omegaIn_12[5] ^ omegaIn_12[7];
assign omegaIni_12 [5] = omegaIn_12[3] ^ omegaIn_12[6];
assign omegaIni_12 [6] = omegaIn_12[0] ^ omegaIn_12[4] ^ omegaIn_12[7];
assign omegaIni_12 [7] = omegaIn_12[0] ^ omegaIn_12[1] ^ omegaIn_12[5];
assign omegaIni_13 [0] = omegaIn_13[0] ^ omegaIn_13[1] ^ omegaIn_13[5];
assign omegaIni_13 [1] = omegaIn_13[0] ^ omegaIn_13[1] ^ omegaIn_13[2] ^ omegaIn_13[6];
assign omegaIni_13 [2] = omegaIn_13[0] ^ omegaIn_13[2] ^ omegaIn_13[3] ^ omegaIn_13[5] ^ omegaIn_13[7];
assign omegaIni_13 [3] = omegaIn_13[3] ^ omegaIn_13[4] ^ omegaIn_13[5] ^ omegaIn_13[6];
assign omegaIni_13 [4] = omegaIn_13[1] ^ omegaIn_13[4] ^ omegaIn_13[6] ^ omegaIn_13[7];
assign omegaIni_13 [5] = omegaIn_13[2] ^ omegaIn_13[5] ^ omegaIn_13[7];
assign omegaIni_13 [6] = omegaIn_13[3] ^ omegaIn_13[6];
assign omegaIni_13 [7] = omegaIn_13[0] ^ omegaIn_13[4] ^ omegaIn_13[7];
assign omegaIni_14 [0] = omegaIn_14[0] ^ omegaIn_14[4] ^ omegaIn_14[7];
assign omegaIni_14 [1] = omegaIn_14[0] ^ omegaIn_14[1] ^ omegaIn_14[5];
assign omegaIni_14 [2] = omegaIn_14[1] ^ omegaIn_14[2] ^ omegaIn_14[4] ^ omegaIn_14[6] ^ omegaIn_14[7];
assign omegaIni_14 [3] = omegaIn_14[2] ^ omegaIn_14[3] ^ omegaIn_14[4] ^ omegaIn_14[5];
assign omegaIni_14 [4] = omegaIn_14[0] ^ omegaIn_14[3] ^ omegaIn_14[5] ^ omegaIn_14[6] ^ omegaIn_14[7];
assign omegaIni_14 [5] = omegaIn_14[1] ^ omegaIn_14[4] ^ omegaIn_14[6] ^ omegaIn_14[7];
assign omegaIni_14 [6] = omegaIn_14[2] ^ omegaIn_14[5] ^ omegaIn_14[7];
assign omegaIni_14 [7] = omegaIn_14[3] ^ omegaIn_14[6];
assign omegaIni_15 [0] = omegaIn_15[3] ^ omegaIn_15[6];
assign omegaIni_15 [1] = omegaIn_15[0] ^ omegaIn_15[4] ^ omegaIn_15[7];
assign omegaIni_15 [2] = omegaIn_15[0] ^ omegaIn_15[1] ^ omegaIn_15[3] ^ omegaIn_15[5] ^ omegaIn_15[6];
assign omegaIni_15 [3] = omegaIn_15[1] ^ omegaIn_15[2] ^ omegaIn_15[3] ^ omegaIn_15[4] ^ omegaIn_15[7];
assign omegaIni_15 [4] = omegaIn_15[2] ^ omegaIn_15[4] ^ omegaIn_15[5] ^ omegaIn_15[6];
assign omegaIni_15 [5] = omegaIn_15[0] ^ omegaIn_15[3] ^ omegaIn_15[5] ^ omegaIn_15[6] ^ omegaIn_15[7];
assign omegaIni_15 [6] = omegaIn_15[1] ^ omegaIn_15[4] ^ omegaIn_15[6] ^ omegaIn_15[7];
assign omegaIni_15 [7] = omegaIn_15[2] ^ omegaIn_15[5] ^ omegaIn_15[7];
assign omegaIni_16 [0] = omegaIn_16[2] ^ omegaIn_16[5] ^ omegaIn_16[7];
assign omegaIni_16 [1] = omegaIn_16[3] ^ omegaIn_16[6];
assign omegaIni_16 [2] = omegaIn_16[0] ^ omegaIn_16[2] ^ omegaIn_16[4] ^ omegaIn_16[5];
assign omegaIni_16 [3] = omegaIn_16[0] ^ omegaIn_16[1] ^ omegaIn_16[2] ^ omegaIn_16[3] ^ omegaIn_16[6] ^ omegaIn_16[7];
assign omegaIni_16 [4] = omegaIn_16[1] ^ omegaIn_16[3] ^ omegaIn_16[4] ^ omegaIn_16[5];
assign omegaIni_16 [5] = omegaIn_16[2] ^ omegaIn_16[4] ^ omegaIn_16[5] ^ omegaIn_16[6];
assign omegaIni_16 [6] = omegaIn_16[0] ^ omegaIn_16[3] ^ omegaIn_16[5] ^ omegaIn_16[6] ^ omegaIn_16[7];
assign omegaIni_16 [7] = omegaIn_16[1] ^ omegaIn_16[4] ^ omegaIn_16[6] ^ omegaIn_16[7];
assign omegaIni_17 [0] = omegaIn_17[1] ^ omegaIn_17[4] ^ omegaIn_17[6] ^ omegaIn_17[7];
assign omegaIni_17 [1] = omegaIn_17[2] ^ omegaIn_17[5] ^ omegaIn_17[7];
assign omegaIni_17 [2] = omegaIn_17[1] ^ omegaIn_17[3] ^ omegaIn_17[4] ^ omegaIn_17[7];
assign omegaIni_17 [3] = omegaIn_17[0] ^ omegaIn_17[1] ^ omegaIn_17[2] ^ omegaIn_17[5] ^ omegaIn_17[6] ^ omegaIn_17[7];
assign omegaIni_17 [4] = omegaIn_17[0] ^ omegaIn_17[2] ^ omegaIn_17[3] ^ omegaIn_17[4];
assign omegaIni_17 [5] = omegaIn_17[1] ^ omegaIn_17[3] ^ omegaIn_17[4] ^ omegaIn_17[5];
assign omegaIni_17 [6] = omegaIn_17[2] ^ omegaIn_17[4] ^ omegaIn_17[5] ^ omegaIn_17[6];
assign omegaIni_17 [7] = omegaIn_17[0] ^ omegaIn_17[3] ^ omegaIn_17[5] ^ omegaIn_17[6] ^ omegaIn_17[7];
assign omegaIni_18 [0] = omegaIn_18[0] ^ omegaIn_18[3] ^ omegaIn_18[5] ^ omegaIn_18[6] ^ omegaIn_18[7];
assign omegaIni_18 [1] = omegaIn_18[1] ^ omegaIn_18[4] ^ omegaIn_18[6] ^ omegaIn_18[7];
assign omegaIni_18 [2] = omegaIn_18[0] ^ omegaIn_18[2] ^ omegaIn_18[3] ^ omegaIn_18[6];
assign omegaIni_18 [3] = omegaIn_18[0] ^ omegaIn_18[1] ^ omegaIn_18[4] ^ omegaIn_18[5] ^ omegaIn_18[6];
assign omegaIni_18 [4] = omegaIn_18[1] ^ omegaIn_18[2] ^ omegaIn_18[3];
assign omegaIni_18 [5] = omegaIn_18[0] ^ omegaIn_18[2] ^ omegaIn_18[3] ^ omegaIn_18[4];
assign omegaIni_18 [6] = omegaIn_18[1] ^ omegaIn_18[3] ^ omegaIn_18[4] ^ omegaIn_18[5];
assign omegaIni_18 [7] = omegaIn_18[2] ^ omegaIn_18[4] ^ omegaIn_18[5] ^ omegaIn_18[6];
assign omegaIni_19 [0] = omegaIn_19[2] ^ omegaIn_19[4] ^ omegaIn_19[5] ^ omegaIn_19[6];
assign omegaIni_19 [1] = omegaIn_19[0] ^ omegaIn_19[3] ^ omegaIn_19[5] ^ omegaIn_19[6] ^ omegaIn_19[7];
assign omegaIni_19 [2] = omegaIn_19[1] ^ omegaIn_19[2] ^ omegaIn_19[5] ^ omegaIn_19[7];
assign omegaIni_19 [3] = omegaIn_19[0] ^ omegaIn_19[3] ^ omegaIn_19[4] ^ omegaIn_19[5];
assign omegaIni_19 [4] = omegaIn_19[0] ^ omegaIn_19[1] ^ omegaIn_19[2];
assign omegaIni_19 [5] = omegaIn_19[1] ^ omegaIn_19[2] ^ omegaIn_19[3];
assign omegaIni_19 [6] = omegaIn_19[0] ^ omegaIn_19[2] ^ omegaIn_19[3] ^ omegaIn_19[4];
assign omegaIni_19 [7] = omegaIn_19[1] ^ omegaIn_19[3] ^ omegaIn_19[4] ^ omegaIn_19[5];
assign omegaIni_20 [0] = omegaIn_20[1] ^ omegaIn_20[3] ^ omegaIn_20[4] ^ omegaIn_20[5];
assign omegaIni_20 [1] = omegaIn_20[2] ^ omegaIn_20[4] ^ omegaIn_20[5] ^ omegaIn_20[6];
assign omegaIni_20 [2] = omegaIn_20[0] ^ omegaIn_20[1] ^ omegaIn_20[4] ^ omegaIn_20[6] ^ omegaIn_20[7];
assign omegaIni_20 [3] = omegaIn_20[2] ^ omegaIn_20[3] ^ omegaIn_20[4] ^ omegaIn_20[7];
assign omegaIni_20 [4] = omegaIn_20[0] ^ omegaIn_20[1];
assign omegaIni_20 [5] = omegaIn_20[0] ^ omegaIn_20[1] ^ omegaIn_20[2];
assign omegaIni_20 [6] = omegaIn_20[1] ^ omegaIn_20[2] ^ omegaIn_20[3];
assign omegaIni_20 [7] = omegaIn_20[0] ^ omegaIn_20[2] ^ omegaIn_20[3] ^ omegaIn_20[4];
assign omegaIni_21 [0] = omegaIn_21[0] ^ omegaIn_21[2] ^ omegaIn_21[3] ^ omegaIn_21[4];
assign omegaIni_21 [1] = omegaIn_21[1] ^ omegaIn_21[3] ^ omegaIn_21[4] ^ omegaIn_21[5];
assign omegaIni_21 [2] = omegaIn_21[0] ^ omegaIn_21[3] ^ omegaIn_21[5] ^ omegaIn_21[6];
assign omegaIni_21 [3] = omegaIn_21[1] ^ omegaIn_21[2] ^ omegaIn_21[3] ^ omegaIn_21[6] ^ omegaIn_21[7];
assign omegaIni_21 [4] = omegaIn_21[0] ^ omegaIn_21[7];
assign omegaIni_21 [5] = omegaIn_21[0] ^ omegaIn_21[1];
assign omegaIni_21 [6] = omegaIn_21[0] ^ omegaIn_21[1] ^ omegaIn_21[2];
assign omegaIni_21 [7] = omegaIn_21[1] ^ omegaIn_21[2] ^ omegaIn_21[3];
 
 
 
//------------------------------------------------------------------------
//- omegaNew
//------------------------------------------------------------------------
reg [7:0] omegaReg_0;
reg [7:0] omegaReg_1;
reg [7:0] omegaReg_2;
reg [7:0] omegaReg_3;
reg [7:0] omegaReg_4;
reg [7:0] omegaReg_5;
reg [7:0] omegaReg_6;
reg [7:0] omegaReg_7;
reg [7:0] omegaReg_8;
reg [7:0] omegaReg_9;
reg [7:0] omegaReg_10;
reg [7:0] omegaReg_11;
reg [7:0] omegaReg_12;
reg [7:0] omegaReg_13;
reg [7:0] omegaReg_14;
reg [7:0] omegaReg_15;
reg [7:0] omegaReg_16;
reg [7:0] omegaReg_17;
reg [7:0] omegaReg_18;
reg [7:0] omegaReg_19;
reg [7:0] omegaReg_20;
reg [7:0] omegaReg_21;
wire [7:0] omegaNew_0;
wire [7:0] omegaNew_1;
wire [7:0] omegaNew_2;
wire [7:0] omegaNew_3;
wire [7:0] omegaNew_4;
wire [7:0] omegaNew_5;
wire [7:0] omegaNew_6;
wire [7:0] omegaNew_7;
wire [7:0] omegaNew_8;
wire [7:0] omegaNew_9;
wire [7:0] omegaNew_10;
wire [7:0] omegaNew_11;
wire [7:0] omegaNew_12;
wire [7:0] omegaNew_13;
wire [7:0] omegaNew_14;
wire [7:0] omegaNew_15;
wire [7:0] omegaNew_16;
wire [7:0] omegaNew_17;
wire [7:0] omegaNew_18;
wire [7:0] omegaNew_19;
wire [7:0] omegaNew_20;
wire [7:0] omegaNew_21;
 
 
assign omegaNew_0 [0] = omegaReg_0[0];
assign omegaNew_0 [1] = omegaReg_0[1];
assign omegaNew_0 [2] = omegaReg_0[2];
assign omegaNew_0 [3] = omegaReg_0[3];
assign omegaNew_0 [4] = omegaReg_0[4];
assign omegaNew_0 [5] = omegaReg_0[5];
assign omegaNew_0 [6] = omegaReg_0[6];
assign omegaNew_0 [7] = omegaReg_0[7];
assign omegaNew_1 [0] = omegaReg_1[7];
assign omegaNew_1 [1] = omegaReg_1[0];
assign omegaNew_1 [2] = omegaReg_1[1] ^ omegaReg_1[7];
assign omegaNew_1 [3] = omegaReg_1[2] ^ omegaReg_1[7];
assign omegaNew_1 [4] = omegaReg_1[3] ^ omegaReg_1[7];
assign omegaNew_1 [5] = omegaReg_1[4];
assign omegaNew_1 [6] = omegaReg_1[5];
assign omegaNew_1 [7] = omegaReg_1[6];
assign omegaNew_2 [0] = omegaReg_2[6];
assign omegaNew_2 [1] = omegaReg_2[7];
assign omegaNew_2 [2] = omegaReg_2[0] ^ omegaReg_2[6];
assign omegaNew_2 [3] = omegaReg_2[1] ^ omegaReg_2[6] ^ omegaReg_2[7];
assign omegaNew_2 [4] = omegaReg_2[2] ^ omegaReg_2[6] ^ omegaReg_2[7];
assign omegaNew_2 [5] = omegaReg_2[3] ^ omegaReg_2[7];
assign omegaNew_2 [6] = omegaReg_2[4];
assign omegaNew_2 [7] = omegaReg_2[5];
assign omegaNew_3 [0] = omegaReg_3[5];
assign omegaNew_3 [1] = omegaReg_3[6];
assign omegaNew_3 [2] = omegaReg_3[5] ^ omegaReg_3[7];
assign omegaNew_3 [3] = omegaReg_3[0] ^ omegaReg_3[5] ^ omegaReg_3[6];
assign omegaNew_3 [4] = omegaReg_3[1] ^ omegaReg_3[5] ^ omegaReg_3[6] ^ omegaReg_3[7];
assign omegaNew_3 [5] = omegaReg_3[2] ^ omegaReg_3[6] ^ omegaReg_3[7];
assign omegaNew_3 [6] = omegaReg_3[3] ^ omegaReg_3[7];
assign omegaNew_3 [7] = omegaReg_3[4];
assign omegaNew_4 [0] = omegaReg_4[4];
assign omegaNew_4 [1] = omegaReg_4[5];
assign omegaNew_4 [2] = omegaReg_4[4] ^ omegaReg_4[6];
assign omegaNew_4 [3] = omegaReg_4[4] ^ omegaReg_4[5] ^ omegaReg_4[7];
assign omegaNew_4 [4] = omegaReg_4[0] ^ omegaReg_4[4] ^ omegaReg_4[5] ^ omegaReg_4[6];
assign omegaNew_4 [5] = omegaReg_4[1] ^ omegaReg_4[5] ^ omegaReg_4[6] ^ omegaReg_4[7];
assign omegaNew_4 [6] = omegaReg_4[2] ^ omegaReg_4[6] ^ omegaReg_4[7];
assign omegaNew_4 [7] = omegaReg_4[3] ^ omegaReg_4[7];
assign omegaNew_5 [0] = omegaReg_5[3] ^ omegaReg_5[7];
assign omegaNew_5 [1] = omegaReg_5[4];
assign omegaNew_5 [2] = omegaReg_5[3] ^ omegaReg_5[5] ^ omegaReg_5[7];
assign omegaNew_5 [3] = omegaReg_5[3] ^ omegaReg_5[4] ^ omegaReg_5[6] ^ omegaReg_5[7];
assign omegaNew_5 [4] = omegaReg_5[3] ^ omegaReg_5[4] ^ omegaReg_5[5];
assign omegaNew_5 [5] = omegaReg_5[0] ^ omegaReg_5[4] ^ omegaReg_5[5] ^ omegaReg_5[6];
assign omegaNew_5 [6] = omegaReg_5[1] ^ omegaReg_5[5] ^ omegaReg_5[6] ^ omegaReg_5[7];
assign omegaNew_5 [7] = omegaReg_5[2] ^ omegaReg_5[6] ^ omegaReg_5[7];
assign omegaNew_6 [0] = omegaReg_6[2] ^ omegaReg_6[6] ^ omegaReg_6[7];
assign omegaNew_6 [1] = omegaReg_6[3] ^ omegaReg_6[7];
assign omegaNew_6 [2] = omegaReg_6[2] ^ omegaReg_6[4] ^ omegaReg_6[6] ^ omegaReg_6[7];
assign omegaNew_6 [3] = omegaReg_6[2] ^ omegaReg_6[3] ^ omegaReg_6[5] ^ omegaReg_6[6];
assign omegaNew_6 [4] = omegaReg_6[2] ^ omegaReg_6[3] ^ omegaReg_6[4];
assign omegaNew_6 [5] = omegaReg_6[3] ^ omegaReg_6[4] ^ omegaReg_6[5];
assign omegaNew_6 [6] = omegaReg_6[0] ^ omegaReg_6[4] ^ omegaReg_6[5] ^ omegaReg_6[6];
assign omegaNew_6 [7] = omegaReg_6[1] ^ omegaReg_6[5] ^ omegaReg_6[6] ^ omegaReg_6[7];
assign omegaNew_7 [0] = omegaReg_7[1] ^ omegaReg_7[5] ^ omegaReg_7[6] ^ omegaReg_7[7];
assign omegaNew_7 [1] = omegaReg_7[2] ^ omegaReg_7[6] ^ omegaReg_7[7];
assign omegaNew_7 [2] = omegaReg_7[1] ^ omegaReg_7[3] ^ omegaReg_7[5] ^ omegaReg_7[6];
assign omegaNew_7 [3] = omegaReg_7[1] ^ omegaReg_7[2] ^ omegaReg_7[4] ^ omegaReg_7[5];
assign omegaNew_7 [4] = omegaReg_7[1] ^ omegaReg_7[2] ^ omegaReg_7[3] ^ omegaReg_7[7];
assign omegaNew_7 [5] = omegaReg_7[2] ^ omegaReg_7[3] ^ omegaReg_7[4];
assign omegaNew_7 [6] = omegaReg_7[3] ^ omegaReg_7[4] ^ omegaReg_7[5];
assign omegaNew_7 [7] = omegaReg_7[0] ^ omegaReg_7[4] ^ omegaReg_7[5] ^ omegaReg_7[6];
assign omegaNew_8 [0] = omegaReg_8[0] ^ omegaReg_8[4] ^ omegaReg_8[5] ^ omegaReg_8[6];
assign omegaNew_8 [1] = omegaReg_8[1] ^ omegaReg_8[5] ^ omegaReg_8[6] ^ omegaReg_8[7];
assign omegaNew_8 [2] = omegaReg_8[0] ^ omegaReg_8[2] ^ omegaReg_8[4] ^ omegaReg_8[5] ^ omegaReg_8[7];
assign omegaNew_8 [3] = omegaReg_8[0] ^ omegaReg_8[1] ^ omegaReg_8[3] ^ omegaReg_8[4];
assign omegaNew_8 [4] = omegaReg_8[0] ^ omegaReg_8[1] ^ omegaReg_8[2] ^ omegaReg_8[6];
assign omegaNew_8 [5] = omegaReg_8[1] ^ omegaReg_8[2] ^ omegaReg_8[3] ^ omegaReg_8[7];
assign omegaNew_8 [6] = omegaReg_8[2] ^ omegaReg_8[3] ^ omegaReg_8[4];
assign omegaNew_8 [7] = omegaReg_8[3] ^ omegaReg_8[4] ^ omegaReg_8[5];
assign omegaNew_9 [0] = omegaReg_9[3] ^ omegaReg_9[4] ^ omegaReg_9[5];
assign omegaNew_9 [1] = omegaReg_9[0] ^ omegaReg_9[4] ^ omegaReg_9[5] ^ omegaReg_9[6];
assign omegaNew_9 [2] = omegaReg_9[1] ^ omegaReg_9[3] ^ omegaReg_9[4] ^ omegaReg_9[6] ^ omegaReg_9[7];
assign omegaNew_9 [3] = omegaReg_9[0] ^ omegaReg_9[2] ^ omegaReg_9[3] ^ omegaReg_9[7];
assign omegaNew_9 [4] = omegaReg_9[0] ^ omegaReg_9[1] ^ omegaReg_9[5];
assign omegaNew_9 [5] = omegaReg_9[0] ^ omegaReg_9[1] ^ omegaReg_9[2] ^ omegaReg_9[6];
assign omegaNew_9 [6] = omegaReg_9[1] ^ omegaReg_9[2] ^ omegaReg_9[3] ^ omegaReg_9[7];
assign omegaNew_9 [7] = omegaReg_9[2] ^ omegaReg_9[3] ^ omegaReg_9[4];
assign omegaNew_10 [0] = omegaReg_10[2] ^ omegaReg_10[3] ^ omegaReg_10[4];
assign omegaNew_10 [1] = omegaReg_10[3] ^ omegaReg_10[4] ^ omegaReg_10[5];
assign omegaNew_10 [2] = omegaReg_10[0] ^ omegaReg_10[2] ^ omegaReg_10[3] ^ omegaReg_10[5] ^ omegaReg_10[6];
assign omegaNew_10 [3] = omegaReg_10[1] ^ omegaReg_10[2] ^ omegaReg_10[6] ^ omegaReg_10[7];
assign omegaNew_10 [4] = omegaReg_10[0] ^ omegaReg_10[4] ^ omegaReg_10[7];
assign omegaNew_10 [5] = omegaReg_10[0] ^ omegaReg_10[1] ^ omegaReg_10[5];
assign omegaNew_10 [6] = omegaReg_10[0] ^ omegaReg_10[1] ^ omegaReg_10[2] ^ omegaReg_10[6];
assign omegaNew_10 [7] = omegaReg_10[1] ^ omegaReg_10[2] ^ omegaReg_10[3] ^ omegaReg_10[7];
assign omegaNew_11 [0] = omegaReg_11[1] ^ omegaReg_11[2] ^ omegaReg_11[3] ^ omegaReg_11[7];
assign omegaNew_11 [1] = omegaReg_11[2] ^ omegaReg_11[3] ^ omegaReg_11[4];
assign omegaNew_11 [2] = omegaReg_11[1] ^ omegaReg_11[2] ^ omegaReg_11[4] ^ omegaReg_11[5] ^ omegaReg_11[7];
assign omegaNew_11 [3] = omegaReg_11[0] ^ omegaReg_11[1] ^ omegaReg_11[5] ^ omegaReg_11[6] ^ omegaReg_11[7];
assign omegaNew_11 [4] = omegaReg_11[3] ^ omegaReg_11[6];
assign omegaNew_11 [5] = omegaReg_11[0] ^ omegaReg_11[4] ^ omegaReg_11[7];
assign omegaNew_11 [6] = omegaReg_11[0] ^ omegaReg_11[1] ^ omegaReg_11[5];
assign omegaNew_11 [7] = omegaReg_11[0] ^ omegaReg_11[1] ^ omegaReg_11[2] ^ omegaReg_11[6];
assign omegaNew_12 [0] = omegaReg_12[0] ^ omegaReg_12[1] ^ omegaReg_12[2] ^ omegaReg_12[6];
assign omegaNew_12 [1] = omegaReg_12[1] ^ omegaReg_12[2] ^ omegaReg_12[3] ^ omegaReg_12[7];
assign omegaNew_12 [2] = omegaReg_12[0] ^ omegaReg_12[1] ^ omegaReg_12[3] ^ omegaReg_12[4] ^ omegaReg_12[6];
assign omegaNew_12 [3] = omegaReg_12[0] ^ omegaReg_12[4] ^ omegaReg_12[5] ^ omegaReg_12[6] ^ omegaReg_12[7];
assign omegaNew_12 [4] = omegaReg_12[2] ^ omegaReg_12[5] ^ omegaReg_12[7];
assign omegaNew_12 [5] = omegaReg_12[3] ^ omegaReg_12[6];
assign omegaNew_12 [6] = omegaReg_12[0] ^ omegaReg_12[4] ^ omegaReg_12[7];
assign omegaNew_12 [7] = omegaReg_12[0] ^ omegaReg_12[1] ^ omegaReg_12[5];
assign omegaNew_13 [0] = omegaReg_13[0] ^ omegaReg_13[1] ^ omegaReg_13[5];
assign omegaNew_13 [1] = omegaReg_13[0] ^ omegaReg_13[1] ^ omegaReg_13[2] ^ omegaReg_13[6];
assign omegaNew_13 [2] = omegaReg_13[0] ^ omegaReg_13[2] ^ omegaReg_13[3] ^ omegaReg_13[5] ^ omegaReg_13[7];
assign omegaNew_13 [3] = omegaReg_13[3] ^ omegaReg_13[4] ^ omegaReg_13[5] ^ omegaReg_13[6];
assign omegaNew_13 [4] = omegaReg_13[1] ^ omegaReg_13[4] ^ omegaReg_13[6] ^ omegaReg_13[7];
assign omegaNew_13 [5] = omegaReg_13[2] ^ omegaReg_13[5] ^ omegaReg_13[7];
assign omegaNew_13 [6] = omegaReg_13[3] ^ omegaReg_13[6];
assign omegaNew_13 [7] = omegaReg_13[0] ^ omegaReg_13[4] ^ omegaReg_13[7];
assign omegaNew_14 [0] = omegaReg_14[0] ^ omegaReg_14[4] ^ omegaReg_14[7];
assign omegaNew_14 [1] = omegaReg_14[0] ^ omegaReg_14[1] ^ omegaReg_14[5];
assign omegaNew_14 [2] = omegaReg_14[1] ^ omegaReg_14[2] ^ omegaReg_14[4] ^ omegaReg_14[6] ^ omegaReg_14[7];
assign omegaNew_14 [3] = omegaReg_14[2] ^ omegaReg_14[3] ^ omegaReg_14[4] ^ omegaReg_14[5];
assign omegaNew_14 [4] = omegaReg_14[0] ^ omegaReg_14[3] ^ omegaReg_14[5] ^ omegaReg_14[6] ^ omegaReg_14[7];
assign omegaNew_14 [5] = omegaReg_14[1] ^ omegaReg_14[4] ^ omegaReg_14[6] ^ omegaReg_14[7];
assign omegaNew_14 [6] = omegaReg_14[2] ^ omegaReg_14[5] ^ omegaReg_14[7];
assign omegaNew_14 [7] = omegaReg_14[3] ^ omegaReg_14[6];
assign omegaNew_15 [0] = omegaReg_15[3] ^ omegaReg_15[6];
assign omegaNew_15 [1] = omegaReg_15[0] ^ omegaReg_15[4] ^ omegaReg_15[7];
assign omegaNew_15 [2] = omegaReg_15[0] ^ omegaReg_15[1] ^ omegaReg_15[3] ^ omegaReg_15[5] ^ omegaReg_15[6];
assign omegaNew_15 [3] = omegaReg_15[1] ^ omegaReg_15[2] ^ omegaReg_15[3] ^ omegaReg_15[4] ^ omegaReg_15[7];
assign omegaNew_15 [4] = omegaReg_15[2] ^ omegaReg_15[4] ^ omegaReg_15[5] ^ omegaReg_15[6];
assign omegaNew_15 [5] = omegaReg_15[0] ^ omegaReg_15[3] ^ omegaReg_15[5] ^ omegaReg_15[6] ^ omegaReg_15[7];
assign omegaNew_15 [6] = omegaReg_15[1] ^ omegaReg_15[4] ^ omegaReg_15[6] ^ omegaReg_15[7];
assign omegaNew_15 [7] = omegaReg_15[2] ^ omegaReg_15[5] ^ omegaReg_15[7];
assign omegaNew_16 [0] = omegaReg_16[2] ^ omegaReg_16[5] ^ omegaReg_16[7];
assign omegaNew_16 [1] = omegaReg_16[3] ^ omegaReg_16[6];
assign omegaNew_16 [2] = omegaReg_16[0] ^ omegaReg_16[2] ^ omegaReg_16[4] ^ omegaReg_16[5];
assign omegaNew_16 [3] = omegaReg_16[0] ^ omegaReg_16[1] ^ omegaReg_16[2] ^ omegaReg_16[3] ^ omegaReg_16[6] ^ omegaReg_16[7];
assign omegaNew_16 [4] = omegaReg_16[1] ^ omegaReg_16[3] ^ omegaReg_16[4] ^ omegaReg_16[5];
assign omegaNew_16 [5] = omegaReg_16[2] ^ omegaReg_16[4] ^ omegaReg_16[5] ^ omegaReg_16[6];
assign omegaNew_16 [6] = omegaReg_16[0] ^ omegaReg_16[3] ^ omegaReg_16[5] ^ omegaReg_16[6] ^ omegaReg_16[7];
assign omegaNew_16 [7] = omegaReg_16[1] ^ omegaReg_16[4] ^ omegaReg_16[6] ^ omegaReg_16[7];
assign omegaNew_17 [0] = omegaReg_17[1] ^ omegaReg_17[4] ^ omegaReg_17[6] ^ omegaReg_17[7];
assign omegaNew_17 [1] = omegaReg_17[2] ^ omegaReg_17[5] ^ omegaReg_17[7];
assign omegaNew_17 [2] = omegaReg_17[1] ^ omegaReg_17[3] ^ omegaReg_17[4] ^ omegaReg_17[7];
assign omegaNew_17 [3] = omegaReg_17[0] ^ omegaReg_17[1] ^ omegaReg_17[2] ^ omegaReg_17[5] ^ omegaReg_17[6] ^ omegaReg_17[7];
assign omegaNew_17 [4] = omegaReg_17[0] ^ omegaReg_17[2] ^ omegaReg_17[3] ^ omegaReg_17[4];
assign omegaNew_17 [5] = omegaReg_17[1] ^ omegaReg_17[3] ^ omegaReg_17[4] ^ omegaReg_17[5];
assign omegaNew_17 [6] = omegaReg_17[2] ^ omegaReg_17[4] ^ omegaReg_17[5] ^ omegaReg_17[6];
assign omegaNew_17 [7] = omegaReg_17[0] ^ omegaReg_17[3] ^ omegaReg_17[5] ^ omegaReg_17[6] ^ omegaReg_17[7];
assign omegaNew_18 [0] = omegaReg_18[0] ^ omegaReg_18[3] ^ omegaReg_18[5] ^ omegaReg_18[6] ^ omegaReg_18[7];
assign omegaNew_18 [1] = omegaReg_18[1] ^ omegaReg_18[4] ^ omegaReg_18[6] ^ omegaReg_18[7];
assign omegaNew_18 [2] = omegaReg_18[0] ^ omegaReg_18[2] ^ omegaReg_18[3] ^ omegaReg_18[6];
assign omegaNew_18 [3] = omegaReg_18[0] ^ omegaReg_18[1] ^ omegaReg_18[4] ^ omegaReg_18[5] ^ omegaReg_18[6];
assign omegaNew_18 [4] = omegaReg_18[1] ^ omegaReg_18[2] ^ omegaReg_18[3];
assign omegaNew_18 [5] = omegaReg_18[0] ^ omegaReg_18[2] ^ omegaReg_18[3] ^ omegaReg_18[4];
assign omegaNew_18 [6] = omegaReg_18[1] ^ omegaReg_18[3] ^ omegaReg_18[4] ^ omegaReg_18[5];
assign omegaNew_18 [7] = omegaReg_18[2] ^ omegaReg_18[4] ^ omegaReg_18[5] ^ omegaReg_18[6];
assign omegaNew_19 [0] = omegaReg_19[2] ^ omegaReg_19[4] ^ omegaReg_19[5] ^ omegaReg_19[6];
assign omegaNew_19 [1] = omegaReg_19[0] ^ omegaReg_19[3] ^ omegaReg_19[5] ^ omegaReg_19[6] ^ omegaReg_19[7];
assign omegaNew_19 [2] = omegaReg_19[1] ^ omegaReg_19[2] ^ omegaReg_19[5] ^ omegaReg_19[7];
assign omegaNew_19 [3] = omegaReg_19[0] ^ omegaReg_19[3] ^ omegaReg_19[4] ^ omegaReg_19[5];
assign omegaNew_19 [4] = omegaReg_19[0] ^ omegaReg_19[1] ^ omegaReg_19[2];
assign omegaNew_19 [5] = omegaReg_19[1] ^ omegaReg_19[2] ^ omegaReg_19[3];
assign omegaNew_19 [6] = omegaReg_19[0] ^ omegaReg_19[2] ^ omegaReg_19[3] ^ omegaReg_19[4];
assign omegaNew_19 [7] = omegaReg_19[1] ^ omegaReg_19[3] ^ omegaReg_19[4] ^ omegaReg_19[5];
assign omegaNew_20 [0] = omegaReg_20[1] ^ omegaReg_20[3] ^ omegaReg_20[4] ^ omegaReg_20[5];
assign omegaNew_20 [1] = omegaReg_20[2] ^ omegaReg_20[4] ^ omegaReg_20[5] ^ omegaReg_20[6];
assign omegaNew_20 [2] = omegaReg_20[0] ^ omegaReg_20[1] ^ omegaReg_20[4] ^ omegaReg_20[6] ^ omegaReg_20[7];
assign omegaNew_20 [3] = omegaReg_20[2] ^ omegaReg_20[3] ^ omegaReg_20[4] ^ omegaReg_20[7];
assign omegaNew_20 [4] = omegaReg_20[0] ^ omegaReg_20[1];
assign omegaNew_20 [5] = omegaReg_20[0] ^ omegaReg_20[1] ^ omegaReg_20[2];
assign omegaNew_20 [6] = omegaReg_20[1] ^ omegaReg_20[2] ^ omegaReg_20[3];
assign omegaNew_20 [7] = omegaReg_20[0] ^ omegaReg_20[2] ^ omegaReg_20[3] ^ omegaReg_20[4];
assign omegaNew_21 [0] = omegaReg_21[0] ^ omegaReg_21[2] ^ omegaReg_21[3] ^ omegaReg_21[4];
assign omegaNew_21 [1] = omegaReg_21[1] ^ omegaReg_21[3] ^ omegaReg_21[4] ^ omegaReg_21[5];
assign omegaNew_21 [2] = omegaReg_21[0] ^ omegaReg_21[3] ^ omegaReg_21[5] ^ omegaReg_21[6];
assign omegaNew_21 [3] = omegaReg_21[1] ^ omegaReg_21[2] ^ omegaReg_21[3] ^ omegaReg_21[6] ^ omegaReg_21[7];
assign omegaNew_21 [4] = omegaReg_21[0] ^ omegaReg_21[7];
assign omegaNew_21 [5] = omegaReg_21[0] ^ omegaReg_21[1];
assign omegaNew_21 [6] = omegaReg_21[0] ^ omegaReg_21[1] ^ omegaReg_21[2];
assign omegaNew_21 [7] = omegaReg_21[1] ^ omegaReg_21[2] ^ omegaReg_21[3];
 
 
 
//------------------------------------------------------------------
// + omegaReg_0,..., omegaReg_21
//- registers
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaReg_0 [7:0] <= 8'd0;
omegaReg_1 [7:0] <= 8'd0;
omegaReg_2 [7:0] <= 8'd0;
omegaReg_3 [7:0] <= 8'd0;
omegaReg_4 [7:0] <= 8'd0;
omegaReg_5 [7:0] <= 8'd0;
omegaReg_6 [7:0] <= 8'd0;
omegaReg_7 [7:0] <= 8'd0;
omegaReg_8 [7:0] <= 8'd0;
omegaReg_9 [7:0] <= 8'd0;
omegaReg_10 [7:0] <= 8'd0;
omegaReg_11 [7:0] <= 8'd0;
omegaReg_12 [7:0] <= 8'd0;
omegaReg_13 [7:0] <= 8'd0;
omegaReg_14 [7:0] <= 8'd0;
omegaReg_15 [7:0] <= 8'd0;
omegaReg_16 [7:0] <= 8'd0;
omegaReg_17 [7:0] <= 8'd0;
omegaReg_18 [7:0] <= 8'd0;
omegaReg_19 [7:0] <= 8'd0;
omegaReg_20 [7:0] <= 8'd0;
omegaReg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
omegaReg_0 [7:0] <= omegaIni_0 [7:0];
omegaReg_1 [7:0] <= omegaIni_1 [7:0];
omegaReg_2 [7:0] <= omegaIni_2 [7:0];
omegaReg_3 [7:0] <= omegaIni_3 [7:0];
omegaReg_4 [7:0] <= omegaIni_4 [7:0];
omegaReg_5 [7:0] <= omegaIni_5 [7:0];
omegaReg_6 [7:0] <= omegaIni_6 [7:0];
omegaReg_7 [7:0] <= omegaIni_7 [7:0];
omegaReg_8 [7:0] <= omegaIni_8 [7:0];
omegaReg_9 [7:0] <= omegaIni_9 [7:0];
omegaReg_10 [7:0] <= omegaIni_10 [7:0];
omegaReg_11 [7:0] <= omegaIni_11 [7:0];
omegaReg_12 [7:0] <= omegaIni_12 [7:0];
omegaReg_13 [7:0] <= omegaIni_13 [7:0];
omegaReg_14 [7:0] <= omegaIni_14 [7:0];
omegaReg_15 [7:0] <= omegaIni_15 [7:0];
omegaReg_16 [7:0] <= omegaIni_16 [7:0];
omegaReg_17 [7:0] <= omegaIni_17 [7:0];
omegaReg_18 [7:0] <= omegaIni_18 [7:0];
omegaReg_19 [7:0] <= omegaIni_19 [7:0];
omegaReg_20 [7:0] <= omegaIni_20 [7:0];
omegaReg_21 [7:0] <= omegaIni_21 [7:0];
end
else begin
omegaReg_0 [7:0] <= omegaNew_0 [7:0];
omegaReg_1 [7:0] <= omegaNew_1 [7:0];
omegaReg_2 [7:0] <= omegaNew_2 [7:0];
omegaReg_3 [7:0] <= omegaNew_3 [7:0];
omegaReg_4 [7:0] <= omegaNew_4 [7:0];
omegaReg_5 [7:0] <= omegaNew_5 [7:0];
omegaReg_6 [7:0] <= omegaNew_6 [7:0];
omegaReg_7 [7:0] <= omegaNew_7 [7:0];
omegaReg_8 [7:0] <= omegaNew_8 [7:0];
omegaReg_9 [7:0] <= omegaNew_9 [7:0];
omegaReg_10 [7:0] <= omegaNew_10 [7:0];
omegaReg_11 [7:0] <= omegaNew_11 [7:0];
omegaReg_12 [7:0] <= omegaNew_12 [7:0];
omegaReg_13 [7:0] <= omegaNew_13 [7:0];
omegaReg_14 [7:0] <= omegaNew_14 [7:0];
omegaReg_15 [7:0] <= omegaNew_15 [7:0];
omegaReg_16 [7:0] <= omegaNew_16 [7:0];
omegaReg_17 [7:0] <= omegaNew_17 [7:0];
omegaReg_18 [7:0] <= omegaNew_18 [7:0];
omegaReg_19 [7:0] <= omegaNew_19 [7:0];
omegaReg_20 [7:0] <= omegaNew_20 [7:0];
omegaReg_21 [7:0] <= omegaNew_21 [7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
//- epsilonIni
//------------------------------------------------------------------------
wire [7:0] epsilonIni_0;
wire [7:0] epsilonIni_1;
wire [7:0] epsilonIni_2;
wire [7:0] epsilonIni_3;
wire [7:0] epsilonIni_4;
wire [7:0] epsilonIni_5;
wire [7:0] epsilonIni_6;
wire [7:0] epsilonIni_7;
wire [7:0] epsilonIni_8;
wire [7:0] epsilonIni_9;
wire [7:0] epsilonIni_10;
wire [7:0] epsilonIni_11;
wire [7:0] epsilonIni_12;
wire [7:0] epsilonIni_13;
wire [7:0] epsilonIni_14;
wire [7:0] epsilonIni_15;
wire [7:0] epsilonIni_16;
wire [7:0] epsilonIni_17;
wire [7:0] epsilonIni_18;
wire [7:0] epsilonIni_19;
wire [7:0] epsilonIni_20;
wire [7:0] epsilonIni_21;
wire [7:0] epsilonIni_22;
 
 
assign epsilonIni_0 [0] = epsilonIn_0[0];
assign epsilonIni_0 [1] = epsilonIn_0[1];
assign epsilonIni_0 [2] = epsilonIn_0[2];
assign epsilonIni_0 [3] = epsilonIn_0[3];
assign epsilonIni_0 [4] = epsilonIn_0[4];
assign epsilonIni_0 [5] = epsilonIn_0[5];
assign epsilonIni_0 [6] = epsilonIn_0[6];
assign epsilonIni_0 [7] = epsilonIn_0[7];
assign epsilonIni_1 [0] = epsilonIn_1[7];
assign epsilonIni_1 [1] = epsilonIn_1[0];
assign epsilonIni_1 [2] = epsilonIn_1[1] ^ epsilonIn_1[7];
assign epsilonIni_1 [3] = epsilonIn_1[2] ^ epsilonIn_1[7];
assign epsilonIni_1 [4] = epsilonIn_1[3] ^ epsilonIn_1[7];
assign epsilonIni_1 [5] = epsilonIn_1[4];
assign epsilonIni_1 [6] = epsilonIn_1[5];
assign epsilonIni_1 [7] = epsilonIn_1[6];
assign epsilonIni_2 [0] = epsilonIn_2[6];
assign epsilonIni_2 [1] = epsilonIn_2[7];
assign epsilonIni_2 [2] = epsilonIn_2[0] ^ epsilonIn_2[6];
assign epsilonIni_2 [3] = epsilonIn_2[1] ^ epsilonIn_2[6] ^ epsilonIn_2[7];
assign epsilonIni_2 [4] = epsilonIn_2[2] ^ epsilonIn_2[6] ^ epsilonIn_2[7];
assign epsilonIni_2 [5] = epsilonIn_2[3] ^ epsilonIn_2[7];
assign epsilonIni_2 [6] = epsilonIn_2[4];
assign epsilonIni_2 [7] = epsilonIn_2[5];
assign epsilonIni_3 [0] = epsilonIn_3[5];
assign epsilonIni_3 [1] = epsilonIn_3[6];
assign epsilonIni_3 [2] = epsilonIn_3[5] ^ epsilonIn_3[7];
assign epsilonIni_3 [3] = epsilonIn_3[0] ^ epsilonIn_3[5] ^ epsilonIn_3[6];
assign epsilonIni_3 [4] = epsilonIn_3[1] ^ epsilonIn_3[5] ^ epsilonIn_3[6] ^ epsilonIn_3[7];
assign epsilonIni_3 [5] = epsilonIn_3[2] ^ epsilonIn_3[6] ^ epsilonIn_3[7];
assign epsilonIni_3 [6] = epsilonIn_3[3] ^ epsilonIn_3[7];
assign epsilonIni_3 [7] = epsilonIn_3[4];
assign epsilonIni_4 [0] = epsilonIn_4[4];
assign epsilonIni_4 [1] = epsilonIn_4[5];
assign epsilonIni_4 [2] = epsilonIn_4[4] ^ epsilonIn_4[6];
assign epsilonIni_4 [3] = epsilonIn_4[4] ^ epsilonIn_4[5] ^ epsilonIn_4[7];
assign epsilonIni_4 [4] = epsilonIn_4[0] ^ epsilonIn_4[4] ^ epsilonIn_4[5] ^ epsilonIn_4[6];
assign epsilonIni_4 [5] = epsilonIn_4[1] ^ epsilonIn_4[5] ^ epsilonIn_4[6] ^ epsilonIn_4[7];
assign epsilonIni_4 [6] = epsilonIn_4[2] ^ epsilonIn_4[6] ^ epsilonIn_4[7];
assign epsilonIni_4 [7] = epsilonIn_4[3] ^ epsilonIn_4[7];
assign epsilonIni_5 [0] = epsilonIn_5[3] ^ epsilonIn_5[7];
assign epsilonIni_5 [1] = epsilonIn_5[4];
assign epsilonIni_5 [2] = epsilonIn_5[3] ^ epsilonIn_5[5] ^ epsilonIn_5[7];
assign epsilonIni_5 [3] = epsilonIn_5[3] ^ epsilonIn_5[4] ^ epsilonIn_5[6] ^ epsilonIn_5[7];
assign epsilonIni_5 [4] = epsilonIn_5[3] ^ epsilonIn_5[4] ^ epsilonIn_5[5];
assign epsilonIni_5 [5] = epsilonIn_5[0] ^ epsilonIn_5[4] ^ epsilonIn_5[5] ^ epsilonIn_5[6];
assign epsilonIni_5 [6] = epsilonIn_5[1] ^ epsilonIn_5[5] ^ epsilonIn_5[6] ^ epsilonIn_5[7];
assign epsilonIni_5 [7] = epsilonIn_5[2] ^ epsilonIn_5[6] ^ epsilonIn_5[7];
assign epsilonIni_6 [0] = epsilonIn_6[2] ^ epsilonIn_6[6] ^ epsilonIn_6[7];
assign epsilonIni_6 [1] = epsilonIn_6[3] ^ epsilonIn_6[7];
assign epsilonIni_6 [2] = epsilonIn_6[2] ^ epsilonIn_6[4] ^ epsilonIn_6[6] ^ epsilonIn_6[7];
assign epsilonIni_6 [3] = epsilonIn_6[2] ^ epsilonIn_6[3] ^ epsilonIn_6[5] ^ epsilonIn_6[6];
assign epsilonIni_6 [4] = epsilonIn_6[2] ^ epsilonIn_6[3] ^ epsilonIn_6[4];
assign epsilonIni_6 [5] = epsilonIn_6[3] ^ epsilonIn_6[4] ^ epsilonIn_6[5];
assign epsilonIni_6 [6] = epsilonIn_6[0] ^ epsilonIn_6[4] ^ epsilonIn_6[5] ^ epsilonIn_6[6];
assign epsilonIni_6 [7] = epsilonIn_6[1] ^ epsilonIn_6[5] ^ epsilonIn_6[6] ^ epsilonIn_6[7];
assign epsilonIni_7 [0] = epsilonIn_7[1] ^ epsilonIn_7[5] ^ epsilonIn_7[6] ^ epsilonIn_7[7];
assign epsilonIni_7 [1] = epsilonIn_7[2] ^ epsilonIn_7[6] ^ epsilonIn_7[7];
assign epsilonIni_7 [2] = epsilonIn_7[1] ^ epsilonIn_7[3] ^ epsilonIn_7[5] ^ epsilonIn_7[6];
assign epsilonIni_7 [3] = epsilonIn_7[1] ^ epsilonIn_7[2] ^ epsilonIn_7[4] ^ epsilonIn_7[5];
assign epsilonIni_7 [4] = epsilonIn_7[1] ^ epsilonIn_7[2] ^ epsilonIn_7[3] ^ epsilonIn_7[7];
assign epsilonIni_7 [5] = epsilonIn_7[2] ^ epsilonIn_7[3] ^ epsilonIn_7[4];
assign epsilonIni_7 [6] = epsilonIn_7[3] ^ epsilonIn_7[4] ^ epsilonIn_7[5];
assign epsilonIni_7 [7] = epsilonIn_7[0] ^ epsilonIn_7[4] ^ epsilonIn_7[5] ^ epsilonIn_7[6];
assign epsilonIni_8 [0] = epsilonIn_8[0] ^ epsilonIn_8[4] ^ epsilonIn_8[5] ^ epsilonIn_8[6];
assign epsilonIni_8 [1] = epsilonIn_8[1] ^ epsilonIn_8[5] ^ epsilonIn_8[6] ^ epsilonIn_8[7];
assign epsilonIni_8 [2] = epsilonIn_8[0] ^ epsilonIn_8[2] ^ epsilonIn_8[4] ^ epsilonIn_8[5] ^ epsilonIn_8[7];
assign epsilonIni_8 [3] = epsilonIn_8[0] ^ epsilonIn_8[1] ^ epsilonIn_8[3] ^ epsilonIn_8[4];
assign epsilonIni_8 [4] = epsilonIn_8[0] ^ epsilonIn_8[1] ^ epsilonIn_8[2] ^ epsilonIn_8[6];
assign epsilonIni_8 [5] = epsilonIn_8[1] ^ epsilonIn_8[2] ^ epsilonIn_8[3] ^ epsilonIn_8[7];
assign epsilonIni_8 [6] = epsilonIn_8[2] ^ epsilonIn_8[3] ^ epsilonIn_8[4];
assign epsilonIni_8 [7] = epsilonIn_8[3] ^ epsilonIn_8[4] ^ epsilonIn_8[5];
assign epsilonIni_9 [0] = epsilonIn_9[3] ^ epsilonIn_9[4] ^ epsilonIn_9[5];
assign epsilonIni_9 [1] = epsilonIn_9[0] ^ epsilonIn_9[4] ^ epsilonIn_9[5] ^ epsilonIn_9[6];
assign epsilonIni_9 [2] = epsilonIn_9[1] ^ epsilonIn_9[3] ^ epsilonIn_9[4] ^ epsilonIn_9[6] ^ epsilonIn_9[7];
assign epsilonIni_9 [3] = epsilonIn_9[0] ^ epsilonIn_9[2] ^ epsilonIn_9[3] ^ epsilonIn_9[7];
assign epsilonIni_9 [4] = epsilonIn_9[0] ^ epsilonIn_9[1] ^ epsilonIn_9[5];
assign epsilonIni_9 [5] = epsilonIn_9[0] ^ epsilonIn_9[1] ^ epsilonIn_9[2] ^ epsilonIn_9[6];
assign epsilonIni_9 [6] = epsilonIn_9[1] ^ epsilonIn_9[2] ^ epsilonIn_9[3] ^ epsilonIn_9[7];
assign epsilonIni_9 [7] = epsilonIn_9[2] ^ epsilonIn_9[3] ^ epsilonIn_9[4];
assign epsilonIni_10 [0] = epsilonIn_10[2] ^ epsilonIn_10[3] ^ epsilonIn_10[4];
assign epsilonIni_10 [1] = epsilonIn_10[3] ^ epsilonIn_10[4] ^ epsilonIn_10[5];
assign epsilonIni_10 [2] = epsilonIn_10[0] ^ epsilonIn_10[2] ^ epsilonIn_10[3] ^ epsilonIn_10[5] ^ epsilonIn_10[6];
assign epsilonIni_10 [3] = epsilonIn_10[1] ^ epsilonIn_10[2] ^ epsilonIn_10[6] ^ epsilonIn_10[7];
assign epsilonIni_10 [4] = epsilonIn_10[0] ^ epsilonIn_10[4] ^ epsilonIn_10[7];
assign epsilonIni_10 [5] = epsilonIn_10[0] ^ epsilonIn_10[1] ^ epsilonIn_10[5];
assign epsilonIni_10 [6] = epsilonIn_10[0] ^ epsilonIn_10[1] ^ epsilonIn_10[2] ^ epsilonIn_10[6];
assign epsilonIni_10 [7] = epsilonIn_10[1] ^ epsilonIn_10[2] ^ epsilonIn_10[3] ^ epsilonIn_10[7];
assign epsilonIni_11 [0] = epsilonIn_11[1] ^ epsilonIn_11[2] ^ epsilonIn_11[3] ^ epsilonIn_11[7];
assign epsilonIni_11 [1] = epsilonIn_11[2] ^ epsilonIn_11[3] ^ epsilonIn_11[4];
assign epsilonIni_11 [2] = epsilonIn_11[1] ^ epsilonIn_11[2] ^ epsilonIn_11[4] ^ epsilonIn_11[5] ^ epsilonIn_11[7];
assign epsilonIni_11 [3] = epsilonIn_11[0] ^ epsilonIn_11[1] ^ epsilonIn_11[5] ^ epsilonIn_11[6] ^ epsilonIn_11[7];
assign epsilonIni_11 [4] = epsilonIn_11[3] ^ epsilonIn_11[6];
assign epsilonIni_11 [5] = epsilonIn_11[0] ^ epsilonIn_11[4] ^ epsilonIn_11[7];
assign epsilonIni_11 [6] = epsilonIn_11[0] ^ epsilonIn_11[1] ^ epsilonIn_11[5];
assign epsilonIni_11 [7] = epsilonIn_11[0] ^ epsilonIn_11[1] ^ epsilonIn_11[2] ^ epsilonIn_11[6];
assign epsilonIni_12 [0] = epsilonIn_12[0] ^ epsilonIn_12[1] ^ epsilonIn_12[2] ^ epsilonIn_12[6];
assign epsilonIni_12 [1] = epsilonIn_12[1] ^ epsilonIn_12[2] ^ epsilonIn_12[3] ^ epsilonIn_12[7];
assign epsilonIni_12 [2] = epsilonIn_12[0] ^ epsilonIn_12[1] ^ epsilonIn_12[3] ^ epsilonIn_12[4] ^ epsilonIn_12[6];
assign epsilonIni_12 [3] = epsilonIn_12[0] ^ epsilonIn_12[4] ^ epsilonIn_12[5] ^ epsilonIn_12[6] ^ epsilonIn_12[7];
assign epsilonIni_12 [4] = epsilonIn_12[2] ^ epsilonIn_12[5] ^ epsilonIn_12[7];
assign epsilonIni_12 [5] = epsilonIn_12[3] ^ epsilonIn_12[6];
assign epsilonIni_12 [6] = epsilonIn_12[0] ^ epsilonIn_12[4] ^ epsilonIn_12[7];
assign epsilonIni_12 [7] = epsilonIn_12[0] ^ epsilonIn_12[1] ^ epsilonIn_12[5];
assign epsilonIni_13 [0] = epsilonIn_13[0] ^ epsilonIn_13[1] ^ epsilonIn_13[5];
assign epsilonIni_13 [1] = epsilonIn_13[0] ^ epsilonIn_13[1] ^ epsilonIn_13[2] ^ epsilonIn_13[6];
assign epsilonIni_13 [2] = epsilonIn_13[0] ^ epsilonIn_13[2] ^ epsilonIn_13[3] ^ epsilonIn_13[5] ^ epsilonIn_13[7];
assign epsilonIni_13 [3] = epsilonIn_13[3] ^ epsilonIn_13[4] ^ epsilonIn_13[5] ^ epsilonIn_13[6];
assign epsilonIni_13 [4] = epsilonIn_13[1] ^ epsilonIn_13[4] ^ epsilonIn_13[6] ^ epsilonIn_13[7];
assign epsilonIni_13 [5] = epsilonIn_13[2] ^ epsilonIn_13[5] ^ epsilonIn_13[7];
assign epsilonIni_13 [6] = epsilonIn_13[3] ^ epsilonIn_13[6];
assign epsilonIni_13 [7] = epsilonIn_13[0] ^ epsilonIn_13[4] ^ epsilonIn_13[7];
assign epsilonIni_14 [0] = epsilonIn_14[0] ^ epsilonIn_14[4] ^ epsilonIn_14[7];
assign epsilonIni_14 [1] = epsilonIn_14[0] ^ epsilonIn_14[1] ^ epsilonIn_14[5];
assign epsilonIni_14 [2] = epsilonIn_14[1] ^ epsilonIn_14[2] ^ epsilonIn_14[4] ^ epsilonIn_14[6] ^ epsilonIn_14[7];
assign epsilonIni_14 [3] = epsilonIn_14[2] ^ epsilonIn_14[3] ^ epsilonIn_14[4] ^ epsilonIn_14[5];
assign epsilonIni_14 [4] = epsilonIn_14[0] ^ epsilonIn_14[3] ^ epsilonIn_14[5] ^ epsilonIn_14[6] ^ epsilonIn_14[7];
assign epsilonIni_14 [5] = epsilonIn_14[1] ^ epsilonIn_14[4] ^ epsilonIn_14[6] ^ epsilonIn_14[7];
assign epsilonIni_14 [6] = epsilonIn_14[2] ^ epsilonIn_14[5] ^ epsilonIn_14[7];
assign epsilonIni_14 [7] = epsilonIn_14[3] ^ epsilonIn_14[6];
assign epsilonIni_15 [0] = epsilonIn_15[3] ^ epsilonIn_15[6];
assign epsilonIni_15 [1] = epsilonIn_15[0] ^ epsilonIn_15[4] ^ epsilonIn_15[7];
assign epsilonIni_15 [2] = epsilonIn_15[0] ^ epsilonIn_15[1] ^ epsilonIn_15[3] ^ epsilonIn_15[5] ^ epsilonIn_15[6];
assign epsilonIni_15 [3] = epsilonIn_15[1] ^ epsilonIn_15[2] ^ epsilonIn_15[3] ^ epsilonIn_15[4] ^ epsilonIn_15[7];
assign epsilonIni_15 [4] = epsilonIn_15[2] ^ epsilonIn_15[4] ^ epsilonIn_15[5] ^ epsilonIn_15[6];
assign epsilonIni_15 [5] = epsilonIn_15[0] ^ epsilonIn_15[3] ^ epsilonIn_15[5] ^ epsilonIn_15[6] ^ epsilonIn_15[7];
assign epsilonIni_15 [6] = epsilonIn_15[1] ^ epsilonIn_15[4] ^ epsilonIn_15[6] ^ epsilonIn_15[7];
assign epsilonIni_15 [7] = epsilonIn_15[2] ^ epsilonIn_15[5] ^ epsilonIn_15[7];
assign epsilonIni_16 [0] = epsilonIn_16[2] ^ epsilonIn_16[5] ^ epsilonIn_16[7];
assign epsilonIni_16 [1] = epsilonIn_16[3] ^ epsilonIn_16[6];
assign epsilonIni_16 [2] = epsilonIn_16[0] ^ epsilonIn_16[2] ^ epsilonIn_16[4] ^ epsilonIn_16[5];
assign epsilonIni_16 [3] = epsilonIn_16[0] ^ epsilonIn_16[1] ^ epsilonIn_16[2] ^ epsilonIn_16[3] ^ epsilonIn_16[6] ^ epsilonIn_16[7];
assign epsilonIni_16 [4] = epsilonIn_16[1] ^ epsilonIn_16[3] ^ epsilonIn_16[4] ^ epsilonIn_16[5];
assign epsilonIni_16 [5] = epsilonIn_16[2] ^ epsilonIn_16[4] ^ epsilonIn_16[5] ^ epsilonIn_16[6];
assign epsilonIni_16 [6] = epsilonIn_16[0] ^ epsilonIn_16[3] ^ epsilonIn_16[5] ^ epsilonIn_16[6] ^ epsilonIn_16[7];
assign epsilonIni_16 [7] = epsilonIn_16[1] ^ epsilonIn_16[4] ^ epsilonIn_16[6] ^ epsilonIn_16[7];
assign epsilonIni_17 [0] = epsilonIn_17[1] ^ epsilonIn_17[4] ^ epsilonIn_17[6] ^ epsilonIn_17[7];
assign epsilonIni_17 [1] = epsilonIn_17[2] ^ epsilonIn_17[5] ^ epsilonIn_17[7];
assign epsilonIni_17 [2] = epsilonIn_17[1] ^ epsilonIn_17[3] ^ epsilonIn_17[4] ^ epsilonIn_17[7];
assign epsilonIni_17 [3] = epsilonIn_17[0] ^ epsilonIn_17[1] ^ epsilonIn_17[2] ^ epsilonIn_17[5] ^ epsilonIn_17[6] ^ epsilonIn_17[7];
assign epsilonIni_17 [4] = epsilonIn_17[0] ^ epsilonIn_17[2] ^ epsilonIn_17[3] ^ epsilonIn_17[4];
assign epsilonIni_17 [5] = epsilonIn_17[1] ^ epsilonIn_17[3] ^ epsilonIn_17[4] ^ epsilonIn_17[5];
assign epsilonIni_17 [6] = epsilonIn_17[2] ^ epsilonIn_17[4] ^ epsilonIn_17[5] ^ epsilonIn_17[6];
assign epsilonIni_17 [7] = epsilonIn_17[0] ^ epsilonIn_17[3] ^ epsilonIn_17[5] ^ epsilonIn_17[6] ^ epsilonIn_17[7];
assign epsilonIni_18 [0] = epsilonIn_18[0] ^ epsilonIn_18[3] ^ epsilonIn_18[5] ^ epsilonIn_18[6] ^ epsilonIn_18[7];
assign epsilonIni_18 [1] = epsilonIn_18[1] ^ epsilonIn_18[4] ^ epsilonIn_18[6] ^ epsilonIn_18[7];
assign epsilonIni_18 [2] = epsilonIn_18[0] ^ epsilonIn_18[2] ^ epsilonIn_18[3] ^ epsilonIn_18[6];
assign epsilonIni_18 [3] = epsilonIn_18[0] ^ epsilonIn_18[1] ^ epsilonIn_18[4] ^ epsilonIn_18[5] ^ epsilonIn_18[6];
assign epsilonIni_18 [4] = epsilonIn_18[1] ^ epsilonIn_18[2] ^ epsilonIn_18[3];
assign epsilonIni_18 [5] = epsilonIn_18[0] ^ epsilonIn_18[2] ^ epsilonIn_18[3] ^ epsilonIn_18[4];
assign epsilonIni_18 [6] = epsilonIn_18[1] ^ epsilonIn_18[3] ^ epsilonIn_18[4] ^ epsilonIn_18[5];
assign epsilonIni_18 [7] = epsilonIn_18[2] ^ epsilonIn_18[4] ^ epsilonIn_18[5] ^ epsilonIn_18[6];
assign epsilonIni_19 [0] = epsilonIn_19[2] ^ epsilonIn_19[4] ^ epsilonIn_19[5] ^ epsilonIn_19[6];
assign epsilonIni_19 [1] = epsilonIn_19[0] ^ epsilonIn_19[3] ^ epsilonIn_19[5] ^ epsilonIn_19[6] ^ epsilonIn_19[7];
assign epsilonIni_19 [2] = epsilonIn_19[1] ^ epsilonIn_19[2] ^ epsilonIn_19[5] ^ epsilonIn_19[7];
assign epsilonIni_19 [3] = epsilonIn_19[0] ^ epsilonIn_19[3] ^ epsilonIn_19[4] ^ epsilonIn_19[5];
assign epsilonIni_19 [4] = epsilonIn_19[0] ^ epsilonIn_19[1] ^ epsilonIn_19[2];
assign epsilonIni_19 [5] = epsilonIn_19[1] ^ epsilonIn_19[2] ^ epsilonIn_19[3];
assign epsilonIni_19 [6] = epsilonIn_19[0] ^ epsilonIn_19[2] ^ epsilonIn_19[3] ^ epsilonIn_19[4];
assign epsilonIni_19 [7] = epsilonIn_19[1] ^ epsilonIn_19[3] ^ epsilonIn_19[4] ^ epsilonIn_19[5];
assign epsilonIni_20 [0] = epsilonIn_20[1] ^ epsilonIn_20[3] ^ epsilonIn_20[4] ^ epsilonIn_20[5];
assign epsilonIni_20 [1] = epsilonIn_20[2] ^ epsilonIn_20[4] ^ epsilonIn_20[5] ^ epsilonIn_20[6];
assign epsilonIni_20 [2] = epsilonIn_20[0] ^ epsilonIn_20[1] ^ epsilonIn_20[4] ^ epsilonIn_20[6] ^ epsilonIn_20[7];
assign epsilonIni_20 [3] = epsilonIn_20[2] ^ epsilonIn_20[3] ^ epsilonIn_20[4] ^ epsilonIn_20[7];
assign epsilonIni_20 [4] = epsilonIn_20[0] ^ epsilonIn_20[1];
assign epsilonIni_20 [5] = epsilonIn_20[0] ^ epsilonIn_20[1] ^ epsilonIn_20[2];
assign epsilonIni_20 [6] = epsilonIn_20[1] ^ epsilonIn_20[2] ^ epsilonIn_20[3];
assign epsilonIni_20 [7] = epsilonIn_20[0] ^ epsilonIn_20[2] ^ epsilonIn_20[3] ^ epsilonIn_20[4];
assign epsilonIni_21 [0] = epsilonIn_21[0] ^ epsilonIn_21[2] ^ epsilonIn_21[3] ^ epsilonIn_21[4];
assign epsilonIni_21 [1] = epsilonIn_21[1] ^ epsilonIn_21[3] ^ epsilonIn_21[4] ^ epsilonIn_21[5];
assign epsilonIni_21 [2] = epsilonIn_21[0] ^ epsilonIn_21[3] ^ epsilonIn_21[5] ^ epsilonIn_21[6];
assign epsilonIni_21 [3] = epsilonIn_21[1] ^ epsilonIn_21[2] ^ epsilonIn_21[3] ^ epsilonIn_21[6] ^ epsilonIn_21[7];
assign epsilonIni_21 [4] = epsilonIn_21[0] ^ epsilonIn_21[7];
assign epsilonIni_21 [5] = epsilonIn_21[0] ^ epsilonIn_21[1];
assign epsilonIni_21 [6] = epsilonIn_21[0] ^ epsilonIn_21[1] ^ epsilonIn_21[2];
assign epsilonIni_21 [7] = epsilonIn_21[1] ^ epsilonIn_21[2] ^ epsilonIn_21[3];
assign epsilonIni_22 [0] = epsilonIn_22[1] ^ epsilonIn_22[2] ^ epsilonIn_22[3];
assign epsilonIni_22 [1] = epsilonIn_22[0] ^ epsilonIn_22[2] ^ epsilonIn_22[3] ^ epsilonIn_22[4];
assign epsilonIni_22 [2] = epsilonIn_22[2] ^ epsilonIn_22[4] ^ epsilonIn_22[5];
assign epsilonIni_22 [3] = epsilonIn_22[0] ^ epsilonIn_22[1] ^ epsilonIn_22[2] ^ epsilonIn_22[5] ^ epsilonIn_22[6];
assign epsilonIni_22 [4] = epsilonIn_22[6] ^ epsilonIn_22[7];
assign epsilonIni_22 [5] = epsilonIn_22[0] ^ epsilonIn_22[7];
assign epsilonIni_22 [6] = epsilonIn_22[0] ^ epsilonIn_22[1];
assign epsilonIni_22 [7] = epsilonIn_22[0] ^ epsilonIn_22[1] ^ epsilonIn_22[2];
 
 
 
//------------------------------------------------------------------------
//- epsilonNew
//------------------------------------------------------------------------
reg [7:0] epsilonReg_0;
reg [7:0] epsilonReg_1;
reg [7:0] epsilonReg_2;
reg [7:0] epsilonReg_3;
reg [7:0] epsilonReg_4;
reg [7:0] epsilonReg_5;
reg [7:0] epsilonReg_6;
reg [7:0] epsilonReg_7;
reg [7:0] epsilonReg_8;
reg [7:0] epsilonReg_9;
reg [7:0] epsilonReg_10;
reg [7:0] epsilonReg_11;
reg [7:0] epsilonReg_12;
reg [7:0] epsilonReg_13;
reg [7:0] epsilonReg_14;
reg [7:0] epsilonReg_15;
reg [7:0] epsilonReg_16;
reg [7:0] epsilonReg_17;
reg [7:0] epsilonReg_18;
reg [7:0] epsilonReg_19;
reg [7:0] epsilonReg_20;
reg [7:0] epsilonReg_21;
reg [7:0] epsilonReg_22;
wire [7:0] epsilonNew_0;
wire [7:0] epsilonNew_1;
wire [7:0] epsilonNew_2;
wire [7:0] epsilonNew_3;
wire [7:0] epsilonNew_4;
wire [7:0] epsilonNew_5;
wire [7:0] epsilonNew_6;
wire [7:0] epsilonNew_7;
wire [7:0] epsilonNew_8;
wire [7:0] epsilonNew_9;
wire [7:0] epsilonNew_10;
wire [7:0] epsilonNew_11;
wire [7:0] epsilonNew_12;
wire [7:0] epsilonNew_13;
wire [7:0] epsilonNew_14;
wire [7:0] epsilonNew_15;
wire [7:0] epsilonNew_16;
wire [7:0] epsilonNew_17;
wire [7:0] epsilonNew_18;
wire [7:0] epsilonNew_19;
wire [7:0] epsilonNew_20;
wire [7:0] epsilonNew_21;
wire [7:0] epsilonNew_22;
 
 
assign epsilonNew_0 [0] = epsilonReg_0[0];
assign epsilonNew_0 [1] = epsilonReg_0[1];
assign epsilonNew_0 [2] = epsilonReg_0[2];
assign epsilonNew_0 [3] = epsilonReg_0[3];
assign epsilonNew_0 [4] = epsilonReg_0[4];
assign epsilonNew_0 [5] = epsilonReg_0[5];
assign epsilonNew_0 [6] = epsilonReg_0[6];
assign epsilonNew_0 [7] = epsilonReg_0[7];
assign epsilonNew_1 [0] = epsilonReg_1[7];
assign epsilonNew_1 [1] = epsilonReg_1[0];
assign epsilonNew_1 [2] = epsilonReg_1[1] ^ epsilonReg_1[7];
assign epsilonNew_1 [3] = epsilonReg_1[2] ^ epsilonReg_1[7];
assign epsilonNew_1 [4] = epsilonReg_1[3] ^ epsilonReg_1[7];
assign epsilonNew_1 [5] = epsilonReg_1[4];
assign epsilonNew_1 [6] = epsilonReg_1[5];
assign epsilonNew_1 [7] = epsilonReg_1[6];
assign epsilonNew_2 [0] = epsilonReg_2[6];
assign epsilonNew_2 [1] = epsilonReg_2[7];
assign epsilonNew_2 [2] = epsilonReg_2[0] ^ epsilonReg_2[6];
assign epsilonNew_2 [3] = epsilonReg_2[1] ^ epsilonReg_2[6] ^ epsilonReg_2[7];
assign epsilonNew_2 [4] = epsilonReg_2[2] ^ epsilonReg_2[6] ^ epsilonReg_2[7];
assign epsilonNew_2 [5] = epsilonReg_2[3] ^ epsilonReg_2[7];
assign epsilonNew_2 [6] = epsilonReg_2[4];
assign epsilonNew_2 [7] = epsilonReg_2[5];
assign epsilonNew_3 [0] = epsilonReg_3[5];
assign epsilonNew_3 [1] = epsilonReg_3[6];
assign epsilonNew_3 [2] = epsilonReg_3[5] ^ epsilonReg_3[7];
assign epsilonNew_3 [3] = epsilonReg_3[0] ^ epsilonReg_3[5] ^ epsilonReg_3[6];
assign epsilonNew_3 [4] = epsilonReg_3[1] ^ epsilonReg_3[5] ^ epsilonReg_3[6] ^ epsilonReg_3[7];
assign epsilonNew_3 [5] = epsilonReg_3[2] ^ epsilonReg_3[6] ^ epsilonReg_3[7];
assign epsilonNew_3 [6] = epsilonReg_3[3] ^ epsilonReg_3[7];
assign epsilonNew_3 [7] = epsilonReg_3[4];
assign epsilonNew_4 [0] = epsilonReg_4[4];
assign epsilonNew_4 [1] = epsilonReg_4[5];
assign epsilonNew_4 [2] = epsilonReg_4[4] ^ epsilonReg_4[6];
assign epsilonNew_4 [3] = epsilonReg_4[4] ^ epsilonReg_4[5] ^ epsilonReg_4[7];
assign epsilonNew_4 [4] = epsilonReg_4[0] ^ epsilonReg_4[4] ^ epsilonReg_4[5] ^ epsilonReg_4[6];
assign epsilonNew_4 [5] = epsilonReg_4[1] ^ epsilonReg_4[5] ^ epsilonReg_4[6] ^ epsilonReg_4[7];
assign epsilonNew_4 [6] = epsilonReg_4[2] ^ epsilonReg_4[6] ^ epsilonReg_4[7];
assign epsilonNew_4 [7] = epsilonReg_4[3] ^ epsilonReg_4[7];
assign epsilonNew_5 [0] = epsilonReg_5[3] ^ epsilonReg_5[7];
assign epsilonNew_5 [1] = epsilonReg_5[4];
assign epsilonNew_5 [2] = epsilonReg_5[3] ^ epsilonReg_5[5] ^ epsilonReg_5[7];
assign epsilonNew_5 [3] = epsilonReg_5[3] ^ epsilonReg_5[4] ^ epsilonReg_5[6] ^ epsilonReg_5[7];
assign epsilonNew_5 [4] = epsilonReg_5[3] ^ epsilonReg_5[4] ^ epsilonReg_5[5];
assign epsilonNew_5 [5] = epsilonReg_5[0] ^ epsilonReg_5[4] ^ epsilonReg_5[5] ^ epsilonReg_5[6];
assign epsilonNew_5 [6] = epsilonReg_5[1] ^ epsilonReg_5[5] ^ epsilonReg_5[6] ^ epsilonReg_5[7];
assign epsilonNew_5 [7] = epsilonReg_5[2] ^ epsilonReg_5[6] ^ epsilonReg_5[7];
assign epsilonNew_6 [0] = epsilonReg_6[2] ^ epsilonReg_6[6] ^ epsilonReg_6[7];
assign epsilonNew_6 [1] = epsilonReg_6[3] ^ epsilonReg_6[7];
assign epsilonNew_6 [2] = epsilonReg_6[2] ^ epsilonReg_6[4] ^ epsilonReg_6[6] ^ epsilonReg_6[7];
assign epsilonNew_6 [3] = epsilonReg_6[2] ^ epsilonReg_6[3] ^ epsilonReg_6[5] ^ epsilonReg_6[6];
assign epsilonNew_6 [4] = epsilonReg_6[2] ^ epsilonReg_6[3] ^ epsilonReg_6[4];
assign epsilonNew_6 [5] = epsilonReg_6[3] ^ epsilonReg_6[4] ^ epsilonReg_6[5];
assign epsilonNew_6 [6] = epsilonReg_6[0] ^ epsilonReg_6[4] ^ epsilonReg_6[5] ^ epsilonReg_6[6];
assign epsilonNew_6 [7] = epsilonReg_6[1] ^ epsilonReg_6[5] ^ epsilonReg_6[6] ^ epsilonReg_6[7];
assign epsilonNew_7 [0] = epsilonReg_7[1] ^ epsilonReg_7[5] ^ epsilonReg_7[6] ^ epsilonReg_7[7];
assign epsilonNew_7 [1] = epsilonReg_7[2] ^ epsilonReg_7[6] ^ epsilonReg_7[7];
assign epsilonNew_7 [2] = epsilonReg_7[1] ^ epsilonReg_7[3] ^ epsilonReg_7[5] ^ epsilonReg_7[6];
assign epsilonNew_7 [3] = epsilonReg_7[1] ^ epsilonReg_7[2] ^ epsilonReg_7[4] ^ epsilonReg_7[5];
assign epsilonNew_7 [4] = epsilonReg_7[1] ^ epsilonReg_7[2] ^ epsilonReg_7[3] ^ epsilonReg_7[7];
assign epsilonNew_7 [5] = epsilonReg_7[2] ^ epsilonReg_7[3] ^ epsilonReg_7[4];
assign epsilonNew_7 [6] = epsilonReg_7[3] ^ epsilonReg_7[4] ^ epsilonReg_7[5];
assign epsilonNew_7 [7] = epsilonReg_7[0] ^ epsilonReg_7[4] ^ epsilonReg_7[5] ^ epsilonReg_7[6];
assign epsilonNew_8 [0] = epsilonReg_8[0] ^ epsilonReg_8[4] ^ epsilonReg_8[5] ^ epsilonReg_8[6];
assign epsilonNew_8 [1] = epsilonReg_8[1] ^ epsilonReg_8[5] ^ epsilonReg_8[6] ^ epsilonReg_8[7];
assign epsilonNew_8 [2] = epsilonReg_8[0] ^ epsilonReg_8[2] ^ epsilonReg_8[4] ^ epsilonReg_8[5] ^ epsilonReg_8[7];
assign epsilonNew_8 [3] = epsilonReg_8[0] ^ epsilonReg_8[1] ^ epsilonReg_8[3] ^ epsilonReg_8[4];
assign epsilonNew_8 [4] = epsilonReg_8[0] ^ epsilonReg_8[1] ^ epsilonReg_8[2] ^ epsilonReg_8[6];
assign epsilonNew_8 [5] = epsilonReg_8[1] ^ epsilonReg_8[2] ^ epsilonReg_8[3] ^ epsilonReg_8[7];
assign epsilonNew_8 [6] = epsilonReg_8[2] ^ epsilonReg_8[3] ^ epsilonReg_8[4];
assign epsilonNew_8 [7] = epsilonReg_8[3] ^ epsilonReg_8[4] ^ epsilonReg_8[5];
assign epsilonNew_9 [0] = epsilonReg_9[3] ^ epsilonReg_9[4] ^ epsilonReg_9[5];
assign epsilonNew_9 [1] = epsilonReg_9[0] ^ epsilonReg_9[4] ^ epsilonReg_9[5] ^ epsilonReg_9[6];
assign epsilonNew_9 [2] = epsilonReg_9[1] ^ epsilonReg_9[3] ^ epsilonReg_9[4] ^ epsilonReg_9[6] ^ epsilonReg_9[7];
assign epsilonNew_9 [3] = epsilonReg_9[0] ^ epsilonReg_9[2] ^ epsilonReg_9[3] ^ epsilonReg_9[7];
assign epsilonNew_9 [4] = epsilonReg_9[0] ^ epsilonReg_9[1] ^ epsilonReg_9[5];
assign epsilonNew_9 [5] = epsilonReg_9[0] ^ epsilonReg_9[1] ^ epsilonReg_9[2] ^ epsilonReg_9[6];
assign epsilonNew_9 [6] = epsilonReg_9[1] ^ epsilonReg_9[2] ^ epsilonReg_9[3] ^ epsilonReg_9[7];
assign epsilonNew_9 [7] = epsilonReg_9[2] ^ epsilonReg_9[3] ^ epsilonReg_9[4];
assign epsilonNew_10 [0] = epsilonReg_10[2] ^ epsilonReg_10[3] ^ epsilonReg_10[4];
assign epsilonNew_10 [1] = epsilonReg_10[3] ^ epsilonReg_10[4] ^ epsilonReg_10[5];
assign epsilonNew_10 [2] = epsilonReg_10[0] ^ epsilonReg_10[2] ^ epsilonReg_10[3] ^ epsilonReg_10[5] ^ epsilonReg_10[6];
assign epsilonNew_10 [3] = epsilonReg_10[1] ^ epsilonReg_10[2] ^ epsilonReg_10[6] ^ epsilonReg_10[7];
assign epsilonNew_10 [4] = epsilonReg_10[0] ^ epsilonReg_10[4] ^ epsilonReg_10[7];
assign epsilonNew_10 [5] = epsilonReg_10[0] ^ epsilonReg_10[1] ^ epsilonReg_10[5];
assign epsilonNew_10 [6] = epsilonReg_10[0] ^ epsilonReg_10[1] ^ epsilonReg_10[2] ^ epsilonReg_10[6];
assign epsilonNew_10 [7] = epsilonReg_10[1] ^ epsilonReg_10[2] ^ epsilonReg_10[3] ^ epsilonReg_10[7];
assign epsilonNew_11 [0] = epsilonReg_11[1] ^ epsilonReg_11[2] ^ epsilonReg_11[3] ^ epsilonReg_11[7];
assign epsilonNew_11 [1] = epsilonReg_11[2] ^ epsilonReg_11[3] ^ epsilonReg_11[4];
assign epsilonNew_11 [2] = epsilonReg_11[1] ^ epsilonReg_11[2] ^ epsilonReg_11[4] ^ epsilonReg_11[5] ^ epsilonReg_11[7];
assign epsilonNew_11 [3] = epsilonReg_11[0] ^ epsilonReg_11[1] ^ epsilonReg_11[5] ^ epsilonReg_11[6] ^ epsilonReg_11[7];
assign epsilonNew_11 [4] = epsilonReg_11[3] ^ epsilonReg_11[6];
assign epsilonNew_11 [5] = epsilonReg_11[0] ^ epsilonReg_11[4] ^ epsilonReg_11[7];
assign epsilonNew_11 [6] = epsilonReg_11[0] ^ epsilonReg_11[1] ^ epsilonReg_11[5];
assign epsilonNew_11 [7] = epsilonReg_11[0] ^ epsilonReg_11[1] ^ epsilonReg_11[2] ^ epsilonReg_11[6];
assign epsilonNew_12 [0] = epsilonReg_12[0] ^ epsilonReg_12[1] ^ epsilonReg_12[2] ^ epsilonReg_12[6];
assign epsilonNew_12 [1] = epsilonReg_12[1] ^ epsilonReg_12[2] ^ epsilonReg_12[3] ^ epsilonReg_12[7];
assign epsilonNew_12 [2] = epsilonReg_12[0] ^ epsilonReg_12[1] ^ epsilonReg_12[3] ^ epsilonReg_12[4] ^ epsilonReg_12[6];
assign epsilonNew_12 [3] = epsilonReg_12[0] ^ epsilonReg_12[4] ^ epsilonReg_12[5] ^ epsilonReg_12[6] ^ epsilonReg_12[7];
assign epsilonNew_12 [4] = epsilonReg_12[2] ^ epsilonReg_12[5] ^ epsilonReg_12[7];
assign epsilonNew_12 [5] = epsilonReg_12[3] ^ epsilonReg_12[6];
assign epsilonNew_12 [6] = epsilonReg_12[0] ^ epsilonReg_12[4] ^ epsilonReg_12[7];
assign epsilonNew_12 [7] = epsilonReg_12[0] ^ epsilonReg_12[1] ^ epsilonReg_12[5];
assign epsilonNew_13 [0] = epsilonReg_13[0] ^ epsilonReg_13[1] ^ epsilonReg_13[5];
assign epsilonNew_13 [1] = epsilonReg_13[0] ^ epsilonReg_13[1] ^ epsilonReg_13[2] ^ epsilonReg_13[6];
assign epsilonNew_13 [2] = epsilonReg_13[0] ^ epsilonReg_13[2] ^ epsilonReg_13[3] ^ epsilonReg_13[5] ^ epsilonReg_13[7];
assign epsilonNew_13 [3] = epsilonReg_13[3] ^ epsilonReg_13[4] ^ epsilonReg_13[5] ^ epsilonReg_13[6];
assign epsilonNew_13 [4] = epsilonReg_13[1] ^ epsilonReg_13[4] ^ epsilonReg_13[6] ^ epsilonReg_13[7];
assign epsilonNew_13 [5] = epsilonReg_13[2] ^ epsilonReg_13[5] ^ epsilonReg_13[7];
assign epsilonNew_13 [6] = epsilonReg_13[3] ^ epsilonReg_13[6];
assign epsilonNew_13 [7] = epsilonReg_13[0] ^ epsilonReg_13[4] ^ epsilonReg_13[7];
assign epsilonNew_14 [0] = epsilonReg_14[0] ^ epsilonReg_14[4] ^ epsilonReg_14[7];
assign epsilonNew_14 [1] = epsilonReg_14[0] ^ epsilonReg_14[1] ^ epsilonReg_14[5];
assign epsilonNew_14 [2] = epsilonReg_14[1] ^ epsilonReg_14[2] ^ epsilonReg_14[4] ^ epsilonReg_14[6] ^ epsilonReg_14[7];
assign epsilonNew_14 [3] = epsilonReg_14[2] ^ epsilonReg_14[3] ^ epsilonReg_14[4] ^ epsilonReg_14[5];
assign epsilonNew_14 [4] = epsilonReg_14[0] ^ epsilonReg_14[3] ^ epsilonReg_14[5] ^ epsilonReg_14[6] ^ epsilonReg_14[7];
assign epsilonNew_14 [5] = epsilonReg_14[1] ^ epsilonReg_14[4] ^ epsilonReg_14[6] ^ epsilonReg_14[7];
assign epsilonNew_14 [6] = epsilonReg_14[2] ^ epsilonReg_14[5] ^ epsilonReg_14[7];
assign epsilonNew_14 [7] = epsilonReg_14[3] ^ epsilonReg_14[6];
assign epsilonNew_15 [0] = epsilonReg_15[3] ^ epsilonReg_15[6];
assign epsilonNew_15 [1] = epsilonReg_15[0] ^ epsilonReg_15[4] ^ epsilonReg_15[7];
assign epsilonNew_15 [2] = epsilonReg_15[0] ^ epsilonReg_15[1] ^ epsilonReg_15[3] ^ epsilonReg_15[5] ^ epsilonReg_15[6];
assign epsilonNew_15 [3] = epsilonReg_15[1] ^ epsilonReg_15[2] ^ epsilonReg_15[3] ^ epsilonReg_15[4] ^ epsilonReg_15[7];
assign epsilonNew_15 [4] = epsilonReg_15[2] ^ epsilonReg_15[4] ^ epsilonReg_15[5] ^ epsilonReg_15[6];
assign epsilonNew_15 [5] = epsilonReg_15[0] ^ epsilonReg_15[3] ^ epsilonReg_15[5] ^ epsilonReg_15[6] ^ epsilonReg_15[7];
assign epsilonNew_15 [6] = epsilonReg_15[1] ^ epsilonReg_15[4] ^ epsilonReg_15[6] ^ epsilonReg_15[7];
assign epsilonNew_15 [7] = epsilonReg_15[2] ^ epsilonReg_15[5] ^ epsilonReg_15[7];
assign epsilonNew_16 [0] = epsilonReg_16[2] ^ epsilonReg_16[5] ^ epsilonReg_16[7];
assign epsilonNew_16 [1] = epsilonReg_16[3] ^ epsilonReg_16[6];
assign epsilonNew_16 [2] = epsilonReg_16[0] ^ epsilonReg_16[2] ^ epsilonReg_16[4] ^ epsilonReg_16[5];
assign epsilonNew_16 [3] = epsilonReg_16[0] ^ epsilonReg_16[1] ^ epsilonReg_16[2] ^ epsilonReg_16[3] ^ epsilonReg_16[6] ^ epsilonReg_16[7];
assign epsilonNew_16 [4] = epsilonReg_16[1] ^ epsilonReg_16[3] ^ epsilonReg_16[4] ^ epsilonReg_16[5];
assign epsilonNew_16 [5] = epsilonReg_16[2] ^ epsilonReg_16[4] ^ epsilonReg_16[5] ^ epsilonReg_16[6];
assign epsilonNew_16 [6] = epsilonReg_16[0] ^ epsilonReg_16[3] ^ epsilonReg_16[5] ^ epsilonReg_16[6] ^ epsilonReg_16[7];
assign epsilonNew_16 [7] = epsilonReg_16[1] ^ epsilonReg_16[4] ^ epsilonReg_16[6] ^ epsilonReg_16[7];
assign epsilonNew_17 [0] = epsilonReg_17[1] ^ epsilonReg_17[4] ^ epsilonReg_17[6] ^ epsilonReg_17[7];
assign epsilonNew_17 [1] = epsilonReg_17[2] ^ epsilonReg_17[5] ^ epsilonReg_17[7];
assign epsilonNew_17 [2] = epsilonReg_17[1] ^ epsilonReg_17[3] ^ epsilonReg_17[4] ^ epsilonReg_17[7];
assign epsilonNew_17 [3] = epsilonReg_17[0] ^ epsilonReg_17[1] ^ epsilonReg_17[2] ^ epsilonReg_17[5] ^ epsilonReg_17[6] ^ epsilonReg_17[7];
assign epsilonNew_17 [4] = epsilonReg_17[0] ^ epsilonReg_17[2] ^ epsilonReg_17[3] ^ epsilonReg_17[4];
assign epsilonNew_17 [5] = epsilonReg_17[1] ^ epsilonReg_17[3] ^ epsilonReg_17[4] ^ epsilonReg_17[5];
assign epsilonNew_17 [6] = epsilonReg_17[2] ^ epsilonReg_17[4] ^ epsilonReg_17[5] ^ epsilonReg_17[6];
assign epsilonNew_17 [7] = epsilonReg_17[0] ^ epsilonReg_17[3] ^ epsilonReg_17[5] ^ epsilonReg_17[6] ^ epsilonReg_17[7];
assign epsilonNew_18 [0] = epsilonReg_18[0] ^ epsilonReg_18[3] ^ epsilonReg_18[5] ^ epsilonReg_18[6] ^ epsilonReg_18[7];
assign epsilonNew_18 [1] = epsilonReg_18[1] ^ epsilonReg_18[4] ^ epsilonReg_18[6] ^ epsilonReg_18[7];
assign epsilonNew_18 [2] = epsilonReg_18[0] ^ epsilonReg_18[2] ^ epsilonReg_18[3] ^ epsilonReg_18[6];
assign epsilonNew_18 [3] = epsilonReg_18[0] ^ epsilonReg_18[1] ^ epsilonReg_18[4] ^ epsilonReg_18[5] ^ epsilonReg_18[6];
assign epsilonNew_18 [4] = epsilonReg_18[1] ^ epsilonReg_18[2] ^ epsilonReg_18[3];
assign epsilonNew_18 [5] = epsilonReg_18[0] ^ epsilonReg_18[2] ^ epsilonReg_18[3] ^ epsilonReg_18[4];
assign epsilonNew_18 [6] = epsilonReg_18[1] ^ epsilonReg_18[3] ^ epsilonReg_18[4] ^ epsilonReg_18[5];
assign epsilonNew_18 [7] = epsilonReg_18[2] ^ epsilonReg_18[4] ^ epsilonReg_18[5] ^ epsilonReg_18[6];
assign epsilonNew_19 [0] = epsilonReg_19[2] ^ epsilonReg_19[4] ^ epsilonReg_19[5] ^ epsilonReg_19[6];
assign epsilonNew_19 [1] = epsilonReg_19[0] ^ epsilonReg_19[3] ^ epsilonReg_19[5] ^ epsilonReg_19[6] ^ epsilonReg_19[7];
assign epsilonNew_19 [2] = epsilonReg_19[1] ^ epsilonReg_19[2] ^ epsilonReg_19[5] ^ epsilonReg_19[7];
assign epsilonNew_19 [3] = epsilonReg_19[0] ^ epsilonReg_19[3] ^ epsilonReg_19[4] ^ epsilonReg_19[5];
assign epsilonNew_19 [4] = epsilonReg_19[0] ^ epsilonReg_19[1] ^ epsilonReg_19[2];
assign epsilonNew_19 [5] = epsilonReg_19[1] ^ epsilonReg_19[2] ^ epsilonReg_19[3];
assign epsilonNew_19 [6] = epsilonReg_19[0] ^ epsilonReg_19[2] ^ epsilonReg_19[3] ^ epsilonReg_19[4];
assign epsilonNew_19 [7] = epsilonReg_19[1] ^ epsilonReg_19[3] ^ epsilonReg_19[4] ^ epsilonReg_19[5];
assign epsilonNew_20 [0] = epsilonReg_20[1] ^ epsilonReg_20[3] ^ epsilonReg_20[4] ^ epsilonReg_20[5];
assign epsilonNew_20 [1] = epsilonReg_20[2] ^ epsilonReg_20[4] ^ epsilonReg_20[5] ^ epsilonReg_20[6];
assign epsilonNew_20 [2] = epsilonReg_20[0] ^ epsilonReg_20[1] ^ epsilonReg_20[4] ^ epsilonReg_20[6] ^ epsilonReg_20[7];
assign epsilonNew_20 [3] = epsilonReg_20[2] ^ epsilonReg_20[3] ^ epsilonReg_20[4] ^ epsilonReg_20[7];
assign epsilonNew_20 [4] = epsilonReg_20[0] ^ epsilonReg_20[1];
assign epsilonNew_20 [5] = epsilonReg_20[0] ^ epsilonReg_20[1] ^ epsilonReg_20[2];
assign epsilonNew_20 [6] = epsilonReg_20[1] ^ epsilonReg_20[2] ^ epsilonReg_20[3];
assign epsilonNew_20 [7] = epsilonReg_20[0] ^ epsilonReg_20[2] ^ epsilonReg_20[3] ^ epsilonReg_20[4];
assign epsilonNew_21 [0] = epsilonReg_21[0] ^ epsilonReg_21[2] ^ epsilonReg_21[3] ^ epsilonReg_21[4];
assign epsilonNew_21 [1] = epsilonReg_21[1] ^ epsilonReg_21[3] ^ epsilonReg_21[4] ^ epsilonReg_21[5];
assign epsilonNew_21 [2] = epsilonReg_21[0] ^ epsilonReg_21[3] ^ epsilonReg_21[5] ^ epsilonReg_21[6];
assign epsilonNew_21 [3] = epsilonReg_21[1] ^ epsilonReg_21[2] ^ epsilonReg_21[3] ^ epsilonReg_21[6] ^ epsilonReg_21[7];
assign epsilonNew_21 [4] = epsilonReg_21[0] ^ epsilonReg_21[7];
assign epsilonNew_21 [5] = epsilonReg_21[0] ^ epsilonReg_21[1];
assign epsilonNew_21 [6] = epsilonReg_21[0] ^ epsilonReg_21[1] ^ epsilonReg_21[2];
assign epsilonNew_21 [7] = epsilonReg_21[1] ^ epsilonReg_21[2] ^ epsilonReg_21[3];
assign epsilonNew_22 [0] = epsilonReg_22[1] ^ epsilonReg_22[2] ^ epsilonReg_22[3];
assign epsilonNew_22 [1] = epsilonReg_22[0] ^ epsilonReg_22[2] ^ epsilonReg_22[3] ^ epsilonReg_22[4];
assign epsilonNew_22 [2] = epsilonReg_22[2] ^ epsilonReg_22[4] ^ epsilonReg_22[5];
assign epsilonNew_22 [3] = epsilonReg_22[0] ^ epsilonReg_22[1] ^ epsilonReg_22[2] ^ epsilonReg_22[5] ^ epsilonReg_22[6];
assign epsilonNew_22 [4] = epsilonReg_22[6] ^ epsilonReg_22[7];
assign epsilonNew_22 [5] = epsilonReg_22[0] ^ epsilonReg_22[7];
assign epsilonNew_22 [6] = epsilonReg_22[0] ^ epsilonReg_22[1];
assign epsilonNew_22 [7] = epsilonReg_22[0] ^ epsilonReg_22[1] ^ epsilonReg_22[2];
 
 
 
//------------------------------------------------------------------
// + epsilonReg_0,..., epsilonReg_22
//- registers
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= 8'd0;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
epsilonReg_0 [7:0] <= epsilonIni_0 [7:0];
epsilonReg_1 [7:0] <= epsilonIni_1 [7:0];
epsilonReg_2 [7:0] <= epsilonIni_2 [7:0];
epsilonReg_3 [7:0] <= epsilonIni_3 [7:0];
epsilonReg_4 [7:0] <= epsilonIni_4 [7:0];
epsilonReg_5 [7:0] <= epsilonIni_5 [7:0];
epsilonReg_6 [7:0] <= epsilonIni_6 [7:0];
epsilonReg_7 [7:0] <= epsilonIni_7 [7:0];
epsilonReg_8 [7:0] <= epsilonIni_8 [7:0];
epsilonReg_9 [7:0] <= epsilonIni_9 [7:0];
epsilonReg_10 [7:0] <= epsilonIni_10 [7:0];
epsilonReg_11 [7:0] <= epsilonIni_11 [7:0];
epsilonReg_12 [7:0] <= epsilonIni_12 [7:0];
epsilonReg_13 [7:0] <= epsilonIni_13 [7:0];
epsilonReg_14 [7:0] <= epsilonIni_14 [7:0];
epsilonReg_15 [7:0] <= epsilonIni_15 [7:0];
epsilonReg_16 [7:0] <= epsilonIni_16 [7:0];
epsilonReg_17 [7:0] <= epsilonIni_17 [7:0];
epsilonReg_18 [7:0] <= epsilonIni_18 [7:0];
epsilonReg_19 [7:0] <= epsilonIni_19 [7:0];
epsilonReg_20 [7:0] <= epsilonIni_20 [7:0];
epsilonReg_21 [7:0] <= epsilonIni_21 [7:0];
epsilonReg_22 [7:0] <= epsilonIni_22 [7:0];
end
else begin
epsilonReg_0 [7:0] <= epsilonNew_0 [7:0];
epsilonReg_1 [7:0] <= epsilonNew_1 [7:0];
epsilonReg_2 [7:0] <= epsilonNew_2 [7:0];
epsilonReg_3 [7:0] <= epsilonNew_3 [7:0];
epsilonReg_4 [7:0] <= epsilonNew_4 [7:0];
epsilonReg_5 [7:0] <= epsilonNew_5 [7:0];
epsilonReg_6 [7:0] <= epsilonNew_6 [7:0];
epsilonReg_7 [7:0] <= epsilonNew_7 [7:0];
epsilonReg_8 [7:0] <= epsilonNew_8 [7:0];
epsilonReg_9 [7:0] <= epsilonNew_9 [7:0];
epsilonReg_10 [7:0] <= epsilonNew_10 [7:0];
epsilonReg_11 [7:0] <= epsilonNew_11 [7:0];
epsilonReg_12 [7:0] <= epsilonNew_12 [7:0];
epsilonReg_13 [7:0] <= epsilonNew_13 [7:0];
epsilonReg_14 [7:0] <= epsilonNew_14 [7:0];
epsilonReg_15 [7:0] <= epsilonNew_15 [7:0];
epsilonReg_16 [7:0] <= epsilonNew_16 [7:0];
epsilonReg_17 [7:0] <= epsilonNew_17 [7:0];
epsilonReg_18 [7:0] <= epsilonNew_18 [7:0];
epsilonReg_19 [7:0] <= epsilonNew_19 [7:0];
epsilonReg_20 [7:0] <= epsilonNew_20 [7:0];
epsilonReg_21 [7:0] <= epsilonNew_21 [7:0];
epsilonReg_22 [7:0] <= epsilonNew_22 [7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
// Generate Error Pattern: Lambda
//------------------------------------------------------------------------
always @( lambdaReg_0 or lambdaReg_1 or lambdaReg_2 or lambdaReg_3 or lambdaReg_4 or lambdaReg_5 or lambdaReg_6 or lambdaReg_7 or lambdaReg_8 or lambdaReg_9 or lambdaReg_10 or lambdaReg_11 or lambdaReg_12 or lambdaReg_13 or lambdaReg_14 or lambdaReg_15 or lambdaReg_16 or lambdaReg_17 or lambdaReg_18 or lambdaReg_19 or lambdaReg_20 or lambdaReg_21 ) begin
lambdaSum [7:0] = lambdaReg_0[7:0] ^ lambdaReg_1[7:0] ^ lambdaReg_2[7:0] ^ lambdaReg_3[7:0] ^ lambdaReg_4[7:0] ^ lambdaReg_5[7:0] ^ lambdaReg_6[7:0] ^ lambdaReg_7[7:0] ^ lambdaReg_8[7:0] ^ lambdaReg_9[7:0] ^ lambdaReg_10[7:0] ^ lambdaReg_11[7:0] ^ lambdaReg_12[7:0] ^ lambdaReg_13[7:0] ^ lambdaReg_14[7:0] ^ lambdaReg_15[7:0] ^ lambdaReg_16[7:0] ^ lambdaReg_17[7:0] ^ lambdaReg_18[7:0] ^ lambdaReg_19[7:0] ^ lambdaReg_20[7:0] ^ lambdaReg_21[7:0];
lambdaEven [7:0] = lambdaReg_0[7:0] ^ lambdaReg_2[7:0] ^ lambdaReg_4[7:0] ^ lambdaReg_6[7:0] ^ lambdaReg_8[7:0] ^ lambdaReg_10[7:0] ^ lambdaReg_12[7:0] ^ lambdaReg_14[7:0] ^ lambdaReg_16[7:0] ^ lambdaReg_18[7:0] ^ lambdaReg_20[7:0];
lambdaOdd [7:0] = lambdaReg_1[7:0] ^ lambdaReg_3[7:0] ^ lambdaReg_5[7:0] ^ lambdaReg_7[7:0] ^ lambdaReg_9[7:0] ^ lambdaReg_11[7:0] ^ lambdaReg_13[7:0] ^ lambdaReg_15[7:0] ^ lambdaReg_17[7:0] ^ lambdaReg_19[7:0] ^ lambdaReg_21[7:0];
end
 
 
 
//------------------------------------------------------------------------
// Generate Error Pattern: Omega
//------------------------------------------------------------------------
always @( omegaReg_0 or omegaReg_1 or omegaReg_2 or omegaReg_3 or omegaReg_4 or omegaReg_5 or omegaReg_6 or omegaReg_7 or omegaReg_8 or omegaReg_9 or omegaReg_10 or omegaReg_11 or omegaReg_12 or omegaReg_13 or omegaReg_14 or omegaReg_15 or omegaReg_16 or omegaReg_17 or omegaReg_18 or omegaReg_19 or omegaReg_20 or omegaReg_21 ) begin
omegaSum [7:0] = omegaReg_0[7:0] ^ omegaReg_1[7:0] ^ omegaReg_2[7:0] ^ omegaReg_3[7:0] ^ omegaReg_4[7:0] ^ omegaReg_5[7:0] ^ omegaReg_6[7:0] ^ omegaReg_7[7:0] ^ omegaReg_8[7:0] ^ omegaReg_9[7:0] ^ omegaReg_10[7:0] ^ omegaReg_11[7:0] ^ omegaReg_12[7:0] ^ omegaReg_13[7:0] ^ omegaReg_14[7:0] ^ omegaReg_15[7:0] ^ omegaReg_16[7:0] ^ omegaReg_17[7:0] ^ omegaReg_18[7:0] ^ omegaReg_19[7:0] ^ omegaReg_20[7:0] ^ omegaReg_21[7:0];
end
 
 
 
//------------------------------------------------------------------------
//- Generate Error Pattern: Epsilon
//------------------------------------------------------------------------
always @( epsilonReg_0 or epsilonReg_1 or epsilonReg_2 or epsilonReg_3 or epsilonReg_4 or epsilonReg_5 or epsilonReg_6 or epsilonReg_7 or epsilonReg_8 or epsilonReg_9 or epsilonReg_10 or epsilonReg_11 or epsilonReg_12 or epsilonReg_13 or epsilonReg_14 or epsilonReg_15 or epsilonReg_16 or epsilonReg_17 or epsilonReg_18 or epsilonReg_19 or epsilonReg_20 or epsilonReg_21 or epsilonReg_22 ) begin
epsilonSum [7:0] = epsilonReg_0[7:0] ^ epsilonReg_1[7:0] ^ epsilonReg_2[7:0] ^ epsilonReg_3[7:0] ^ epsilonReg_4[7:0] ^ epsilonReg_5[7:0] ^ epsilonReg_6[7:0] ^ epsilonReg_7[7:0] ^ epsilonReg_8[7:0] ^ epsilonReg_9[7:0] ^ epsilonReg_10[7:0] ^ epsilonReg_11[7:0] ^ epsilonReg_12[7:0] ^ epsilonReg_13[7:0] ^ epsilonReg_14[7:0] ^ epsilonReg_15[7:0] ^ epsilonReg_16[7:0] ^ epsilonReg_17[7:0] ^ epsilonReg_18[7:0] ^ epsilonReg_19[7:0] ^ epsilonReg_20[7:0] ^ epsilonReg_21[7:0] ^ epsilonReg_22[7:0];
epsilonOdd [7:0] = epsilonReg_1[7:0] ^ epsilonReg_3[7:0] ^ epsilonReg_5[7:0] ^ epsilonReg_7[7:0] ^ epsilonReg_9[7:0] ^ epsilonReg_11[7:0] ^ epsilonReg_13[7:0] ^ epsilonReg_15[7:0] ^ epsilonReg_17[7:0] ^ epsilonReg_19[7:0] ^ epsilonReg_21[7:0];
end
 
 
 
//------------------------------------------------------------------------
//- RsDecodeMult instantiation, RsDecodeMult_MuldE0 && RsDecodeMult_MuldE1
//------------------------------------------------------------------------
RsDecodeMult RsDecodeMult_MuldE0 (.A(lambdaOddReg[7:0]), .B(epsilonSumReg[7:0]), .P(denomE0[7:0]));
RsDecodeMult RsDecodeMult_MuldE1 (.A(lambdaSumReg[7:0]), .B(epsilonOddReg[7:0]), .P(denomE1[7:0]));
 
 
//------------------------------------------------------------------------
//- RsDecodeInv instantiation, RsDecodeInv_InvE0 && RsDecodeInv_InvE1
//------------------------------------------------------------------------
RsDecodeInv RsDecodeInv_InvE0 (.B(denomE0Reg[7:0]), .R(denomE0Inv[7:0]));
RsDecodeInv RsDecodeInv_InvE1 (.B(denomE1Reg[7:0]), .R(denomE1Inv[7:0]));
 
 
//------------------------------------------------------------------------
//- RsDecodeMult instantiation, RsDecodeMult_MulE0 && RsDecodeMult_MulE1
//------------------------------------------------------------------------
RsDecodeMult RsDecodeMult_MulE0 (.A(numeReg2[7:0]), .B(denomE0InvReg[7:0]), .P(errorValueE0[7:0]));
RsDecodeMult RsDecodeMult_MulE1 (.A(numeReg2[7:0]), .B(denomE1InvReg[7:0]), .P(errorValueE1[7:0]));
 
 
 
 
//------------------------------------------------------------------------
// + lambdaSumReg, denomE1Reg, denomE1InvReg, epsilonSumReg, epsilonOddReg
// + lambdaEvenReg, lambdaEvenReg2, lambdaEvenReg3, lambdaOddReg, lambdaOddReg2, lambdaOddReg3, denomE0Reg, denomE0InvReg
// + omegaSumReg, numeReg, numeReg2
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaSumReg [7:0] <= 8'd0;
lambdaEvenReg [7:0] <= 8'd0;
lambdaEvenReg2 [7:0] <= 8'd0;
lambdaEvenReg3 [7:0] <= 8'd0;
lambdaOddReg [7:0] <= 8'd0;
lambdaOddReg2 [7:0] <= 8'd0;
lambdaOddReg3 [7:0] <= 8'd0;
denomE0Reg [7:0] <= 8'd0;
denomE1Reg [7:0] <= 8'd0;
denomE0InvReg [7:0] <= 8'd0;
denomE1InvReg [7:0] <= 8'd0;
omegaSumReg [7:0] <= 8'd0;
numeReg [7:0] <= 8'd0;
numeReg2 [7:0] <= 8'd0;
epsilonSumReg [7:0] <= 8'd0;
epsilonOddReg [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
lambdaSumReg <= lambdaSum;
lambdaEvenReg3 <= lambdaEvenReg2;
lambdaEvenReg2 <= lambdaEvenReg;
lambdaEvenReg <= lambdaEven;
lambdaOddReg3 <= lambdaOddReg2;
lambdaOddReg2 <= lambdaOddReg;
lambdaOddReg <= lambdaOdd;
denomE0Reg <= denomE0;
denomE1Reg <= denomE1;
denomE0InvReg <= denomE0Inv;
denomE1InvReg <= denomE1Inv;
numeReg2 <= numeReg;
numeReg <= omegaSumReg;
omegaSumReg <= omegaSum;
epsilonSumReg <= epsilonSum;
epsilonOddReg <= epsilonOdd;
end
end
 
 
 
//------------------------------------------------------------------
// + errorOut
//-
//------------------------------------------------------------------
reg [7:0] errorOut;
always @(erasureIn or lambdaEvenReg3 or lambdaOddReg3 or errorValueE0 or errorValueE1) begin
if (erasureIn == 1'b1) begin
errorOut = errorValueE1;
end
else if (lambdaEvenReg3 == lambdaOddReg3) begin
errorOut = errorValueE0;
end
else begin
errorOut = 8'd0;
end
end
 
 
 
//------------------------------------------------------------------------
// + numErrorReg
//- Count Error
//------------------------------------------------------------------------
reg [4:0] numErrorReg;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numErrorReg [4:0] <= 5'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
numErrorReg <= 5'd0;
end
else if (lambdaEven == lambdaOdd) begin
numErrorReg <= numErrorReg + 5'd1;
end
end
end
 
 
 
//------------------------------------------------------------------
// + numErrorReg2
//------------------------------------------------------------------
reg [4:0] numErrorReg2;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numErrorReg2 <= 5'd0;
end
else if ((enable == 1'b1) && (doneOrg == 1'b1)) begin
if (lambdaEven == lambdaOdd) begin
numErrorReg2 <= numErrorReg + 5'd1;
end
else begin
numErrorReg2 <= numErrorReg;
end
end
end
//------------------------------------------------------------------------
//- Output Ports
//------------------------------------------------------------------------
assign numError = numErrorReg2;
 
 
endmodule
/trunk/example/rtl/RsDecodeEuclide.v
0,0 → 1,1208
//===================================================================
// Module Name : RsDecodeEuclide
// File Name : RsDecodeEuclide.v
// Function : Rs Decoder Euclide algorithm Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeEuclide(
CLK, // system clock
RESET, // system reset
enable, // enable signal
sync, // sync signal
syndrome_0, // syndrome polynom 0
syndrome_1, // syndrome polynom 1
syndrome_2, // syndrome polynom 2
syndrome_3, // syndrome polynom 3
syndrome_4, // syndrome polynom 4
syndrome_5, // syndrome polynom 5
syndrome_6, // syndrome polynom 6
syndrome_7, // syndrome polynom 7
syndrome_8, // syndrome polynom 8
syndrome_9, // syndrome polynom 9
syndrome_10, // syndrome polynom 10
syndrome_11, // syndrome polynom 11
syndrome_12, // syndrome polynom 12
syndrome_13, // syndrome polynom 13
syndrome_14, // syndrome polynom 14
syndrome_15, // syndrome polynom 15
syndrome_16, // syndrome polynom 16
syndrome_17, // syndrome polynom 17
syndrome_18, // syndrome polynom 18
syndrome_19, // syndrome polynom 19
syndrome_20, // syndrome polynom 20
syndrome_21, // syndrome polynom 21
numErasure, // erasure amount
lambda_0, // lambda polynom 0
lambda_1, // lambda polynom 1
lambda_2, // lambda polynom 2
lambda_3, // lambda polynom 3
lambda_4, // lambda polynom 4
lambda_5, // lambda polynom 5
lambda_6, // lambda polynom 6
lambda_7, // lambda polynom 7
lambda_8, // lambda polynom 8
lambda_9, // lambda polynom 9
lambda_10, // lambda polynom 10
lambda_11, // lambda polynom 11
lambda_12, // lambda polynom 12
lambda_13, // lambda polynom 13
lambda_14, // lambda polynom 14
lambda_15, // lambda polynom 15
lambda_16, // lambda polynom 16
lambda_17, // lambda polynom 17
lambda_18, // lambda polynom 18
lambda_19, // lambda polynom 19
lambda_20, // lambda polynom 20
lambda_21, // lambda polynom 21
omega_0, // omega polynom 0
omega_1, // omega polynom 1
omega_2, // omega polynom 2
omega_3, // omega polynom 3
omega_4, // omega polynom 4
omega_5, // omega polynom 5
omega_6, // omega polynom 6
omega_7, // omega polynom 7
omega_8, // omega polynom 8
omega_9, // omega polynom 9
omega_10, // omega polynom 10
omega_11, // omega polynom 11
omega_12, // omega polynom 12
omega_13, // omega polynom 13
omega_14, // omega polynom 14
omega_15, // omega polynom 15
omega_16, // omega polynom 16
omega_17, // omega polynom 17
omega_18, // omega polynom 18
omega_19, // omega polynom 19
omega_20, // omega polynom 20
omega_21, // omega polynom 21
numShifted, // shift amount
done // done signal
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input sync; // sync signal
input [7:0] syndrome_0; // syndrome polynom 0
input [7:0] syndrome_1; // syndrome polynom 1
input [7:0] syndrome_2; // syndrome polynom 2
input [7:0] syndrome_3; // syndrome polynom 3
input [7:0] syndrome_4; // syndrome polynom 4
input [7:0] syndrome_5; // syndrome polynom 5
input [7:0] syndrome_6; // syndrome polynom 6
input [7:0] syndrome_7; // syndrome polynom 7
input [7:0] syndrome_8; // syndrome polynom 8
input [7:0] syndrome_9; // syndrome polynom 9
input [7:0] syndrome_10; // syndrome polynom 10
input [7:0] syndrome_11; // syndrome polynom 11
input [7:0] syndrome_12; // syndrome polynom 12
input [7:0] syndrome_13; // syndrome polynom 13
input [7:0] syndrome_14; // syndrome polynom 14
input [7:0] syndrome_15; // syndrome polynom 15
input [7:0] syndrome_16; // syndrome polynom 16
input [7:0] syndrome_17; // syndrome polynom 17
input [7:0] syndrome_18; // syndrome polynom 18
input [7:0] syndrome_19; // syndrome polynom 19
input [7:0] syndrome_20; // syndrome polynom 20
input [7:0] syndrome_21; // syndrome polynom 21
input [4:0] numErasure; // erasure amount
 
output [7:0] lambda_0; // lambda polynom 0
output [7:0] lambda_1; // lambda polynom 1
output [7:0] lambda_2; // lambda polynom 2
output [7:0] lambda_3; // lambda polynom 3
output [7:0] lambda_4; // lambda polynom 4
output [7:0] lambda_5; // lambda polynom 5
output [7:0] lambda_6; // lambda polynom 6
output [7:0] lambda_7; // lambda polynom 7
output [7:0] lambda_8; // lambda polynom 8
output [7:0] lambda_9; // lambda polynom 9
output [7:0] lambda_10; // lambda polynom 10
output [7:0] lambda_11; // lambda polynom 11
output [7:0] lambda_12; // lambda polynom 12
output [7:0] lambda_13; // lambda polynom 13
output [7:0] lambda_14; // lambda polynom 14
output [7:0] lambda_15; // lambda polynom 15
output [7:0] lambda_16; // lambda polynom 16
output [7:0] lambda_17; // lambda polynom 17
output [7:0] lambda_18; // lambda polynom 18
output [7:0] lambda_19; // lambda polynom 19
output [7:0] lambda_20; // lambda polynom 20
output [7:0] lambda_21; // lambda polynom 21
output [7:0] omega_0; // omega polynom 0
output [7:0] omega_1; // omega polynom 1
output [7:0] omega_2; // omega polynom 2
output [7:0] omega_3; // omega polynom 3
output [7:0] omega_4; // omega polynom 4
output [7:0] omega_5; // omega polynom 5
output [7:0] omega_6; // omega polynom 6
output [7:0] omega_7; // omega polynom 7
output [7:0] omega_8; // omega polynom 8
output [7:0] omega_9; // omega polynom 9
output [7:0] omega_10; // omega polynom 10
output [7:0] omega_11; // omega polynom 11
output [7:0] omega_12; // omega polynom 12
output [7:0] omega_13; // omega polynom 13
output [7:0] omega_14; // omega polynom 14
output [7:0] omega_15; // omega polynom 15
output [7:0] omega_16; // omega polynom 16
output [7:0] omega_17; // omega polynom 17
output [7:0] omega_18; // omega polynom 18
output [7:0] omega_19; // omega polynom 19
output [7:0] omega_20; // omega polynom 20
output [7:0] omega_21; // omega polynom 21
output [4:0] numShifted; // shift amount
output done; // done signal
 
 
 
 
 
//------------------------------------------------------------------------
// -registers
//------------------------------------------------------------------------
reg [7:0] omegaBkp_0;
reg [7:0] omegaBkp_1;
reg [7:0] omegaBkp_2;
reg [7:0] omegaBkp_3;
reg [7:0] omegaBkp_4;
reg [7:0] omegaBkp_5;
reg [7:0] omegaBkp_6;
reg [7:0] omegaBkp_7;
reg [7:0] omegaBkp_8;
reg [7:0] omegaBkp_9;
reg [7:0] omegaBkp_10;
reg [7:0] omegaBkp_11;
reg [7:0] omegaBkp_12;
reg [7:0] omegaBkp_13;
reg [7:0] omegaBkp_14;
reg [7:0] omegaBkp_15;
reg [7:0] omegaBkp_16;
reg [7:0] omegaBkp_17;
reg [7:0] omegaBkp_18;
reg [7:0] omegaBkp_19;
reg [7:0] omegaBkp_20;
reg [7:0] omegaBkp_21;
reg [7:0] lambdaBkp_0;
reg [7:0] lambdaBkp_1;
reg [7:0] lambdaBkp_2;
reg [7:0] lambdaBkp_3;
reg [7:0] lambdaBkp_4;
reg [7:0] lambdaBkp_5;
reg [7:0] lambdaBkp_6;
reg [7:0] lambdaBkp_7;
reg [7:0] lambdaBkp_8;
reg [7:0] lambdaBkp_9;
reg [7:0] lambdaBkp_10;
reg [7:0] lambdaBkp_11;
reg [7:0] lambdaBkp_12;
reg [7:0] lambdaBkp_13;
reg [7:0] lambdaBkp_14;
reg [7:0] lambdaBkp_15;
reg [7:0] lambdaBkp_16;
reg [7:0] lambdaBkp_17;
reg [7:0] lambdaBkp_18;
reg [7:0] lambdaBkp_19;
reg [7:0] lambdaBkp_20;
reg [7:0] lambdaBkp_21;
reg [7:0] lambdaInner_0;
reg [7:0] lambdaInner_1;
reg [7:0] lambdaInner_2;
reg [7:0] lambdaInner_3;
reg [7:0] lambdaInner_4;
reg [7:0] lambdaInner_5;
reg [7:0] lambdaInner_6;
reg [7:0] lambdaInner_7;
reg [7:0] lambdaInner_8;
reg [7:0] lambdaInner_9;
reg [7:0] lambdaInner_10;
reg [7:0] lambdaInner_11;
reg [7:0] lambdaInner_12;
reg [7:0] lambdaInner_13;
reg [7:0] lambdaInner_14;
reg [7:0] lambdaInner_15;
reg [7:0] lambdaInner_16;
reg [7:0] lambdaInner_17;
reg [7:0] lambdaInner_18;
reg [7:0] lambdaInner_19;
reg [7:0] lambdaInner_20;
reg [7:0] lambdaInner_21;
reg [7:0] lambdaXorReg_0;
reg [7:0] lambdaXorReg_1;
reg [7:0] lambdaXorReg_2;
reg [7:0] lambdaXorReg_3;
reg [7:0] lambdaXorReg_4;
reg [7:0] lambdaXorReg_5;
reg [7:0] lambdaXorReg_6;
reg [7:0] lambdaXorReg_7;
reg [7:0] lambdaXorReg_8;
reg [7:0] lambdaXorReg_9;
reg [7:0] lambdaXorReg_10;
reg [7:0] lambdaXorReg_11;
reg [7:0] lambdaXorReg_12;
reg [7:0] lambdaXorReg_13;
reg [7:0] lambdaXorReg_14;
reg [7:0] lambdaXorReg_15;
reg [7:0] lambdaXorReg_16;
reg [7:0] lambdaXorReg_17;
reg [7:0] lambdaXorReg_18;
reg [7:0] lambdaXorReg_19;
reg [7:0] lambdaXorReg_20;
wire [7:0] omegaMultqNew_0;
wire [7:0] omegaMultqNew_1;
wire [7:0] omegaMultqNew_2;
wire [7:0] omegaMultqNew_3;
wire [7:0] omegaMultqNew_4;
wire [7:0] omegaMultqNew_5;
wire [7:0] omegaMultqNew_6;
wire [7:0] omegaMultqNew_7;
wire [7:0] omegaMultqNew_8;
wire [7:0] omegaMultqNew_9;
wire [7:0] omegaMultqNew_10;
wire [7:0] omegaMultqNew_11;
wire [7:0] omegaMultqNew_12;
wire [7:0] omegaMultqNew_13;
wire [7:0] omegaMultqNew_14;
wire [7:0] omegaMultqNew_15;
wire [7:0] omegaMultqNew_16;
wire [7:0] omegaMultqNew_17;
wire [7:0] omegaMultqNew_18;
wire [7:0] omegaMultqNew_19;
wire [7:0] omegaMultqNew_20;
wire [7:0] lambdaMultqNew_0;
wire [7:0] lambdaMultqNew_1;
wire [7:0] lambdaMultqNew_2;
wire [7:0] lambdaMultqNew_3;
wire [7:0] lambdaMultqNew_4;
wire [7:0] lambdaMultqNew_5;
wire [7:0] lambdaMultqNew_6;
wire [7:0] lambdaMultqNew_7;
wire [7:0] lambdaMultqNew_8;
wire [7:0] lambdaMultqNew_9;
wire [7:0] lambdaMultqNew_10;
wire [7:0] lambdaMultqNew_11;
wire [7:0] lambdaMultqNew_12;
wire [7:0] lambdaMultqNew_13;
wire [7:0] lambdaMultqNew_14;
wire [7:0] lambdaMultqNew_15;
wire [7:0] lambdaMultqNew_16;
wire [7:0] lambdaMultqNew_17;
wire [7:0] lambdaMultqNew_18;
wire [7:0] lambdaMultqNew_19;
wire [7:0] lambdaMultqNew_20;
wire [7:0] lambdaMultqNew_21;
reg [4:0] offset;
reg [4:0] numShiftedReg;
 
 
 
//------------------------------------------------------------------------
// + phase
// Counters
//------------------------------------------------------------------------
reg [1:0] phase;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
phase [1:0] <= 2'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
phase [1:0] <= 2'd1;
end
else if (phase [1:0] == 2'd2) begin
phase [1:0] <= 2'd0;
end
else begin
phase [1:0] <= phase [1:0] + 2'd1;
end
end
end
 
 
 
//------------------------------------------------------------------------
// + count
//- Counter
//------------------------------------------------------------------------
reg [6:0] count;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [6:0] <= 7'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
count [6:0] <= 7'd1;
end
else if ( (count [6:0]==7'd0) || (count [6:0]==7'd69) ) begin
count [6:0] <= 7'd0;
end
else begin
count [6:0] <= count [6:0] + 7'd1;
end
end
end
 
 
 
//------------------------------------------------------------------
// + skip
//------------------------------------------------------------------
reg [7:0] omegaInner_0;
reg [7:0] omegaInner_1;
reg [7:0] omegaInner_2;
reg [7:0] omegaInner_3;
reg [7:0] omegaInner_4;
reg [7:0] omegaInner_5;
reg [7:0] omegaInner_6;
reg [7:0] omegaInner_7;
reg [7:0] omegaInner_8;
reg [7:0] omegaInner_9;
reg [7:0] omegaInner_10;
reg [7:0] omegaInner_11;
reg [7:0] omegaInner_12;
reg [7:0] omegaInner_13;
reg [7:0] omegaInner_14;
reg [7:0] omegaInner_15;
reg [7:0] omegaInner_16;
reg [7:0] omegaInner_17;
reg [7:0] omegaInner_18;
reg [7:0] omegaInner_19;
reg [7:0] omegaInner_20;
reg [7:0] omegaInner_21;
reg skip;
 
always @(omegaInner_21) begin
if (omegaInner_21 [7:0] == 8'd0) begin
skip = 1'b1;
end else begin
skip = 1'b0;
end
end
 
 
//------------------------------------------------------------------------
// + done
//------------------------------------------------------------------------
reg done;
always @(count) begin
if (count[6:0] == 7'd69) begin
done = 1'b1;
end
else begin
done = 1'b0;
end
end
 
 
//------------------------------------------------------------------
// + euclideSteps
//------------------------------------------------------------------
reg [6:0] euclideSteps;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
euclideSteps <= 7'd0;
end
else if (sync) begin
case (numErasure[4:0])
5'd0: begin
euclideSteps[6:0] <= 7'd69; // step: 0
end
5'd1: begin
euclideSteps[6:0] <= 7'd63; // step: 1
end
5'd2: begin
euclideSteps[6:0] <= 7'd63; // step: 2
end
5'd3: begin
euclideSteps[6:0] <= 7'd57; // step: 3
end
5'd4: begin
euclideSteps[6:0] <= 7'd57; // step: 4
end
5'd5: begin
euclideSteps[6:0] <= 7'd51; // step: 5
end
5'd6: begin
euclideSteps[6:0] <= 7'd51; // step: 6
end
5'd7: begin
euclideSteps[6:0] <= 7'd45; // step: 7
end
5'd8: begin
euclideSteps[6:0] <= 7'd45; // step: 8
end
5'd9: begin
euclideSteps[6:0] <= 7'd39; // step: 9
end
5'd10: begin
euclideSteps[6:0] <= 7'd39; // step: 10
end
5'd11: begin
euclideSteps[6:0] <= 7'd33; // step: 11
end
5'd12: begin
euclideSteps[6:0] <= 7'd33; // step: 12
end
5'd13: begin
euclideSteps[6:0] <= 7'd27; // step: 13
end
5'd14: begin
euclideSteps[6:0] <= 7'd27; // step: 14
end
5'd15: begin
euclideSteps[6:0] <= 7'd21; // step: 15
end
5'd16: begin
euclideSteps[6:0] <= 7'd21; // step: 16
end
5'd17: begin
euclideSteps[6:0] <= 7'd15; // step: 17
end
5'd18: begin
euclideSteps[6:0] <= 7'd15; // step: 18
end
5'd19: begin
euclideSteps[6:0] <= 7'd9; // step: 19
end
5'd20: begin
euclideSteps[6:0] <= 7'd9; // step: 20
end
5'd21: begin
euclideSteps[6:0] <= 7'd3; // step: 21
end
5'd22: begin
euclideSteps[6:0] <= 7'd3; // step: 22
end
default: begin
euclideSteps[6:0] <= 7'd0;
end
endcase
end
end
 
 
//------------------------------------------------------------------
// + enable_E
//------------------------------------------------------------------
reg enable_E;
always @(sync or count or enable or numErasure or euclideSteps) begin
if (numErasure[4:0] <= 5'd22) begin
if ((sync == 1'b1) || (count[6:0] <= euclideSteps[6:0])) begin
enable_E = enable;
end
else begin
enable_E = 1'b0;
end
end
else begin
if ((sync == 1'b1) || (count[6:0] <= 7'd3)) begin
enable_E = enable;
end
else begin
enable_E = 1'b0;
end
end
end
 
 
//------------------------------------------------------------------------
// Get Partial Q
//------------------------------------------------------------------------
wire [7:0] omegaInv;
reg [7:0] omegaInvReg;
wire [7:0] qNew;
reg [7:0] qNewReg;
reg [7:0] omegaBkpReg;
 
RsDecodeInv RsDecodeInv_Q (.B(omegaInner_21[7:0]), .R(omegaInv[7:0]));
RsDecodeMult RsDecodeMult_Q (.A(omegaBkpReg[7:0]), .B(omegaInvReg[7:0]), .P(qNew[7:0]) );
 
 
//------------------------------------------------------------------
// + omegaInvReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaInvReg <= 8'd0;
end
else if (enable == 1'b1) begin
omegaInvReg <= omegaInv;
end
end
 
 
//------------------------------------------------------------------
// + omegaBkpReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaBkpReg <= 8'd0;
end
else if (enable == 1'b1) begin
omegaBkpReg <= omegaBkp_21[7:0];
end
end
 
 
//------------------------------------------------------------------
// + qNewReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
qNewReg <= 8'd0;
end
else if (enable == 1'b1) begin
qNewReg <= qNew;
end
end
 
 
//------------------------------------------------------------------------
// + omegaMultqNew_0,..., omegaMultqNew_18
//- QT = qNewReg * omegaInner
//- Multipliers
//------------------------------------------------------------------------
RsDecodeMult RsDecodeMult_PDIV0 (.A(qNewReg[7:0]), .B(omegaInner_0[7:0]), .P(omegaMultqNew_0[7:0]) );
RsDecodeMult RsDecodeMult_PDIV1 (.A(qNewReg[7:0]), .B(omegaInner_1[7:0]), .P(omegaMultqNew_1[7:0]) );
RsDecodeMult RsDecodeMult_PDIV2 (.A(qNewReg[7:0]), .B(omegaInner_2[7:0]), .P(omegaMultqNew_2[7:0]) );
RsDecodeMult RsDecodeMult_PDIV3 (.A(qNewReg[7:0]), .B(omegaInner_3[7:0]), .P(omegaMultqNew_3[7:0]) );
RsDecodeMult RsDecodeMult_PDIV4 (.A(qNewReg[7:0]), .B(omegaInner_4[7:0]), .P(omegaMultqNew_4[7:0]) );
RsDecodeMult RsDecodeMult_PDIV5 (.A(qNewReg[7:0]), .B(omegaInner_5[7:0]), .P(omegaMultqNew_5[7:0]) );
RsDecodeMult RsDecodeMult_PDIV6 (.A(qNewReg[7:0]), .B(omegaInner_6[7:0]), .P(omegaMultqNew_6[7:0]) );
RsDecodeMult RsDecodeMult_PDIV7 (.A(qNewReg[7:0]), .B(omegaInner_7[7:0]), .P(omegaMultqNew_7[7:0]) );
RsDecodeMult RsDecodeMult_PDIV8 (.A(qNewReg[7:0]), .B(omegaInner_8[7:0]), .P(omegaMultqNew_8[7:0]) );
RsDecodeMult RsDecodeMult_PDIV9 (.A(qNewReg[7:0]), .B(omegaInner_9[7:0]), .P(omegaMultqNew_9[7:0]) );
RsDecodeMult RsDecodeMult_PDIV10 (.A(qNewReg[7:0]), .B(omegaInner_10[7:0]), .P(omegaMultqNew_10[7:0]) );
RsDecodeMult RsDecodeMult_PDIV11 (.A(qNewReg[7:0]), .B(omegaInner_11[7:0]), .P(omegaMultqNew_11[7:0]) );
RsDecodeMult RsDecodeMult_PDIV12 (.A(qNewReg[7:0]), .B(omegaInner_12[7:0]), .P(omegaMultqNew_12[7:0]) );
RsDecodeMult RsDecodeMult_PDIV13 (.A(qNewReg[7:0]), .B(omegaInner_13[7:0]), .P(omegaMultqNew_13[7:0]) );
RsDecodeMult RsDecodeMult_PDIV14 (.A(qNewReg[7:0]), .B(omegaInner_14[7:0]), .P(omegaMultqNew_14[7:0]) );
RsDecodeMult RsDecodeMult_PDIV15 (.A(qNewReg[7:0]), .B(omegaInner_15[7:0]), .P(omegaMultqNew_15[7:0]) );
RsDecodeMult RsDecodeMult_PDIV16 (.A(qNewReg[7:0]), .B(omegaInner_16[7:0]), .P(omegaMultqNew_16[7:0]) );
RsDecodeMult RsDecodeMult_PDIV17 (.A(qNewReg[7:0]), .B(omegaInner_17[7:0]), .P(omegaMultqNew_17[7:0]) );
RsDecodeMult RsDecodeMult_PDIV18 (.A(qNewReg[7:0]), .B(omegaInner_18[7:0]), .P(omegaMultqNew_18[7:0]) );
RsDecodeMult RsDecodeMult_PDIV19 (.A(qNewReg[7:0]), .B(omegaInner_19[7:0]), .P(omegaMultqNew_19[7:0]) );
RsDecodeMult RsDecodeMult_PDIV20 (.A(qNewReg[7:0]), .B(omegaInner_20[7:0]), .P(omegaMultqNew_20[7:0]) );
 
 
//------------------------------------------------------------------------
// + lambdaMultqNew_0, ..., QA_19
//- QA22 = qNewReg * lambdaInner
//- Multipliers
//------------------------------------------------------------------------
RsDecodeMult RsDecodeMult_PMUL0 (.A(qNewReg[7:0]), .B(lambdaInner_0[7:0]), .P(lambdaMultqNew_0[7:0]) );
RsDecodeMult RsDecodeMult_PMUL1 (.A(qNewReg[7:0]), .B(lambdaInner_1[7:0]), .P(lambdaMultqNew_1[7:0]) );
RsDecodeMult RsDecodeMult_PMUL2 (.A(qNewReg[7:0]), .B(lambdaInner_2[7:0]), .P(lambdaMultqNew_2[7:0]) );
RsDecodeMult RsDecodeMult_PMUL3 (.A(qNewReg[7:0]), .B(lambdaInner_3[7:0]), .P(lambdaMultqNew_3[7:0]) );
RsDecodeMult RsDecodeMult_PMUL4 (.A(qNewReg[7:0]), .B(lambdaInner_4[7:0]), .P(lambdaMultqNew_4[7:0]) );
RsDecodeMult RsDecodeMult_PMUL5 (.A(qNewReg[7:0]), .B(lambdaInner_5[7:0]), .P(lambdaMultqNew_5[7:0]) );
RsDecodeMult RsDecodeMult_PMUL6 (.A(qNewReg[7:0]), .B(lambdaInner_6[7:0]), .P(lambdaMultqNew_6[7:0]) );
RsDecodeMult RsDecodeMult_PMUL7 (.A(qNewReg[7:0]), .B(lambdaInner_7[7:0]), .P(lambdaMultqNew_7[7:0]) );
RsDecodeMult RsDecodeMult_PMUL8 (.A(qNewReg[7:0]), .B(lambdaInner_8[7:0]), .P(lambdaMultqNew_8[7:0]) );
RsDecodeMult RsDecodeMult_PMUL9 (.A(qNewReg[7:0]), .B(lambdaInner_9[7:0]), .P(lambdaMultqNew_9[7:0]) );
RsDecodeMult RsDecodeMult_PMUL10 (.A(qNewReg[7:0]), .B(lambdaInner_10[7:0]), .P(lambdaMultqNew_10[7:0]) );
RsDecodeMult RsDecodeMult_PMUL11 (.A(qNewReg[7:0]), .B(lambdaInner_11[7:0]), .P(lambdaMultqNew_11[7:0]) );
RsDecodeMult RsDecodeMult_PMUL12 (.A(qNewReg[7:0]), .B(lambdaInner_12[7:0]), .P(lambdaMultqNew_12[7:0]) );
RsDecodeMult RsDecodeMult_PMUL13 (.A(qNewReg[7:0]), .B(lambdaInner_13[7:0]), .P(lambdaMultqNew_13[7:0]) );
RsDecodeMult RsDecodeMult_PMUL14 (.A(qNewReg[7:0]), .B(lambdaInner_14[7:0]), .P(lambdaMultqNew_14[7:0]) );
RsDecodeMult RsDecodeMult_PMUL15 (.A(qNewReg[7:0]), .B(lambdaInner_15[7:0]), .P(lambdaMultqNew_15[7:0]) );
RsDecodeMult RsDecodeMult_PMUL16 (.A(qNewReg[7:0]), .B(lambdaInner_16[7:0]), .P(lambdaMultqNew_16[7:0]) );
RsDecodeMult RsDecodeMult_PMUL17 (.A(qNewReg[7:0]), .B(lambdaInner_17[7:0]), .P(lambdaMultqNew_17[7:0]) );
RsDecodeMult RsDecodeMult_PMUL18 (.A(qNewReg[7:0]), .B(lambdaInner_18[7:0]), .P(lambdaMultqNew_18[7:0]) );
RsDecodeMult RsDecodeMult_PMUL19 (.A(qNewReg[7:0]), .B(lambdaInner_19[7:0]), .P(lambdaMultqNew_19[7:0]) );
RsDecodeMult RsDecodeMult_PMUL20 (.A(qNewReg[7:0]), .B(lambdaInner_20[7:0]), .P(lambdaMultqNew_20[7:0]) );
RsDecodeMult RsDecodeMult_PMUL21 (.A(qNewReg[7:0]), .B(lambdaInner_21[7:0]), .P(lambdaMultqNew_21[7:0]) );
 
 
//------------------------------------------------------------------------
// + omegaBkp_0, ..., omegaBkp_19
//- Registers
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaBkp_0 [7:0] <= 8'd0;
omegaBkp_1 [7:0] <= 8'd0;
omegaBkp_2 [7:0] <= 8'd0;
omegaBkp_3 [7:0] <= 8'd0;
omegaBkp_4 [7:0] <= 8'd0;
omegaBkp_5 [7:0] <= 8'd0;
omegaBkp_6 [7:0] <= 8'd0;
omegaBkp_7 [7:0] <= 8'd0;
omegaBkp_8 [7:0] <= 8'd0;
omegaBkp_9 [7:0] <= 8'd0;
omegaBkp_10 [7:0] <= 8'd0;
omegaBkp_11 [7:0] <= 8'd0;
omegaBkp_12 [7:0] <= 8'd0;
omegaBkp_13 [7:0] <= 8'd0;
omegaBkp_14 [7:0] <= 8'd0;
omegaBkp_15 [7:0] <= 8'd0;
omegaBkp_16 [7:0] <= 8'd0;
omegaBkp_17 [7:0] <= 8'd0;
omegaBkp_18 [7:0] <= 8'd0;
omegaBkp_19 [7:0] <= 8'd0;
omegaBkp_20 [7:0] <= 8'd0;
omegaBkp_21 [7:0] <= 8'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
omegaBkp_0 [7:0] <= 8'd0;
omegaBkp_1 [7:0] <= 8'd0;
omegaBkp_2 [7:0] <= 8'd0;
omegaBkp_3 [7:0] <= 8'd0;
omegaBkp_4 [7:0] <= 8'd0;
omegaBkp_5 [7:0] <= 8'd0;
omegaBkp_6 [7:0] <= 8'd0;
omegaBkp_7 [7:0] <= 8'd0;
omegaBkp_8 [7:0] <= 8'd0;
omegaBkp_9 [7:0] <= 8'd0;
omegaBkp_10 [7:0] <= 8'd0;
omegaBkp_11 [7:0] <= 8'd0;
omegaBkp_12 [7:0] <= 8'd0;
omegaBkp_13 [7:0] <= 8'd0;
omegaBkp_14 [7:0] <= 8'd0;
omegaBkp_15 [7:0] <= 8'd0;
omegaBkp_16 [7:0] <= 8'd0;
omegaBkp_17 [7:0] <= 8'd0;
omegaBkp_18 [7:0] <= 8'd0;
omegaBkp_19 [7:0] <= 8'd0;
omegaBkp_20 [7:0] <= 8'd0;
omegaBkp_21[7:0] <= 8'd1;
end
else if (phase[1:0] == 2'b00) begin
if ((skip== 1'b0) && (offset == 5'd0)) begin
omegaBkp_0 [7:0] <= omegaInner_0[7:0];
omegaBkp_1 [7:0] <= omegaInner_1[7:0];
omegaBkp_2 [7:0] <= omegaInner_2[7:0];
omegaBkp_3 [7:0] <= omegaInner_3[7:0];
omegaBkp_4 [7:0] <= omegaInner_4[7:0];
omegaBkp_5 [7:0] <= omegaInner_5[7:0];
omegaBkp_6 [7:0] <= omegaInner_6[7:0];
omegaBkp_7 [7:0] <= omegaInner_7[7:0];
omegaBkp_8 [7:0] <= omegaInner_8[7:0];
omegaBkp_9 [7:0] <= omegaInner_9[7:0];
omegaBkp_10 [7:0] <= omegaInner_10[7:0];
omegaBkp_11 [7:0] <= omegaInner_11[7:0];
omegaBkp_12 [7:0] <= omegaInner_12[7:0];
omegaBkp_13 [7:0] <= omegaInner_13[7:0];
omegaBkp_14 [7:0] <= omegaInner_14[7:0];
omegaBkp_15 [7:0] <= omegaInner_15[7:0];
omegaBkp_16 [7:0] <= omegaInner_16[7:0];
omegaBkp_17 [7:0] <= omegaInner_17[7:0];
omegaBkp_18 [7:0] <= omegaInner_18[7:0];
omegaBkp_19 [7:0] <= omegaInner_19[7:0];
omegaBkp_20 [7:0] <= omegaInner_20[7:0];
omegaBkp_21 [7:0] <= omegaInner_21[7:0];
end
else if (skip== 1'b0) begin
omegaBkp_0 [7:0] <= 8'd0;
omegaBkp_1 [7:0] <= omegaMultqNew_0[7:0] ^ omegaBkp_0[7:0];
omegaBkp_2 [7:0] <= omegaMultqNew_1[7:0] ^ omegaBkp_1[7:0];
omegaBkp_3 [7:0] <= omegaMultqNew_2[7:0] ^ omegaBkp_2[7:0];
omegaBkp_4 [7:0] <= omegaMultqNew_3[7:0] ^ omegaBkp_3[7:0];
omegaBkp_5 [7:0] <= omegaMultqNew_4[7:0] ^ omegaBkp_4[7:0];
omegaBkp_6 [7:0] <= omegaMultqNew_5[7:0] ^ omegaBkp_5[7:0];
omegaBkp_7 [7:0] <= omegaMultqNew_6[7:0] ^ omegaBkp_6[7:0];
omegaBkp_8 [7:0] <= omegaMultqNew_7[7:0] ^ omegaBkp_7[7:0];
omegaBkp_9 [7:0] <= omegaMultqNew_8[7:0] ^ omegaBkp_8[7:0];
omegaBkp_10 [7:0] <= omegaMultqNew_9[7:0] ^ omegaBkp_9[7:0];
omegaBkp_11 [7:0] <= omegaMultqNew_10[7:0] ^ omegaBkp_10[7:0];
omegaBkp_12 [7:0] <= omegaMultqNew_11[7:0] ^ omegaBkp_11[7:0];
omegaBkp_13 [7:0] <= omegaMultqNew_12[7:0] ^ omegaBkp_12[7:0];
omegaBkp_14 [7:0] <= omegaMultqNew_13[7:0] ^ omegaBkp_13[7:0];
omegaBkp_15 [7:0] <= omegaMultqNew_14[7:0] ^ omegaBkp_14[7:0];
omegaBkp_16 [7:0] <= omegaMultqNew_15[7:0] ^ omegaBkp_15[7:0];
omegaBkp_17 [7:0] <= omegaMultqNew_16[7:0] ^ omegaBkp_16[7:0];
omegaBkp_18 [7:0] <= omegaMultqNew_17[7:0] ^ omegaBkp_17[7:0];
omegaBkp_19 [7:0] <= omegaMultqNew_18[7:0] ^ omegaBkp_18[7:0];
omegaBkp_20 [7:0] <= omegaMultqNew_19[7:0] ^ omegaBkp_19[7:0];
omegaBkp_21 [7:0] <= omegaMultqNew_20[7:0] ^ omegaBkp_20[7:0];
end
end
end
end
 
 
//------------------------------------------------------------------
// +omegaInner
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
omegaInner_0 [7:0] <= 8'd0;
omegaInner_1 [7:0] <= 8'd0;
omegaInner_2 [7:0] <= 8'd0;
omegaInner_3 [7:0] <= 8'd0;
omegaInner_4 [7:0] <= 8'd0;
omegaInner_5 [7:0] <= 8'd0;
omegaInner_6 [7:0] <= 8'd0;
omegaInner_7 [7:0] <= 8'd0;
omegaInner_8 [7:0] <= 8'd0;
omegaInner_9 [7:0] <= 8'd0;
omegaInner_10 [7:0] <= 8'd0;
omegaInner_11 [7:0] <= 8'd0;
omegaInner_12 [7:0] <= 8'd0;
omegaInner_13 [7:0] <= 8'd0;
omegaInner_14 [7:0] <= 8'd0;
omegaInner_15 [7:0] <= 8'd0;
omegaInner_16 [7:0] <= 8'd0;
omegaInner_17 [7:0] <= 8'd0;
omegaInner_18 [7:0] <= 8'd0;
omegaInner_19 [7:0] <= 8'd0;
omegaInner_20 [7:0] <= 8'd0;
omegaInner_21 [7:0] <= 8'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
omegaInner_0 [7:0] <= syndrome_0[7:0];
omegaInner_1 [7:0] <= syndrome_1[7:0];
omegaInner_2 [7:0] <= syndrome_2[7:0];
omegaInner_3 [7:0] <= syndrome_3[7:0];
omegaInner_4 [7:0] <= syndrome_4[7:0];
omegaInner_5 [7:0] <= syndrome_5[7:0];
omegaInner_6 [7:0] <= syndrome_6[7:0];
omegaInner_7 [7:0] <= syndrome_7[7:0];
omegaInner_8 [7:0] <= syndrome_8[7:0];
omegaInner_9 [7:0] <= syndrome_9[7:0];
omegaInner_10 [7:0] <= syndrome_10[7:0];
omegaInner_11 [7:0] <= syndrome_11[7:0];
omegaInner_12 [7:0] <= syndrome_12[7:0];
omegaInner_13 [7:0] <= syndrome_13[7:0];
omegaInner_14 [7:0] <= syndrome_14[7:0];
omegaInner_15 [7:0] <= syndrome_15[7:0];
omegaInner_16 [7:0] <= syndrome_16[7:0];
omegaInner_17 [7:0] <= syndrome_17[7:0];
omegaInner_18 [7:0] <= syndrome_18[7:0];
omegaInner_19 [7:0] <= syndrome_19[7:0];
omegaInner_20 [7:0] <= syndrome_20[7:0];
omegaInner_21 [7:0] <= syndrome_21[7:0];
end
else if (phase == 2'b00) begin
if ((skip == 1'b0) && (offset == 5'd0)) begin
omegaInner_0 [7:0] <= 8'd0;
omegaInner_1 [7:0] <= omegaMultqNew_0 [7:0] ^ omegaBkp_0 [7:0];
omegaInner_2 [7:0] <= omegaMultqNew_1 [7:0] ^ omegaBkp_1 [7:0];
omegaInner_3 [7:0] <= omegaMultqNew_2 [7:0] ^ omegaBkp_2 [7:0];
omegaInner_4 [7:0] <= omegaMultqNew_3 [7:0] ^ omegaBkp_3 [7:0];
omegaInner_5 [7:0] <= omegaMultqNew_4 [7:0] ^ omegaBkp_4 [7:0];
omegaInner_6 [7:0] <= omegaMultqNew_5 [7:0] ^ omegaBkp_5 [7:0];
omegaInner_7 [7:0] <= omegaMultqNew_6 [7:0] ^ omegaBkp_6 [7:0];
omegaInner_8 [7:0] <= omegaMultqNew_7 [7:0] ^ omegaBkp_7 [7:0];
omegaInner_9 [7:0] <= omegaMultqNew_8 [7:0] ^ omegaBkp_8 [7:0];
omegaInner_10 [7:0] <= omegaMultqNew_9 [7:0] ^ omegaBkp_9 [7:0];
omegaInner_11 [7:0] <= omegaMultqNew_10 [7:0] ^ omegaBkp_10 [7:0];
omegaInner_12 [7:0] <= omegaMultqNew_11 [7:0] ^ omegaBkp_11 [7:0];
omegaInner_13 [7:0] <= omegaMultqNew_12 [7:0] ^ omegaBkp_12 [7:0];
omegaInner_14 [7:0] <= omegaMultqNew_13 [7:0] ^ omegaBkp_13 [7:0];
omegaInner_15 [7:0] <= omegaMultqNew_14 [7:0] ^ omegaBkp_14 [7:0];
omegaInner_16 [7:0] <= omegaMultqNew_15 [7:0] ^ omegaBkp_15 [7:0];
omegaInner_17 [7:0] <= omegaMultqNew_16 [7:0] ^ omegaBkp_16 [7:0];
omegaInner_18 [7:0] <= omegaMultqNew_17 [7:0] ^ omegaBkp_17 [7:0];
omegaInner_19 [7:0] <= omegaMultqNew_18 [7:0] ^ omegaBkp_18 [7:0];
omegaInner_20 [7:0] <= omegaMultqNew_19 [7:0] ^ omegaBkp_19 [7:0];
omegaInner_21 [7:0] <= omegaMultqNew_20 [7:0] ^ omegaBkp_20 [7:0];
end
else if (skip == 1'b1) begin
omegaInner_0 [7:0] <= 8'd0;
omegaInner_1 [7:0] <= omegaInner_0 [7:0];
omegaInner_2 [7:0] <= omegaInner_1 [7:0];
omegaInner_3 [7:0] <= omegaInner_2 [7:0];
omegaInner_4 [7:0] <= omegaInner_3 [7:0];
omegaInner_5 [7:0] <= omegaInner_4 [7:0];
omegaInner_6 [7:0] <= omegaInner_5 [7:0];
omegaInner_7 [7:0] <= omegaInner_6 [7:0];
omegaInner_8 [7:0] <= omegaInner_7 [7:0];
omegaInner_9 [7:0] <= omegaInner_8 [7:0];
omegaInner_10 [7:0] <= omegaInner_9 [7:0];
omegaInner_11 [7:0] <= omegaInner_10 [7:0];
omegaInner_12 [7:0] <= omegaInner_11 [7:0];
omegaInner_13 [7:0] <= omegaInner_12 [7:0];
omegaInner_14 [7:0] <= omegaInner_13 [7:0];
omegaInner_15 [7:0] <= omegaInner_14 [7:0];
omegaInner_16 [7:0] <= omegaInner_15 [7:0];
omegaInner_17 [7:0] <= omegaInner_16 [7:0];
omegaInner_18 [7:0] <= omegaInner_17 [7:0];
omegaInner_19 [7:0] <= omegaInner_18 [7:0];
omegaInner_20 [7:0] <= omegaInner_19 [7:0];
omegaInner_21 [7:0] <= omegaInner_20 [7:0];
end
end
end
end
 
 
//------------------------------------------------------------------
// + lambdaBkp_0,..,lambdaBkp_21
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaBkp_0 [7:0] <= 8'd0;
lambdaBkp_1 [7:0] <= 8'd0;
lambdaBkp_2 [7:0] <= 8'd0;
lambdaBkp_3 [7:0] <= 8'd0;
lambdaBkp_4 [7:0] <= 8'd0;
lambdaBkp_5 [7:0] <= 8'd0;
lambdaBkp_6 [7:0] <= 8'd0;
lambdaBkp_7 [7:0] <= 8'd0;
lambdaBkp_8 [7:0] <= 8'd0;
lambdaBkp_9 [7:0] <= 8'd0;
lambdaBkp_10 [7:0] <= 8'd0;
lambdaBkp_11 [7:0] <= 8'd0;
lambdaBkp_12 [7:0] <= 8'd0;
lambdaBkp_13 [7:0] <= 8'd0;
lambdaBkp_14 [7:0] <= 8'd0;
lambdaBkp_15 [7:0] <= 8'd0;
lambdaBkp_16 [7:0] <= 8'd0;
lambdaBkp_17 [7:0] <= 8'd0;
lambdaBkp_18 [7:0] <= 8'd0;
lambdaBkp_19 [7:0] <= 8'd0;
lambdaBkp_20 [7:0] <= 8'd0;
lambdaBkp_21 [7:0] <= 8'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
lambdaBkp_0 [7:0] <= 8'd0;
lambdaBkp_1 [7:0] <= 8'd0;
lambdaBkp_2 [7:0] <= 8'd0;
lambdaBkp_3 [7:0] <= 8'd0;
lambdaBkp_4 [7:0] <= 8'd0;
lambdaBkp_5 [7:0] <= 8'd0;
lambdaBkp_6 [7:0] <= 8'd0;
lambdaBkp_7 [7:0] <= 8'd0;
lambdaBkp_8 [7:0] <= 8'd0;
lambdaBkp_9 [7:0] <= 8'd0;
lambdaBkp_10 [7:0] <= 8'd0;
lambdaBkp_11 [7:0] <= 8'd0;
lambdaBkp_12 [7:0] <= 8'd0;
lambdaBkp_13 [7:0] <= 8'd0;
lambdaBkp_14 [7:0] <= 8'd0;
lambdaBkp_15 [7:0] <= 8'd0;
lambdaBkp_16 [7:0] <= 8'd0;
lambdaBkp_17 [7:0] <= 8'd0;
lambdaBkp_18 [7:0] <= 8'd0;
lambdaBkp_19 [7:0] <= 8'd0;
lambdaBkp_20 [7:0] <= 8'd0;
lambdaBkp_21 [7:0] <= 8'd0;
end
else if ((phase == 2'b00) && (skip == 1'b0) && (offset == 5'd0)) begin
lambdaBkp_0 [7:0] <= lambdaInner_0[7:0];
lambdaBkp_1 [7:0] <= lambdaInner_1[7:0];
lambdaBkp_2 [7:0] <= lambdaInner_2[7:0];
lambdaBkp_3 [7:0] <= lambdaInner_3[7:0];
lambdaBkp_4 [7:0] <= lambdaInner_4[7:0];
lambdaBkp_5 [7:0] <= lambdaInner_5[7:0];
lambdaBkp_6 [7:0] <= lambdaInner_6[7:0];
lambdaBkp_7 [7:0] <= lambdaInner_7[7:0];
lambdaBkp_8 [7:0] <= lambdaInner_8[7:0];
lambdaBkp_9 [7:0] <= lambdaInner_9[7:0];
lambdaBkp_10 [7:0] <= lambdaInner_10[7:0];
lambdaBkp_11 [7:0] <= lambdaInner_11[7:0];
lambdaBkp_12 [7:0] <= lambdaInner_12[7:0];
lambdaBkp_13 [7:0] <= lambdaInner_13[7:0];
lambdaBkp_14 [7:0] <= lambdaInner_14[7:0];
lambdaBkp_15 [7:0] <= lambdaInner_15[7:0];
lambdaBkp_16 [7:0] <= lambdaInner_16[7:0];
lambdaBkp_17 [7:0] <= lambdaInner_17[7:0];
lambdaBkp_18 [7:0] <= lambdaInner_18[7:0];
lambdaBkp_19 [7:0] <= lambdaInner_19[7:0];
lambdaBkp_20 [7:0] <= lambdaInner_20[7:0];
lambdaBkp_21 [7:0] <= lambdaInner_21[7:0];
end
end
end
 
 
//------------------------------------------------------------------
// + lambdaInner_0, lambdaInner_21
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaInner_0 [7:0] <= 8'd0;
lambdaInner_1 [7:0] <= 8'd0;
lambdaInner_2 [7:0] <= 8'd0;
lambdaInner_3 [7:0] <= 8'd0;
lambdaInner_4 [7:0] <= 8'd0;
lambdaInner_5 [7:0] <= 8'd0;
lambdaInner_6 [7:0] <= 8'd0;
lambdaInner_7 [7:0] <= 8'd0;
lambdaInner_8 [7:0] <= 8'd0;
lambdaInner_9 [7:0] <= 8'd0;
lambdaInner_10 [7:0] <= 8'd0;
lambdaInner_11 [7:0] <= 8'd0;
lambdaInner_12 [7:0] <= 8'd0;
lambdaInner_13 [7:0] <= 8'd0;
lambdaInner_14 [7:0] <= 8'd0;
lambdaInner_15 [7:0] <= 8'd0;
lambdaInner_16 [7:0] <= 8'd0;
lambdaInner_17 [7:0] <= 8'd0;
lambdaInner_18 [7:0] <= 8'd0;
lambdaInner_19 [7:0] <= 8'd0;
lambdaInner_20 [7:0] <= 8'd0;
lambdaInner_21 [7:0] <= 8'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
lambdaInner_0 [7:0] <= 8'd1;
lambdaInner_1 [7:0] <= 8'd0;
lambdaInner_2 [7:0] <= 8'd0;
lambdaInner_3 [7:0] <= 8'd0;
lambdaInner_4 [7:0] <= 8'd0;
lambdaInner_5 [7:0] <= 8'd0;
lambdaInner_6 [7:0] <= 8'd0;
lambdaInner_7 [7:0] <= 8'd0;
lambdaInner_8 [7:0] <= 8'd0;
lambdaInner_9 [7:0] <= 8'd0;
lambdaInner_10 [7:0] <= 8'd0;
lambdaInner_11 [7:0] <= 8'd0;
lambdaInner_12 [7:0] <= 8'd0;
lambdaInner_13 [7:0] <= 8'd0;
lambdaInner_14 [7:0] <= 8'd0;
lambdaInner_15 [7:0] <= 8'd0;
lambdaInner_16 [7:0] <= 8'd0;
lambdaInner_17 [7:0] <= 8'd0;
lambdaInner_18 [7:0] <= 8'd0;
lambdaInner_19 [7:0] <= 8'd0;
lambdaInner_20 [7:0] <= 8'd0;
lambdaInner_21 [7:0] <= 8'd0;
end
else if ((phase[1:0] == 2'b00) && (skip == 1'b0) && (offset== 5'd0)) begin
lambdaInner_0 [7:0] <= lambdaBkp_0 [7:0] ^ lambdaMultqNew_0 [7:0];
lambdaInner_1 [7:0] <= lambdaBkp_1 [7:0] ^ lambdaMultqNew_1 [7:0] ^ lambdaXorReg_0 [7:0];
lambdaInner_2 [7:0] <= lambdaBkp_2 [7:0] ^ lambdaMultqNew_2 [7:0] ^ lambdaXorReg_1 [7:0];
lambdaInner_3 [7:0] <= lambdaBkp_3 [7:0] ^ lambdaMultqNew_3 [7:0] ^ lambdaXorReg_2 [7:0];
lambdaInner_4 [7:0] <= lambdaBkp_4 [7:0] ^ lambdaMultqNew_4 [7:0] ^ lambdaXorReg_3 [7:0];
lambdaInner_5 [7:0] <= lambdaBkp_5 [7:0] ^ lambdaMultqNew_5 [7:0] ^ lambdaXorReg_4 [7:0];
lambdaInner_6 [7:0] <= lambdaBkp_6 [7:0] ^ lambdaMultqNew_6 [7:0] ^ lambdaXorReg_5 [7:0];
lambdaInner_7 [7:0] <= lambdaBkp_7 [7:0] ^ lambdaMultqNew_7 [7:0] ^ lambdaXorReg_6 [7:0];
lambdaInner_8 [7:0] <= lambdaBkp_8 [7:0] ^ lambdaMultqNew_8 [7:0] ^ lambdaXorReg_7 [7:0];
lambdaInner_9 [7:0] <= lambdaBkp_9 [7:0] ^ lambdaMultqNew_9 [7:0] ^ lambdaXorReg_8 [7:0];
lambdaInner_10 [7:0] <= lambdaBkp_10 [7:0] ^ lambdaMultqNew_10 [7:0] ^ lambdaXorReg_9 [7:0];
lambdaInner_11 [7:0] <= lambdaBkp_11 [7:0] ^ lambdaMultqNew_11 [7:0] ^ lambdaXorReg_10 [7:0];
lambdaInner_12 [7:0] <= lambdaBkp_12 [7:0] ^ lambdaMultqNew_12 [7:0] ^ lambdaXorReg_11 [7:0];
lambdaInner_13 [7:0] <= lambdaBkp_13 [7:0] ^ lambdaMultqNew_13 [7:0] ^ lambdaXorReg_12 [7:0];
lambdaInner_14 [7:0] <= lambdaBkp_14 [7:0] ^ lambdaMultqNew_14 [7:0] ^ lambdaXorReg_13 [7:0];
lambdaInner_15 [7:0] <= lambdaBkp_15 [7:0] ^ lambdaMultqNew_15 [7:0] ^ lambdaXorReg_14 [7:0];
lambdaInner_16 [7:0] <= lambdaBkp_16 [7:0] ^ lambdaMultqNew_16 [7:0] ^ lambdaXorReg_15 [7:0];
lambdaInner_17 [7:0] <= lambdaBkp_17 [7:0] ^ lambdaMultqNew_17 [7:0] ^ lambdaXorReg_16 [7:0];
lambdaInner_18 [7:0] <= lambdaBkp_18 [7:0] ^ lambdaMultqNew_18 [7:0] ^ lambdaXorReg_17 [7:0];
lambdaInner_19 [7:0] <= lambdaBkp_19 [7:0] ^ lambdaMultqNew_19 [7:0] ^ lambdaXorReg_18 [7:0];
lambdaInner_20 [7:0] <= lambdaBkp_20 [7:0] ^ lambdaMultqNew_20 [7:0] ^ lambdaXorReg_19 [7:0];
lambdaInner_21 [7:0] <= lambdaBkp_21 [7:0] ^ lambdaMultqNew_21 [7:0] ^ lambdaXorReg_20 [7:0];
end
end
end
 
 
//------------------------------------------------------------------
// + lambdaXorReg_0,..., lambdaXorReg_22
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
lambdaXorReg_0 [7:0] <= 8'd0;
lambdaXorReg_1 [7:0] <= 8'd0;
lambdaXorReg_2 [7:0] <= 8'd0;
lambdaXorReg_3 [7:0] <= 8'd0;
lambdaXorReg_4 [7:0] <= 8'd0;
lambdaXorReg_5 [7:0] <= 8'd0;
lambdaXorReg_6 [7:0] <= 8'd0;
lambdaXorReg_7 [7:0] <= 8'd0;
lambdaXorReg_8 [7:0] <= 8'd0;
lambdaXorReg_9 [7:0] <= 8'd0;
lambdaXorReg_10 [7:0] <= 8'd0;
lambdaXorReg_11 [7:0] <= 8'd0;
lambdaXorReg_12 [7:0] <= 8'd0;
lambdaXorReg_13 [7:0] <= 8'd0;
lambdaXorReg_14 [7:0] <= 8'd0;
lambdaXorReg_15 [7:0] <= 8'd0;
lambdaXorReg_16 [7:0] <= 8'd0;
lambdaXorReg_17 [7:0] <= 8'd0;
lambdaXorReg_18 [7:0] <= 8'd0;
lambdaXorReg_19 [7:0] <= 8'd0;
lambdaXorReg_20 [7:0] <= 8'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
lambdaXorReg_0 [7:0] <= 8'd0;
lambdaXorReg_1 [7:0] <= 8'd0;
lambdaXorReg_2 [7:0] <= 8'd0;
lambdaXorReg_3 [7:0] <= 8'd0;
lambdaXorReg_4 [7:0] <= 8'd0;
lambdaXorReg_5 [7:0] <= 8'd0;
lambdaXorReg_6 [7:0] <= 8'd0;
lambdaXorReg_7 [7:0] <= 8'd0;
lambdaXorReg_8 [7:0] <= 8'd0;
lambdaXorReg_9 [7:0] <= 8'd0;
lambdaXorReg_10 [7:0] <= 8'd0;
lambdaXorReg_11 [7:0] <= 8'd0;
lambdaXorReg_12 [7:0] <= 8'd0;
lambdaXorReg_13 [7:0] <= 8'd0;
lambdaXorReg_14 [7:0] <= 8'd0;
lambdaXorReg_15 [7:0] <= 8'd0;
lambdaXorReg_16 [7:0] <= 8'd0;
lambdaXorReg_17 [7:0] <= 8'd0;
lambdaXorReg_18 [7:0] <= 8'd0;
lambdaXorReg_19 [7:0] <= 8'd0;
lambdaXorReg_20 [7:0] <= 8'd0;
end
else if (phase == 2'b00) begin
if ((skip == 1'b0) && (offset == 5'd0)) begin
lambdaXorReg_0 [7:0] <= 8'd0;
lambdaXorReg_1 [7:0] <= 8'd0;
lambdaXorReg_2 [7:0] <= 8'd0;
lambdaXorReg_3 [7:0] <= 8'd0;
lambdaXorReg_4 [7:0] <= 8'd0;
lambdaXorReg_5 [7:0] <= 8'd0;
lambdaXorReg_6 [7:0] <= 8'd0;
lambdaXorReg_7 [7:0] <= 8'd0;
lambdaXorReg_8 [7:0] <= 8'd0;
lambdaXorReg_9 [7:0] <= 8'd0;
lambdaXorReg_10 [7:0] <= 8'd0;
lambdaXorReg_11 [7:0] <= 8'd0;
lambdaXorReg_12 [7:0] <= 8'd0;
lambdaXorReg_13 [7:0] <= 8'd0;
lambdaXorReg_14 [7:0] <= 8'd0;
lambdaXorReg_15 [7:0] <= 8'd0;
lambdaXorReg_16 [7:0] <= 8'd0;
lambdaXorReg_17 [7:0] <= 8'd0;
lambdaXorReg_18 [7:0] <= 8'd0;
lambdaXorReg_19 [7:0] <= 8'd0;
lambdaXorReg_20 [7:0] <= 8'd0;
end
else if (skip == 1'b0) begin
lambdaXorReg_0 [7:0] <= lambdaMultqNew_0 [7:0];
lambdaXorReg_1 [7:0] <= lambdaMultqNew_1 [7:0] ^ lambdaXorReg_0[7:0];
lambdaXorReg_2 [7:0] <= lambdaMultqNew_2 [7:0] ^ lambdaXorReg_1[7:0];
lambdaXorReg_3 [7:0] <= lambdaMultqNew_3 [7:0] ^ lambdaXorReg_2[7:0];
lambdaXorReg_4 [7:0] <= lambdaMultqNew_4 [7:0] ^ lambdaXorReg_3[7:0];
lambdaXorReg_5 [7:0] <= lambdaMultqNew_5 [7:0] ^ lambdaXorReg_4[7:0];
lambdaXorReg_6 [7:0] <= lambdaMultqNew_6 [7:0] ^ lambdaXorReg_5[7:0];
lambdaXorReg_7 [7:0] <= lambdaMultqNew_7 [7:0] ^ lambdaXorReg_6[7:0];
lambdaXorReg_8 [7:0] <= lambdaMultqNew_8 [7:0] ^ lambdaXorReg_7[7:0];
lambdaXorReg_9 [7:0] <= lambdaMultqNew_9 [7:0] ^ lambdaXorReg_8[7:0];
lambdaXorReg_10 [7:0] <= lambdaMultqNew_10 [7:0] ^ lambdaXorReg_9[7:0];
lambdaXorReg_11 [7:0] <= lambdaMultqNew_11 [7:0] ^ lambdaXorReg_10[7:0];
lambdaXorReg_12 [7:0] <= lambdaMultqNew_12 [7:0] ^ lambdaXorReg_11[7:0];
lambdaXorReg_13 [7:0] <= lambdaMultqNew_13 [7:0] ^ lambdaXorReg_12[7:0];
lambdaXorReg_14 [7:0] <= lambdaMultqNew_14 [7:0] ^ lambdaXorReg_13[7:0];
lambdaXorReg_15 [7:0] <= lambdaMultqNew_15 [7:0] ^ lambdaXorReg_14[7:0];
lambdaXorReg_16 [7:0] <= lambdaMultqNew_16 [7:0] ^ lambdaXorReg_15[7:0];
lambdaXorReg_17 [7:0] <= lambdaMultqNew_17 [7:0] ^ lambdaXorReg_16[7:0];
lambdaXorReg_18 [7:0] <= lambdaMultqNew_18 [7:0] ^ lambdaXorReg_17[7:0];
lambdaXorReg_19 [7:0] <= lambdaMultqNew_19 [7:0] ^ lambdaXorReg_18[7:0];
lambdaXorReg_20 [7:0] <= lambdaMultqNew_20 [7:0] ^ lambdaXorReg_19[7:0];
end
end
end
end
 
 
//------------------------------------------------------------------
// + offset
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
offset [4:0] <= 5'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
offset [4:0] <= 5'd1;
end
else if (phase [1:0] == 2'b00) begin
if ((skip == 1'b0) && (offset[4:0]==5'd0)) begin
offset [4:0] <= 5'd1;
end
else if (skip == 1'b1) begin
offset [4:0] <= offset [4:0] + 5'd1;
end
else begin
offset [4:0] <= offset [4:0] - 5'd1;
end
end
end
end
 
 
//------------------------------------------------------------------
// + numShiftedReg
//------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
numShiftedReg [4:0] <= 5'd0;
end
else if (enable_E == 1'b1) begin
if (sync == 1'b1) begin
numShiftedReg <= 5'd0;
end
else if (phase == 2'd0) begin
if ((skip == 1'b0) && (offset == 5'd0)) begin
numShiftedReg <= numShiftedReg + 5'd1;
end
else if (skip == 1'b1) begin
numShiftedReg <= numShiftedReg + 5'd1;
end
end
end
end
 
 
//------------------------------------------------------------------------
//- OutputPorts
//------------------------------------------------------------------------
assign lambda_0 [7:0] = lambdaInner_0 [7:0];
assign lambda_1 [7:0] = lambdaInner_1 [7:0];
assign lambda_2 [7:0] = lambdaInner_2 [7:0];
assign lambda_3 [7:0] = lambdaInner_3 [7:0];
assign lambda_4 [7:0] = lambdaInner_4 [7:0];
assign lambda_5 [7:0] = lambdaInner_5 [7:0];
assign lambda_6 [7:0] = lambdaInner_6 [7:0];
assign lambda_7 [7:0] = lambdaInner_7 [7:0];
assign lambda_8 [7:0] = lambdaInner_8 [7:0];
assign lambda_9 [7:0] = lambdaInner_9 [7:0];
assign lambda_10 [7:0] = lambdaInner_10 [7:0];
assign lambda_11 [7:0] = lambdaInner_11 [7:0];
assign lambda_12 [7:0] = lambdaInner_12 [7:0];
assign lambda_13 [7:0] = lambdaInner_13 [7:0];
assign lambda_14 [7:0] = lambdaInner_14 [7:0];
assign lambda_15 [7:0] = lambdaInner_15 [7:0];
assign lambda_16 [7:0] = lambdaInner_16 [7:0];
assign lambda_17 [7:0] = lambdaInner_17 [7:0];
assign lambda_18 [7:0] = lambdaInner_18 [7:0];
assign lambda_19 [7:0] = lambdaInner_19 [7:0];
assign lambda_20 [7:0] = lambdaInner_20 [7:0];
assign lambda_21 [7:0] = lambdaInner_21 [7:0];
 
assign omega_0 [7:0] = omegaInner_0 [7:0];
assign omega_1 [7:0] = omegaInner_1 [7:0];
assign omega_2 [7:0] = omegaInner_2 [7:0];
assign omega_3 [7:0] = omegaInner_3 [7:0];
assign omega_4 [7:0] = omegaInner_4 [7:0];
assign omega_5 [7:0] = omegaInner_5 [7:0];
assign omega_6 [7:0] = omegaInner_6 [7:0];
assign omega_7 [7:0] = omegaInner_7 [7:0];
assign omega_8 [7:0] = omegaInner_8 [7:0];
assign omega_9 [7:0] = omegaInner_9 [7:0];
assign omega_10 [7:0] = omegaInner_10 [7:0];
assign omega_11 [7:0] = omegaInner_11 [7:0];
assign omega_12 [7:0] = omegaInner_12 [7:0];
assign omega_13 [7:0] = omegaInner_13 [7:0];
assign omega_14 [7:0] = omegaInner_14 [7:0];
assign omega_15 [7:0] = omegaInner_15 [7:0];
assign omega_16 [7:0] = omegaInner_16 [7:0];
assign omega_17 [7:0] = omegaInner_17 [7:0];
assign omega_18 [7:0] = omegaInner_18 [7:0];
assign omega_19 [7:0] = omegaInner_19 [7:0];
assign omega_20 [7:0] = omegaInner_20 [7:0];
assign omega_21 [7:0] = omegaInner_21 [7:0];
assign numShifted = numShiftedReg;
 
 
endmodule
/trunk/example/rtl/RsDecodeDegree.v
0,0 → 1,135
//===================================================================
// Module Name : RsDecodeDegree
// File Name : RsDecodeDegree.v
// Function : Rs Decoder Degree Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeDegree(
polynom_0,
polynom_1,
polynom_2,
polynom_3,
polynom_4,
polynom_5,
polynom_6,
polynom_7,
polynom_8,
polynom_9,
polynom_10,
polynom_11,
polynom_12,
polynom_13,
polynom_14,
polynom_15,
polynom_16,
polynom_17,
polynom_18,
polynom_19,
polynom_20,
polynom_21,
degree
);
 
 
input [7:0] polynom_0; // polynom 0
input [7:0] polynom_1; // polynom 1
input [7:0] polynom_2; // polynom 2
input [7:0] polynom_3; // polynom 3
input [7:0] polynom_4; // polynom 4
input [7:0] polynom_5; // polynom 5
input [7:0] polynom_6; // polynom 6
input [7:0] polynom_7; // polynom 7
input [7:0] polynom_8; // polynom 8
input [7:0] polynom_9; // polynom 9
input [7:0] polynom_10; // polynom 10
input [7:0] polynom_11; // polynom 11
input [7:0] polynom_12; // polynom 12
input [7:0] polynom_13; // polynom 13
input [7:0] polynom_14; // polynom 14
input [7:0] polynom_15; // polynom 15
input [7:0] polynom_16; // polynom 16
input [7:0] polynom_17; // polynom 17
input [7:0] polynom_18; // polynom 18
input [7:0] polynom_19; // polynom 19
input [7:0] polynom_20; // polynom 20
input [7:0] polynom_21; // polynom 21
output [4:0] degree; // polynom degree
 
 
 
//------------------------------------------------------------------------
//- registers
//------------------------------------------------------------------------
//---------------------------------------------------------------
//- step 0
//---------------------------------------------------------------
wire [4:0] winner0Step0;
assign winner0Step0 =(polynom_1 [7:0] == 8'd0) ? ((polynom_0 [7:0] == 8'd0) ? 5'd0 : 5'd0): 5'd1;
wire [4:0] winner1Step0;
assign winner1Step0 =(polynom_3 [7:0] == 8'd0) ? ((polynom_2 [7:0] == 8'd0) ? 5'd0 : 5'd2): 5'd3;
wire [4:0] winner2Step0;
assign winner2Step0 =(polynom_5 [7:0] == 8'd0) ? ((polynom_4 [7:0] == 8'd0) ? 5'd0 : 5'd4): 5'd5;
wire [4:0] winner3Step0;
assign winner3Step0 =(polynom_7 [7:0] == 8'd0) ? ((polynom_6 [7:0] == 8'd0) ? 5'd0 : 5'd6): 5'd7;
wire [4:0] winner4Step0;
assign winner4Step0 =(polynom_9 [7:0] == 8'd0) ? ((polynom_8 [7:0] == 8'd0) ? 5'd0 : 5'd8): 5'd9;
wire [4:0] winner5Step0;
assign winner5Step0 =(polynom_11 [7:0] == 8'd0) ? ((polynom_10 [7:0] == 8'd0) ? 5'd0 : 5'd10): 5'd11;
wire [4:0] winner6Step0;
assign winner6Step0 =(polynom_13 [7:0] == 8'd0) ? ((polynom_12 [7:0] == 8'd0) ? 5'd0 : 5'd12): 5'd13;
wire [4:0] winner7Step0;
assign winner7Step0 =(polynom_15 [7:0] == 8'd0) ? ((polynom_14 [7:0] == 8'd0) ? 5'd0 : 5'd14): 5'd15;
wire [4:0] winner8Step0;
assign winner8Step0 =(polynom_17 [7:0] == 8'd0) ? ((polynom_16 [7:0] == 8'd0) ? 5'd0 : 5'd16): 5'd17;
wire [4:0] winner9Step0;
assign winner9Step0 =(polynom_19 [7:0] == 8'd0) ? ((polynom_18 [7:0] == 8'd0) ? 5'd0 : 5'd18): 5'd19;
wire [4:0] winner10Step0;
assign winner10Step0 =(polynom_21 [7:0] == 8'd0) ? ((polynom_20 [7:0] == 8'd0) ? 5'd0 : 5'd20): 5'd21;
//---------------------------------------------------------------
//- step 1
//---------------------------------------------------------------
wire [4:0] winner0Step1;
assign winner0Step1 =( winner1Step0 [4:0] < winner0Step0 [4:0]) ? winner0Step0 [4:0]: winner1Step0 [4:0];
wire [4:0] winner1Step1;
assign winner1Step1 =( winner3Step0 [4:0] < winner2Step0 [4:0]) ? winner2Step0 [4:0]: winner3Step0 [4:0];
wire [4:0] winner2Step1;
assign winner2Step1 =( winner5Step0 [4:0] < winner4Step0 [4:0]) ? winner4Step0 [4:0]: winner5Step0 [4:0];
wire [4:0] winner3Step1;
assign winner3Step1 =( winner7Step0 [4:0] < winner6Step0 [4:0]) ? winner6Step0 [4:0]: winner7Step0 [4:0];
wire [4:0] winner4Step1;
assign winner4Step1 =( winner9Step0 [4:0] < winner8Step0 [4:0]) ? winner8Step0 [4:0]: winner9Step0 [4:0];
//---------------------------------------------------------------
//- step 2
//---------------------------------------------------------------
wire [4:0] winner0Step2;
assign winner0Step2 =( winner1Step1 [4:0] < winner0Step1 [4:0]) ? winner0Step1 [4:0]: winner1Step1 [4:0];
wire [4:0] winner1Step2;
assign winner1Step2 =( winner3Step1 [4:0] < winner2Step1 [4:0]) ? winner2Step1 [4:0]: winner3Step1 [4:0];
wire [4:0] winner2Step2;
assign winner2Step2 =( winner10Step0 [4:0] < winner4Step1 [4:0]) ? winner4Step1 [4:0]: winner10Step0 [4:0];
//---------------------------------------------------------------
//- step 3
//---------------------------------------------------------------
wire [4:0] winner0Step3;
assign winner0Step3 =( winner1Step2 [4:0] < winner0Step2 [4:0]) ? winner0Step2 [4:0]: winner1Step2 [4:0];
//---------------------------------------------------------------
//- step 4
//---------------------------------------------------------------
wire [4:0] winner0Step4;
assign winner0Step4 =( winner2Step2 [4:0] < winner0Step3 [4:0]) ? winner0Step3 [4:0]: winner2Step2 [4:0];
//---------------------------------------------------------------
//---------------------------------------------------------------
assign degree [4:0] = winner0Step4 [4:0] ;
 
 
 
endmodule
/trunk/example/rtl/RsEncodeTop.v
0,0 → 1,461
//===================================================================
// Module Name : RsEncodeTop
// File Name : RsEncodeTop.v
// Function : Rs Encoder Top Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsEncodeTop(
CLK, // system clock
RESET, // system reset
enable, // rs encoder enable signal
startPls, // rs encoder sync signal
dataIn, // rs encoder data in
dataOut // rs encoder data out
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // rs encoder enable signal
input startPls; // rs encoder sync signal
input [7:0] dataIn; // rs encoder data in
output [7:0] dataOut; // rs encoder data out
 
 
 
//---------------------------------------------------------------
//- registers
//---------------------------------------------------------------
reg [7:0] count;
reg dataValid;
reg [7:0] feedbackReg;
wire [7:0] mult_0;
wire [7:0] mult_1;
wire [7:0] mult_2;
wire [7:0] mult_3;
wire [7:0] mult_4;
wire [7:0] mult_5;
wire [7:0] mult_6;
wire [7:0] mult_7;
wire [7:0] mult_8;
wire [7:0] mult_9;
wire [7:0] mult_10;
wire [7:0] mult_11;
wire [7:0] mult_12;
wire [7:0] mult_13;
wire [7:0] mult_14;
wire [7:0] mult_15;
wire [7:0] mult_16;
wire [7:0] mult_17;
wire [7:0] mult_18;
wire [7:0] mult_19;
wire [7:0] mult_20;
wire [7:0] mult_21;
reg [7:0] syndromeReg_0;
reg [7:0] syndromeReg_1;
reg [7:0] syndromeReg_2;
reg [7:0] syndromeReg_3;
reg [7:0] syndromeReg_4;
reg [7:0] syndromeReg_5;
reg [7:0] syndromeReg_6;
reg [7:0] syndromeReg_7;
reg [7:0] syndromeReg_8;
reg [7:0] syndromeReg_9;
reg [7:0] syndromeReg_10;
reg [7:0] syndromeReg_11;
reg [7:0] syndromeReg_12;
reg [7:0] syndromeReg_13;
reg [7:0] syndromeReg_14;
reg [7:0] syndromeReg_15;
reg [7:0] syndromeReg_16;
reg [7:0] syndromeReg_17;
reg [7:0] syndromeReg_18;
reg [7:0] syndromeReg_19;
reg [7:0] syndromeReg_20;
reg [7:0] syndromeReg_21;
reg [7:0] dataReg;
reg [7:0] syndromeRegFF;
reg [7:0] wireOut;
 
 
 
//---------------------------------------------------------------
//- count
//---------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (startPls == 1'b1) begin
count[7:0] <= 8'd1;
end
else if ((count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
count[7:0] <= 8'd0;
end
else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
 
 
 
//---------------------------------------------------------------
//- dataValid
//---------------------------------------------------------------
always @(count or startPls) begin
if (startPls == 1'b1 || (count[7:0] < 8'd233)) begin
dataValid = 1'b1;
end
else begin
dataValid = 1'b0;
end
end
 
 
 
 
//---------------------------------------------------------------
//- Multipliers
//---------------------------------------------------------------
assign mult_9[0] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_9[1] = feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_9[2] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_9[3] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_9[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6];
assign mult_9[5] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_9[6] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_9[7] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_15[0] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_15[1] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5];
assign mult_15[2] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_15[3] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_15[4] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_15[5] = feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_15[6] = feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_15[7] = feedbackReg[3] ^ feedbackReg[6];
assign mult_12[0] = feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_12[1] = feedbackReg[4] ^ feedbackReg[6];
assign mult_12[2] = feedbackReg[3];
assign mult_12[3] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_12[4] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_12[5] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_12[6] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_12[7] = feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_10[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_10[1] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[7];
assign mult_10[2] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_10[3] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_10[4] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_10[5] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_10[6] = feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_10[7] = feedbackReg[0] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_6[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_6[1] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_6[2] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_6[3] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_6[4] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_6[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_6[6] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_6[7] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_17[0] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_17[1] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_17[2] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_17[3] = feedbackReg[3] ^ feedbackReg[4];
assign mult_17[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_17[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4];
assign mult_17[6] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
assign mult_17[7] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_7[0] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[6];
assign mult_7[1] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_7[2] = feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_7[3] = feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_7[4] = feedbackReg[2] ^ feedbackReg[7];
assign mult_7[5] = feedbackReg[3];
assign mult_7[6] = feedbackReg[0] ^ feedbackReg[4];
assign mult_7[7] = feedbackReg[1] ^ feedbackReg[5];
assign mult_2[0] = feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_2[1] = feedbackReg[0] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_2[2] = feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_2[3] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_2[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_2[5] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_2[6] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_2[7] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_14[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_14[1] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_14[2] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_14[3] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_14[4] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_14[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_14[6] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_14[7] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_4[0] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_4[1] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
assign mult_4[2] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_4[3] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3];
assign mult_4[4] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_4[5] = feedbackReg[1] ^ feedbackReg[4];
assign mult_4[6] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[5];
assign mult_4[7] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[6];
assign mult_3[0] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_3[1] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_3[2] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_3[3] = feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_3[4] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_3[5] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_3[6] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_3[7] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_1[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_1[1] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_1[2] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_1[3] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_1[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_1[5] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_1[6] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_1[7] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_20[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_20[1] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_20[2] = feedbackReg[2] ^ feedbackReg[4];
assign mult_20[3] = feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_20[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_20[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_20[6] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_20[7] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_8[0] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_8[1] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_8[2] = feedbackReg[1] ^ feedbackReg[3];
assign mult_8[3] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_8[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
assign mult_8[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_8[6] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_8[7] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_11[0] = feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_11[1] = feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_11[2] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_11[3] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[4];
assign mult_11[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_11[5] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_11[6] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_11[7] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_21[0] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_21[1] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_21[2] = feedbackReg[5];
assign mult_21[3] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_21[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_21[5] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_21[6] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_21[7] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_5[0] = feedbackReg[2] ^ feedbackReg[4];
assign mult_5[1] = feedbackReg[0] ^ feedbackReg[3] ^ feedbackReg[5];
assign mult_5[2] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6];
assign mult_5[3] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_5[4] = feedbackReg[0] ^ feedbackReg[5];
assign mult_5[5] = feedbackReg[1] ^ feedbackReg[6];
assign mult_5[6] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[7];
assign mult_5[7] = feedbackReg[1] ^ feedbackReg[3];
assign mult_13[0] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[7];
assign mult_13[1] = feedbackReg[1] ^ feedbackReg[3];
assign mult_13[2] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_13[3] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_13[4] = feedbackReg[3] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_13[5] = feedbackReg[4] ^ feedbackReg[7];
assign mult_13[6] = feedbackReg[0] ^ feedbackReg[5];
assign mult_13[7] = feedbackReg[1] ^ feedbackReg[6];
assign mult_16[0] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_16[1] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_16[2] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2];
assign mult_16[3] = feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_16[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_16[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_16[6] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_16[7] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_0[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_0[1] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_0[2] = feedbackReg[0] ^ feedbackReg[1];
assign mult_0[3] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_0[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3];
assign mult_0[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_0[6] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_0[7] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_18[0] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_18[1] = feedbackReg[2] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_18[2] = feedbackReg[1] ^ feedbackReg[4] ^ feedbackReg[7];
assign mult_18[3] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_18[4] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_18[5] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[7];
assign mult_18[6] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4];
assign mult_18[7] = feedbackReg[0] ^ feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5];
assign mult_19[0] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[5] ^ feedbackReg[6];
assign mult_19[1] = feedbackReg[0] ^ feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_19[2] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5] ^ feedbackReg[6] ^ feedbackReg[7];
assign mult_19[3] = feedbackReg[1] ^ feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
assign mult_19[4] = feedbackReg[1] ^ feedbackReg[2] ^ feedbackReg[4];
assign mult_19[5] = feedbackReg[2] ^ feedbackReg[3] ^ feedbackReg[5];
assign mult_19[6] = feedbackReg[3] ^ feedbackReg[4] ^ feedbackReg[6];
assign mult_19[7] = feedbackReg[0] ^ feedbackReg[4] ^ feedbackReg[5] ^ feedbackReg[7];
 
 
 
//---------------------------------------------------------------
//- syndromeReg
//---------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
syndromeReg_0 [7:0] <= 8'd0;
syndromeReg_1 [7:0] <= 8'd0;
syndromeReg_2 [7:0] <= 8'd0;
syndromeReg_3 [7:0] <= 8'd0;
syndromeReg_4 [7:0] <= 8'd0;
syndromeReg_5 [7:0] <= 8'd0;
syndromeReg_6 [7:0] <= 8'd0;
syndromeReg_7 [7:0] <= 8'd0;
syndromeReg_8 [7:0] <= 8'd0;
syndromeReg_9 [7:0] <= 8'd0;
syndromeReg_10 [7:0] <= 8'd0;
syndromeReg_11 [7:0] <= 8'd0;
syndromeReg_12 [7:0] <= 8'd0;
syndromeReg_13 [7:0] <= 8'd0;
syndromeReg_14 [7:0] <= 8'd0;
syndromeReg_15 [7:0] <= 8'd0;
syndromeReg_16 [7:0] <= 8'd0;
syndromeReg_17 [7:0] <= 8'd0;
syndromeReg_18 [7:0] <= 8'd0;
syndromeReg_19 [7:0] <= 8'd0;
syndromeReg_20 [7:0] <= 8'd0;
syndromeReg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (startPls == 1'b1) begin
syndromeReg_0 [7:0] <= mult_0 [7:0];
syndromeReg_1 [7:0] <= mult_1 [7:0];
syndromeReg_2 [7:0] <= mult_2 [7:0];
syndromeReg_3 [7:0] <= mult_3 [7:0];
syndromeReg_4 [7:0] <= mult_4 [7:0];
syndromeReg_5 [7:0] <= mult_5 [7:0];
syndromeReg_6 [7:0] <= mult_6 [7:0];
syndromeReg_7 [7:0] <= mult_7 [7:0];
syndromeReg_8 [7:0] <= mult_8 [7:0];
syndromeReg_9 [7:0] <= mult_9 [7:0];
syndromeReg_10 [7:0] <= mult_10 [7:0];
syndromeReg_11 [7:0] <= mult_11 [7:0];
syndromeReg_12 [7:0] <= mult_12 [7:0];
syndromeReg_13 [7:0] <= mult_13 [7:0];
syndromeReg_14 [7:0] <= mult_14 [7:0];
syndromeReg_15 [7:0] <= mult_15 [7:0];
syndromeReg_16 [7:0] <= mult_16 [7:0];
syndromeReg_17 [7:0] <= mult_17 [7:0];
syndromeReg_18 [7:0] <= mult_18 [7:0];
syndromeReg_19 [7:0] <= mult_19 [7:0];
syndromeReg_20 [7:0] <= mult_20 [7:0];
syndromeReg_21 [7:0] <= mult_21 [7:0];
end
else begin
syndromeReg_0 [7:0] <= mult_0 [7:0];
syndromeReg_1 [7:0] <= (syndromeReg_0 [7:0] ^ mult_1 [7:0]);
syndromeReg_2 [7:0] <= (syndromeReg_1 [7:0] ^ mult_2 [7:0]);
syndromeReg_3 [7:0] <= (syndromeReg_2 [7:0] ^ mult_3 [7:0]);
syndromeReg_4 [7:0] <= (syndromeReg_3 [7:0] ^ mult_4 [7:0]);
syndromeReg_5 [7:0] <= (syndromeReg_4 [7:0] ^ mult_5 [7:0]);
syndromeReg_6 [7:0] <= (syndromeReg_5 [7:0] ^ mult_6 [7:0]);
syndromeReg_7 [7:0] <= (syndromeReg_6 [7:0] ^ mult_7 [7:0]);
syndromeReg_8 [7:0] <= (syndromeReg_7 [7:0] ^ mult_8 [7:0]);
syndromeReg_9 [7:0] <= (syndromeReg_8 [7:0] ^ mult_9 [7:0]);
syndromeReg_10 [7:0] <= (syndromeReg_9 [7:0] ^ mult_10 [7:0]);
syndromeReg_11 [7:0] <= (syndromeReg_10 [7:0] ^ mult_11 [7:0]);
syndromeReg_12 [7:0] <= (syndromeReg_11 [7:0] ^ mult_12 [7:0]);
syndromeReg_13 [7:0] <= (syndromeReg_12 [7:0] ^ mult_13 [7:0]);
syndromeReg_14 [7:0] <= (syndromeReg_13 [7:0] ^ mult_14 [7:0]);
syndromeReg_15 [7:0] <= (syndromeReg_14 [7:0] ^ mult_15 [7:0]);
syndromeReg_16 [7:0] <= (syndromeReg_15 [7:0] ^ mult_16 [7:0]);
syndromeReg_17 [7:0] <= (syndromeReg_16 [7:0] ^ mult_17 [7:0]);
syndromeReg_18 [7:0] <= (syndromeReg_17 [7:0] ^ mult_18 [7:0]);
syndromeReg_19 [7:0] <= (syndromeReg_18 [7:0] ^ mult_19 [7:0]);
syndromeReg_20 [7:0] <= (syndromeReg_19 [7:0] ^ mult_20 [7:0]);
syndromeReg_21 [7:0] <= (syndromeReg_20 [7:0] ^ mult_21 [7:0]);
end
end
end
 
 
 
//---------------------------------------------------------------
//- feedbackReg
//---------------------------------------------------------------
always @( startPls, dataValid, dataIn, syndromeReg_21 ) begin
if (startPls == 1'b1) begin
feedbackReg[7:0] = dataIn[7:0];
end
else if (dataValid == 1'b1) begin
feedbackReg [7:0] = dataIn[7:0] ^ syndromeReg_21 [7:0];
end
else begin
feedbackReg [7:0] = 8'd0;
end
end
 
 
 
//---------------------------------------------------------------
//- dataReg syndromeRegFF
//---------------------------------------------------------------
always @(posedge CLK, negedge RESET) begin
if (~RESET) begin
dataReg [7:0] <= 8'd0;
syndromeRegFF [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
dataReg [7:0] <= dataIn [7:0];
syndromeRegFF [7:0] <= syndromeReg_21 [7:0];
end
end
 
 
 
//---------------------------------------------------------------
//- wireOut
//---------------------------------------------------------------
always @( count, dataReg, syndromeRegFF) begin
if (count [7:0]<= 8'd233) begin
wireOut[7:0] = dataReg[7:0];
end
else begin
wireOut[7:0] = syndromeRegFF[7:0];
end
end
 
 
 
//---------------------------------------------------------------
//- dataOutInner
//---------------------------------------------------------------
reg [7:0] dataOutInner;
always @(posedge CLK, negedge RESET) begin
if (~RESET) begin
dataOutInner <= 8'd0;
end
else begin
dataOutInner <= wireOut;
end
end
 
 
 
//---------------------------------------------------------------
//- Output ports
//---------------------------------------------------------------
assign dataOut = dataOutInner;
 
 
 
endmodule
/trunk/example/rtl/RsDecodeInv.v
0,0 → 1,801
//===================================================================
// Module Name : RsDecodeInv
// File Name : RsDecodeInv.v
// Function : Rs Decoder Inverse calculation Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeInv(
B, // data in
R // data out
);
 
 
input [7:0] B; // data in
output [7:0] R; // data out
 
 
reg [7:0] R;
 
 
always @(B) begin
case (B)
8'd0: begin
R = 8'd0;
end
8'd1: begin
R = 8'd1;
end
8'd2: begin
R = 8'd142;
end
8'd3: begin
R = 8'd244;
end
8'd4: begin
R = 8'd71;
end
8'd5: begin
R = 8'd167;
end
8'd6: begin
R = 8'd122;
end
8'd7: begin
R = 8'd186;
end
8'd8: begin
R = 8'd173;
end
8'd9: begin
R = 8'd157;
end
8'd10: begin
R = 8'd221;
end
8'd11: begin
R = 8'd152;
end
8'd12: begin
R = 8'd61;
end
8'd13: begin
R = 8'd170;
end
8'd14: begin
R = 8'd93;
end
8'd15: begin
R = 8'd150;
end
8'd16: begin
R = 8'd216;
end
8'd17: begin
R = 8'd114;
end
8'd18: begin
R = 8'd192;
end
8'd19: begin
R = 8'd88;
end
8'd20: begin
R = 8'd224;
end
8'd21: begin
R = 8'd62;
end
8'd22: begin
R = 8'd76;
end
8'd23: begin
R = 8'd102;
end
8'd24: begin
R = 8'd144;
end
8'd25: begin
R = 8'd222;
end
8'd26: begin
R = 8'd85;
end
8'd27: begin
R = 8'd128;
end
8'd28: begin
R = 8'd160;
end
8'd29: begin
R = 8'd131;
end
8'd30: begin
R = 8'd75;
end
8'd31: begin
R = 8'd42;
end
8'd32: begin
R = 8'd108;
end
8'd33: begin
R = 8'd237;
end
8'd34: begin
R = 8'd57;
end
8'd35: begin
R = 8'd81;
end
8'd36: begin
R = 8'd96;
end
8'd37: begin
R = 8'd86;
end
8'd38: begin
R = 8'd44;
end
8'd39: begin
R = 8'd138;
end
8'd40: begin
R = 8'd112;
end
8'd41: begin
R = 8'd208;
end
8'd42: begin
R = 8'd31;
end
8'd43: begin
R = 8'd74;
end
8'd44: begin
R = 8'd38;
end
8'd45: begin
R = 8'd139;
end
8'd46: begin
R = 8'd51;
end
8'd47: begin
R = 8'd110;
end
8'd48: begin
R = 8'd72;
end
8'd49: begin
R = 8'd137;
end
8'd50: begin
R = 8'd111;
end
8'd51: begin
R = 8'd46;
end
8'd52: begin
R = 8'd164;
end
8'd53: begin
R = 8'd195;
end
8'd54: begin
R = 8'd64;
end
8'd55: begin
R = 8'd94;
end
8'd56: begin
R = 8'd80;
end
8'd57: begin
R = 8'd34;
end
8'd58: begin
R = 8'd207;
end
8'd59: begin
R = 8'd169;
end
8'd60: begin
R = 8'd171;
end
8'd61: begin
R = 8'd12;
end
8'd62: begin
R = 8'd21;
end
8'd63: begin
R = 8'd225;
end
8'd64: begin
R = 8'd54;
end
8'd65: begin
R = 8'd95;
end
8'd66: begin
R = 8'd248;
end
8'd67: begin
R = 8'd213;
end
8'd68: begin
R = 8'd146;
end
8'd69: begin
R = 8'd78;
end
8'd70: begin
R = 8'd166;
end
8'd71: begin
R = 8'd4;
end
8'd72: begin
R = 8'd48;
end
8'd73: begin
R = 8'd136;
end
8'd74: begin
R = 8'd43;
end
8'd75: begin
R = 8'd30;
end
8'd76: begin
R = 8'd22;
end
8'd77: begin
R = 8'd103;
end
8'd78: begin
R = 8'd69;
end
8'd79: begin
R = 8'd147;
end
8'd80: begin
R = 8'd56;
end
8'd81: begin
R = 8'd35;
end
8'd82: begin
R = 8'd104;
end
8'd83: begin
R = 8'd140;
end
8'd84: begin
R = 8'd129;
end
8'd85: begin
R = 8'd26;
end
8'd86: begin
R = 8'd37;
end
8'd87: begin
R = 8'd97;
end
8'd88: begin
R = 8'd19;
end
8'd89: begin
R = 8'd193;
end
8'd90: begin
R = 8'd203;
end
8'd91: begin
R = 8'd99;
end
8'd92: begin
R = 8'd151;
end
8'd93: begin
R = 8'd14;
end
8'd94: begin
R = 8'd55;
end
8'd95: begin
R = 8'd65;
end
8'd96: begin
R = 8'd36;
end
8'd97: begin
R = 8'd87;
end
8'd98: begin
R = 8'd202;
end
8'd99: begin
R = 8'd91;
end
8'd100: begin
R = 8'd185;
end
8'd101: begin
R = 8'd196;
end
8'd102: begin
R = 8'd23;
end
8'd103: begin
R = 8'd77;
end
8'd104: begin
R = 8'd82;
end
8'd105: begin
R = 8'd141;
end
8'd106: begin
R = 8'd239;
end
8'd107: begin
R = 8'd179;
end
8'd108: begin
R = 8'd32;
end
8'd109: begin
R = 8'd236;
end
8'd110: begin
R = 8'd47;
end
8'd111: begin
R = 8'd50;
end
8'd112: begin
R = 8'd40;
end
8'd113: begin
R = 8'd209;
end
8'd114: begin
R = 8'd17;
end
8'd115: begin
R = 8'd217;
end
8'd116: begin
R = 8'd233;
end
8'd117: begin
R = 8'd251;
end
8'd118: begin
R = 8'd218;
end
8'd119: begin
R = 8'd121;
end
8'd120: begin
R = 8'd219;
end
8'd121: begin
R = 8'd119;
end
8'd122: begin
R = 8'd6;
end
8'd123: begin
R = 8'd187;
end
8'd124: begin
R = 8'd132;
end
8'd125: begin
R = 8'd205;
end
8'd126: begin
R = 8'd254;
end
8'd127: begin
R = 8'd252;
end
8'd128: begin
R = 8'd27;
end
8'd129: begin
R = 8'd84;
end
8'd130: begin
R = 8'd161;
end
8'd131: begin
R = 8'd29;
end
8'd132: begin
R = 8'd124;
end
8'd133: begin
R = 8'd204;
end
8'd134: begin
R = 8'd228;
end
8'd135: begin
R = 8'd176;
end
8'd136: begin
R = 8'd73;
end
8'd137: begin
R = 8'd49;
end
8'd138: begin
R = 8'd39;
end
8'd139: begin
R = 8'd45;
end
8'd140: begin
R = 8'd83;
end
8'd141: begin
R = 8'd105;
end
8'd142: begin
R = 8'd2;
end
8'd143: begin
R = 8'd245;
end
8'd144: begin
R = 8'd24;
end
8'd145: begin
R = 8'd223;
end
8'd146: begin
R = 8'd68;
end
8'd147: begin
R = 8'd79;
end
8'd148: begin
R = 8'd155;
end
8'd149: begin
R = 8'd188;
end
8'd150: begin
R = 8'd15;
end
8'd151: begin
R = 8'd92;
end
8'd152: begin
R = 8'd11;
end
8'd153: begin
R = 8'd220;
end
8'd154: begin
R = 8'd189;
end
8'd155: begin
R = 8'd148;
end
8'd156: begin
R = 8'd172;
end
8'd157: begin
R = 8'd9;
end
8'd158: begin
R = 8'd199;
end
8'd159: begin
R = 8'd162;
end
8'd160: begin
R = 8'd28;
end
8'd161: begin
R = 8'd130;
end
8'd162: begin
R = 8'd159;
end
8'd163: begin
R = 8'd198;
end
8'd164: begin
R = 8'd52;
end
8'd165: begin
R = 8'd194;
end
8'd166: begin
R = 8'd70;
end
8'd167: begin
R = 8'd5;
end
8'd168: begin
R = 8'd206;
end
8'd169: begin
R = 8'd59;
end
8'd170: begin
R = 8'd13;
end
8'd171: begin
R = 8'd60;
end
8'd172: begin
R = 8'd156;
end
8'd173: begin
R = 8'd8;
end
8'd174: begin
R = 8'd190;
end
8'd175: begin
R = 8'd183;
end
8'd176: begin
R = 8'd135;
end
8'd177: begin
R = 8'd229;
end
8'd178: begin
R = 8'd238;
end
8'd179: begin
R = 8'd107;
end
8'd180: begin
R = 8'd235;
end
8'd181: begin
R = 8'd242;
end
8'd182: begin
R = 8'd191;
end
8'd183: begin
R = 8'd175;
end
8'd184: begin
R = 8'd197;
end
8'd185: begin
R = 8'd100;
end
8'd186: begin
R = 8'd7;
end
8'd187: begin
R = 8'd123;
end
8'd188: begin
R = 8'd149;
end
8'd189: begin
R = 8'd154;
end
8'd190: begin
R = 8'd174;
end
8'd191: begin
R = 8'd182;
end
8'd192: begin
R = 8'd18;
end
8'd193: begin
R = 8'd89;
end
8'd194: begin
R = 8'd165;
end
8'd195: begin
R = 8'd53;
end
8'd196: begin
R = 8'd101;
end
8'd197: begin
R = 8'd184;
end
8'd198: begin
R = 8'd163;
end
8'd199: begin
R = 8'd158;
end
8'd200: begin
R = 8'd210;
end
8'd201: begin
R = 8'd247;
end
8'd202: begin
R = 8'd98;
end
8'd203: begin
R = 8'd90;
end
8'd204: begin
R = 8'd133;
end
8'd205: begin
R = 8'd125;
end
8'd206: begin
R = 8'd168;
end
8'd207: begin
R = 8'd58;
end
8'd208: begin
R = 8'd41;
end
8'd209: begin
R = 8'd113;
end
8'd210: begin
R = 8'd200;
end
8'd211: begin
R = 8'd246;
end
8'd212: begin
R = 8'd249;
end
8'd213: begin
R = 8'd67;
end
8'd214: begin
R = 8'd215;
end
8'd215: begin
R = 8'd214;
end
8'd216: begin
R = 8'd16;
end
8'd217: begin
R = 8'd115;
end
8'd218: begin
R = 8'd118;
end
8'd219: begin
R = 8'd120;
end
8'd220: begin
R = 8'd153;
end
8'd221: begin
R = 8'd10;
end
8'd222: begin
R = 8'd25;
end
8'd223: begin
R = 8'd145;
end
8'd224: begin
R = 8'd20;
end
8'd225: begin
R = 8'd63;
end
8'd226: begin
R = 8'd230;
end
8'd227: begin
R = 8'd240;
end
8'd228: begin
R = 8'd134;
end
8'd229: begin
R = 8'd177;
end
8'd230: begin
R = 8'd226;
end
8'd231: begin
R = 8'd241;
end
8'd232: begin
R = 8'd250;
end
8'd233: begin
R = 8'd116;
end
8'd234: begin
R = 8'd243;
end
8'd235: begin
R = 8'd180;
end
8'd236: begin
R = 8'd109;
end
8'd237: begin
R = 8'd33;
end
8'd238: begin
R = 8'd178;
end
8'd239: begin
R = 8'd106;
end
8'd240: begin
R = 8'd227;
end
8'd241: begin
R = 8'd231;
end
8'd242: begin
R = 8'd181;
end
8'd243: begin
R = 8'd234;
end
8'd244: begin
R = 8'd3;
end
8'd245: begin
R = 8'd143;
end
8'd246: begin
R = 8'd211;
end
8'd247: begin
R = 8'd201;
end
8'd248: begin
R = 8'd66;
end
8'd249: begin
R = 8'd212;
end
8'd250: begin
R = 8'd232;
end
8'd251: begin
R = 8'd117;
end
8'd252: begin
R = 8'd127;
end
8'd253: begin
R = 8'd255;
end
8'd254: begin
R = 8'd126;
end
default: begin
R = 8'd253;
end
endcase
end
endmodule
/trunk/example/rtl/RsDecodeDelay.v
0,0 → 1,103
//===================================================================
// Module Name : RsDecodeDelay
// File Name : RsDecodeDelay.v
// Function : Rs DpRam Memory controller Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeDelay(
CLK, // system clock
RESET, // system reset
enable, // enable signal
dataIn, // data input
dataOut // data output
);
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input [8:0] dataIn; // data input
output [8:0] dataOut; // data output
 
 
 
//------------------------------------------------------------------------
//- registers
//------------------------------------------------------------------------
reg [8:0] writePointer;
reg [8:0] readPointer;
wire [8:0] dpramRdData;
 
 
 
//------------------------------------------------------------------------
//- RAM memory instantiation
//------------------------------------------------------------------------
RsDecodeDpRam RsDecodeDpRam(
// Outputs
.q(dpramRdData),
// Inputs
.clock(CLK),
.data(dataIn [8:0]),
.rdaddress(readPointer),
.rden(enable),
.wraddress(writePointer),
.wren(enable)
);
 
 
 
//------------------------------------------------------------------------
//+ dataOut
//------------------------------------------------------------------------
assign dataOut[8:0] = dpramRdData;
 
 
 
//------------------------------------------------------------------------
//- Write Pointer
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
writePointer <= 9'd351;
end
else if (enable == 1'b1) begin
if (writePointer == 9'd351) begin
writePointer <= 9'd0;
end
else begin
writePointer <= writePointer + 9'd1;
end
end
end
 
 
 
//------------------------------------------------------------------------
//- Read Pointer
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
readPointer [8:0] <= 9'd0;
end
else if (enable == 1'b1) begin
if (readPointer == 9'd351) begin
readPointer <= 9'd0;
end
else begin
readPointer <= readPointer + 9'd1;
end
end
end
 
 
 
endmodule
/trunk/example/rtl/RsDecodeSyndrome.v
0,0 → 1,453
//===================================================================
// Module Name : RsDecodeSyndrome
// File Name : RsDecodeSyndrome.v
// Function : Rs Decoder syndrome calculation
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeSyndrome(
CLK, // system clock
RESET, // system reset
enable, // enable signal
sync, // sync signal
dataIn, // data input
syndrome_0, // syndrome polynom 0
syndrome_1, // syndrome polynom 1
syndrome_2, // syndrome polynom 2
syndrome_3, // syndrome polynom 3
syndrome_4, // syndrome polynom 4
syndrome_5, // syndrome polynom 5
syndrome_6, // syndrome polynom 6
syndrome_7, // syndrome polynom 7
syndrome_8, // syndrome polynom 8
syndrome_9, // syndrome polynom 9
syndrome_10, // syndrome polynom 10
syndrome_11, // syndrome polynom 11
syndrome_12, // syndrome polynom 12
syndrome_13, // syndrome polynom 13
syndrome_14, // syndrome polynom 14
syndrome_15, // syndrome polynom 15
syndrome_16, // syndrome polynom 16
syndrome_17, // syndrome polynom 17
syndrome_18, // syndrome polynom 18
syndrome_19, // syndrome polynom 19
syndrome_20, // syndrome polynom 20
syndrome_21, // syndrome polynom 21
done // done signal
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input sync; // sync signal
input [7:0] dataIn; // data input
output [7:0] syndrome_0; // syndrome polynom 0
output [7:0] syndrome_1; // syndrome polynom 1
output [7:0] syndrome_2; // syndrome polynom 2
output [7:0] syndrome_3; // syndrome polynom 3
output [7:0] syndrome_4; // syndrome polynom 4
output [7:0] syndrome_5; // syndrome polynom 5
output [7:0] syndrome_6; // syndrome polynom 6
output [7:0] syndrome_7; // syndrome polynom 7
output [7:0] syndrome_8; // syndrome polynom 8
output [7:0] syndrome_9; // syndrome polynom 9
output [7:0] syndrome_10; // syndrome polynom 10
output [7:0] syndrome_11; // syndrome polynom 11
output [7:0] syndrome_12; // syndrome polynom 12
output [7:0] syndrome_13; // syndrome polynom 13
output [7:0] syndrome_14; // syndrome polynom 14
output [7:0] syndrome_15; // syndrome polynom 15
output [7:0] syndrome_16; // syndrome polynom 16
output [7:0] syndrome_17; // syndrome polynom 17
output [7:0] syndrome_18; // syndrome polynom 18
output [7:0] syndrome_19; // syndrome polynom 19
output [7:0] syndrome_20; // syndrome polynom 20
output [7:0] syndrome_21; // syndrome polynom 21
output done; // done signal
 
 
//------------------------------------------------------------------------
// + count
//- Counter
//------------------------------------------------------------------------
reg [7:0] count;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
count[7:0] <= 8'd1;
end
else if ( (count[7:0] ==8'd0) || (count[7:0] ==8'd255)) begin
count[7:0] <= 8'd0;
end
else begin
count[7:0] <= count[7:0] + 8'd1;
end
end
end
 
 
 
//------------------------------------------------------------------------
// + done
//------------------------------------------------------------------------
reg done;
always @(count) begin
if (count ==8'd255) begin
done = 1'b1;
end
else begin
done = 1'b0;
end
end
 
 
//------------------------------------------------------------------------
// + product_0,..., product_21
//- Syndrome Generator
//------------------------------------------------------------------------
wire [7:0] product_0;
wire [7:0] product_1;
wire [7:0] product_2;
wire [7:0] product_3;
wire [7:0] product_4;
wire [7:0] product_5;
wire [7:0] product_6;
wire [7:0] product_7;
wire [7:0] product_8;
wire [7:0] product_9;
wire [7:0] product_10;
wire [7:0] product_11;
wire [7:0] product_12;
wire [7:0] product_13;
wire [7:0] product_14;
wire [7:0] product_15;
wire [7:0] product_16;
wire [7:0] product_17;
wire [7:0] product_18;
wire [7:0] product_19;
wire [7:0] product_20;
wire [7:0] product_21;
 
reg [7:0] reg_0;
reg [7:0] reg_1;
reg [7:0] reg_2;
reg [7:0] reg_3;
reg [7:0] reg_4;
reg [7:0] reg_5;
reg [7:0] reg_6;
reg [7:0] reg_7;
reg [7:0] reg_8;
reg [7:0] reg_9;
reg [7:0] reg_10;
reg [7:0] reg_11;
reg [7:0] reg_12;
reg [7:0] reg_13;
reg [7:0] reg_14;
reg [7:0] reg_15;
reg [7:0] reg_16;
reg [7:0] reg_17;
reg [7:0] reg_18;
reg [7:0] reg_19;
reg [7:0] reg_20;
reg [7:0] reg_21;
 
assign product_0 [0] = reg_0[0];
assign product_0 [1] = reg_0[1];
assign product_0 [2] = reg_0[2];
assign product_0 [3] = reg_0[3];
assign product_0 [4] = reg_0[4];
assign product_0 [5] = reg_0[5];
assign product_0 [6] = reg_0[6];
assign product_0 [7] = reg_0[7];
assign product_1 [0] = reg_1[7];
assign product_1 [1] = reg_1[0];
assign product_1 [2] = reg_1[1] ^ reg_1[7];
assign product_1 [3] = reg_1[2] ^ reg_1[7];
assign product_1 [4] = reg_1[3] ^ reg_1[7];
assign product_1 [5] = reg_1[4];
assign product_1 [6] = reg_1[5];
assign product_1 [7] = reg_1[6];
assign product_2 [0] = reg_2[6];
assign product_2 [1] = reg_2[7];
assign product_2 [2] = reg_2[0] ^ reg_2[6];
assign product_2 [3] = reg_2[1] ^ reg_2[6] ^ reg_2[7];
assign product_2 [4] = reg_2[2] ^ reg_2[6] ^ reg_2[7];
assign product_2 [5] = reg_2[3] ^ reg_2[7];
assign product_2 [6] = reg_2[4];
assign product_2 [7] = reg_2[5];
assign product_3 [0] = reg_3[5];
assign product_3 [1] = reg_3[6];
assign product_3 [2] = reg_3[5] ^ reg_3[7];
assign product_3 [3] = reg_3[0] ^ reg_3[5] ^ reg_3[6];
assign product_3 [4] = reg_3[1] ^ reg_3[5] ^ reg_3[6] ^ reg_3[7];
assign product_3 [5] = reg_3[2] ^ reg_3[6] ^ reg_3[7];
assign product_3 [6] = reg_3[3] ^ reg_3[7];
assign product_3 [7] = reg_3[4];
assign product_4 [0] = reg_4[4];
assign product_4 [1] = reg_4[5];
assign product_4 [2] = reg_4[4] ^ reg_4[6];
assign product_4 [3] = reg_4[4] ^ reg_4[5] ^ reg_4[7];
assign product_4 [4] = reg_4[0] ^ reg_4[4] ^ reg_4[5] ^ reg_4[6];
assign product_4 [5] = reg_4[1] ^ reg_4[5] ^ reg_4[6] ^ reg_4[7];
assign product_4 [6] = reg_4[2] ^ reg_4[6] ^ reg_4[7];
assign product_4 [7] = reg_4[3] ^ reg_4[7];
assign product_5 [0] = reg_5[3] ^ reg_5[7];
assign product_5 [1] = reg_5[4];
assign product_5 [2] = reg_5[3] ^ reg_5[5] ^ reg_5[7];
assign product_5 [3] = reg_5[3] ^ reg_5[4] ^ reg_5[6] ^ reg_5[7];
assign product_5 [4] = reg_5[3] ^ reg_5[4] ^ reg_5[5];
assign product_5 [5] = reg_5[0] ^ reg_5[4] ^ reg_5[5] ^ reg_5[6];
assign product_5 [6] = reg_5[1] ^ reg_5[5] ^ reg_5[6] ^ reg_5[7];
assign product_5 [7] = reg_5[2] ^ reg_5[6] ^ reg_5[7];
assign product_6 [0] = reg_6[2] ^ reg_6[6] ^ reg_6[7];
assign product_6 [1] = reg_6[3] ^ reg_6[7];
assign product_6 [2] = reg_6[2] ^ reg_6[4] ^ reg_6[6] ^ reg_6[7];
assign product_6 [3] = reg_6[2] ^ reg_6[3] ^ reg_6[5] ^ reg_6[6];
assign product_6 [4] = reg_6[2] ^ reg_6[3] ^ reg_6[4];
assign product_6 [5] = reg_6[3] ^ reg_6[4] ^ reg_6[5];
assign product_6 [6] = reg_6[0] ^ reg_6[4] ^ reg_6[5] ^ reg_6[6];
assign product_6 [7] = reg_6[1] ^ reg_6[5] ^ reg_6[6] ^ reg_6[7];
assign product_7 [0] = reg_7[1] ^ reg_7[5] ^ reg_7[6] ^ reg_7[7];
assign product_7 [1] = reg_7[2] ^ reg_7[6] ^ reg_7[7];
assign product_7 [2] = reg_7[1] ^ reg_7[3] ^ reg_7[5] ^ reg_7[6];
assign product_7 [3] = reg_7[1] ^ reg_7[2] ^ reg_7[4] ^ reg_7[5];
assign product_7 [4] = reg_7[1] ^ reg_7[2] ^ reg_7[3] ^ reg_7[7];
assign product_7 [5] = reg_7[2] ^ reg_7[3] ^ reg_7[4];
assign product_7 [6] = reg_7[3] ^ reg_7[4] ^ reg_7[5];
assign product_7 [7] = reg_7[0] ^ reg_7[4] ^ reg_7[5] ^ reg_7[6];
assign product_8 [0] = reg_8[0] ^ reg_8[4] ^ reg_8[5] ^ reg_8[6];
assign product_8 [1] = reg_8[1] ^ reg_8[5] ^ reg_8[6] ^ reg_8[7];
assign product_8 [2] = reg_8[0] ^ reg_8[2] ^ reg_8[4] ^ reg_8[5] ^ reg_8[7];
assign product_8 [3] = reg_8[0] ^ reg_8[1] ^ reg_8[3] ^ reg_8[4];
assign product_8 [4] = reg_8[0] ^ reg_8[1] ^ reg_8[2] ^ reg_8[6];
assign product_8 [5] = reg_8[1] ^ reg_8[2] ^ reg_8[3] ^ reg_8[7];
assign product_8 [6] = reg_8[2] ^ reg_8[3] ^ reg_8[4];
assign product_8 [7] = reg_8[3] ^ reg_8[4] ^ reg_8[5];
assign product_9 [0] = reg_9[3] ^ reg_9[4] ^ reg_9[5];
assign product_9 [1] = reg_9[0] ^ reg_9[4] ^ reg_9[5] ^ reg_9[6];
assign product_9 [2] = reg_9[1] ^ reg_9[3] ^ reg_9[4] ^ reg_9[6] ^ reg_9[7];
assign product_9 [3] = reg_9[0] ^ reg_9[2] ^ reg_9[3] ^ reg_9[7];
assign product_9 [4] = reg_9[0] ^ reg_9[1] ^ reg_9[5];
assign product_9 [5] = reg_9[0] ^ reg_9[1] ^ reg_9[2] ^ reg_9[6];
assign product_9 [6] = reg_9[1] ^ reg_9[2] ^ reg_9[3] ^ reg_9[7];
assign product_9 [7] = reg_9[2] ^ reg_9[3] ^ reg_9[4];
assign product_10 [0] = reg_10[2] ^ reg_10[3] ^ reg_10[4];
assign product_10 [1] = reg_10[3] ^ reg_10[4] ^ reg_10[5];
assign product_10 [2] = reg_10[0] ^ reg_10[2] ^ reg_10[3] ^ reg_10[5] ^ reg_10[6];
assign product_10 [3] = reg_10[1] ^ reg_10[2] ^ reg_10[6] ^ reg_10[7];
assign product_10 [4] = reg_10[0] ^ reg_10[4] ^ reg_10[7];
assign product_10 [5] = reg_10[0] ^ reg_10[1] ^ reg_10[5];
assign product_10 [6] = reg_10[0] ^ reg_10[1] ^ reg_10[2] ^ reg_10[6];
assign product_10 [7] = reg_10[1] ^ reg_10[2] ^ reg_10[3] ^ reg_10[7];
assign product_11 [0] = reg_11[1] ^ reg_11[2] ^ reg_11[3] ^ reg_11[7];
assign product_11 [1] = reg_11[2] ^ reg_11[3] ^ reg_11[4];
assign product_11 [2] = reg_11[1] ^ reg_11[2] ^ reg_11[4] ^ reg_11[5] ^ reg_11[7];
assign product_11 [3] = reg_11[0] ^ reg_11[1] ^ reg_11[5] ^ reg_11[6] ^ reg_11[7];
assign product_11 [4] = reg_11[3] ^ reg_11[6];
assign product_11 [5] = reg_11[0] ^ reg_11[4] ^ reg_11[7];
assign product_11 [6] = reg_11[0] ^ reg_11[1] ^ reg_11[5];
assign product_11 [7] = reg_11[0] ^ reg_11[1] ^ reg_11[2] ^ reg_11[6];
assign product_12 [0] = reg_12[0] ^ reg_12[1] ^ reg_12[2] ^ reg_12[6];
assign product_12 [1] = reg_12[1] ^ reg_12[2] ^ reg_12[3] ^ reg_12[7];
assign product_12 [2] = reg_12[0] ^ reg_12[1] ^ reg_12[3] ^ reg_12[4] ^ reg_12[6];
assign product_12 [3] = reg_12[0] ^ reg_12[4] ^ reg_12[5] ^ reg_12[6] ^ reg_12[7];
assign product_12 [4] = reg_12[2] ^ reg_12[5] ^ reg_12[7];
assign product_12 [5] = reg_12[3] ^ reg_12[6];
assign product_12 [6] = reg_12[0] ^ reg_12[4] ^ reg_12[7];
assign product_12 [7] = reg_12[0] ^ reg_12[1] ^ reg_12[5];
assign product_13 [0] = reg_13[0] ^ reg_13[1] ^ reg_13[5];
assign product_13 [1] = reg_13[0] ^ reg_13[1] ^ reg_13[2] ^ reg_13[6];
assign product_13 [2] = reg_13[0] ^ reg_13[2] ^ reg_13[3] ^ reg_13[5] ^ reg_13[7];
assign product_13 [3] = reg_13[3] ^ reg_13[4] ^ reg_13[5] ^ reg_13[6];
assign product_13 [4] = reg_13[1] ^ reg_13[4] ^ reg_13[6] ^ reg_13[7];
assign product_13 [5] = reg_13[2] ^ reg_13[5] ^ reg_13[7];
assign product_13 [6] = reg_13[3] ^ reg_13[6];
assign product_13 [7] = reg_13[0] ^ reg_13[4] ^ reg_13[7];
assign product_14 [0] = reg_14[0] ^ reg_14[4] ^ reg_14[7];
assign product_14 [1] = reg_14[0] ^ reg_14[1] ^ reg_14[5];
assign product_14 [2] = reg_14[1] ^ reg_14[2] ^ reg_14[4] ^ reg_14[6] ^ reg_14[7];
assign product_14 [3] = reg_14[2] ^ reg_14[3] ^ reg_14[4] ^ reg_14[5];
assign product_14 [4] = reg_14[0] ^ reg_14[3] ^ reg_14[5] ^ reg_14[6] ^ reg_14[7];
assign product_14 [5] = reg_14[1] ^ reg_14[4] ^ reg_14[6] ^ reg_14[7];
assign product_14 [6] = reg_14[2] ^ reg_14[5] ^ reg_14[7];
assign product_14 [7] = reg_14[3] ^ reg_14[6];
assign product_15 [0] = reg_15[3] ^ reg_15[6];
assign product_15 [1] = reg_15[0] ^ reg_15[4] ^ reg_15[7];
assign product_15 [2] = reg_15[0] ^ reg_15[1] ^ reg_15[3] ^ reg_15[5] ^ reg_15[6];
assign product_15 [3] = reg_15[1] ^ reg_15[2] ^ reg_15[3] ^ reg_15[4] ^ reg_15[7];
assign product_15 [4] = reg_15[2] ^ reg_15[4] ^ reg_15[5] ^ reg_15[6];
assign product_15 [5] = reg_15[0] ^ reg_15[3] ^ reg_15[5] ^ reg_15[6] ^ reg_15[7];
assign product_15 [6] = reg_15[1] ^ reg_15[4] ^ reg_15[6] ^ reg_15[7];
assign product_15 [7] = reg_15[2] ^ reg_15[5] ^ reg_15[7];
assign product_16 [0] = reg_16[2] ^ reg_16[5] ^ reg_16[7];
assign product_16 [1] = reg_16[3] ^ reg_16[6];
assign product_16 [2] = reg_16[0] ^ reg_16[2] ^ reg_16[4] ^ reg_16[5];
assign product_16 [3] = reg_16[0] ^ reg_16[1] ^ reg_16[2] ^ reg_16[3] ^ reg_16[6] ^ reg_16[7];
assign product_16 [4] = reg_16[1] ^ reg_16[3] ^ reg_16[4] ^ reg_16[5];
assign product_16 [5] = reg_16[2] ^ reg_16[4] ^ reg_16[5] ^ reg_16[6];
assign product_16 [6] = reg_16[0] ^ reg_16[3] ^ reg_16[5] ^ reg_16[6] ^ reg_16[7];
assign product_16 [7] = reg_16[1] ^ reg_16[4] ^ reg_16[6] ^ reg_16[7];
assign product_17 [0] = reg_17[1] ^ reg_17[4] ^ reg_17[6] ^ reg_17[7];
assign product_17 [1] = reg_17[2] ^ reg_17[5] ^ reg_17[7];
assign product_17 [2] = reg_17[1] ^ reg_17[3] ^ reg_17[4] ^ reg_17[7];
assign product_17 [3] = reg_17[0] ^ reg_17[1] ^ reg_17[2] ^ reg_17[5] ^ reg_17[6] ^ reg_17[7];
assign product_17 [4] = reg_17[0] ^ reg_17[2] ^ reg_17[3] ^ reg_17[4];
assign product_17 [5] = reg_17[1] ^ reg_17[3] ^ reg_17[4] ^ reg_17[5];
assign product_17 [6] = reg_17[2] ^ reg_17[4] ^ reg_17[5] ^ reg_17[6];
assign product_17 [7] = reg_17[0] ^ reg_17[3] ^ reg_17[5] ^ reg_17[6] ^ reg_17[7];
assign product_18 [0] = reg_18[0] ^ reg_18[3] ^ reg_18[5] ^ reg_18[6] ^ reg_18[7];
assign product_18 [1] = reg_18[1] ^ reg_18[4] ^ reg_18[6] ^ reg_18[7];
assign product_18 [2] = reg_18[0] ^ reg_18[2] ^ reg_18[3] ^ reg_18[6];
assign product_18 [3] = reg_18[0] ^ reg_18[1] ^ reg_18[4] ^ reg_18[5] ^ reg_18[6];
assign product_18 [4] = reg_18[1] ^ reg_18[2] ^ reg_18[3];
assign product_18 [5] = reg_18[0] ^ reg_18[2] ^ reg_18[3] ^ reg_18[4];
assign product_18 [6] = reg_18[1] ^ reg_18[3] ^ reg_18[4] ^ reg_18[5];
assign product_18 [7] = reg_18[2] ^ reg_18[4] ^ reg_18[5] ^ reg_18[6];
assign product_19 [0] = reg_19[2] ^ reg_19[4] ^ reg_19[5] ^ reg_19[6];
assign product_19 [1] = reg_19[0] ^ reg_19[3] ^ reg_19[5] ^ reg_19[6] ^ reg_19[7];
assign product_19 [2] = reg_19[1] ^ reg_19[2] ^ reg_19[5] ^ reg_19[7];
assign product_19 [3] = reg_19[0] ^ reg_19[3] ^ reg_19[4] ^ reg_19[5];
assign product_19 [4] = reg_19[0] ^ reg_19[1] ^ reg_19[2];
assign product_19 [5] = reg_19[1] ^ reg_19[2] ^ reg_19[3];
assign product_19 [6] = reg_19[0] ^ reg_19[2] ^ reg_19[3] ^ reg_19[4];
assign product_19 [7] = reg_19[1] ^ reg_19[3] ^ reg_19[4] ^ reg_19[5];
assign product_20 [0] = reg_20[1] ^ reg_20[3] ^ reg_20[4] ^ reg_20[5];
assign product_20 [1] = reg_20[2] ^ reg_20[4] ^ reg_20[5] ^ reg_20[6];
assign product_20 [2] = reg_20[0] ^ reg_20[1] ^ reg_20[4] ^ reg_20[6] ^ reg_20[7];
assign product_20 [3] = reg_20[2] ^ reg_20[3] ^ reg_20[4] ^ reg_20[7];
assign product_20 [4] = reg_20[0] ^ reg_20[1];
assign product_20 [5] = reg_20[0] ^ reg_20[1] ^ reg_20[2];
assign product_20 [6] = reg_20[1] ^ reg_20[2] ^ reg_20[3];
assign product_20 [7] = reg_20[0] ^ reg_20[2] ^ reg_20[3] ^ reg_20[4];
assign product_21 [0] = reg_21[0] ^ reg_21[2] ^ reg_21[3] ^ reg_21[4];
assign product_21 [1] = reg_21[1] ^ reg_21[3] ^ reg_21[4] ^ reg_21[5];
assign product_21 [2] = reg_21[0] ^ reg_21[3] ^ reg_21[5] ^ reg_21[6];
assign product_21 [3] = reg_21[1] ^ reg_21[2] ^ reg_21[3] ^ reg_21[6] ^ reg_21[7];
assign product_21 [4] = reg_21[0] ^ reg_21[7];
assign product_21 [5] = reg_21[0] ^ reg_21[1];
assign product_21 [6] = reg_21[0] ^ reg_21[1] ^ reg_21[2];
assign product_21 [7] = reg_21[1] ^ reg_21[2] ^ reg_21[3];
 
 
 
//------------------------------------------------------------------------
// + REG_0,..., REG_21
//------------------------------------------------------------------------
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
reg_0 [7:0] <= 8'd0;
reg_1 [7:0] <= 8'd0;
reg_2 [7:0] <= 8'd0;
reg_3 [7:0] <= 8'd0;
reg_4 [7:0] <= 8'd0;
reg_5 [7:0] <= 8'd0;
reg_6 [7:0] <= 8'd0;
reg_7 [7:0] <= 8'd0;
reg_8 [7:0] <= 8'd0;
reg_9 [7:0] <= 8'd0;
reg_10 [7:0] <= 8'd0;
reg_11 [7:0] <= 8'd0;
reg_12 [7:0] <= 8'd0;
reg_13 [7:0] <= 8'd0;
reg_14 [7:0] <= 8'd0;
reg_15 [7:0] <= 8'd0;
reg_16 [7:0] <= 8'd0;
reg_17 [7:0] <= 8'd0;
reg_18 [7:0] <= 8'd0;
reg_19 [7:0] <= 8'd0;
reg_20 [7:0] <= 8'd0;
reg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
reg_0 [7:0] <= dataIn[7:0];
reg_1 [7:0] <= dataIn[7:0];
reg_2 [7:0] <= dataIn[7:0];
reg_3 [7:0] <= dataIn[7:0];
reg_4 [7:0] <= dataIn[7:0];
reg_5 [7:0] <= dataIn[7:0];
reg_6 [7:0] <= dataIn[7:0];
reg_7 [7:0] <= dataIn[7:0];
reg_8 [7:0] <= dataIn[7:0];
reg_9 [7:0] <= dataIn[7:0];
reg_10 [7:0] <= dataIn[7:0];
reg_11 [7:0] <= dataIn[7:0];
reg_12 [7:0] <= dataIn[7:0];
reg_13 [7:0] <= dataIn[7:0];
reg_14 [7:0] <= dataIn[7:0];
reg_15 [7:0] <= dataIn[7:0];
reg_16 [7:0] <= dataIn[7:0];
reg_17 [7:0] <= dataIn[7:0];
reg_18 [7:0] <= dataIn[7:0];
reg_19 [7:0] <= dataIn[7:0];
reg_20 [7:0] <= dataIn[7:0];
reg_21 [7:0] <= dataIn[7:0];
end
else begin
reg_0 [7:0] <= dataIn [7:0] ^ product_0[7:0];
reg_1 [7:0] <= dataIn [7:0] ^ product_1[7:0];
reg_2 [7:0] <= dataIn [7:0] ^ product_2[7:0];
reg_3 [7:0] <= dataIn [7:0] ^ product_3[7:0];
reg_4 [7:0] <= dataIn [7:0] ^ product_4[7:0];
reg_5 [7:0] <= dataIn [7:0] ^ product_5[7:0];
reg_6 [7:0] <= dataIn [7:0] ^ product_6[7:0];
reg_7 [7:0] <= dataIn [7:0] ^ product_7[7:0];
reg_8 [7:0] <= dataIn [7:0] ^ product_8[7:0];
reg_9 [7:0] <= dataIn [7:0] ^ product_9[7:0];
reg_10 [7:0] <= dataIn [7:0] ^ product_10[7:0];
reg_11 [7:0] <= dataIn [7:0] ^ product_11[7:0];
reg_12 [7:0] <= dataIn [7:0] ^ product_12[7:0];
reg_13 [7:0] <= dataIn [7:0] ^ product_13[7:0];
reg_14 [7:0] <= dataIn [7:0] ^ product_14[7:0];
reg_15 [7:0] <= dataIn [7:0] ^ product_15[7:0];
reg_16 [7:0] <= dataIn [7:0] ^ product_16[7:0];
reg_17 [7:0] <= dataIn [7:0] ^ product_17[7:0];
reg_18 [7:0] <= dataIn [7:0] ^ product_18[7:0];
reg_19 [7:0] <= dataIn [7:0] ^ product_19[7:0];
reg_20 [7:0] <= dataIn [7:0] ^ product_20[7:0];
reg_21 [7:0] <= dataIn [7:0] ^ product_21[7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
//- Output Ports
//------------------------------------------------------------------------
assign syndrome_0[7:0] = reg_0[7:0];
assign syndrome_1[7:0] = reg_1[7:0];
assign syndrome_2[7:0] = reg_2[7:0];
assign syndrome_3[7:0] = reg_3[7:0];
assign syndrome_4[7:0] = reg_4[7:0];
assign syndrome_5[7:0] = reg_5[7:0];
assign syndrome_6[7:0] = reg_6[7:0];
assign syndrome_7[7:0] = reg_7[7:0];
assign syndrome_8[7:0] = reg_8[7:0];
assign syndrome_9[7:0] = reg_9[7:0];
assign syndrome_10[7:0] = reg_10[7:0];
assign syndrome_11[7:0] = reg_11[7:0];
assign syndrome_12[7:0] = reg_12[7:0];
assign syndrome_13[7:0] = reg_13[7:0];
assign syndrome_14[7:0] = reg_14[7:0];
assign syndrome_15[7:0] = reg_15[7:0];
assign syndrome_16[7:0] = reg_16[7:0];
assign syndrome_17[7:0] = reg_17[7:0];
assign syndrome_18[7:0] = reg_18[7:0];
assign syndrome_19[7:0] = reg_19[7:0];
assign syndrome_20[7:0] = reg_20[7:0];
assign syndrome_21[7:0] = reg_21[7:0];
 
endmodule
/trunk/example/rtl/RsDecodeMult.v
0,0 → 1,66
//===================================================================
// Module Name : RsDecodeMult
// File Name : RsDecodeMult.v
// Function : Rs Decoder Multiplier Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodeMult(
A, // input A
B, // input B
P // output P = A*B in Galois Field
);
 
 
input [7:0] A; // input A
input [7:0] B; // input B
output [7:0] P; // output P = A*B in Galois Field
 
 
 
//------------------------------------------------------------------------
// + M
//-
//------------------------------------------------------------------------
wire [14:0] M;
 
 
 
assign M[0] = (A[0] & B[0]);
assign M[1] = (A[0] & B[1]) ^ (A[1] & B[0]);
assign M[2] = (A[0] & B[2]) ^ (A[1] & B[1]) ^ (A[2] & B[0]);
assign M[3] = (A[0] & B[3]) ^ (A[1] & B[2]) ^ (A[2] & B[1]) ^ (A[3] & B[0]);
assign M[4] = (A[0] & B[4]) ^ (A[1] & B[3]) ^ (A[2] & B[2]) ^ (A[3] & B[1]) ^ (A[4] & B[0]);
assign M[5] = (A[0] & B[5]) ^ (A[1] & B[4]) ^ (A[2] & B[3]) ^ (A[3] & B[2]) ^ (A[4] & B[1]) ^ (A[5] & B[0]);
assign M[6] = (A[0] & B[6]) ^ (A[1] & B[5]) ^ (A[2] & B[4]) ^ (A[3] & B[3]) ^ (A[4] & B[2]) ^ (A[5] & B[1]) ^ (A[6] & B[0]);
assign M[7] = (A[0] & B[7]) ^ (A[1] & B[6]) ^ (A[2] & B[5]) ^ (A[3] & B[4]) ^ (A[4] & B[3]) ^ (A[5] & B[2]) ^ (A[6] & B[1]) ^ (A[7] & B[0]);
assign M[8] = (A[1] & B[7]) ^ (A[2] & B[6]) ^ (A[3] & B[5]) ^ (A[4] & B[4]) ^ (A[5] & B[3]) ^ (A[6] & B[2]) ^ (A[7] & B[1]);
assign M[9] = (A[2] & B[7]) ^ (A[3] & B[6]) ^ (A[4] & B[5]) ^ (A[5] & B[4]) ^ (A[6] & B[3]) ^ (A[7] & B[2]);
assign M[10] = (A[3] & B[7]) ^ (A[4] & B[6]) ^ (A[5] & B[5]) ^ (A[6] & B[4]) ^ (A[7] & B[3]);
assign M[11] = (A[4] & B[7]) ^ (A[5] & B[6]) ^ (A[6] & B[5]) ^ (A[7] & B[4]);
assign M[12] = (A[5] & B[7]) ^ (A[6] & B[6]) ^ (A[7] & B[5]);
assign M[13] = (A[6] & B[7]) ^ (A[7] & B[6]);
assign M[14] = (A[7] & B[7]);
//------------------------------------------------------------------------
// + P
//-
//------------------------------------------------------------------------
assign P[0] = M[0] ^ M[8] ^ M[12] ^ M[13] ^ M[14];
assign P[1] = M[1] ^ M[9] ^ M[13] ^ M[14];
assign P[2] = M[2] ^ M[8] ^ M[10] ^ M[12] ^ M[13];
assign P[3] = M[3] ^ M[8] ^ M[9] ^ M[11] ^ M[12];
assign P[4] = M[4] ^ M[8] ^ M[9] ^ M[10] ^ M[14];
assign P[5] = M[5] ^ M[9] ^ M[10] ^ M[11];
assign P[6] = M[6] ^ M[10] ^ M[11] ^ M[12];
assign P[7] = M[7] ^ M[11] ^ M[12] ^ M[13];
 
 
endmodule
/trunk/example/rtl/RsDecodePolymul.v
0,0 → 1,618
//===================================================================
// Module Name : RsDecodePolymul
// File Name : RsDecodePolymul.v
// Function : Rs Decoder polymul calculation Module
//
// Revision History:
// Date By Version Change Description
//===================================================================
// 2009/02/03 Gael Sapience 1.0 Original
//
//===================================================================
// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd.
//
 
 
module RsDecodePolymul(
CLK, // system clock
RESET, // system reset
enable, // enable signal
sync, // sync signal
syndromeIn_0, // syndrome polynom 0
syndromeIn_1, // syndrome polynom 1
syndromeIn_2, // syndrome polynom 2
syndromeIn_3, // syndrome polynom 3
syndromeIn_4, // syndrome polynom 4
syndromeIn_5, // syndrome polynom 5
syndromeIn_6, // syndrome polynom 6
syndromeIn_7, // syndrome polynom 7
syndromeIn_8, // syndrome polynom 8
syndromeIn_9, // syndrome polynom 9
syndromeIn_10, // syndrome polynom 10
syndromeIn_11, // syndrome polynom 11
syndromeIn_12, // syndrome polynom 12
syndromeIn_13, // syndrome polynom 13
syndromeIn_14, // syndrome polynom 14
syndromeIn_15, // syndrome polynom 15
syndromeIn_16, // syndrome polynom 16
syndromeIn_17, // syndrome polynom 17
syndromeIn_18, // syndrome polynom 18
syndromeIn_19, // syndrome polynom 19
syndromeIn_20, // syndrome polynom 20
syndromeIn_21, // syndrome polynom 21
epsilon_0, // epsilon polynom 0
epsilon_1, // epsilon polynom 1
epsilon_2, // epsilon polynom 2
epsilon_3, // epsilon polynom 3
epsilon_4, // epsilon polynom 4
epsilon_5, // epsilon polynom 5
epsilon_6, // epsilon polynom 6
epsilon_7, // epsilon polynom 7
epsilon_8, // epsilon polynom 8
epsilon_9, // epsilon polynom 9
epsilon_10, // epsilon polynom 10
epsilon_11, // epsilon polynom 11
epsilon_12, // epsilon polynom 12
epsilon_13, // epsilon polynom 13
epsilon_14, // epsilon polynom 14
epsilon_15, // epsilon polynom 15
epsilon_16, // epsilon polynom 16
epsilon_17, // epsilon polynom 17
epsilon_18, // epsilon polynom 18
epsilon_19, // epsilon polynom 19
epsilon_20, // epsilon polynom 20
epsilon_21, // epsilon polynom 21
epsilon_22, // epsilon polynom 22
syndromeOut_0, // modified syndrome polynom 0
syndromeOut_1, // modified syndrome polynom 1
syndromeOut_2, // modified syndrome polynom 2
syndromeOut_3, // modified syndrome polynom 3
syndromeOut_4, // modified syndrome polynom 4
syndromeOut_5, // modified syndrome polynom 5
syndromeOut_6, // modified syndrome polynom 6
syndromeOut_7, // modified syndrome polynom 7
syndromeOut_8, // modified syndrome polynom 8
syndromeOut_9, // modified syndrome polynom 9
syndromeOut_10, // modified syndrome polynom 10
syndromeOut_11, // modified syndrome polynom 11
syndromeOut_12, // modified syndrome polynom 12
syndromeOut_13, // modified syndrome polynom 13
syndromeOut_14, // modified syndrome polynom 14
syndromeOut_15, // modified syndrome polynom 15
syndromeOut_16, // modified syndrome polynom 16
syndromeOut_17, // modified syndrome polynom 17
syndromeOut_18, // modified syndrome polynom 18
syndromeOut_19, // modified syndrome polynom 19
syndromeOut_20, // modified syndrome polynom 20
syndromeOut_21, // modified syndrome polynom 21
done // done signal
);
 
 
input CLK; // system clock
input RESET; // system reset
input enable; // enable signal
input sync; // sync signal
input [7:0] syndromeIn_0; // syndrome polynom 0
input [7:0] syndromeIn_1; // syndrome polynom 1
input [7:0] syndromeIn_2; // syndrome polynom 2
input [7:0] syndromeIn_3; // syndrome polynom 3
input [7:0] syndromeIn_4; // syndrome polynom 4
input [7:0] syndromeIn_5; // syndrome polynom 5
input [7:0] syndromeIn_6; // syndrome polynom 6
input [7:0] syndromeIn_7; // syndrome polynom 7
input [7:0] syndromeIn_8; // syndrome polynom 8
input [7:0] syndromeIn_9; // syndrome polynom 9
input [7:0] syndromeIn_10; // syndrome polynom 10
input [7:0] syndromeIn_11; // syndrome polynom 11
input [7:0] syndromeIn_12; // syndrome polynom 12
input [7:0] syndromeIn_13; // syndrome polynom 13
input [7:0] syndromeIn_14; // syndrome polynom 14
input [7:0] syndromeIn_15; // syndrome polynom 15
input [7:0] syndromeIn_16; // syndrome polynom 16
input [7:0] syndromeIn_17; // syndrome polynom 17
input [7:0] syndromeIn_18; // syndrome polynom 18
input [7:0] syndromeIn_19; // syndrome polynom 19
input [7:0] syndromeIn_20; // syndrome polynom 20
input [7:0] syndromeIn_21; // syndrome polynom 21
input [7:0] epsilon_0; // epsilon polynom 0
input [7:0] epsilon_1; // epsilon polynom 1
input [7:0] epsilon_2; // epsilon polynom 2
input [7:0] epsilon_3; // epsilon polynom 3
input [7:0] epsilon_4; // epsilon polynom 4
input [7:0] epsilon_5; // epsilon polynom 5
input [7:0] epsilon_6; // epsilon polynom 6
input [7:0] epsilon_7; // epsilon polynom 7
input [7:0] epsilon_8; // epsilon polynom 8
input [7:0] epsilon_9; // epsilon polynom 9
input [7:0] epsilon_10; // epsilon polynom 10
input [7:0] epsilon_11; // epsilon polynom 11
input [7:0] epsilon_12; // epsilon polynom 12
input [7:0] epsilon_13; // epsilon polynom 13
input [7:0] epsilon_14; // epsilon polynom 14
input [7:0] epsilon_15; // epsilon polynom 15
input [7:0] epsilon_16; // epsilon polynom 16
input [7:0] epsilon_17; // epsilon polynom 17
input [7:0] epsilon_18; // epsilon polynom 18
input [7:0] epsilon_19; // epsilon polynom 19
input [7:0] epsilon_20; // epsilon polynom 20
input [7:0] epsilon_21; // epsilon polynom 21
input [7:0] epsilon_22; // epsilon polynom 22
 
output [7:0] syndromeOut_0; // modified syndrome polynom 0
output [7:0] syndromeOut_1; // modified syndrome polynom 1
output [7:0] syndromeOut_2; // modified syndrome polynom 2
output [7:0] syndromeOut_3; // modified syndrome polynom 3
output [7:0] syndromeOut_4; // modified syndrome polynom 4
output [7:0] syndromeOut_5; // modified syndrome polynom 5
output [7:0] syndromeOut_6; // modified syndrome polynom 6
output [7:0] syndromeOut_7; // modified syndrome polynom 7
output [7:0] syndromeOut_8; // modified syndrome polynom 8
output [7:0] syndromeOut_9; // modified syndrome polynom 9
output [7:0] syndromeOut_10; // modified syndrome polynom 10
output [7:0] syndromeOut_11; // modified syndrome polynom 11
output [7:0] syndromeOut_12; // modified syndrome polynom 12
output [7:0] syndromeOut_13; // modified syndrome polynom 13
output [7:0] syndromeOut_14; // modified syndrome polynom 14
output [7:0] syndromeOut_15; // modified syndrome polynom 15
output [7:0] syndromeOut_16; // modified syndrome polynom 16
output [7:0] syndromeOut_17; // modified syndrome polynom 17
output [7:0] syndromeOut_18; // modified syndrome polynom 18
output [7:0] syndromeOut_19; // modified syndrome polynom 19
output [7:0] syndromeOut_20; // modified syndrome polynom 20
output [7:0] syndromeOut_21; // modified syndrome polynom 21
output done; // done signal
 
 
 
 
 
//------------------------------------------------------------------------
// + count
//- Counter
//------------------------------------------------------------------------
reg [4:0] count;
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
count [4:0] <= 5'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
count[4:0] <= 5'd1;
end
else if ((count[4:0] ==5'd0) || (count[4:0] ==5'd23)) begin
count[4:0] <= 5'd0;
end
else begin
count[4:0] <= count[4:0] + 5'd1;
end
end
end
 
 
//------------------------------------------------------------------------
// + done
//------------------------------------------------------------------------
reg done;
always @(count) begin
if (count[4:0] == 5'd23) begin
done = 1'b1;
end
else begin
done = 1'b0;
end
end
 
 
//------------------------------------------------------------------------
// + syndromeReg_0,..., syndromeReg_21
//------------------------------------------------------------------------
reg [7:0] syndromeReg_0;
reg [7:0] syndromeReg_1;
reg [7:0] syndromeReg_2;
reg [7:0] syndromeReg_3;
reg [7:0] syndromeReg_4;
reg [7:0] syndromeReg_5;
reg [7:0] syndromeReg_6;
reg [7:0] syndromeReg_7;
reg [7:0] syndromeReg_8;
reg [7:0] syndromeReg_9;
reg [7:0] syndromeReg_10;
reg [7:0] syndromeReg_11;
reg [7:0] syndromeReg_12;
reg [7:0] syndromeReg_13;
reg [7:0] syndromeReg_14;
reg [7:0] syndromeReg_15;
reg [7:0] syndromeReg_16;
reg [7:0] syndromeReg_17;
reg [7:0] syndromeReg_18;
reg [7:0] syndromeReg_19;
reg [7:0] syndromeReg_20;
reg [7:0] syndromeReg_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
syndromeReg_0 [7:0] <= 8'd0;
syndromeReg_1 [7:0] <= 8'd0;
syndromeReg_2 [7:0] <= 8'd0;
syndromeReg_3 [7:0] <= 8'd0;
syndromeReg_4 [7:0] <= 8'd0;
syndromeReg_5 [7:0] <= 8'd0;
syndromeReg_6 [7:0] <= 8'd0;
syndromeReg_7 [7:0] <= 8'd0;
syndromeReg_8 [7:0] <= 8'd0;
syndromeReg_9 [7:0] <= 8'd0;
syndromeReg_10 [7:0] <= 8'd0;
syndromeReg_11 [7:0] <= 8'd0;
syndromeReg_12 [7:0] <= 8'd0;
syndromeReg_13 [7:0] <= 8'd0;
syndromeReg_14 [7:0] <= 8'd0;
syndromeReg_15 [7:0] <= 8'd0;
syndromeReg_16 [7:0] <= 8'd0;
syndromeReg_17 [7:0] <= 8'd0;
syndromeReg_18 [7:0] <= 8'd0;
syndromeReg_19 [7:0] <= 8'd0;
syndromeReg_20 [7:0] <= 8'd0;
syndromeReg_21 [7:0] <= 8'd0;
end
else if ((enable == 1'b1) && (sync == 1'b1)) begin
syndromeReg_0 [7:0] <= syndromeIn_0 [7:0];
syndromeReg_1 [7:0] <= syndromeIn_1 [7:0];
syndromeReg_2 [7:0] <= syndromeIn_2 [7:0];
syndromeReg_3 [7:0] <= syndromeIn_3 [7:0];
syndromeReg_4 [7:0] <= syndromeIn_4 [7:0];
syndromeReg_5 [7:0] <= syndromeIn_5 [7:0];
syndromeReg_6 [7:0] <= syndromeIn_6 [7:0];
syndromeReg_7 [7:0] <= syndromeIn_7 [7:0];
syndromeReg_8 [7:0] <= syndromeIn_8 [7:0];
syndromeReg_9 [7:0] <= syndromeIn_9 [7:0];
syndromeReg_10 [7:0] <= syndromeIn_10 [7:0];
syndromeReg_11 [7:0] <= syndromeIn_11 [7:0];
syndromeReg_12 [7:0] <= syndromeIn_12 [7:0];
syndromeReg_13 [7:0] <= syndromeIn_13 [7:0];
syndromeReg_14 [7:0] <= syndromeIn_14 [7:0];
syndromeReg_15 [7:0] <= syndromeIn_15 [7:0];
syndromeReg_16 [7:0] <= syndromeIn_16 [7:0];
syndromeReg_17 [7:0] <= syndromeIn_17 [7:0];
syndromeReg_18 [7:0] <= syndromeIn_18 [7:0];
syndromeReg_19 [7:0] <= syndromeIn_19 [7:0];
syndromeReg_20 [7:0] <= syndromeIn_20 [7:0];
syndromeReg_21 [7:0] <= syndromeIn_21 [7:0];
end
end
//------------------------------------------------------------------------
// + epsilonReg_0,..., epsilonReg_22
//------------------------------------------------------------------------
reg [7:0] epsilonReg_0;
reg [7:0] epsilonReg_1;
reg [7:0] epsilonReg_2;
reg [7:0] epsilonReg_3;
reg [7:0] epsilonReg_4;
reg [7:0] epsilonReg_5;
reg [7:0] epsilonReg_6;
reg [7:0] epsilonReg_7;
reg [7:0] epsilonReg_8;
reg [7:0] epsilonReg_9;
reg [7:0] epsilonReg_10;
reg [7:0] epsilonReg_11;
reg [7:0] epsilonReg_12;
reg [7:0] epsilonReg_13;
reg [7:0] epsilonReg_14;
reg [7:0] epsilonReg_15;
reg [7:0] epsilonReg_16;
reg [7:0] epsilonReg_17;
reg [7:0] epsilonReg_18;
reg [7:0] epsilonReg_19;
reg [7:0] epsilonReg_20;
reg [7:0] epsilonReg_21;
reg [7:0] epsilonReg_22;
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= 8'd0;
epsilonReg_2 [7:0] <= 8'd0;
epsilonReg_3 [7:0] <= 8'd0;
epsilonReg_4 [7:0] <= 8'd0;
epsilonReg_5 [7:0] <= 8'd0;
epsilonReg_6 [7:0] <= 8'd0;
epsilonReg_7 [7:0] <= 8'd0;
epsilonReg_8 [7:0] <= 8'd0;
epsilonReg_9 [7:0] <= 8'd0;
epsilonReg_10 [7:0] <= 8'd0;
epsilonReg_11 [7:0] <= 8'd0;
epsilonReg_12 [7:0] <= 8'd0;
epsilonReg_13 [7:0] <= 8'd0;
epsilonReg_14 [7:0] <= 8'd0;
epsilonReg_15 [7:0] <= 8'd0;
epsilonReg_16 [7:0] <= 8'd0;
epsilonReg_17 [7:0] <= 8'd0;
epsilonReg_18 [7:0] <= 8'd0;
epsilonReg_19 [7:0] <= 8'd0;
epsilonReg_20 [7:0] <= 8'd0;
epsilonReg_21 [7:0] <= 8'd0;
epsilonReg_22 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= epsilon_0[7:0];
epsilonReg_2 [7:0] <= epsilon_1[7:0];
epsilonReg_3 [7:0] <= epsilon_2[7:0];
epsilonReg_4 [7:0] <= epsilon_3[7:0];
epsilonReg_5 [7:0] <= epsilon_4[7:0];
epsilonReg_6 [7:0] <= epsilon_5[7:0];
epsilonReg_7 [7:0] <= epsilon_6[7:0];
epsilonReg_8 [7:0] <= epsilon_7[7:0];
epsilonReg_9 [7:0] <= epsilon_8[7:0];
epsilonReg_10 [7:0] <= epsilon_9[7:0];
epsilonReg_11 [7:0] <= epsilon_10[7:0];
epsilonReg_12 [7:0] <= epsilon_11[7:0];
epsilonReg_13 [7:0] <= epsilon_12[7:0];
epsilonReg_14 [7:0] <= epsilon_13[7:0];
epsilonReg_15 [7:0] <= epsilon_14[7:0];
epsilonReg_16 [7:0] <= epsilon_15[7:0];
epsilonReg_17 [7:0] <= epsilon_16[7:0];
epsilonReg_18 [7:0] <= epsilon_17[7:0];
epsilonReg_19 [7:0] <= epsilon_18[7:0];
epsilonReg_20 [7:0] <= epsilon_19[7:0];
epsilonReg_21 [7:0] <= epsilon_20[7:0];
epsilonReg_22 [7:0] <= epsilon_21[7:0];
end
else begin
epsilonReg_0 [7:0] <= 8'd0;
epsilonReg_1 [7:0] <= epsilonReg_0[7:0];
epsilonReg_2 [7:0] <= epsilonReg_1[7:0];
epsilonReg_3 [7:0] <= epsilonReg_2[7:0];
epsilonReg_4 [7:0] <= epsilonReg_3[7:0];
epsilonReg_5 [7:0] <= epsilonReg_4[7:0];
epsilonReg_6 [7:0] <= epsilonReg_5[7:0];
epsilonReg_7 [7:0] <= epsilonReg_6[7:0];
epsilonReg_8 [7:0] <= epsilonReg_7[7:0];
epsilonReg_9 [7:0] <= epsilonReg_8[7:0];
epsilonReg_10 [7:0] <= epsilonReg_9[7:0];
epsilonReg_11 [7:0] <= epsilonReg_10[7:0];
epsilonReg_12 [7:0] <= epsilonReg_11[7:0];
epsilonReg_13 [7:0] <= epsilonReg_12[7:0];
epsilonReg_14 [7:0] <= epsilonReg_13[7:0];
epsilonReg_15 [7:0] <= epsilonReg_14[7:0];
epsilonReg_16 [7:0] <= epsilonReg_15[7:0];
epsilonReg_17 [7:0] <= epsilonReg_16[7:0];
epsilonReg_18 [7:0] <= epsilonReg_17[7:0];
epsilonReg_19 [7:0] <= epsilonReg_18[7:0];
epsilonReg_20 [7:0] <= epsilonReg_19[7:0];
epsilonReg_21 [7:0] <= epsilonReg_20[7:0];
epsilonReg_22 [7:0] <= epsilonReg_21[7:0];
end
end
end
 
 
//------------------------------------------------------------------------
// + epsilonMsb
//------------------------------------------------------------------------
reg [7:0] epsilonMsb;
 
always @(sync or epsilon_22 or epsilonReg_22 ) begin
if (sync == 1'b1) begin
epsilonMsb [7:0] = epsilon_22 [7:0];
end
else begin
epsilonMsb [7:0] = epsilonReg_22 [7:0];
end
end
 
 
//------------------------------------------------------------------------
// + product_0,..., product_21
//------------------------------------------------------------------------
wire [7:0] product_0;
wire [7:0] product_1;
wire [7:0] product_2;
wire [7:0] product_3;
wire [7:0] product_4;
wire [7:0] product_5;
wire [7:0] product_6;
wire [7:0] product_7;
wire [7:0] product_8;
wire [7:0] product_9;
wire [7:0] product_10;
wire [7:0] product_11;
wire [7:0] product_12;
wire [7:0] product_13;
wire [7:0] product_14;
wire [7:0] product_15;
wire [7:0] product_16;
wire [7:0] product_17;
wire [7:0] product_18;
wire [7:0] product_19;
wire [7:0] product_20;
wire [7:0] product_21;
 
 
RsDecodeMult RsDecodeMult_0 ( .A(epsilonMsb[7:0]), .B(syndromeReg_0[7:0]), .P(product_0[7:0]));
RsDecodeMult RsDecodeMult_1 ( .A(epsilonMsb[7:0]), .B(syndromeReg_1[7:0]), .P(product_1[7:0]));
RsDecodeMult RsDecodeMult_2 ( .A(epsilonMsb[7:0]), .B(syndromeReg_2[7:0]), .P(product_2[7:0]));
RsDecodeMult RsDecodeMult_3 ( .A(epsilonMsb[7:0]), .B(syndromeReg_3[7:0]), .P(product_3[7:0]));
RsDecodeMult RsDecodeMult_4 ( .A(epsilonMsb[7:0]), .B(syndromeReg_4[7:0]), .P(product_4[7:0]));
RsDecodeMult RsDecodeMult_5 ( .A(epsilonMsb[7:0]), .B(syndromeReg_5[7:0]), .P(product_5[7:0]));
RsDecodeMult RsDecodeMult_6 ( .A(epsilonMsb[7:0]), .B(syndromeReg_6[7:0]), .P(product_6[7:0]));
RsDecodeMult RsDecodeMult_7 ( .A(epsilonMsb[7:0]), .B(syndromeReg_7[7:0]), .P(product_7[7:0]));
RsDecodeMult RsDecodeMult_8 ( .A(epsilonMsb[7:0]), .B(syndromeReg_8[7:0]), .P(product_8[7:0]));
RsDecodeMult RsDecodeMult_9 ( .A(epsilonMsb[7:0]), .B(syndromeReg_9[7:0]), .P(product_9[7:0]));
RsDecodeMult RsDecodeMult_10 ( .A(epsilonMsb[7:0]), .B(syndromeReg_10[7:0]), .P(product_10[7:0]));
RsDecodeMult RsDecodeMult_11 ( .A(epsilonMsb[7:0]), .B(syndromeReg_11[7:0]), .P(product_11[7:0]));
RsDecodeMult RsDecodeMult_12 ( .A(epsilonMsb[7:0]), .B(syndromeReg_12[7:0]), .P(product_12[7:0]));
RsDecodeMult RsDecodeMult_13 ( .A(epsilonMsb[7:0]), .B(syndromeReg_13[7:0]), .P(product_13[7:0]));
RsDecodeMult RsDecodeMult_14 ( .A(epsilonMsb[7:0]), .B(syndromeReg_14[7:0]), .P(product_14[7:0]));
RsDecodeMult RsDecodeMult_15 ( .A(epsilonMsb[7:0]), .B(syndromeReg_15[7:0]), .P(product_15[7:0]));
RsDecodeMult RsDecodeMult_16 ( .A(epsilonMsb[7:0]), .B(syndromeReg_16[7:0]), .P(product_16[7:0]));
RsDecodeMult RsDecodeMult_17 ( .A(epsilonMsb[7:0]), .B(syndromeReg_17[7:0]), .P(product_17[7:0]));
RsDecodeMult RsDecodeMult_18 ( .A(epsilonMsb[7:0]), .B(syndromeReg_18[7:0]), .P(product_18[7:0]));
RsDecodeMult RsDecodeMult_19 ( .A(epsilonMsb[7:0]), .B(syndromeReg_19[7:0]), .P(product_19[7:0]));
RsDecodeMult RsDecodeMult_20 ( .A(epsilonMsb[7:0]), .B(syndromeReg_20[7:0]), .P(product_20[7:0]));
RsDecodeMult RsDecodeMult_21 ( .A(epsilonMsb[7:0]), .B(syndromeReg_21[7:0]), .P(product_21[7:0]));
 
 
 
//------------------------------------------------------------------------
// + sumReg_0,..., sumReg_21
//------------------------------------------------------------------------
reg [7:0] sumReg_0;
reg [7:0] sumReg_1;
reg [7:0] sumReg_2;
reg [7:0] sumReg_3;
reg [7:0] sumReg_4;
reg [7:0] sumReg_5;
reg [7:0] sumReg_6;
reg [7:0] sumReg_7;
reg [7:0] sumReg_8;
reg [7:0] sumReg_9;
reg [7:0] sumReg_10;
reg [7:0] sumReg_11;
reg [7:0] sumReg_12;
reg [7:0] sumReg_13;
reg [7:0] sumReg_14;
reg [7:0] sumReg_15;
reg [7:0] sumReg_16;
reg [7:0] sumReg_17;
reg [7:0] sumReg_18;
reg [7:0] sumReg_19;
reg [7:0] sumReg_20;
reg [7:0] sumReg_21;
 
 
always @(posedge CLK or negedge RESET) begin
if (~RESET) begin
sumReg_0 [7:0] <= 8'd0;
sumReg_1 [7:0] <= 8'd0;
sumReg_2 [7:0] <= 8'd0;
sumReg_3 [7:0] <= 8'd0;
sumReg_4 [7:0] <= 8'd0;
sumReg_5 [7:0] <= 8'd0;
sumReg_6 [7:0] <= 8'd0;
sumReg_7 [7:0] <= 8'd0;
sumReg_8 [7:0] <= 8'd0;
sumReg_9 [7:0] <= 8'd0;
sumReg_10 [7:0] <= 8'd0;
sumReg_11 [7:0] <= 8'd0;
sumReg_12 [7:0] <= 8'd0;
sumReg_13 [7:0] <= 8'd0;
sumReg_14 [7:0] <= 8'd0;
sumReg_15 [7:0] <= 8'd0;
sumReg_16 [7:0] <= 8'd0;
sumReg_17 [7:0] <= 8'd0;
sumReg_18 [7:0] <= 8'd0;
sumReg_19 [7:0] <= 8'd0;
sumReg_20 [7:0] <= 8'd0;
sumReg_21 [7:0] <= 8'd0;
end
else if (enable == 1'b1) begin
if (sync == 1'b1) begin
if (epsilon_22[7:0] != 8'd0) begin
sumReg_0 [7:0] <= syndromeIn_0 [7:0];
sumReg_1 [7:0] <= syndromeIn_1 [7:0];
sumReg_2 [7:0] <= syndromeIn_2 [7:0];
sumReg_3 [7:0] <= syndromeIn_3 [7:0];
sumReg_4 [7:0] <= syndromeIn_4 [7:0];
sumReg_5 [7:0] <= syndromeIn_5 [7:0];
sumReg_6 [7:0] <= syndromeIn_6 [7:0];
sumReg_7 [7:0] <= syndromeIn_7 [7:0];
sumReg_8 [7:0] <= syndromeIn_8 [7:0];
sumReg_9 [7:0] <= syndromeIn_9 [7:0];
sumReg_10 [7:0] <= syndromeIn_10 [7:0];
sumReg_11 [7:0] <= syndromeIn_11 [7:0];
sumReg_12 [7:0] <= syndromeIn_12 [7:0];
sumReg_13 [7:0] <= syndromeIn_13 [7:0];
sumReg_14 [7:0] <= syndromeIn_14 [7:0];
sumReg_15 [7:0] <= syndromeIn_15 [7:0];
sumReg_16 [7:0] <= syndromeIn_16 [7:0];
sumReg_17 [7:0] <= syndromeIn_17 [7:0];
sumReg_18 [7:0] <= syndromeIn_18 [7:0];
sumReg_19 [7:0] <= syndromeIn_19 [7:0];
sumReg_20 [7:0] <= syndromeIn_20 [7:0];
sumReg_21 [7:0] <= syndromeIn_21 [7:0];
end
else begin
sumReg_0 [7:0] <= 8'd0;
sumReg_1 [7:0] <= 8'd0;
sumReg_2 [7:0] <= 8'd0;
sumReg_3 [7:0] <= 8'd0;
sumReg_4 [7:0] <= 8'd0;
sumReg_5 [7:0] <= 8'd0;
sumReg_6 [7:0] <= 8'd0;
sumReg_7 [7:0] <= 8'd0;
sumReg_8 [7:0] <= 8'd0;
sumReg_9 [7:0] <= 8'd0;
sumReg_10 [7:0] <= 8'd0;
sumReg_11 [7:0] <= 8'd0;
sumReg_12 [7:0] <= 8'd0;
sumReg_13 [7:0] <= 8'd0;
sumReg_14 [7:0] <= 8'd0;
sumReg_15 [7:0] <= 8'd0;
sumReg_16 [7:0] <= 8'd0;
sumReg_17 [7:0] <= 8'd0;
sumReg_18 [7:0] <= 8'd0;
sumReg_19 [7:0] <= 8'd0;
sumReg_20 [7:0] <= 8'd0;
sumReg_21 [7:0] <= 8'd0;
end
end
else begin
sumReg_0 [7:0] <= product_0 [7:0];
sumReg_1 [7:0] <= sumReg_0 [7:0] ^ product_1 [7:0];
sumReg_2 [7:0] <= sumReg_1 [7:0] ^ product_2 [7:0];
sumReg_3 [7:0] <= sumReg_2 [7:0] ^ product_3 [7:0];
sumReg_4 [7:0] <= sumReg_3 [7:0] ^ product_4 [7:0];
sumReg_5 [7:0] <= sumReg_4 [7:0] ^ product_5 [7:0];
sumReg_6 [7:0] <= sumReg_5 [7:0] ^ product_6 [7:0];
sumReg_7 [7:0] <= sumReg_6 [7:0] ^ product_7 [7:0];
sumReg_8 [7:0] <= sumReg_7 [7:0] ^ product_8 [7:0];
sumReg_9 [7:0] <= sumReg_8 [7:0] ^ product_9 [7:0];
sumReg_10 [7:0] <= sumReg_9 [7:0] ^ product_10 [7:0];
sumReg_11 [7:0] <= sumReg_10 [7:0] ^ product_11 [7:0];
sumReg_12 [7:0] <= sumReg_11 [7:0] ^ product_12 [7:0];
sumReg_13 [7:0] <= sumReg_12 [7:0] ^ product_13 [7:0];
sumReg_14 [7:0] <= sumReg_13 [7:0] ^ product_14 [7:0];
sumReg_15 [7:0] <= sumReg_14 [7:0] ^ product_15 [7:0];
sumReg_16 [7:0] <= sumReg_15 [7:0] ^ product_16 [7:0];
sumReg_17 [7:0] <= sumReg_16 [7:0] ^ product_17 [7:0];
sumReg_18 [7:0] <= sumReg_17 [7:0] ^ product_18 [7:0];
sumReg_19 [7:0] <= sumReg_18 [7:0] ^ product_19 [7:0];
sumReg_20 [7:0] <= sumReg_19 [7:0] ^ product_20 [7:0];
sumReg_21 [7:0] <= sumReg_20 [7:0] ^ product_21 [7:0];
end
end
end
 
 
 
//------------------------------------------------------------------------
// Output signals
//------------------------------------------------------------------------
assign syndromeOut_0 [7:0] = sumReg_0 [7:0];
assign syndromeOut_1 [7:0] = sumReg_1 [7:0];
assign syndromeOut_2 [7:0] = sumReg_2 [7:0];
assign syndromeOut_3 [7:0] = sumReg_3 [7:0];
assign syndromeOut_4 [7:0] = sumReg_4 [7:0];
assign syndromeOut_5 [7:0] = sumReg_5 [7:0];
assign syndromeOut_6 [7:0] = sumReg_6 [7:0];
assign syndromeOut_7 [7:0] = sumReg_7 [7:0];
assign syndromeOut_8 [7:0] = sumReg_8 [7:0];
assign syndromeOut_9 [7:0] = sumReg_9 [7:0];
assign syndromeOut_10 [7:0] = sumReg_10 [7:0];
assign syndromeOut_11 [7:0] = sumReg_11 [7:0];
assign syndromeOut_12 [7:0] = sumReg_12 [7:0];
assign syndromeOut_13 [7:0] = sumReg_13 [7:0];
assign syndromeOut_14 [7:0] = sumReg_14 [7:0];
assign syndromeOut_15 [7:0] = sumReg_15 [7:0];
assign syndromeOut_16 [7:0] = sumReg_16 [7:0];
assign syndromeOut_17 [7:0] = sumReg_17 [7:0];
assign syndromeOut_18 [7:0] = sumReg_18 [7:0];
assign syndromeOut_19 [7:0] = sumReg_19 [7:0];
assign syndromeOut_20 [7:0] = sumReg_20 [7:0];
assign syndromeOut_21 [7:0] = sumReg_21 [7:0];
 
 
endmodule
/trunk/example/rtl
trunk/example/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/example/sim/simReedSolomon.v =================================================================== --- trunk/example/sim/simReedSolomon.v (nonexistent) +++ trunk/example/sim/simReedSolomon.v (revision 4) @@ -0,0 +1,777 @@ +//=================================================================== +// Module Name : simReedSolomon +// File Name : simReedSolomon.v +// Function : Rs bench Module +// +// Revision History: +// Date By Version Change Description +//=================================================================== +// 2009/02/03 Gael Sapience 1.0 Original +// +//=================================================================== +// (C) COPYRIGHT 2009 SYSTEM LSI CO., Ltd. +// + + +module simReedSolomon; + + + //------------------------------------------------------------------------ + // global registers + //------------------------------------------------------------------------ + reg CLK; // RSenc && RSdec system clock signal + reg RESET; // RSenc && RSdec system reset + + + //------------------------------------------------------------------------ + // RS decoder registers & wires + //------------------------------------------------------------------------ + reg rsdecEnable; // RSdec system enable + reg rsdecSync; // RSdec sync signal + reg rsdecErasureIn; // RSdec erasure Input signal + reg [7:0] rsdecDataIn; // Rsdec Data Input signal + + + wire rsdecOutStartPls; // RSdec first decoded symbol trigger + wire rsdecOutDone; // RSdec last decoder symbol trigger + wire [7:0] rsdecOutData; // RSdec output data signal + wire [7:0] rsdecErrorNum; // RSdec Error amount statistics + wire [7:0] rsdecErasureNum; // RSdec Erasure amount statistics + wire rsdecFail; // RSdec Pass/Fail output flag + wire rsdecOutEnable; // RSdec output enable + wire [7:0] rsdecDelayedData; // RSdec delayed data + + + //------------------------------------------------------------------------ + // RS encoder registers & wires + //------------------------------------------------------------------------ + reg rsencEnable; // RSenc data enable input + reg rsencStartPls; // RSenc Start Pulse input + reg [7:0] rsencDataIn; // RSenc data in + wire [7:0] rsencDataOut; // RSenc data out + + + //------------------------------------------------------------------------ + //RS Decoder Top module Instantiation + //------------------------------------------------------------------------ + RsDecodeTop RsDecodeTop( + // Inputs + .CLK (CLK), // system clock + .RESET (RESET), // system reset + .enable (rsdecEnable), // RSdec enable in + .startPls (rsdecSync), // RSdec sync signal + .erasureIn (rsdecErasureIn), // RSdec erasure in + .dataIn (rsdecDataIn), // RSdec data in + // Outputs + .outEnable (rsdecOutEnable), // RSdec enable out + .outStartPls (rsdecOutStartPls), // RSdec start pulse out + .outDone (rsdecOutDone), // RSdec done out + .errorNum (rsdecErrorNum), // RSdec error number + .erasureNum (rsdecErasureNum), // RSdec Erasure number + .fail (rsdecFail), // RSdec Pass/Fail flag + .delayedData (rsdecDelayedData), // RSdec delayed data + .outData (rsdecOutData) // Rsdec data out + ); + + + //------------------------------------------------------------------------ + // RS Encoder Top module Instantiation + //------------------------------------------------------------------------ + RsEncodeTop RsEncodeTop( + // Inputs + .CLK (CLK), // system clock + .RESET (RESET), // system reset + .enable (rsencEnable), // RSenc enable signal + .startPls (rsencStartPls), // RSenc sync signal + // Outputs + .dataIn (rsencDataIn), // RSenc data in + .dataOut (rsencDataOut) // RSenc data out + ); + + + //------------------------------------------------------------------------ + // clock CLK generation + //------------------------------------------------------------------------ + parameter period = 10; + always # (period) CLK =~CLK; + + + //------------------------------------------------------------------------ + // log file + //------------------------------------------------------------------------ + reg simStart; + integer handleA; + initial begin + handleA = $fopen("result.out", "w"); + end + + + //------------------------------------------------------------------------ + //- RSdec Input && Output Data files + //------------------------------------------------------------------------ + reg [23:0] rsdecInputBank [2902:0]; + reg [87:0] rsdecOutputBank [2549:0]; + + initial $readmemh("./RsDecIn.hex", rsdecInputBank); + initial $readmemh("./RsDecOut.hex", rsdecOutputBank); + + + //------------------------------------------------------------------------ + //- RSenc Input && Output Data files + //------------------------------------------------------------------------ + reg [15:0] rsencInputBank [764:0]; + reg [7:0] rsencOutputBank [764:0]; + initial $readmemh("./RsEncIn.hex", rsencInputBank); + initial $readmemh("./RsEncOut.hex", rsencOutputBank); + + + //-------------------------------------------------------------------------- + //- simStartFF1, simStartFF2, simStartFF3 + //-------------------------------------------------------------------------- + reg simStartFF1; + reg simStartFF2; + reg simStartFF3; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + simStartFF1 <= 1'b0; + simStartFF2 <= 1'b0; + simStartFF3 <= 1'b0; + end + else begin + simStartFF1 <= simStart; + simStartFF2 <= simStartFF1; + simStartFF3 <= simStartFF2; + end + end + + + //------------------------------------------------------------------------ + //+ IBankIndex + //------------------------------------------------------------------------ + reg [31:0] IBankIndex; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + IBankIndex <= 32'd0; + end + else if (simStart == 1'b1) begin + IBankIndex <= IBankIndex + 32'd1; + end + end + + +//-------------------------------------------------------------------------- +//- RS Decoder Test Bench +//-------------------------------------------------------------------------- + //-------------------------------------------------------------------------- + //- rsdecInput + //-------------------------------------------------------------------------- + wire [23:0] rsdecInput; + assign rsdecInput = (IBankIndex < 32'd2903) ? rsdecInputBank [IBankIndex] : 24'd0; + + + //------------------------------------------------------------------------ + //+ rsdecSync + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecSync <= 1'b0; + end + else if (simStart == 1'b1) begin + rsdecSync <= rsdecInput[20]; + end + end + + + //------------------------------------------------------------------------ + //+ rsdecEnable + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecEnable <= 1'b0; + end + else if (simStart == 1'b1) begin + rsdecEnable <= rsdecInput[16]; + end + end + + + //------------------------------------------------------------------------ + //+ rsdecErasureIn + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecErasureIn <= 1'b0; + end + else begin + rsdecErasureIn <= rsdecInput[12]; + end + end + + + //------------------------------------------------------------------------ + //+ rsdecDataIn + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecDataIn <= 8'd0; + end + else begin + rsdecDataIn <= rsdecInput[7:0]; + end + end + + + //------------------------------------------------------------------------ + //+ rsdecOBankIndex + //------------------------------------------------------------------------ + reg [31:0] rsdecOBankIndex; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecOBankIndex <= 32'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecOBankIndex <= rsdecOBankIndex + 32'd1; + end + end + + + //-------------------------------------------------------------------------- + //- rsdecOutput + //-------------------------------------------------------------------------- + wire [87:0] rsdecOutput; + assign rsdecOutput = (rsdecOBankIndex < 32'd2550) ? rsdecOutputBank [rsdecOBankIndex] : 48'd0; + + + //-------------------------------------------------------------------------- + //+ rsdecExpNumError + //-------------------------------------------------------------------------- + reg [7:0] rsdecExpNumError; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecExpNumError <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecExpNumError <= rsdecOutput[47:36]; + end + else begin + rsdecExpNumError <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecTheoricalNumError + //-------------------------------------------------------------------------- + reg [7:0] rsdecTheoricalNumError; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecTheoricalNumError <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecTheoricalNumError <= rsdecOutput[75:64]; + end + else begin + rsdecTheoricalNumError <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecExpNumErasure + //-------------------------------------------------------------------------- + reg [7:0] rsdecExpNumErasure; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecExpNumErasure <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecExpNumErasure <= rsdecOutput[31:24]; + end + else begin + rsdecExpNumErasure <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecTheoricalNumErasure + //-------------------------------------------------------------------------- + reg [7:0] rsdecTheoricalNumErasure; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecTheoricalNumErasure <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecTheoricalNumErasure <= rsdecOutput[59:52]; + end + else begin + rsdecTheoricalNumErasure <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecTheoricalSyndromeLength + //-------------------------------------------------------------------------- + reg [12:0] rsdecTheoricalSyndromeLength; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecTheoricalSyndromeLength <= 13'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecTheoricalSyndromeLength <= {1'b0, rsdecOutput[87:76]}; + end + else begin + rsdecTheoricalSyndromeLength <= 13'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecExpFailFlag + //-------------------------------------------------------------------------- + reg rsdecExpFailFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecExpFailFlag <= 1'b0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecExpFailFlag <= rsdecOutput[48]; + end + end + //-------------------------------------------------------------------------- + //+ rsdecExpData + //-------------------------------------------------------------------------- + reg [7:0] rsdecExpData; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecExpData <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecExpData <= rsdecOutput[7:0]; + end + else begin + rsdecExpData <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecExpDelayedData + //-------------------------------------------------------------------------- + reg [7:0] rsdecExpDelayedData; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecExpDelayedData <= 8'd0; + end + else if (rsdecOutEnable == 1'b1) begin + rsdecExpDelayedData <= rsdecOutput[19:12]; + end + else begin + rsdecExpDelayedData <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsdecOutDataFF, rsdecOutEnableFF + //-------------------------------------------------------------------------- + reg [7:0] rsdecOutDataFF; + reg rsdecOutEnableFF; + reg [7:0] rsdecErrorNumFF; + reg [7:0] rsdecErasureNumFF; + reg rsdecFailFF; + reg [7:0] rsdecDelayedDataFF; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsdecOutDataFF <= 8'd0; + rsdecOutEnableFF <= 1'b0; + rsdecDelayedDataFF <= 8'd0; + rsdecErrorNumFF <= 8'd0; + rsdecErasureNumFF <= 8'd0; + rsdecFailFF <= 1'b0; + end + else begin + rsdecOutDataFF <= rsdecOutData; + rsdecOutEnableFF <= rsdecOutEnable; + rsdecDelayedDataFF <= rsdecDelayedData; + rsdecErrorNumFF <= rsdecErrorNum; + rsdecErasureNumFF <= rsdecErasureNum; + rsdecFailFF <= rsdecFail; + end + end + + + //-------------------------------------------------------------------------- + //+ rsDecDelayedDataFlag, rsDecNGDelayedDataFlag + //-------------------------------------------------------------------------- + reg rsDecDelayedDataFlag; + reg rsDecNGDelayedDataFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsDecDelayedDataFlag <= 1'b0; + rsDecNGDelayedDataFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsdecDelayedDataFF == rsdecExpDelayedData) begin + rsDecDelayedDataFlag <= 1'b0; + end + else begin + rsDecDelayedDataFlag <= 1'b1; + rsDecNGDelayedDataFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder: Delayed Data Pin NG!!!!"); + end + end + else begin + rsDecDelayedDataFlag <= 1'b0; + end + end + + + + + + + //-------------------------------------------------------------------------- + //+ rsDecDataFlag, rsDecNGDataFlag + //-------------------------------------------------------------------------- + reg rsDecDataFlag; + reg rsDecNGDataFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsDecDataFlag <= 1'b0; + rsDecNGDataFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsdecOutDataFF == rsdecExpData) begin + rsDecDataFlag <= 1'b0; + end + else begin + rsDecDataFlag <= 1'b1; + rsDecNGDataFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Data Out: NG!!!!"); + end + end + else begin + rsDecDataFlag <= 1'b0; + end + end + + + + //-------------------------------------------------------------------------- + //+ rsDecErasureFlag, rsDecNGErasureFlag + //-------------------------------------------------------------------------- + reg rsDecErasureFlag; + reg rsDecNGErasureFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsDecErasureFlag <= 1'b0; + rsDecNGErasureFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsdecErasureNumFF == rsdecExpNumErasure) begin + rsDecErasureFlag <= 1'b0; + end + else begin + rsDecErasureFlag <= 1'b1; + rsDecNGErasureFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Erasure Pin: NG!!!!"); + end + end + else begin + rsDecErasureFlag <= 1'b0; + end + end + + + + //-------------------------------------------------------------------------- + //+ rsDecErrorFlag, rsDecNGErrorFlag + //-------------------------------------------------------------------------- + reg rsDecErrorFlag; + reg rsDecNGErrorFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsDecErrorFlag <= 1'b0; + rsDecNGErrorFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsdecErrorNumFF == rsdecExpNumError) begin + rsDecErrorFlag <= 1'b0; + end + else begin + rsDecErrorFlag <= 1'b1; + rsDecNGErrorFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Error Pin : NG!!!!"); + end + end + else begin + rsDecErrorFlag <= 1'b0; + end + end + + + + //-------------------------------------------------------------------------- + //+ rsDecFailPinFlag, rsDecNGFailPinFlag + //-------------------------------------------------------------------------- + reg rsDecFailPinFlag; + reg rsDecNGFailPinFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsDecFailPinFlag <= 1'b0; + rsDecNGFailPinFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsdecFailFF == rsdecExpFailFlag) begin + rsDecFailPinFlag <= 1'b0; + end + else begin + rsDecFailPinFlag <= 1'b1; + rsDecNGFailPinFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : NG!!!!"); + end + end + else begin + rsDecFailPinFlag <= 1'b0; + end + end + + + + //-------------------------------------------------------------------------- + //+ rsDecCorrectionAmount + //-------------------------------------------------------------------------- + wire [12:0] rsDecCorrectionAmount; + assign rsDecCorrectionAmount = rsdecTheoricalNumErasure + rsdecTheoricalNumError*2; + + + //-------------------------------------------------------------------------- + //+ passFailPinThFlag + //-------------------------------------------------------------------------- + reg passFailPinThFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + passFailPinThFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin + if (rsdecFailFF==1'b1) begin + passFailPinThFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Pass Fail Pin : Th NG!!!!"); + end + end + end + end + //-------------------------------------------------------------------------- + //+ ErasurePinThFlag + //-------------------------------------------------------------------------- + reg ErasurePinThFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + ErasurePinThFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin + if (rsdecErasureNumFF != rsdecTheoricalNumErasure) begin + ErasurePinThFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Erasure Pin : Th NG!!!!"); + end + end + end + end + //-------------------------------------------------------------------------- + //+ ErrorPinThFlag + //-------------------------------------------------------------------------- + reg ErrorPinThFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + ErrorPinThFlag <= 1'b0; + end + else if (rsdecOutEnableFF == 1'b1) begin + if (rsDecCorrectionAmount <= rsdecTheoricalSyndromeLength) begin + if (rsdecErrorNumFF != rsdecTheoricalNumError) begin + ErrorPinThFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Decoder Error Pin : Th NG!!!!"); + end + end + end + end +//-------------------------------------------------------------------------- +//- RS Encoder Test Bench +//-------------------------------------------------------------------------- + //-------------------------------------------------------------------------- + //- rsencInput + //-------------------------------------------------------------------------- + wire [15:0] rsencInput; + assign rsencInput = (IBankIndex < 32'd765) ? rsencInputBank [IBankIndex] : 16'd0; + + + //------------------------------------------------------------------------ + //+ rsencStartPls + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsencStartPls <= 1'b0; + end + else if (simStart == 1'b1) begin + rsencStartPls <= rsencInput[12]; + end + end + + + //------------------------------------------------------------------------ + //+ rsencEnable + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsencEnable <= 1'b0; + end + else begin + rsencEnable <= rsencInput[8]; + end + end + + + //------------------------------------------------------------------------ + //+ rsencDataIn + //------------------------------------------------------------------------ + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsencDataIn <= 8'd0; + end + else begin + rsencDataIn <= rsencInput[7:0]; + end + end + + + //------------------------------------------------------------------------ + //+ rsencOBankIndex + //------------------------------------------------------------------------ + reg [31:0] rsencOBankIndex; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsencOBankIndex <= 32'd0; + end + else if (simStartFF2 == 1'b1) begin + rsencOBankIndex <= rsencOBankIndex + 32'd1; + end + end + + + //-------------------------------------------------------------------------- + //- rsencOutput + //-------------------------------------------------------------------------- + wire [7:0] rsencOutput; + assign rsencOutput = (rsencOBankIndex < 32'd765) ? rsencOutputBank [rsencOBankIndex] : 8'd0; + + + //-------------------------------------------------------------------------- + //+ rsencExpData + //-------------------------------------------------------------------------- + reg [7:0] rsencExpData; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsencExpData <= 8'd0; + end + else if (simStartFF2 == 1'b1) begin + rsencExpData <= rsencOutput[7:0]; + end + else begin + rsencExpData <= 8'd0; + end + end + + + //-------------------------------------------------------------------------- + //+ rsEncPassFailFlag, rsEncFailFlag + //-------------------------------------------------------------------------- + reg rsEncPassFailFlag; + reg rsEncFailFlag; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + rsEncPassFailFlag <= 1'b0; + rsEncFailFlag <= 1'b0; + end + else if ((simStartFF3 == 1'b1) && (rsencOBankIndex < 32'd766)) begin + if (rsencDataOut == rsencExpData) begin + rsEncPassFailFlag <= 1'b0; + end + else begin + rsEncPassFailFlag <= 1'b1; + rsEncFailFlag <= 1'b1; + $fdisplay(handleA,"Reed Solomon Encoder: NG!!!!"); + end + end + else begin + rsEncPassFailFlag <= 1'b0; + end + end + //------------------------------------------------------------------------ + // + simOver + //------------------------------------------------------------------------ + reg simOver; + always @(posedge CLK or negedge RESET) begin + if (~RESET) begin + simOver <= 1'b0; + end + else if ((rsencOBankIndex > 32'd766) && (rsdecOBankIndex > 32'd2549)) begin + simOver <= 1'b1; + $fclose(handleA); + $finish; + end + end + //------------------------------------------------------------------------ + //- TIMING + //------------------------------------------------------------------------ + initial begin + simStart = 1'b0; + CLK = 0; + RESET = 1; + #(period*2) RESET = 0; + #(period*2) RESET = 1; + #(period*20) simStart = 1'b1; + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + #(period*99999999); + end +endmodule Index: trunk/example/sim/IPSpecs.txt =================================================================== --- trunk/example/sim/IPSpecs.txt (nonexistent) +++ trunk/example/sim/IPSpecs.txt (revision 4) @@ -0,0 +1,27 @@ +//================================================================= +// RS-IP Global Settings +//================================================================= +- Path Folder : No Path Specified +- Symbol Bit Width: 8 bits +- IP Mode: Encoder + Decoder +- Data Symbol Amount: 233 symbols +- Data+Redundancy Symbol Amount: 255 symbols +- Primitive Polynomial: 285 + + +//================================================================= +// RS-IP Encoder Settings +//================================================================= +- RTL sim block amount: 3 Blocks + + +//================================================================= +// RS-IP Decoder Settings +//================================================================= +- Erasure Decoding: Yes +- Decoder Statisctics Pin: Yes +- Decoder Result Pin: Yes +- Delayed Data Pin: Yes +- RTL sim block amount: 10 Blocks +- RTL sim Input Error Rate: 25 * 10^-2 Percent +- RTL sim Input Erasure Rate: 3 * 10^-0 Percent Index: trunk/example/sim/RsEncIn.hex =================================================================== --- trunk/example/sim/RsEncIn.hex (nonexistent) +++ trunk/example/sim/RsEncIn.hex (revision 4) @@ -0,0 +1,769 @@ +// SYNC, ENABLE, DATA[7:0] +// WORD Number: 0 +1_1_E1 +0_1_BC +0_1_06 +0_1_84 +0_1_29 +0_1_49 +0_1_6D +0_1_69 +0_1_72 +0_1_CF +0_1_FD +0_1_92 +0_1_A7 +0_1_57 +0_1_2D +0_1_ED +0_1_17 +0_1_C8 +0_1_D6 +0_1_3D +0_1_84 +0_1_AD +0_1_E8 +0_1_04 +0_1_76 +0_1_38 +0_1_5C +0_1_A7 +0_1_D5 +0_1_87 +0_1_69 +0_1_CD +0_1_B7 +0_1_27 +0_1_FB +0_1_08 +0_1_77 +0_1_D7 +0_1_61 +0_1_B7 +0_1_07 +0_1_8E +0_1_45 +0_1_2B +0_1_87 +0_1_BF +0_1_E2 +0_1_08 +0_1_16 +0_1_DB +0_1_71 +0_1_EE +0_1_E8 +0_1_18 +0_1_E4 +0_1_59 +0_1_98 +0_1_71 +0_1_D7 +0_1_C6 +0_1_C0 +0_1_ED +0_1_C4 +0_1_18 +0_1_C8 +0_1_25 +0_1_76 +0_1_39 +0_1_FB +0_1_00 +0_1_C0 +0_1_04 +0_1_E0 +0_1_C2 +0_1_6E +0_1_63 +0_1_C7 +0_1_45 +0_1_7C +0_1_B4 +0_1_A2 +0_1_85 +0_1_86 +0_1_72 +0_1_16 +0_1_63 +0_1_80 +0_1_11 +0_1_D2 +0_1_A2 +0_1_A7 +0_1_29 +0_1_20 +0_1_36 +0_1_B7 +0_1_D7 +0_1_B9 +0_1_BE +0_1_5F +0_1_61 +0_1_DE +0_1_4F +0_1_F2 +0_1_18 +0_1_A4 +0_1_73 +0_1_5F +0_1_83 +0_1_90 +0_1_71 +0_1_63 +0_1_B9 +0_1_63 +0_1_CF +0_1_FD +0_1_0F +0_1_37 +0_1_16 +0_1_23 +0_1_F3 +0_1_CB +0_1_D5 +0_1_B3 +0_1_18 +0_1_1C +0_1_E8 +0_1_AC +0_1_D4 +0_1_35 +0_1_FA +0_1_9E +0_1_C6 +0_1_47 +0_1_49 +0_1_5F +0_1_BB +0_1_FC +0_1_A9 +0_1_00 +0_1_D2 +0_1_09 +0_1_CC +0_1_FF +0_1_DF +0_1_03 +0_1_C0 +0_1_BE +0_1_0E +0_1_73 +0_1_B9 +0_1_34 +0_1_C9 +0_1_2C +0_1_11 +0_1_E3 +0_1_DB +0_1_DC +0_1_8D +0_1_0A +0_1_D5 +0_1_E2 +0_1_E2 +0_1_1B +0_1_B0 +0_1_5F +0_1_78 +0_1_6F +0_1_B5 +0_1_90 +0_1_6D +0_1_39 +0_1_9A +0_1_5B +0_1_DD +0_1_B9 +0_1_EE +0_1_27 +0_1_61 +0_1_B2 +0_1_B7 +0_1_F1 +0_1_D5 +0_1_1D +0_1_59 +0_1_9C +0_1_5F +0_1_1F +0_1_B9 +0_1_89 +0_1_AC +0_1_39 +0_1_A3 +0_1_68 +0_1_7D +0_1_BF +0_1_69 +0_1_4E +0_1_63 +0_1_8B +0_1_CD +0_1_07 +0_1_C6 +0_1_F2 +0_1_21 +0_1_AD +0_1_2C +0_1_F7 +0_1_AD +0_1_79 +0_1_B8 +0_1_BF +0_1_51 +0_1_DA +0_1_F1 +0_1_45 +0_1_6C +0_1_C4 +0_1_C6 +0_1_4F +0_1_FC +0_1_4B +0_1_CE +0_1_A1 +0_1_06 +0_1_70 +0_1_D4 +0_1_70 +0_1_38 +0_1_3B +0_1_92 +0_1_19 +0_1_CD +0_1_0A +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +// WORD Number: 1 +1_1_BD +0_1_13 +0_1_B1 +0_1_28 +0_1_42 +0_1_22 +0_1_E5 +0_1_A1 +0_1_D0 +0_1_CE +0_1_26 +0_1_55 +0_1_96 +0_1_14 +0_1_C9 +0_1_4C +0_1_4E +0_1_5B +0_1_EA +0_1_49 +0_1_7A +0_1_AA +0_1_C5 +0_1_A2 +0_1_ED +0_1_17 +0_1_64 +0_1_4E +0_1_8E +0_1_83 +0_1_7B +0_1_40 +0_1_59 +0_1_84 +0_1_90 +0_1_F3 +0_1_A6 +0_1_A3 +0_1_5E +0_1_47 +0_1_AE +0_1_C8 +0_1_7C +0_1_8B +0_1_4B +0_1_F2 +0_1_3A +0_1_DB +0_1_FF +0_1_2B +0_1_CC +0_1_AC +0_1_38 +0_1_BC +0_1_AA +0_1_A5 +0_1_D2 +0_1_9D +0_1_36 +0_1_B1 +0_1_DE +0_1_2F +0_1_9F +0_1_52 +0_1_A2 +0_1_2D +0_1_06 +0_1_38 +0_1_E0 +0_1_E0 +0_1_E0 +0_1_12 +0_1_5C +0_1_93 +0_1_9C +0_1_A4 +0_1_98 +0_1_47 +0_1_85 +0_1_19 +0_1_E2 +0_1_A8 +0_1_E9 +0_1_9B +0_1_90 +0_1_3F +0_1_7B +0_1_22 +0_1_8B +0_1_E8 +0_1_F6 +0_1_89 +0_1_0A +0_1_87 +0_1_03 +0_1_E7 +0_1_A0 +0_1_F7 +0_1_5D +0_1_1C +0_1_79 +0_1_43 +0_1_33 +0_1_AA +0_1_E1 +0_1_19 +0_1_CE +0_1_C7 +0_1_05 +0_1_7B +0_1_73 +0_1_B0 +0_1_FE +0_1_B8 +0_1_8B +0_1_3F +0_1_0B +0_1_9B +0_1_01 +0_1_C0 +0_1_1E +0_1_E2 +0_1_EC +0_1_01 +0_1_9B +0_1_F1 +0_1_6E +0_1_A8 +0_1_5C +0_1_C8 +0_1_DB +0_1_C9 +0_1_F8 +0_1_33 +0_1_1E +0_1_B8 +0_1_45 +0_1_40 +0_1_59 +0_1_1C +0_1_1B +0_1_F6 +0_1_CC +0_1_45 +0_1_5B +0_1_44 +0_1_F8 +0_1_C0 +0_1_30 +0_1_38 +0_1_04 +0_1_28 +0_1_95 +0_1_72 +0_1_5F +0_1_3E +0_1_18 +0_1_D7 +0_1_A7 +0_1_3C +0_1_DD +0_1_8A +0_1_CA +0_1_67 +0_1_E5 +0_1_18 +0_1_6B +0_1_E4 +0_1_90 +0_1_F2 +0_1_87 +0_1_CC +0_1_61 +0_1_21 +0_1_58 +0_1_83 +0_1_02 +0_1_35 +0_1_79 +0_1_45 +0_1_88 +0_1_7E +0_1_4C +0_1_01 +0_1_F7 +0_1_7F +0_1_99 +0_1_6B +0_1_09 +0_1_A0 +0_1_77 +0_1_4D +0_1_2B +0_1_23 +0_1_70 +0_1_1D +0_1_C9 +0_1_59 +0_1_E0 +0_1_D5 +0_1_CB +0_1_16 +0_1_9E +0_1_FF +0_1_60 +0_1_62 +0_1_DE +0_1_0F +0_1_FA +0_1_71 +0_1_56 +0_1_F6 +0_1_9A +0_1_D6 +0_1_A0 +0_1_F4 +0_1_4D +0_1_F3 +0_1_E0 +0_1_AE +0_1_F6 +0_1_B4 +0_1_A6 +0_1_80 +0_1_4F +0_1_7D +0_1_16 +0_1_14 +0_1_2B +0_1_60 +0_1_46 +0_1_34 +0_1_FE +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +// WORD Number: 2 +1_1_94 +0_1_E7 +0_1_DC +0_1_9E +0_1_22 +0_1_28 +0_1_94 +0_1_4B +0_1_E2 +0_1_D7 +0_1_FC +0_1_EE +0_1_A6 +0_1_C9 +0_1_A9 +0_1_9E +0_1_B5 +0_1_7D +0_1_2F +0_1_68 +0_1_7B +0_1_FC +0_1_7F +0_1_50 +0_1_7E +0_1_03 +0_1_74 +0_1_93 +0_1_94 +0_1_64 +0_1_A8 +0_1_2F +0_1_54 +0_1_AA +0_1_8C +0_1_A5 +0_1_CA +0_1_FC +0_1_B8 +0_1_FE +0_1_6F +0_1_44 +0_1_7F +0_1_0C +0_1_57 +0_1_90 +0_1_C7 +0_1_F2 +0_1_AD +0_1_B8 +0_1_17 +0_1_E7 +0_1_5D +0_1_41 +0_1_F2 +0_1_36 +0_1_10 +0_1_81 +0_1_64 +0_1_89 +0_1_5D +0_1_04 +0_1_DA +0_1_68 +0_1_3D +0_1_2F +0_1_37 +0_1_FD +0_1_C0 +0_1_23 +0_1_23 +0_1_1A +0_1_FF +0_1_E4 +0_1_A6 +0_1_7D +0_1_52 +0_1_BB +0_1_F7 +0_1_52 +0_1_C3 +0_1_D8 +0_1_8E +0_1_F9 +0_1_C2 +0_1_3C +0_1_80 +0_1_0A +0_1_1A +0_1_D6 +0_1_0C +0_1_96 +0_1_23 +0_1_EC +0_1_71 +0_1_B0 +0_1_39 +0_1_BD +0_1_03 +0_1_2C +0_1_6E +0_1_65 +0_1_7E +0_1_A7 +0_1_7C +0_1_00 +0_1_9A +0_1_C8 +0_1_FE +0_1_12 +0_1_E0 +0_1_C4 +0_1_DF +0_1_27 +0_1_BB +0_1_28 +0_1_12 +0_1_B6 +0_1_D2 +0_1_D3 +0_1_83 +0_1_4B +0_1_95 +0_1_41 +0_1_4E +0_1_E5 +0_1_16 +0_1_10 +0_1_30 +0_1_9D +0_1_1B +0_1_BC +0_1_3A +0_1_89 +0_1_71 +0_1_AE +0_1_CD +0_1_E0 +0_1_83 +0_1_75 +0_1_C2 +0_1_5F +0_1_2B +0_1_53 +0_1_E9 +0_1_EB +0_1_C7 +0_1_FB +0_1_B5 +0_1_77 +0_1_90 +0_1_99 +0_1_35 +0_1_28 +0_1_27 +0_1_13 +0_1_46 +0_1_B7 +0_1_71 +0_1_8E +0_1_08 +0_1_18 +0_1_A5 +0_1_35 +0_1_8E +0_1_59 +0_1_A3 +0_1_35 +0_1_DA +0_1_CC +0_1_88 +0_1_0C +0_1_08 +0_1_68 +0_1_7F +0_1_04 +0_1_C9 +0_1_6D +0_1_DA +0_1_FA +0_1_13 +0_1_47 +0_1_61 +0_1_64 +0_1_17 +0_1_B5 +0_1_E9 +0_1_93 +0_1_74 +0_1_2A +0_1_29 +0_1_35 +0_1_AA +0_1_74 +0_1_CA +0_1_1D +0_1_D1 +0_1_9B +0_1_BD +0_1_47 +0_1_8B +0_1_0C +0_1_D1 +0_1_16 +0_1_37 +0_1_F6 +0_1_85 +0_1_E1 +0_1_67 +0_1_F5 +0_1_1A +0_1_AE +0_1_94 +0_1_EE +0_1_ED +0_1_3D +0_1_11 +0_1_3A +0_1_04 +0_1_49 +0_1_3E +0_1_06 +0_1_E7 +0_1_0A +0_1_FE +0_1_F9 +0_1_B1 +0_1_FE +0_1_6B +0_1_18 +0_1_66 +0_1_E9 +0_1_C8 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 +0_1_00 Index: trunk/example/sim/RsEncOut.hex =================================================================== --- trunk/example/sim/RsEncOut.hex (nonexistent) +++ trunk/example/sim/RsEncOut.hex (revision 4) @@ -0,0 +1,769 @@ +// DATA[7:0] +// WORD Number: 0 +E1 +BC +06 +84 +29 +49 +6D +69 +72 +CF +FD +92 +A7 +57 +2D +ED +17 +C8 +D6 +3D +84 +AD +E8 +04 +76 +38 +5C +A7 +D5 +87 +69 +CD +B7 +27 +FB +08 +77 +D7 +61 +B7 +07 +8E +45 +2B +87 +BF +E2 +08 +16 +DB +71 +EE +E8 +18 +E4 +59 +98 +71 +D7 +C6 +C0 +ED +C4 +18 +C8 +25 +76 +39 +FB +00 +C0 +04 +E0 +C2 +6E +63 +C7 +45 +7C +B4 +A2 +85 +86 +72 +16 +63 +80 +11 +D2 +A2 +A7 +29 +20 +36 +B7 +D7 +B9 +BE +5F +61 +DE +4F +F2 +18 +A4 +73 +5F +83 +90 +71 +63 +B9 +63 +CF +FD +0F +37 +16 +23 +F3 +CB +D5 +B3 +18 +1C +E8 +AC +D4 +35 +FA +9E +C6 +47 +49 +5F +BB +FC +A9 +00 +D2 +09 +CC +FF +DF +03 +C0 +BE +0E +73 +B9 +34 +C9 +2C +11 +E3 +DB +DC +8D +0A +D5 +E2 +E2 +1B +B0 +5F +78 +6F +B5 +90 +6D +39 +9A +5B +DD +B9 +EE +27 +61 +B2 +B7 +F1 +D5 +1D +59 +9C +5F +1F +B9 +89 +AC +39 +A3 +68 +7D +BF +69 +4E +63 +8B +CD +07 +C6 +F2 +21 +AD +2C +F7 +AD +79 +B8 +BF +51 +DA +F1 +45 +6C +C4 +C6 +4F +FC +4B +CE +A1 +06 +70 +D4 +70 +38 +3B +92 +19 +CD +0A +1D +2E +B5 +18 +96 +E5 +A9 +8B +EB +15 +E7 +DB +7D +36 +38 +63 +5B +39 +6D +46 +A4 +3A +// WORD Number: 1 +BD +13 +B1 +28 +42 +22 +E5 +A1 +D0 +CE +26 +55 +96 +14 +C9 +4C +4E +5B +EA +49 +7A +AA +C5 +A2 +ED +17 +64 +4E +8E +83 +7B +40 +59 +84 +90 +F3 +A6 +A3 +5E +47 +AE +C8 +7C +8B +4B +F2 +3A +DB +FF +2B +CC +AC +38 +BC +AA +A5 +D2 +9D +36 +B1 +DE +2F +9F +52 +A2 +2D +06 +38 +E0 +E0 +E0 +12 +5C +93 +9C +A4 +98 +47 +85 +19 +E2 +A8 +E9 +9B +90 +3F +7B +22 +8B +E8 +F6 +89 +0A +87 +03 +E7 +A0 +F7 +5D +1C +79 +43 +33 +AA +E1 +19 +CE +C7 +05 +7B +73 +B0 +FE +B8 +8B +3F +0B +9B +01 +C0 +1E +E2 +EC +01 +9B +F1 +6E +A8 +5C +C8 +DB +C9 +F8 +33 +1E +B8 +45 +40 +59 +1C +1B +F6 +CC +45 +5B +44 +F8 +C0 +30 +38 +04 +28 +95 +72 +5F +3E +18 +D7 +A7 +3C +DD +8A +CA +67 +E5 +18 +6B +E4 +90 +F2 +87 +CC +61 +21 +58 +83 +02 +35 +79 +45 +88 +7E +4C +01 +F7 +7F +99 +6B +09 +A0 +77 +4D +2B +23 +70 +1D +C9 +59 +E0 +D5 +CB +16 +9E +FF +60 +62 +DE +0F +FA +71 +56 +F6 +9A +D6 +A0 +F4 +4D +F3 +E0 +AE +F6 +B4 +A6 +80 +4F +7D +16 +14 +2B +60 +46 +34 +FE +44 +73 +3A +FD +E0 +5C +6A +9D +7A +3A +63 +AC +68 +EF +79 +1F +94 +6B +CB +76 +7E +FE +// WORD Number: 2 +94 +E7 +DC +9E +22 +28 +94 +4B +E2 +D7 +FC +EE +A6 +C9 +A9 +9E +B5 +7D +2F +68 +7B +FC +7F +50 +7E +03 +74 +93 +94 +64 +A8 +2F +54 +AA +8C +A5 +CA +FC +B8 +FE +6F +44 +7F +0C +57 +90 +C7 +F2 +AD +B8 +17 +E7 +5D +41 +F2 +36 +10 +81 +64 +89 +5D +04 +DA +68 +3D +2F +37 +FD +C0 +23 +23 +1A +FF +E4 +A6 +7D +52 +BB +F7 +52 +C3 +D8 +8E +F9 +C2 +3C +80 +0A +1A +D6 +0C +96 +23 +EC +71 +B0 +39 +BD +03 +2C +6E +65 +7E +A7 +7C +00 +9A +C8 +FE +12 +E0 +C4 +DF +27 +BB +28 +12 +B6 +D2 +D3 +83 +4B +95 +41 +4E +E5 +16 +10 +30 +9D +1B +BC +3A +89 +71 +AE +CD +E0 +83 +75 +C2 +5F +2B +53 +E9 +EB +C7 +FB +B5 +77 +90 +99 +35 +28 +27 +13 +46 +B7 +71 +8E +08 +18 +A5 +35 +8E +59 +A3 +35 +DA +CC +88 +0C +08 +68 +7F +04 +C9 +6D +DA +FA +13 +47 +61 +64 +17 +B5 +E9 +93 +74 +2A +29 +35 +AA +74 +CA +1D +D1 +9B +BD +47 +8B +0C +D1 +16 +37 +F6 +85 +E1 +67 +F5 +1A +AE +94 +EE +ED +3D +11 +3A +04 +49 +3E +06 +E7 +0A +FE +F9 +B1 +FE +6B +18 +66 +E9 +C8 +C5 +0E +99 +B9 +F3 +D5 +76 +63 +BA +48 +21 +42 +5B +03 +88 +0B +29 +CC +E3 +D9 +73 +74 Index: trunk/example/sim/RsDecIn.hex =================================================================== --- trunk/example/sim/RsDecIn.hex (nonexistent) +++ trunk/example/sim/RsDecIn.hex (revision 4) @@ -0,0 +1,2914 @@ +// SYNC, ENABLE, ERASURE_IN, DATA[7:0] +// WORD Number: 0 +1_1_0_0D7 +0_1_0_0C7 +0_1_0_0AD +0_1_0_086 +0_1_0_04A +0_1_0_045 +0_1_0_0F3 +0_1_0_0B6 +0_1_0_0F3 +0_1_0_0DB +0_1_0_0B8 +0_1_0_00E +0_1_0_037 +0_1_0_070 +0_1_0_01C +0_1_0_0BF +0_1_0_0D1 +0_1_0_0DC +0_1_0_066 +0_1_0_08F +0_1_0_0BD +0_1_0_042 +0_1_0_0F3 +0_1_0_0D1 +0_1_0_055 +0_1_0_0A0 +0_1_0_0A6 +0_1_0_094 +0_1_0_0BB +0_1_0_0A4 +0_1_1_000 +0_1_0_01B +0_1_0_076 +0_1_0_0C2 +0_1_0_035 +0_1_0_08D +0_1_0_060 +0_1_0_083 +0_1_0_0B8 +0_1_0_0EE +0_1_1_000 +0_1_0_020 +0_1_0_0F2 +0_1_0_04E +0_1_0_0B2 +0_1_0_04F +0_1_1_000 +0_1_1_000 +0_1_0_0CF +0_1_0_05D +0_1_0_076 +0_1_0_08E +0_1_0_00A +0_1_0_07D +0_1_0_0E1 +0_1_0_02B +0_1_0_0D8 +0_1_0_060 +0_1_1_000 +0_1_0_069 +0_1_0_095 +0_1_0_005 +0_1_0_04A +0_1_0_06C +0_1_0_023 +0_1_0_0D3 +0_1_0_0B8 +0_1_0_0DF +0_1_0_0D5 +0_1_0_0E5 +0_1_0_051 +0_1_0_0E5 +0_1_1_000 +0_1_0_0A5 +0_1_0_0AA +0_1_0_053 +0_1_0_01E +0_1_0_09C +0_1_0_0F5 +0_1_0_01C +0_1_0_0FE +0_1_0_088 +0_1_0_068 +0_1_0_00D +0_1_0_019 +0_1_1_000 +0_1_0_029 +0_1_0_0BA +0_1_0_0FF +0_1_0_074 +0_1_0_0B8 +0_1_0_0B8 +0_1_0_044 +0_1_0_028 +0_1_1_000 +0_1_0_00C +0_1_0_026 +0_1_0_022 +0_1_0_0C0 +0_1_0_0E4 +0_1_1_000 +0_1_0_012 +0_1_0_0C8 +0_1_0_085 +0_1_0_09F +0_1_0_092 +0_1_0_068 +0_1_0_085 +0_1_0_042 +0_1_0_0FE +0_1_0_05D +0_1_0_03A +0_1_0_0A7 +0_1_0_086 +0_1_0_0E8 +0_1_0_072 +0_1_0_0B3 +0_1_0_081 +0_1_0_0D1 +0_1_0_064 +0_1_0_012 +0_1_0_004 +0_1_0_0AC +0_1_0_0E7 +0_1_0_091 +0_1_0_0B4 +0_1_0_05B +0_1_0_0E2 +0_1_1_000 +0_1_0_0D8 +0_1_0_0D4 +0_1_0_004 +0_1_0_0FB +0_1_0_0B3 +0_1_0_025 +0_1_0_0B5 +0_1_0_042 +0_1_0_010 +0_1_0_0B5 +0_1_0_04C +0_1_0_0E8 +0_1_0_01E +0_1_0_0CC +0_1_0_082 +0_1_0_011 +0_1_0_07E +0_1_0_055 +0_1_0_026 +0_1_1_000 +0_1_0_09B +0_1_0_0E3 +0_1_0_013 +0_1_0_058 +0_1_0_03A +0_1_0_0F3 +0_1_0_060 +0_1_0_041 +0_1_0_052 +0_1_0_071 +0_1_0_0D6 +0_1_0_04E +0_1_0_01D +0_1_0_07D +0_1_0_0A7 +0_1_0_03C +0_1_0_06F +0_1_0_06E +0_1_0_05C +0_1_0_0BD +0_1_0_047 +0_1_0_017 +0_1_0_010 +0_1_0_0D6 +0_1_0_0A3 +0_1_0_04A +0_1_0_0DC +0_1_0_086 +0_1_0_099 +0_1_0_09B +0_1_0_092 +0_1_0_0A8 +0_1_0_0A4 +0_1_0_066 +0_1_0_0AE +0_1_0_01A +0_1_0_03C +0_1_0_014 +0_1_0_089 +0_1_0_01F +0_1_0_0A9 +0_1_1_000 +0_1_0_0D0 +0_1_0_002 +0_1_0_018 +0_1_0_041 +0_1_0_035 +0_1_0_0FD +0_1_0_0EF +0_1_1_000 +0_1_0_064 +0_1_0_058 +0_1_0_05E +0_1_0_018 +0_1_0_039 +0_1_0_0D5 +0_1_0_036 +0_1_0_0E0 +0_1_0_030 +0_1_0_04C +0_1_0_0FF +0_1_0_041 +0_1_0_01D +0_1_0_093 +0_1_0_045 +0_1_0_063 +0_1_1_000 +0_1_0_0A0 +0_1_0_032 +0_1_0_097 +0_1_0_0CC +0_1_0_0F2 +0_1_0_062 +0_1_0_0DD +0_1_0_0B8 +0_1_0_02D +0_1_0_0F2 +0_1_0_0AB +0_1_0_016 +0_1_0_004 +0_1_0_0DA +0_1_0_0E9 +0_1_0_0B4 +0_1_0_05B +0_1_0_025 +0_1_0_006 +0_1_0_0C2 +0_1_0_003 +0_1_0_0F3 +0_1_0_058 +0_1_0_070 +0_1_0_0B8 +0_1_0_091 +0_1_0_09A +0_1_0_0F4 +0_1_0_03A +0_1_0_0B5 +0_1_0_0A4 +0_1_0_001 +0_1_0_061 +0_1_0_045 +0_1_0_01D +0_1_0_079 +0_1_0_0AF +0_1_0_032 +0_1_0_009 +// WORD Number: 1 +1_1_0_085 +0_1_0_091 +0_1_0_002 +0_1_0_0DC +0_1_0_0FD +0_1_0_003 +0_1_0_060 +0_1_0_0E5 +0_1_0_0B5 +0_1_0_09E +0_1_0_08A +0_1_0_0BE +0_1_1_000 +0_1_1_000 +0_1_0_05E +0_1_0_016 +0_1_0_021 +0_1_0_0D9 +0_1_0_0DB +0_1_0_046 +0_1_0_0DE +0_1_1_000 +0_1_0_091 +0_1_0_0EC +0_1_0_0D5 +0_1_0_0A1 +0_1_1_000 +0_1_0_0D5 +0_1_0_0AE +0_1_0_096 +0_1_0_03B +0_1_0_021 +0_1_0_01E +0_1_0_08C +0_1_0_0BF +0_1_0_0A1 +0_1_0_0BC +0_1_0_095 +0_1_0_042 +0_1_0_084 +0_1_0_010 +0_1_0_0E2 +0_1_0_0BC +0_1_0_033 +0_1_0_0ED +0_1_0_0CD +0_1_0_0B4 +0_1_0_079 +0_1_0_001 +0_1_0_01D +0_1_0_059 +0_1_0_0E7 +0_1_0_0AB +0_1_0_086 +0_1_0_02F +0_1_0_077 +0_1_0_00C +0_1_0_070 +0_1_0_087 +0_1_0_06F +0_1_0_061 +0_1_0_0FA +0_1_0_094 +0_1_0_088 +0_1_0_090 +0_1_0_03D +0_1_0_098 +0_1_0_050 +0_1_0_000 +0_1_0_0D5 +0_1_0_055 +0_1_0_0CD +0_1_0_0AE +0_1_0_09E +0_1_0_0C4 +0_1_0_063 +0_1_0_07E +0_1_0_0BB +0_1_0_00A +0_1_0_0F7 +0_1_0_0CF +0_1_0_0DD +0_1_0_0A8 +0_1_0_055 +0_1_1_000 +0_1_0_0C1 +0_1_0_0F2 +0_1_0_0CF +0_1_0_01B +0_1_0_0FB +0_1_0_0C2 +0_1_0_027 +0_1_0_0F8 +0_1_0_0F3 +0_1_0_06D +0_1_0_0B0 +0_1_0_002 +0_1_0_02D +0_1_1_000 +0_1_0_0AF +0_1_0_073 +0_1_0_0CD +0_1_0_082 +0_1_0_007 +0_1_0_0B7 +0_1_0_05A +0_1_0_00C +0_1_0_016 +0_1_0_0C6 +0_1_0_0C2 +0_1_0_05A +0_1_0_0DA +0_1_0_0B0 +0_1_0_09E +0_1_0_030 +0_1_0_058 +0_1_0_079 +0_1_0_0B8 +0_1_0_0C3 +0_1_1_000 +0_1_0_028 +0_1_0_0CA +0_1_0_070 +0_1_0_0C7 +0_1_0_01B +0_1_0_089 +0_1_0_0AE +0_1_0_0DF +0_1_0_09D +0_1_0_0E2 +0_1_0_042 +0_1_0_088 +0_1_0_0BB +0_1_0_084 +0_1_0_0B2 +0_1_0_07C +0_1_0_053 +0_1_0_09E +0_1_0_0FB +0_1_0_013 +0_1_0_06D +0_1_0_0EA +0_1_0_086 +0_1_0_068 +0_1_0_0CE +0_1_0_0EA +0_1_0_059 +0_1_0_0B7 +0_1_0_0CB +0_1_0_072 +0_1_0_08B +0_1_0_00A +0_1_0_05C +0_1_0_066 +0_1_0_0FA +0_1_0_015 +0_1_0_071 +0_1_0_0C5 +0_1_0_040 +0_1_0_05E +0_1_0_089 +0_1_0_0E6 +0_1_0_0E2 +0_1_0_0A1 +0_1_0_080 +0_1_0_002 +0_1_0_0CB +0_1_0_072 +0_1_0_0A8 +0_1_0_0F3 +0_1_0_0F9 +0_1_0_024 +0_1_0_01C +0_1_0_03B +0_1_0_077 +0_1_1_000 +0_1_0_051 +0_1_0_048 +0_1_0_08B +0_1_0_03C +0_1_0_0EE +0_1_0_0F7 +0_1_0_030 +0_1_0_07C +0_1_0_0DE +0_1_0_056 +0_1_0_0C6 +0_1_0_0DA +0_1_0_0A3 +0_1_0_0AE +0_1_0_009 +0_1_0_075 +0_1_0_0ED +0_1_1_000 +0_1_0_040 +0_1_0_0C2 +0_1_0_06B +0_1_0_050 +0_1_0_0B6 +0_1_0_032 +0_1_0_0E1 +0_1_0_0E0 +0_1_0_06E +0_1_0_00F +0_1_0_07B +0_1_0_0BE +0_1_0_013 +0_1_0_0A7 +0_1_0_061 +0_1_0_041 +0_1_0_02E +0_1_0_0AD +0_1_0_08B +0_1_0_04F +0_1_0_09C +0_1_0_0DC +0_1_0_0D7 +0_1_0_022 +0_1_0_03E +0_1_0_0DD +0_1_0_058 +0_1_0_04C +0_1_0_0F2 +0_1_0_06B +0_1_0_0F1 +0_1_0_0F9 +0_1_0_0C2 +0_1_1_000 +0_1_0_023 +0_1_0_075 +0_1_0_05C +0_1_0_004 +0_1_0_024 +0_1_0_0DC +0_1_0_073 +0_1_0_045 +0_1_0_0E6 +0_1_0_0E2 +0_1_0_0A7 +0_1_0_0AD +0_1_0_038 +0_1_0_0B1 +0_1_0_0D5 +0_1_0_02B +0_1_0_075 +0_1_0_091 +0_1_0_082 +0_1_0_03A +0_1_0_042 +0_1_0_084 +0_1_0_03B +0_1_0_059 +0_1_0_030 +0_1_0_02A +0_1_0_077 +// WORD Number: 2 +1_1_0_071 +0_1_0_06F +0_1_0_005 +0_1_0_07E +0_1_0_098 +0_1_0_02E +0_1_0_071 +0_1_0_088 +0_1_0_0CF +0_1_0_0C3 +0_1_0_03D +0_1_0_0C3 +0_1_0_082 +0_1_0_0BF +0_1_0_047 +0_1_0_0E4 +0_1_0_09F +0_1_0_027 +0_1_0_014 +0_1_0_0AF +0_1_0_0ED +0_1_0_076 +0_1_0_0C2 +0_1_0_017 +0_1_0_09E +0_1_0_0E2 +0_1_0_03D +0_1_0_0A7 +0_1_0_027 +0_1_0_0E0 +0_1_0_0B6 +0_1_0_020 +0_1_0_04F +0_1_0_0EA +0_1_0_051 +0_1_0_064 +0_1_0_086 +0_1_0_080 +0_1_0_01E +0_1_0_092 +0_1_0_079 +0_1_0_06D +0_1_0_04B +0_1_0_073 +0_1_0_0E3 +0_1_0_04B +0_1_0_098 +0_1_0_015 +0_1_0_0A6 +0_1_0_049 +0_1_0_00A +0_1_0_0B5 +0_1_0_01A +0_1_0_02C +0_1_0_0E4 +0_1_0_0E2 +0_1_0_0A5 +0_1_0_094 +0_1_0_0D3 +0_1_0_0E0 +0_1_0_08C +0_1_0_081 +0_1_0_069 +0_1_0_04B +0_1_0_008 +0_1_0_015 +0_1_0_0CC +0_1_0_0FC +0_1_0_09D +0_1_0_09C +0_1_0_0B0 +0_1_0_031 +0_1_0_0A7 +0_1_0_0C9 +0_1_0_082 +0_1_0_0E7 +0_1_0_036 +0_1_0_042 +0_1_0_0E6 +0_1_0_08B +0_1_0_01B +0_1_0_060 +0_1_0_064 +0_1_0_0D2 +0_1_0_043 +0_1_0_02F +0_1_0_05E +0_1_0_0E6 +0_1_0_044 +0_1_0_0BD +0_1_0_046 +0_1_0_0C2 +0_1_0_036 +0_1_1_000 +0_1_0_00E +0_1_0_0DF +0_1_0_0C4 +0_1_0_079 +0_1_0_0DF +0_1_0_010 +0_1_0_082 +0_1_1_000 +0_1_0_00D +0_1_0_0AA +0_1_0_082 +0_1_0_060 +0_1_0_04B +0_1_0_0E9 +0_1_0_022 +0_1_0_0AD +0_1_0_01B +0_1_0_08F +0_1_0_027 +0_1_0_0F2 +0_1_0_089 +0_1_0_0CE +0_1_0_010 +0_1_0_088 +0_1_0_019 +0_1_0_068 +0_1_0_0A4 +0_1_0_0E4 +0_1_0_0FE +0_1_0_015 +0_1_0_0CE +0_1_0_018 +0_1_0_08C +0_1_0_025 +0_1_0_0AA +0_1_0_09C +0_1_1_000 +0_1_0_066 +0_1_0_0E0 +0_1_0_04F +0_1_0_01F +0_1_0_048 +0_1_0_031 +0_1_0_0B9 +0_1_0_00C +0_1_0_03F +0_1_0_04F +0_1_0_093 +0_1_0_01E +0_1_0_069 +0_1_0_0F2 +0_1_0_089 +0_1_0_0E1 +0_1_0_071 +0_1_0_028 +0_1_0_03E +0_1_0_0FC +0_1_0_0B3 +0_1_0_0EC +0_1_0_091 +0_1_0_063 +0_1_0_0A1 +0_1_1_000 +0_1_0_01F +0_1_0_0CD +0_1_0_065 +0_1_0_0E3 +0_1_0_008 +0_1_0_069 +0_1_1_000 +0_1_0_05D +0_1_0_0F7 +0_1_0_0CC +0_1_0_052 +0_1_0_0DC +0_1_0_05C +0_1_0_02E +0_1_0_0B2 +0_1_0_066 +0_1_0_0FC +0_1_0_0D7 +0_1_0_061 +0_1_0_0A3 +0_1_0_039 +0_1_0_0D4 +0_1_0_083 +0_1_0_034 +0_1_0_059 +0_1_0_0EE +0_1_0_00E +0_1_0_045 +0_1_0_04C +0_1_0_0DD +0_1_0_02D +0_1_0_066 +0_1_0_0AC +0_1_0_0B8 +0_1_0_0E7 +0_1_0_096 +0_1_0_045 +0_1_0_0B0 +0_1_0_0FC +0_1_1_000 +0_1_0_087 +0_1_0_0FE +0_1_0_00F +0_1_0_0AD +0_1_0_0D2 +0_1_0_01A +0_1_0_00A +0_1_0_00F +0_1_0_0F1 +0_1_0_02E +0_1_0_0BF +0_1_0_063 +0_1_0_0E4 +0_1_0_0CA +0_1_1_000 +0_1_0_0DB +0_1_1_000 +0_1_0_0D9 +0_1_0_0C0 +0_1_0_0D7 +0_1_0_09E +0_1_0_0D4 +0_1_0_083 +0_1_0_0B6 +0_1_0_0CA +0_1_0_035 +0_1_0_0F2 +0_1_0_0EC +0_1_0_0D9 +0_1_0_02F +0_1_0_0CA +0_1_0_055 +0_1_0_00A +0_1_0_09C +0_1_0_0C8 +0_1_0_0CA +0_1_0_03F +0_1_0_0A6 +0_1_0_075 +0_1_0_0CB +0_1_0_07D +0_1_0_0F5 +0_1_0_03A +0_1_0_05C +0_1_0_043 +0_1_0_020 +0_1_1_000 +0_1_0_08B +0_1_0_0F0 +0_1_0_048 +0_1_0_058 +0_1_0_0FD +0_1_0_0BF +0_1_0_036 +0_1_0_0EA +0_1_0_0E6 +0_1_0_03D +0_1_0_016 +// WORD Number: 3 +1_1_0_0C3 +0_1_0_01C +0_1_0_090 +0_1_0_0AA +0_1_0_029 +0_1_0_0B8 +0_1_0_094 +0_1_0_057 +0_1_0_039 +0_1_0_07F +0_1_0_09D +0_1_0_064 +0_1_0_0D8 +0_1_0_091 +0_1_0_0D9 +0_1_0_09B +0_1_0_0B8 +0_1_0_0AB +0_1_0_0A2 +0_1_1_000 +0_1_0_029 +0_1_0_0A8 +0_1_0_0F6 +0_1_0_09B +0_1_0_032 +0_1_0_048 +0_1_0_027 +0_1_0_014 +0_1_0_0E0 +0_1_0_031 +0_1_0_0D3 +0_1_0_01D +0_1_0_0DE +0_1_0_033 +0_1_0_017 +0_1_0_0B0 +0_1_0_046 +0_1_0_0D0 +0_1_0_000 +0_1_0_0F6 +0_1_0_0B7 +0_1_0_0FC +0_1_0_042 +0_1_0_01F +0_1_0_0A8 +0_1_0_021 +0_1_0_02D +0_1_0_091 +0_1_0_0FB +0_1_0_066 +0_1_0_0DC +0_1_0_046 +0_1_0_0D5 +0_1_0_031 +0_1_0_0B0 +0_1_0_06F +0_1_1_000 +0_1_0_0EA +0_1_0_0FD +0_1_0_05E +0_1_0_0A4 +0_1_0_003 +0_1_0_002 +0_1_1_000 +0_1_0_015 +0_1_0_035 +0_1_0_01F +0_1_0_074 +0_1_0_06C +0_1_0_00C +0_1_0_042 +0_1_0_052 +0_1_0_03B +0_1_0_0A5 +0_1_0_0A3 +0_1_0_0E9 +0_1_0_08B +0_1_0_0B7 +0_1_0_0B1 +0_1_0_038 +0_1_0_070 +0_1_0_0D0 +0_1_0_04B +0_1_0_0F3 +0_1_0_0E0 +0_1_0_0E1 +0_1_0_034 +0_1_0_025 +0_1_0_0C4 +0_1_0_0FD +0_1_0_0C1 +0_1_0_01A +0_1_1_000 +0_1_0_05E +0_1_0_0D5 +0_1_0_07C +0_1_0_090 +0_1_0_0A9 +0_1_0_00F +0_1_0_0BC +0_1_0_044 +0_1_0_072 +0_1_0_042 +0_1_0_0B3 +0_1_0_0EE +0_1_0_003 +0_1_0_026 +0_1_0_08A +0_1_0_029 +0_1_0_059 +0_1_0_04D +0_1_0_0D7 +0_1_0_03C +0_1_0_070 +0_1_0_058 +0_1_0_008 +0_1_0_0EF +0_1_0_0C1 +0_1_0_06A +0_1_0_005 +0_1_0_09E +0_1_0_008 +0_1_1_000 +0_1_0_011 +0_1_0_08B +0_1_0_04A +0_1_0_034 +0_1_0_0F1 +0_1_0_078 +0_1_0_017 +0_1_0_051 +0_1_0_051 +0_1_0_076 +0_1_0_00D +0_1_0_0E9 +0_1_0_063 +0_1_0_0F8 +0_1_0_09D +0_1_0_034 +0_1_0_0C9 +0_1_0_02B +0_1_0_012 +0_1_0_0E9 +0_1_0_0B5 +0_1_0_08A +0_1_0_0CE +0_1_0_069 +0_1_0_04F +0_1_0_0AD +0_1_0_0D7 +0_1_0_037 +0_1_0_057 +0_1_0_061 +0_1_0_093 +0_1_0_0B8 +0_1_0_00B +0_1_0_0FE +0_1_0_0D0 +0_1_0_007 +0_1_0_04B +0_1_0_0F5 +0_1_0_007 +0_1_0_04C +0_1_0_0FB +0_1_0_0A9 +0_1_1_000 +0_1_0_01D +0_1_0_0A9 +0_1_0_080 +0_1_0_0FB +0_1_0_036 +0_1_0_06F +0_1_0_039 +0_1_0_0E7 +0_1_0_06D +0_1_0_01B +0_1_0_080 +0_1_0_073 +0_1_0_0E8 +0_1_0_08E +0_1_0_0BF +0_1_0_02D +0_1_0_08D +0_1_0_062 +0_1_0_038 +0_1_0_027 +0_1_0_0BA +0_1_0_0D0 +0_1_0_051 +0_1_0_0F7 +0_1_0_036 +0_1_0_0D0 +0_1_0_02E +0_1_0_002 +0_1_0_068 +0_1_0_081 +0_1_0_085 +0_1_0_0FB +0_1_0_0C7 +0_1_0_0CC +0_1_0_0AE +0_1_0_0A6 +0_1_0_092 +0_1_0_044 +0_1_1_000 +0_1_0_0E2 +0_1_0_0C1 +0_1_0_051 +0_1_0_046 +0_1_0_0E6 +0_1_0_03B +0_1_0_08E +0_1_0_0D0 +0_1_0_098 +0_1_0_049 +0_1_0_06F +0_1_0_049 +0_1_0_04B +0_1_0_04B +0_1_0_027 +0_1_0_02B +0_1_0_0C8 +0_1_0_0AA +0_1_0_0C9 +0_1_0_04C +0_1_0_08F +0_1_0_00D +0_1_0_0AD +0_1_0_0B4 +0_1_0_05F +0_1_0_0D0 +0_1_0_015 +0_1_0_0AB +0_1_0_04B +0_1_0_015 +0_1_0_08E +0_1_0_082 +0_1_1_000 +0_1_0_059 +0_1_0_019 +0_1_0_046 +0_1_0_0C7 +0_1_0_033 +0_1_0_0FD +0_1_0_0B3 +0_1_0_020 +0_1_0_004 +0_1_0_023 +0_1_0_09A +0_1_0_088 +0_1_0_074 +0_1_0_057 +0_1_0_0EE +0_1_0_045 +0_1_0_016 +// WORD Number: 4 +1_1_0_05F +0_1_1_000 +0_1_0_06D +0_1_0_008 +0_1_0_01E +0_1_0_0D9 +0_1_0_0A3 +0_1_0_083 +0_1_0_09F +0_1_0_0C5 +0_1_0_0D3 +0_1_0_059 +0_1_0_025 +0_1_0_058 +0_1_0_0ED +0_1_0_0D0 +0_1_0_0B3 +0_1_1_000 +0_1_0_0BD +0_1_0_092 +0_1_0_018 +0_1_0_026 +0_1_0_010 +0_1_0_048 +0_1_0_029 +0_1_0_095 +0_1_0_018 +0_1_0_06B +0_1_0_04E +0_1_0_0BF +0_1_0_011 +0_1_0_057 +0_1_1_000 +0_1_0_006 +0_1_0_025 +0_1_0_0A2 +0_1_0_010 +0_1_0_0C7 +0_1_0_08D +0_1_1_000 +0_1_0_06C +0_1_0_08C +0_1_0_0FA +0_1_0_076 +0_1_0_01E +0_1_1_000 +0_1_0_033 +0_1_0_0B7 +0_1_1_000 +0_1_0_02D +0_1_0_0FF +0_1_1_000 +0_1_0_028 +0_1_0_05A +0_1_0_045 +0_1_0_030 +0_1_0_0D8 +0_1_0_055 +0_1_0_072 +0_1_0_08E +0_1_0_055 +0_1_0_05D +0_1_0_01B +0_1_0_093 +0_1_0_084 +0_1_0_055 +0_1_0_0E4 +0_1_0_067 +0_1_0_0C0 +0_1_0_0BC +0_1_0_0A0 +0_1_0_09D +0_1_0_01F +0_1_0_0DF +0_1_1_000 +0_1_0_008 +0_1_0_0F6 +0_1_0_04D +0_1_0_0D2 +0_1_0_0D0 +0_1_0_09F +0_1_0_08C +0_1_0_0AC +0_1_0_0C6 +0_1_0_079 +0_1_0_00A +0_1_0_046 +0_1_0_0F5 +0_1_0_031 +0_1_1_000 +0_1_0_049 +0_1_0_079 +0_1_0_040 +0_1_0_090 +0_1_0_0A2 +0_1_0_095 +0_1_0_0B5 +0_1_0_01F +0_1_0_071 +0_1_0_0FF +0_1_0_035 +0_1_0_0A1 +0_1_1_000 +0_1_0_07E +0_1_0_040 +0_1_0_028 +0_1_0_0D9 +0_1_1_000 +0_1_0_0B5 +0_1_0_0A3 +0_1_0_014 +0_1_0_044 +0_1_0_099 +0_1_0_09A +0_1_0_08C +0_1_0_007 +0_1_0_014 +0_1_0_01F +0_1_0_05C +0_1_0_0BE +0_1_0_0BC +0_1_0_001 +0_1_0_064 +0_1_0_0D7 +0_1_0_017 +0_1_0_042 +0_1_0_0F0 +0_1_0_085 +0_1_0_05A +0_1_0_0CB +0_1_0_095 +0_1_0_013 +0_1_0_077 +0_1_0_05F +0_1_0_05C +0_1_0_079 +0_1_0_057 +0_1_0_0CE +0_1_0_023 +0_1_0_02D +0_1_0_064 +0_1_0_06B +0_1_0_03F +0_1_0_03B +0_1_0_04B +0_1_0_0BF +0_1_0_066 +0_1_0_098 +0_1_0_000 +0_1_0_07F +0_1_0_0CD +0_1_0_0B3 +0_1_0_002 +0_1_0_0BC +0_1_0_08D +0_1_0_04E +0_1_0_0E0 +0_1_0_05A +0_1_0_04B +0_1_0_08C +0_1_0_0FC +0_1_0_0C3 +0_1_0_018 +0_1_0_04B +0_1_0_08F +0_1_0_0DC +0_1_0_096 +0_1_0_0B3 +0_1_0_0ED +0_1_0_039 +0_1_0_05C +0_1_0_00F +0_1_0_00B +0_1_0_08D +0_1_0_09C +0_1_0_0DC +0_1_0_03E +0_1_0_064 +0_1_0_003 +0_1_0_020 +0_1_0_045 +0_1_0_014 +0_1_0_0E1 +0_1_0_0FE +0_1_0_08A +0_1_1_000 +0_1_0_08A +0_1_0_086 +0_1_0_0A5 +0_1_0_0C0 +0_1_0_0FC +0_1_0_0D2 +0_1_0_022 +0_1_0_06E +0_1_0_0C2 +0_1_0_04E +0_1_0_084 +0_1_0_002 +0_1_0_018 +0_1_0_057 +0_1_0_089 +0_1_0_0D0 +0_1_0_04F +0_1_0_008 +0_1_0_0B0 +0_1_0_0F0 +0_1_0_073 +0_1_0_050 +0_1_0_0F9 +0_1_0_0EF +0_1_0_02C +0_1_0_048 +0_1_0_0EC +0_1_0_0C4 +0_1_0_0E2 +0_1_0_0C4 +0_1_0_0DC +0_1_0_006 +0_1_0_024 +0_1_0_029 +0_1_0_06D +0_1_0_05C +0_1_1_000 +0_1_0_07E +0_1_0_054 +0_1_0_034 +0_1_0_05A +0_1_0_0C5 +0_1_0_05E +0_1_0_0B8 +0_1_0_029 +0_1_0_08B +0_1_0_0B4 +0_1_0_060 +0_1_0_019 +0_1_0_020 +0_1_0_065 +0_1_0_0B8 +0_1_0_0E4 +0_1_0_00D +0_1_0_0EA +0_1_0_0A0 +0_1_0_01D +0_1_0_097 +0_1_0_097 +0_1_0_0EB +0_1_0_052 +0_1_0_0C7 +0_1_0_0D0 +0_1_0_0CE +0_1_0_01B +0_1_0_0A3 +0_1_0_06A +0_1_0_0FE +0_1_0_0C7 +// WORD Number: 5 +1_1_0_017 +0_1_1_000 +0_1_0_07E +0_1_0_0EA +0_1_0_050 +0_1_0_08D +0_1_0_036 +0_1_0_00E +0_1_0_041 +0_1_0_0E4 +0_1_0_0F2 +0_1_0_0D5 +0_1_0_035 +0_1_0_06D +0_1_0_06D +0_1_0_063 +0_1_0_0D1 +0_1_0_006 +0_1_0_09D +0_1_0_021 +0_1_0_0EB +0_1_1_000 +0_1_0_02E +0_1_0_060 +0_1_0_0A0 +0_1_0_0CD +0_1_0_02E +0_1_0_03F +0_1_0_0A0 +0_1_0_032 +0_1_0_00A +0_1_0_0CE +0_1_1_000 +0_1_0_05C +0_1_0_0B9 +0_1_0_073 +0_1_0_005 +0_1_1_000 +0_1_0_037 +0_1_0_08D +0_1_0_03B +0_1_0_08D +0_1_0_035 +0_1_0_058 +0_1_0_0CD +0_1_0_044 +0_1_0_00F +0_1_0_011 +0_1_0_011 +0_1_0_06A +0_1_0_0FE +0_1_0_05A +0_1_0_031 +0_1_0_057 +0_1_0_08F +0_1_0_0DF +0_1_0_03A +0_1_0_0B5 +0_1_0_053 +0_1_0_03A +0_1_0_06F +0_1_0_084 +0_1_0_0D8 +0_1_0_014 +0_1_0_0E3 +0_1_0_060 +0_1_0_0D9 +0_1_0_08D +0_1_0_047 +0_1_0_007 +0_1_0_0B2 +0_1_0_0DE +0_1_0_000 +0_1_0_016 +0_1_0_016 +0_1_0_03D +0_1_0_07D +0_1_0_013 +0_1_0_004 +0_1_0_002 +0_1_0_0C7 +0_1_0_0B0 +0_1_0_0F7 +0_1_0_007 +0_1_1_000 +0_1_0_04E +0_1_0_05E +0_1_0_054 +0_1_0_033 +0_1_0_0C1 +0_1_0_04B +0_1_0_0FC +0_1_0_02A +0_1_0_053 +0_1_0_06F +0_1_0_042 +0_1_0_082 +0_1_0_00B +0_1_0_046 +0_1_0_000 +0_1_0_0BE +0_1_0_02F +0_1_0_08F +0_1_0_04A +0_1_0_0B7 +0_1_0_007 +0_1_0_0FF +0_1_0_04E +0_1_0_0EC +0_1_0_0E4 +0_1_0_036 +0_1_0_07E +0_1_0_019 +0_1_0_061 +0_1_0_0F2 +0_1_1_000 +0_1_0_00B +0_1_0_0E9 +0_1_0_083 +0_1_0_007 +0_1_0_0B2 +0_1_1_000 +0_1_0_07F +0_1_0_04D +0_1_0_078 +0_1_0_0A7 +0_1_0_0B6 +0_1_0_0A0 +0_1_1_000 +0_1_0_0E4 +0_1_0_068 +0_1_0_094 +0_1_0_013 +0_1_0_0FE +0_1_0_0B6 +0_1_0_017 +0_1_0_089 +0_1_0_0E9 +0_1_0_057 +0_1_0_051 +0_1_0_0C2 +0_1_0_0BE +0_1_0_08C +0_1_0_0CF +0_1_0_02F +0_1_0_004 +0_1_0_056 +0_1_0_0E1 +0_1_0_0EE +0_1_0_02F +0_1_0_0E6 +0_1_0_040 +0_1_0_0E0 +0_1_0_066 +0_1_0_055 +0_1_0_0F4 +0_1_0_001 +0_1_0_089 +0_1_0_095 +0_1_0_075 +0_1_0_0F9 +0_1_0_073 +0_1_0_0A8 +0_1_0_011 +0_1_0_0EE +0_1_0_07C +0_1_0_00F +0_1_0_08D +0_1_1_000 +0_1_0_042 +0_1_1_000 +0_1_0_00F +0_1_0_0A9 +0_1_0_0AA +0_1_0_0EE +0_1_0_03C +0_1_0_032 +0_1_0_021 +0_1_0_08B +0_1_0_09D +0_1_0_0AA +0_1_1_000 +0_1_0_06F +0_1_0_047 +0_1_0_0E4 +0_1_0_00F +0_1_0_036 +0_1_0_0BB +0_1_0_06E +0_1_0_000 +0_1_0_0F4 +0_1_0_00B +0_1_0_021 +0_1_0_040 +0_1_1_000 +0_1_0_03E +0_1_0_0F6 +0_1_0_0B2 +0_1_0_083 +0_1_0_0F6 +0_1_0_01C +0_1_0_09D +0_1_0_0F4 +0_1_0_050 +0_1_0_047 +0_1_0_0AE +0_1_0_044 +0_1_0_00C +0_1_0_04A +0_1_0_041 +0_1_0_0F9 +0_1_0_0EE +0_1_0_0E8 +0_1_0_0DC +0_1_0_007 +0_1_0_063 +0_1_0_0E7 +0_1_0_0FC +0_1_0_08B +0_1_0_068 +0_1_0_067 +0_1_0_015 +0_1_0_0BB +0_1_1_000 +0_1_0_072 +0_1_0_0D4 +0_1_0_01D +0_1_0_0E4 +0_1_0_0D4 +0_1_0_0A7 +0_1_0_0F8 +0_1_0_098 +0_1_0_02D +0_1_0_042 +0_1_0_084 +0_1_0_018 +0_1_0_0A0 +0_1_0_01B +0_1_0_0B0 +0_1_0_0DF +0_1_0_0A5 +0_1_0_062 +0_1_0_0BD +0_1_0_04F +0_1_0_06D +0_1_0_004 +0_1_0_0FD +0_1_0_02C +0_1_0_07F +0_1_0_0FC +0_1_0_0C8 +0_1_0_0B4 +0_1_0_057 +0_1_0_093 +0_1_0_0EF +// WORD Number: 6 +1_1_0_0F5 +0_1_0_09F +0_1_0_092 +0_1_0_098 +0_1_0_0D5 +0_1_0_060 +0_1_0_069 +0_1_1_000 +0_1_0_010 +0_1_0_08E +0_1_0_083 +0_1_0_007 +0_1_0_044 +0_1_0_05E +0_1_0_011 +0_1_0_0A3 +0_1_0_0D9 +0_1_0_0A7 +0_1_0_05B +0_1_0_092 +0_1_0_0E4 +0_1_0_03C +0_1_0_0BE +0_1_0_04E +0_1_0_04B +0_1_0_078 +0_1_0_0F0 +0_1_0_03C +0_1_0_02B +0_1_0_01A +0_1_0_08C +0_1_0_027 +0_1_0_076 +0_1_0_053 +0_1_0_0CA +0_1_0_0ED +0_1_0_0E1 +0_1_0_01E +0_1_0_08D +0_1_0_078 +0_1_0_0FD +0_1_0_0D0 +0_1_0_0A4 +0_1_0_0F0 +0_1_0_0A3 +0_1_0_0F0 +0_1_0_049 +0_1_0_02F +0_1_0_041 +0_1_0_048 +0_1_0_0EE +0_1_0_076 +0_1_0_064 +0_1_0_03C +0_1_0_03A +0_1_0_05E +0_1_0_08D +0_1_0_05B +0_1_0_04E +0_1_0_011 +0_1_0_0E7 +0_1_0_034 +0_1_0_04C +0_1_0_0B9 +0_1_0_041 +0_1_0_06B +0_1_0_01A +0_1_0_039 +0_1_0_047 +0_1_0_00C +0_1_0_063 +0_1_0_01C +0_1_0_0A6 +0_1_0_01E +0_1_0_0DF +0_1_0_0CA +0_1_0_070 +0_1_0_07C +0_1_0_0D5 +0_1_1_000 +0_1_0_0C1 +0_1_0_0E0 +0_1_0_0DE +0_1_0_084 +0_1_0_0A3 +0_1_0_041 +0_1_0_0EB +0_1_0_00E +0_1_0_02F +0_1_0_05F +0_1_0_089 +0_1_0_08A +0_1_0_0F5 +0_1_0_09C +0_1_0_064 +0_1_0_086 +0_1_0_09E +0_1_0_00D +0_1_0_00A +0_1_0_0E4 +0_1_0_0D0 +0_1_0_0D1 +0_1_0_0F2 +0_1_0_0D3 +0_1_0_052 +0_1_0_0A1 +0_1_0_0BD +0_1_0_0FE +0_1_0_071 +0_1_0_0A9 +0_1_0_0BB +0_1_0_003 +0_1_0_0A2 +0_1_0_096 +0_1_0_0B1 +0_1_0_026 +0_1_0_068 +0_1_0_0F1 +0_1_0_0DA +0_1_0_047 +0_1_0_078 +0_1_0_0AB +0_1_0_02B +0_1_0_011 +0_1_0_01C +0_1_0_0F9 +0_1_0_0DB +0_1_0_075 +0_1_0_0D5 +0_1_0_062 +0_1_0_023 +0_1_0_056 +0_1_0_044 +0_1_0_015 +0_1_0_043 +0_1_1_000 +0_1_0_04A +0_1_0_081 +0_1_0_0C5 +0_1_0_0F2 +0_1_0_06F +0_1_1_000 +0_1_0_005 +0_1_0_019 +0_1_0_080 +0_1_0_093 +0_1_0_0F1 +0_1_1_000 +0_1_0_07C +0_1_0_0F4 +0_1_0_00E +0_1_0_0EF +0_1_0_0B2 +0_1_0_068 +0_1_0_0BC +0_1_0_00D +0_1_0_023 +0_1_0_0F3 +0_1_0_0BA +0_1_0_06D +0_1_0_02D +0_1_0_091 +0_1_0_0EC +0_1_0_0F8 +0_1_0_06B +0_1_0_082 +0_1_0_05C +0_1_0_01E +0_1_0_0D7 +0_1_0_0E5 +0_1_0_080 +0_1_0_00F +0_1_0_031 +0_1_0_088 +0_1_0_0BB +0_1_0_02E +0_1_0_0A5 +0_1_0_0FF +0_1_0_025 +0_1_0_0C2 +0_1_0_0A8 +0_1_0_0F3 +0_1_0_08F +0_1_0_0EF +0_1_1_000 +0_1_0_0BD +0_1_0_0C2 +0_1_0_0E6 +0_1_0_0D3 +0_1_0_033 +0_1_0_008 +0_1_1_000 +0_1_0_0EF +0_1_0_0C2 +0_1_0_0EE +0_1_0_030 +0_1_0_00C +0_1_0_0BE +0_1_0_047 +0_1_0_081 +0_1_0_03F +0_1_0_0F5 +0_1_0_074 +0_1_0_0BD +0_1_0_081 +0_1_0_08A +0_1_0_0E3 +0_1_0_029 +0_1_0_057 +0_1_0_001 +0_1_0_0D6 +0_1_0_08D +0_1_0_0B2 +0_1_0_096 +0_1_0_066 +0_1_0_030 +0_1_0_013 +0_1_1_000 +0_1_0_0C7 +0_1_0_003 +0_1_0_0F4 +0_1_0_061 +0_1_0_0CD +0_1_0_01D +0_1_0_064 +0_1_0_01F +0_1_0_0AF +0_1_0_067 +0_1_0_0F1 +0_1_0_071 +0_1_0_00C +0_1_0_099 +0_1_0_0CA +0_1_0_06E +0_1_0_099 +0_1_0_0FC +0_1_0_0C7 +0_1_0_04E +0_1_0_016 +0_1_0_01A +0_1_0_0F8 +0_1_0_07C +0_1_0_083 +0_1_0_0A6 +0_1_0_09C +0_1_0_07C +0_1_0_048 +0_1_0_063 +0_1_0_0DC +0_1_0_049 +0_1_0_011 +0_1_0_085 +0_1_0_0F6 +0_1_0_074 +0_1_0_090 +// WORD Number: 7 +1_1_0_00D +0_1_0_09A +0_1_0_056 +0_1_0_0AC +0_1_0_0F9 +0_1_0_05B +0_1_0_0C8 +0_1_0_077 +0_1_0_075 +0_1_0_086 +0_1_0_0A3 +0_1_0_00A +0_1_0_08D +0_1_0_00B +0_1_0_0EC +0_1_0_0EB +0_1_0_0FE +0_1_0_0C5 +0_1_0_0E0 +0_1_0_0EE +0_1_0_098 +0_1_0_04E +0_1_0_07D +0_1_0_0AA +0_1_0_0E6 +0_1_1_000 +0_1_1_000 +0_1_0_02D +0_1_0_011 +0_1_0_0B8 +0_1_0_03E +0_1_0_0EF +0_1_0_002 +0_1_0_084 +0_1_0_03D +0_1_0_005 +0_1_0_0C7 +0_1_0_061 +0_1_0_064 +0_1_0_097 +0_1_0_038 +0_1_0_0D7 +0_1_0_0E9 +0_1_0_094 +0_1_0_0DA +0_1_0_066 +0_1_0_01A +0_1_0_0A4 +0_1_0_003 +0_1_0_01D +0_1_0_09E +0_1_0_05F +0_1_1_000 +0_1_0_068 +0_1_0_0FE +0_1_0_0BC +0_1_0_0F3 +0_1_0_02A +0_1_0_064 +0_1_0_0CC +0_1_0_040 +0_1_0_00B +0_1_0_0A2 +0_1_0_0A8 +0_1_0_02A +0_1_0_014 +0_1_0_075 +0_1_0_0A8 +0_1_0_0FA +0_1_0_079 +0_1_0_00B +0_1_0_0D5 +0_1_0_0E0 +0_1_0_0B5 +0_1_0_0C4 +0_1_0_0A1 +0_1_0_0DD +0_1_0_0DC +0_1_0_036 +0_1_0_0D6 +0_1_0_0E0 +0_1_0_02D +0_1_0_073 +0_1_0_0CD +0_1_0_030 +0_1_0_0E7 +0_1_0_089 +0_1_0_0E0 +0_1_0_009 +0_1_0_05F +0_1_0_05B +0_1_0_021 +0_1_0_08A +0_1_1_000 +0_1_0_077 +0_1_0_04D +0_1_0_0CF +0_1_0_06F +0_1_0_088 +0_1_0_0FB +0_1_0_05A +0_1_0_04A +0_1_0_0C6 +0_1_0_019 +0_1_0_0B7 +0_1_0_04A +0_1_0_0BB +0_1_0_099 +0_1_0_05F +0_1_1_000 +0_1_0_046 +0_1_0_068 +0_1_0_0DE +0_1_0_01E +0_1_1_000 +0_1_0_0A0 +0_1_0_031 +0_1_0_074 +0_1_0_035 +0_1_0_0FE +0_1_0_072 +0_1_0_0DE +0_1_0_0B3 +0_1_0_096 +0_1_0_0B7 +0_1_0_029 +0_1_0_0C5 +0_1_0_0C5 +0_1_0_037 +0_1_0_0C0 +0_1_0_0FE +0_1_0_068 +0_1_0_0AE +0_1_0_07D +0_1_0_09C +0_1_0_04B +0_1_0_003 +0_1_0_0BE +0_1_0_056 +0_1_0_0E5 +0_1_0_028 +0_1_0_0BC +0_1_0_055 +0_1_0_042 +0_1_0_043 +0_1_0_018 +0_1_0_080 +0_1_0_040 +0_1_0_00B +0_1_1_000 +0_1_0_0FC +0_1_0_0FE +0_1_0_074 +0_1_0_0D0 +0_1_0_0F3 +0_1_0_092 +0_1_0_08E +0_1_0_043 +0_1_0_095 +0_1_0_0FA +0_1_0_0AA +0_1_0_02D +0_1_0_05D +0_1_0_055 +0_1_0_0C0 +0_1_0_0B9 +0_1_0_096 +0_1_0_054 +0_1_0_00D +0_1_0_039 +0_1_0_01D +0_1_0_0EB +0_1_0_000 +0_1_0_075 +0_1_0_068 +0_1_0_04C +0_1_0_057 +0_1_0_042 +0_1_0_0C7 +0_1_0_015 +0_1_0_086 +0_1_0_057 +0_1_0_0EA +0_1_0_0C8 +0_1_0_058 +0_1_0_05D +0_1_0_0A4 +0_1_0_07D +0_1_0_0D8 +0_1_0_045 +0_1_0_0EE +0_1_0_0D3 +0_1_0_072 +0_1_0_0DE +0_1_0_02F +0_1_0_02C +0_1_0_056 +0_1_0_0A7 +0_1_0_0BB +0_1_0_01A +0_1_0_01D +0_1_0_0E2 +0_1_0_099 +0_1_0_014 +0_1_0_0AF +0_1_0_0E9 +0_1_0_089 +0_1_0_06E +0_1_0_064 +0_1_0_0C5 +0_1_0_045 +0_1_0_088 +0_1_0_069 +0_1_0_0FD +0_1_0_008 +0_1_0_045 +0_1_0_066 +0_1_0_0AC +0_1_0_04D +0_1_0_0BE +0_1_0_05D +0_1_0_0D6 +0_1_0_0D9 +0_1_0_038 +0_1_0_0D6 +0_1_0_0FC +0_1_0_0FB +0_1_0_054 +0_1_0_039 +0_1_0_0EE +0_1_0_013 +0_1_0_086 +0_1_0_07B +0_1_0_06F +0_1_0_088 +0_1_0_031 +0_1_0_058 +0_1_0_0D0 +0_1_0_090 +0_1_0_0A2 +0_1_0_0BC +0_1_0_018 +0_1_0_053 +0_1_0_0A7 +0_1_0_077 +0_1_0_08E +0_1_0_0E9 +0_1_0_0A2 +0_1_1_000 +0_1_0_092 +0_1_0_0FD +0_1_0_098 +0_1_0_026 +0_1_0_02F +0_1_0_061 +// WORD Number: 8 +1_1_0_02C +0_1_0_055 +0_1_0_05C +0_1_1_000 +0_1_0_0B2 +0_1_0_0A8 +0_1_0_0F4 +0_1_0_039 +0_1_0_0DD +0_1_0_0CB +0_1_0_0E2 +0_1_0_0A5 +0_1_0_033 +0_1_0_039 +0_1_0_08B +0_1_0_018 +0_1_0_0D5 +0_1_0_09E +0_1_0_0B4 +0_1_0_0CE +0_1_0_062 +0_1_0_032 +0_1_0_08C +0_1_0_0CB +0_1_0_018 +0_1_0_046 +0_1_0_0ED +0_1_0_014 +0_1_0_03C +0_1_0_01C +0_1_0_0DF +0_1_0_01E +0_1_0_0BC +0_1_0_0FC +0_1_0_05E +0_1_0_087 +0_1_0_014 +0_1_1_000 +0_1_0_05D +0_1_0_004 +0_1_0_06E +0_1_0_040 +0_1_0_00A +0_1_1_000 +0_1_0_00D +0_1_0_07B +0_1_0_054 +0_1_0_012 +0_1_0_0EB +0_1_0_054 +0_1_0_0AA +0_1_0_0A7 +0_1_0_0A1 +0_1_0_014 +0_1_0_006 +0_1_0_001 +0_1_0_088 +0_1_0_0BE +0_1_0_02B +0_1_0_067 +0_1_0_01E +0_1_0_0E8 +0_1_0_02B +0_1_0_030 +0_1_0_0AB +0_1_0_0CA +0_1_0_02B +0_1_0_07A +0_1_0_024 +0_1_0_095 +0_1_0_06A +0_1_0_01F +0_1_0_04F +0_1_0_006 +0_1_0_080 +0_1_0_0E5 +0_1_0_028 +0_1_0_03A +0_1_0_0E4 +0_1_0_0F5 +0_1_0_084 +0_1_0_0C4 +0_1_0_0B1 +0_1_0_08F +0_1_0_0F4 +0_1_0_0FD +0_1_0_0AA +0_1_0_0FB +0_1_0_0EC +0_1_0_09B +0_1_0_07B +0_1_0_0C3 +0_1_0_024 +0_1_0_085 +0_1_0_042 +0_1_0_01F +0_1_0_03F +0_1_0_0E6 +0_1_0_04D +0_1_0_0B1 +0_1_0_0AB +0_1_0_080 +0_1_0_025 +0_1_0_072 +0_1_0_0C8 +0_1_0_044 +0_1_0_0CC +0_1_0_0ED +0_1_0_04C +0_1_0_01F +0_1_1_000 +0_1_0_0AB +0_1_0_0E6 +0_1_0_016 +0_1_0_050 +0_1_0_0EE +0_1_0_021 +0_1_0_095 +0_1_0_07F +0_1_0_0A2 +0_1_0_08C +0_1_0_004 +0_1_0_065 +0_1_0_090 +0_1_0_018 +0_1_0_09C +0_1_0_02C +0_1_0_0D5 +0_1_0_0C1 +0_1_0_079 +0_1_0_04C +0_1_0_092 +0_1_0_070 +0_1_0_0F0 +0_1_0_096 +0_1_0_0E6 +0_1_0_020 +0_1_0_022 +0_1_0_077 +0_1_0_019 +0_1_1_000 +0_1_0_0D1 +0_1_0_07B +0_1_0_01A +0_1_0_059 +0_1_0_073 +0_1_0_010 +0_1_0_02C +0_1_0_0F1 +0_1_0_085 +0_1_0_08D +0_1_0_0DC +0_1_0_0AF +0_1_1_000 +0_1_0_072 +0_1_0_036 +0_1_0_0C0 +0_1_0_0D4 +0_1_0_0F1 +0_1_0_038 +0_1_0_078 +0_1_0_0AA +0_1_0_0AE +0_1_0_087 +0_1_0_03D +0_1_0_08B +0_1_0_0C4 +0_1_0_061 +0_1_0_0A1 +0_1_0_0C9 +0_1_0_008 +0_1_0_0D3 +0_1_0_0CE +0_1_0_0F9 +0_1_0_091 +0_1_0_02C +0_1_0_027 +0_1_0_003 +0_1_0_078 +0_1_0_0B1 +0_1_0_02C +0_1_0_075 +0_1_0_0DC +0_1_0_092 +0_1_0_09E +0_1_0_01D +0_1_0_029 +0_1_0_01D +0_1_0_0E4 +0_1_0_0D6 +0_1_0_09A +0_1_0_032 +0_1_0_0AE +0_1_0_0A2 +0_1_0_0FD +0_1_0_0F7 +0_1_0_0D8 +0_1_0_0F9 +0_1_0_0B7 +0_1_0_0CC +0_1_1_000 +0_1_0_061 +0_1_0_007 +0_1_0_082 +0_1_0_00C +0_1_0_03F +0_1_0_08F +0_1_0_0C7 +0_1_0_096 +0_1_0_0ED +0_1_0_010 +0_1_0_0E5 +0_1_0_09A +0_1_0_00C +0_1_0_075 +0_1_1_000 +0_1_0_0A2 +0_1_0_01C +0_1_0_013 +0_1_0_0AD +0_1_1_000 +0_1_0_04A +0_1_0_02F +0_1_0_0AA +0_1_0_0A9 +0_1_0_088 +0_1_0_0C0 +0_1_0_04A +0_1_0_00A +0_1_0_0E3 +0_1_0_077 +0_1_0_010 +0_1_0_039 +0_1_0_05D +0_1_0_091 +0_1_0_011 +0_1_0_0F5 +0_1_0_089 +0_1_0_008 +0_1_0_011 +0_1_0_0FF +0_1_0_0FD +0_1_0_05B +0_1_0_0BA +0_1_0_04E +0_1_0_077 +0_1_0_0A4 +0_1_0_00D +0_1_0_0F1 +0_1_0_050 +0_1_0_0F6 +0_1_0_0ED +0_1_0_058 +0_1_0_013 +0_1_0_073 +// WORD Number: 9 +1_1_0_0E1 +0_1_0_0A3 +0_1_0_0B0 +0_1_0_03B +0_1_0_073 +0_1_0_072 +0_1_0_0ED +0_1_0_0CA +0_1_0_03B +0_1_0_001 +0_1_0_0D1 +0_1_0_0A6 +0_1_0_04A +0_1_0_025 +0_1_0_0B1 +0_1_0_064 +0_1_0_037 +0_1_0_02D +0_1_0_06D +0_1_0_0F5 +0_1_0_07B +0_1_0_0BB +0_1_0_0F2 +0_1_0_0EE +0_1_0_01C +0_1_0_0D2 +0_1_0_003 +0_1_0_025 +0_1_0_089 +0_1_0_02F +0_1_0_03A +0_1_0_0D5 +0_1_0_0C5 +0_1_0_0DD +0_1_0_049 +0_1_0_09D +0_1_0_0C8 +0_1_0_004 +0_1_0_086 +0_1_0_012 +0_1_0_023 +0_1_0_002 +0_1_0_0A7 +0_1_0_0A2 +0_1_0_0E2 +0_1_0_0BC +0_1_0_0C9 +0_1_0_07F +0_1_0_0B6 +0_1_0_036 +0_1_0_0B8 +0_1_0_0E0 +0_1_1_000 +0_1_0_062 +0_1_0_06A +0_1_1_000 +0_1_0_018 +0_1_0_036 +0_1_0_0CC +0_1_0_0E7 +0_1_0_0EE +0_1_0_001 +0_1_0_0C2 +0_1_0_041 +0_1_0_072 +0_1_0_0FF +0_1_0_068 +0_1_0_0AC +0_1_0_056 +0_1_0_02B +0_1_0_09F +0_1_1_000 +0_1_0_004 +0_1_0_054 +0_1_0_0C5 +0_1_0_004 +0_1_0_085 +0_1_0_073 +0_1_0_0C3 +0_1_0_037 +0_1_0_0A2 +0_1_0_03C +0_1_0_04D +0_1_0_02C +0_1_0_049 +0_1_0_0F3 +0_1_0_065 +0_1_0_06C +0_1_0_032 +0_1_0_081 +0_1_0_021 +0_1_0_044 +0_1_0_0C1 +0_1_0_0C7 +0_1_1_000 +0_1_0_0BE +0_1_0_02F +0_1_0_032 +0_1_0_096 +0_1_0_0D0 +0_1_0_0E5 +0_1_0_090 +0_1_0_03E +0_1_0_0D2 +0_1_0_028 +0_1_0_022 +0_1_0_0B3 +0_1_0_035 +0_1_0_0FB +0_1_0_0F2 +0_1_0_0A6 +0_1_0_073 +0_1_0_041 +0_1_0_066 +0_1_0_0B5 +0_1_0_042 +0_1_0_023 +0_1_0_016 +0_1_0_0EC +0_1_0_00D +0_1_0_0B1 +0_1_0_0DB +0_1_0_08B +0_1_0_0A4 +0_1_0_0CC +0_1_0_028 +0_1_0_009 +0_1_0_033 +0_1_0_043 +0_1_0_09E +0_1_0_05A +0_1_0_071 +0_1_0_03C +0_1_0_0DA +0_1_0_06E +0_1_0_019 +0_1_0_0D6 +0_1_0_092 +0_1_0_0FA +0_1_0_09E +0_1_0_00C +0_1_0_0E0 +0_1_1_000 +0_1_1_000 +0_1_0_0DD +0_1_0_0DD +0_1_0_077 +0_1_0_088 +0_1_1_000 +0_1_0_072 +0_1_0_005 +0_1_0_034 +0_1_0_0DF +0_1_0_06B +0_1_0_091 +0_1_0_06F +0_1_0_0D5 +0_1_1_000 +0_1_0_0D9 +0_1_0_087 +0_1_0_0F7 +0_1_0_06A +0_1_0_03C +0_1_0_0F7 +0_1_0_024 +0_1_0_0B2 +0_1_0_034 +0_1_0_0DA +0_1_0_055 +0_1_0_0CC +0_1_0_021 +0_1_0_0A6 +0_1_0_080 +0_1_0_0E6 +0_1_0_048 +0_1_0_016 +0_1_0_0BC +0_1_0_0C9 +0_1_0_01B +0_1_0_068 +0_1_0_0A5 +0_1_0_0B0 +0_1_0_0BB +0_1_0_0C9 +0_1_0_002 +0_1_0_05A +0_1_0_0BB +0_1_0_00E +0_1_0_0A5 +0_1_0_05E +0_1_0_027 +0_1_0_0A4 +0_1_0_093 +0_1_0_0BF +0_1_1_000 +0_1_0_0CA +0_1_0_065 +0_1_0_0C0 +0_1_0_09A +0_1_0_0FD +0_1_0_0EE +0_1_0_0F9 +0_1_0_0B0 +0_1_0_0B4 +0_1_1_000 +0_1_0_0AB +0_1_0_017 +0_1_0_04E +0_1_0_026 +0_1_0_051 +0_1_0_029 +0_1_0_049 +0_1_0_0DD +0_1_0_077 +0_1_0_013 +0_1_0_0B4 +0_1_0_063 +0_1_0_0CF +0_1_0_091 +0_1_0_0E7 +0_1_0_004 +0_1_0_082 +0_1_0_0F9 +0_1_0_071 +0_1_0_05F +0_1_0_0C4 +0_1_0_07B +0_1_0_052 +0_1_0_0C7 +0_1_0_0AB +0_1_0_0A7 +0_1_0_06B +0_1_0_0E9 +0_1_0_046 +0_1_0_0DC +0_1_0_03F +0_1_0_02B +0_1_0_074 +0_1_0_0A7 +0_1_0_0C8 +0_1_0_018 +0_1_0_026 +0_1_0_036 +0_1_0_04D +0_1_0_0A4 +0_1_0_0BB +0_1_0_0B6 +0_1_0_020 +0_1_0_0B3 +0_1_0_0B3 +0_1_0_0A0 +0_1_0_070 +0_1_0_0A6 +0_1_1_000 +0_1_0_0A0 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 +0_1_0_000 Index: trunk/example/sim/RsDecOut.hex =================================================================== --- trunk/example/sim/RsDecOut.hex (nonexistent) +++ trunk/example/sim/RsDecOut.hex (revision 4) @@ -0,0 +1,2561 @@ +// Error Amount, Erasure Amount, DATA[7:0] +// WORD Number: 0 +000_000_000_0_000_000_0D7_0D7 +000_000_000_0_000_000_0C7_0C7 +000_000_000_0_000_000_0AD_0AD +000_000_000_0_000_000_086_086 +000_000_000_0_000_000_04A_04A +000_000_000_0_000_000_045_045 +000_000_000_0_000_000_0F3_0F3 +000_000_000_0_000_000_0B6_0B6 +000_000_000_0_000_000_0F3_0F3 +000_000_000_0_000_000_0DB_0DB +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_00E_00E +000_000_000_0_000_000_037_037 +000_000_000_0_000_000_070_070 +000_000_000_0_000_000_01C_01C +000_000_000_0_000_000_0BF_0BF +000_000_000_0_000_000_0D1_0D1 +000_000_000_0_000_000_0DC_0DC +000_000_000_0_000_000_066_062 +000_000_000_0_000_000_08F_08F +000_000_000_0_000_000_0BD_0BD +000_000_000_0_000_000_042_042 +000_000_000_0_000_000_0F3_0F3 +000_000_000_0_000_000_0D1_0D1 +000_000_000_0_000_000_055_055 +000_000_000_0_000_000_0A0_0A0 +000_000_000_0_000_000_0A6_0A6 +000_000_000_0_000_000_094_094 +000_000_000_0_000_000_0BB_0BB +000_000_000_0_000_000_0A4_0A4 +000_000_000_0_000_000_000_03E +000_000_000_0_000_000_01B_01B +000_000_000_0_000_000_076_076 +000_000_000_0_000_000_0C2_0C2 +000_000_000_0_000_000_035_035 +000_000_000_0_000_000_08D_08D +000_000_000_0_000_000_060_060 +000_000_000_0_000_000_083_083 +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_0EE_0EE +000_000_000_0_000_000_000_0BF +000_000_000_0_000_000_020_020 +000_000_000_0_000_000_0F2_0F2 +000_000_000_0_000_000_04E_04E +000_000_000_0_000_000_0B2_0B2 +000_000_000_0_000_000_04F_04F +000_000_000_0_000_000_000_08D +000_000_000_0_000_000_000_040 +000_000_000_0_000_000_0CF_0CF +000_000_000_0_000_000_05D_05D +000_000_000_0_000_000_076_076 +000_000_000_0_000_000_08E_08E +000_000_000_0_000_000_00A_00A +000_000_000_0_000_000_07D_07D +000_000_000_0_000_000_0E1_0E1 +000_000_000_0_000_000_02B_02B +000_000_000_0_000_000_0D8_0D8 +000_000_000_0_000_000_060_060 +000_000_000_0_000_000_000_08E +000_000_000_0_000_000_069_069 +000_000_000_0_000_000_095_095 +000_000_000_0_000_000_005_005 +000_000_000_0_000_000_04A_04A +000_000_000_0_000_000_06C_06C +000_000_000_0_000_000_023_023 +000_000_000_0_000_000_0D3_0D3 +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_0DF_0DF +000_000_000_0_000_000_0D5_0D5 +000_000_000_0_000_000_0E5_0E5 +000_000_000_0_000_000_051_051 +000_000_000_0_000_000_0E5_0E5 +000_000_000_0_000_000_000_08B +000_000_000_0_000_000_0A5_0A5 +000_000_000_0_000_000_0AA_0AA +000_000_000_0_000_000_053_053 +000_000_000_0_000_000_01E_01E +000_000_000_0_000_000_09C_09C +000_000_000_0_000_000_0F5_0F5 +000_000_000_0_000_000_01C_01C +000_000_000_0_000_000_0FE_0FE +000_000_000_0_000_000_088_088 +000_000_000_0_000_000_068_0CB +000_000_000_0_000_000_00D_00D +000_000_000_0_000_000_019_019 +000_000_000_0_000_000_000_0AF +000_000_000_0_000_000_029_029 +000_000_000_0_000_000_0BA_0BA +000_000_000_0_000_000_0FF_0FF +000_000_000_0_000_000_074_074 +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_044_044 +000_000_000_0_000_000_028_028 +000_000_000_0_000_000_000_051 +000_000_000_0_000_000_00C_00C +000_000_000_0_000_000_026_026 +000_000_000_0_000_000_022_022 +000_000_000_0_000_000_0C0_0C0 +000_000_000_0_000_000_0E4_0E4 +000_000_000_0_000_000_000_070 +000_000_000_0_000_000_012_012 +000_000_000_0_000_000_0C8_0C8 +000_000_000_0_000_000_085_085 +000_000_000_0_000_000_09F_09F +000_000_000_0_000_000_092_092 +000_000_000_0_000_000_068_068 +000_000_000_0_000_000_085_085 +000_000_000_0_000_000_042_042 +000_000_000_0_000_000_0FE_0FE +000_000_000_0_000_000_05D_05D +000_000_000_0_000_000_03A_03A +000_000_000_0_000_000_0A7_0A7 +000_000_000_0_000_000_086_086 +000_000_000_0_000_000_0E8_0E8 +000_000_000_0_000_000_072_072 +000_000_000_0_000_000_0B3_0B3 +000_000_000_0_000_000_081_081 +000_000_000_0_000_000_0D1_0D1 +000_000_000_0_000_000_064_064 +000_000_000_0_000_000_012_012 +000_000_000_0_000_000_004_004 +000_000_000_0_000_000_0AC_0AC +000_000_000_0_000_000_0E7_0E7 +000_000_000_0_000_000_091_091 +000_000_000_0_000_000_0B4_0B4 +000_000_000_0_000_000_05B_05B +000_000_000_0_000_000_0E2_0E2 +000_000_000_0_000_000_000_0C7 +000_000_000_0_000_000_0D8_0D8 +000_000_000_0_000_000_0D4_0D4 +000_000_000_0_000_000_004_004 +000_000_000_0_000_000_0FB_0FB +000_000_000_0_000_000_0B3_0B3 +000_000_000_0_000_000_025_025 +000_000_000_0_000_000_0B5_0B5 +000_000_000_0_000_000_042_042 +000_000_000_0_000_000_010_010 +000_000_000_0_000_000_0B5_0B5 +000_000_000_0_000_000_04C_04C +000_000_000_0_000_000_0E8_0E8 +000_000_000_0_000_000_01E_01E +000_000_000_0_000_000_0CC_0CC +000_000_000_0_000_000_082_082 +000_000_000_0_000_000_011_011 +000_000_000_0_000_000_07E_07E +000_000_000_0_000_000_055_055 +000_000_000_0_000_000_026_026 +000_000_000_0_000_000_000_0A0 +000_000_000_0_000_000_09B_09B +000_000_000_0_000_000_0E3_0E3 +000_000_000_0_000_000_013_013 +000_000_000_0_000_000_058_058 +000_000_000_0_000_000_03A_03A +000_000_000_0_000_000_0F3_0F3 +000_000_000_0_000_000_060_060 +000_000_000_0_000_000_041_041 +000_000_000_0_000_000_052_052 +000_000_000_0_000_000_071_071 +000_000_000_0_000_000_0D6_0D6 +000_000_000_0_000_000_04E_04E +000_000_000_0_000_000_01D_01D +000_000_000_0_000_000_07D_07D +000_000_000_0_000_000_0A7_0A7 +000_000_000_0_000_000_03C_03C +000_000_000_0_000_000_06F_06F +000_000_000_0_000_000_06E_06E +000_000_000_0_000_000_05C_05C +000_000_000_0_000_000_0BD_0BD +000_000_000_0_000_000_047_047 +000_000_000_0_000_000_017_017 +000_000_000_0_000_000_010_010 +000_000_000_0_000_000_0D6_0D6 +000_000_000_0_000_000_0A3_0A3 +000_000_000_0_000_000_04A_04A +000_000_000_0_000_000_0DC_0DC +000_000_000_0_000_000_086_086 +000_000_000_0_000_000_099_099 +000_000_000_0_000_000_09B_09B +000_000_000_0_000_000_092_092 +000_000_000_0_000_000_0A8_0A8 +000_000_000_0_000_000_0A4_0A4 +000_000_000_0_000_000_066_066 +000_000_000_0_000_000_0AE_0AE +000_000_000_0_000_000_01A_01A +000_000_000_0_000_000_03C_03C +000_000_000_0_000_000_014_014 +000_000_000_0_000_000_089_089 +000_000_000_0_000_000_01F_01F +000_000_000_0_000_000_0A9_0A9 +000_000_000_0_000_000_000_099 +000_000_000_0_000_000_0D0_0D0 +000_000_000_0_000_000_002_002 +000_000_000_0_000_000_018_018 +000_000_000_0_000_000_041_041 +000_000_000_0_000_000_035_035 +000_000_000_0_000_000_0FD_0FD +000_000_000_0_000_000_0EF_0EF +000_000_000_0_000_000_000_0AD +000_000_000_0_000_000_064_064 +000_000_000_0_000_000_058_058 +000_000_000_0_000_000_05E_05E +000_000_000_0_000_000_018_018 +000_000_000_0_000_000_039_039 +000_000_000_0_000_000_0D5_0D5 +000_000_000_0_000_000_036_036 +000_000_000_0_000_000_0E0_0E0 +000_000_000_0_000_000_030_030 +000_000_000_0_000_000_04C_04C +000_000_000_0_000_000_0FF_0FF +000_000_000_0_000_000_041_041 +000_000_000_0_000_000_01D_01D +000_000_000_0_000_000_093_093 +000_000_000_0_000_000_045_045 +000_000_000_0_000_000_063_063 +000_000_000_0_000_000_000_01D +000_000_000_0_000_000_0A0_0A0 +000_000_000_0_000_000_032_032 +000_000_000_0_000_000_097_097 +000_000_000_0_000_000_0CC_0CC +000_000_000_0_000_000_0F2_0F2 +000_000_000_0_000_000_062_062 +000_000_000_0_000_000_0DD_0DD +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_02D_02D +000_000_000_0_000_000_0F2_0F2 +000_000_000_0_000_000_0AB_0AB +000_000_000_0_000_000_016_016 +000_000_000_0_000_000_004_004 +000_000_000_0_000_000_0DA_0DA +000_000_000_0_000_000_0E9_0E9 +000_000_000_0_000_000_0B4_0B4 +000_000_000_0_000_000_05B_05B +000_000_000_0_000_000_025_025 +000_000_000_0_000_000_006_006 +000_000_000_0_000_000_0C2_0C2 +000_000_000_0_000_000_003_003 +000_000_000_0_000_000_0F3_0F3 +000_000_000_0_000_000_058_058 +000_000_000_0_000_000_070_070 +000_000_000_0_000_000_0B8_0B8 +000_000_000_0_000_000_091_091 +000_000_000_0_000_000_09A_09A +000_000_000_0_000_000_0F4_0F4 +000_000_000_0_000_000_03A_03A +000_000_000_0_000_000_0B5_0B5 +000_000_000_0_000_000_0A4_0A4 +000_000_000_0_000_000_001_001 +000_000_000_0_000_000_061_061 +000_000_000_0_000_000_045_045 +000_000_000_0_000_000_01D_01D +000_000_000_0_000_000_079_079 +000_000_000_0_000_000_0AF_0AF +000_000_000_0_000_000_032_032 +000_000_000_0_000_000_009_009 +// WORD Number: 1 +016_002_00E_0_002_00E_085_085 +016_002_00E_0_002_00E_091_091 +016_002_00E_0_002_00E_002_002 +016_002_00E_0_002_00E_0DC_0DC +016_002_00E_0_002_00E_0FD_0FD +016_002_00E_0_002_00E_003_003 +016_002_00E_0_002_00E_060_060 +016_002_00E_0_002_00E_0E5_0E5 +016_002_00E_0_002_00E_0B5_0B5 +016_002_00E_0_002_00E_09E_09E +016_002_00E_0_002_00E_08A_08A +016_002_00E_0_002_00E_0BE_0BE +016_002_00E_0_002_00E_000_06D +016_002_00E_0_002_00E_000_0F1 +016_002_00E_0_002_00E_05E_05E +016_002_00E_0_002_00E_016_016 +016_002_00E_0_002_00E_021_021 +016_002_00E_0_002_00E_0D9_0D9 +016_002_00E_0_002_00E_0DB_0DB +016_002_00E_0_002_00E_046_046 +016_002_00E_0_002_00E_0DE_0DE +016_002_00E_0_002_00E_000_0FF +016_002_00E_0_002_00E_091_091 +016_002_00E_0_002_00E_0EC_0EC +016_002_00E_0_002_00E_0D5_0D5 +016_002_00E_0_002_00E_0A1_0A1 +016_002_00E_0_002_00E_000_056 +016_002_00E_0_002_00E_0D5_0D5 +016_002_00E_0_002_00E_0AE_0AE +016_002_00E_0_002_00E_096_096 +016_002_00E_0_002_00E_03B_03B +016_002_00E_0_002_00E_021_021 +016_002_00E_0_002_00E_01E_01E +016_002_00E_0_002_00E_08C_08C +016_002_00E_0_002_00E_0BF_0BF +016_002_00E_0_002_00E_0A1_0A1 +016_002_00E_0_002_00E_0BC_0BC +016_002_00E_0_002_00E_095_095 +016_002_00E_0_002_00E_042_042 +016_002_00E_0_002_00E_084_084 +016_002_00E_0_002_00E_010_010 +016_002_00E_0_002_00E_0E2_0E2 +016_002_00E_0_002_00E_0BC_0BC +016_002_00E_0_002_00E_033_033 +016_002_00E_0_002_00E_0ED_0ED +016_002_00E_0_002_00E_0CD_0CD +016_002_00E_0_002_00E_0B4_0AE +016_002_00E_0_002_00E_079_079 +016_002_00E_0_002_00E_001_001 +016_002_00E_0_002_00E_01D_01D +016_002_00E_0_002_00E_059_059 +016_002_00E_0_002_00E_0E7_0E7 +016_002_00E_0_002_00E_0AB_0AB +016_002_00E_0_002_00E_086_086 +016_002_00E_0_002_00E_02F_02F +016_002_00E_0_002_00E_077_077 +016_002_00E_0_002_00E_00C_00C +016_002_00E_0_002_00E_070_070 +016_002_00E_0_002_00E_087_087 +016_002_00E_0_002_00E_06F_06F +016_002_00E_0_002_00E_061_061 +016_002_00E_0_002_00E_0FA_0FA +016_002_00E_0_002_00E_094_094 +016_002_00E_0_002_00E_088_088 +016_002_00E_0_002_00E_090_090 +016_002_00E_0_002_00E_03D_03D +016_002_00E_0_002_00E_098_098 +016_002_00E_0_002_00E_050_050 +016_002_00E_0_002_00E_000_000 +016_002_00E_0_002_00E_0D5_0D5 +016_002_00E_0_002_00E_055_055 +016_002_00E_0_002_00E_0CD_0CD +016_002_00E_0_002_00E_0AE_0AE +016_002_00E_0_002_00E_09E_09E +016_002_00E_0_002_00E_0C4_0C4 +016_002_00E_0_002_00E_063_063 +016_002_00E_0_002_00E_07E_07E +016_002_00E_0_002_00E_0BB_0BB +016_002_00E_0_002_00E_00A_00A +016_002_00E_0_002_00E_0F7_0F7 +016_002_00E_0_002_00E_0CF_0CF +016_002_00E_0_002_00E_0DD_0DD +016_002_00E_0_002_00E_0A8_0A8 +016_002_00E_0_002_00E_055_055 +016_002_00E_0_002_00E_000_051 +016_002_00E_0_002_00E_0C1_0C1 +016_002_00E_0_002_00E_0F2_0F2 +016_002_00E_0_002_00E_0CF_0CF +016_002_00E_0_002_00E_01B_01B +016_002_00E_0_002_00E_0FB_0FB +016_002_00E_0_002_00E_0C2_0C2 +016_002_00E_0_002_00E_027_027 +016_002_00E_0_002_00E_0F8_0F8 +016_002_00E_0_002_00E_0F3_0F3 +016_002_00E_0_002_00E_06D_06D +016_002_00E_0_002_00E_0B0_0B0 +016_002_00E_0_002_00E_002_002 +016_002_00E_0_002_00E_02D_02D +016_002_00E_0_002_00E_000_0F6 +016_002_00E_0_002_00E_0AF_0AF +016_002_00E_0_002_00E_073_073 +016_002_00E_0_002_00E_0CD_0CD +016_002_00E_0_002_00E_082_082 +016_002_00E_0_002_00E_007_007 +016_002_00E_0_002_00E_0B7_0B7 +016_002_00E_0_002_00E_05A_05A +016_002_00E_0_002_00E_00C_00C +016_002_00E_0_002_00E_016_016 +016_002_00E_0_002_00E_0C6_0C6 +016_002_00E_0_002_00E_0C2_0C2 +016_002_00E_0_002_00E_05A_05A +016_002_00E_0_002_00E_0DA_0DA +016_002_00E_0_002_00E_0B0_0B0 +016_002_00E_0_002_00E_09E_09E +016_002_00E_0_002_00E_030_030 +016_002_00E_0_002_00E_058_058 +016_002_00E_0_002_00E_079_079 +016_002_00E_0_002_00E_0B8_0B8 +016_002_00E_0_002_00E_0C3_0C3 +016_002_00E_0_002_00E_000_03E +016_002_00E_0_002_00E_028_028 +016_002_00E_0_002_00E_0CA_0CA +016_002_00E_0_002_00E_070_070 +016_002_00E_0_002_00E_0C7_0C7 +016_002_00E_0_002_00E_01B_01B +016_002_00E_0_002_00E_089_089 +016_002_00E_0_002_00E_0AE_0AE +016_002_00E_0_002_00E_0DF_0DF +016_002_00E_0_002_00E_09D_09D +016_002_00E_0_002_00E_0E2_0E2 +016_002_00E_0_002_00E_042_042 +016_002_00E_0_002_00E_088_088 +016_002_00E_0_002_00E_0BB_0BB +016_002_00E_0_002_00E_084_084 +016_002_00E_0_002_00E_0B2_0B2 +016_002_00E_0_002_00E_07C_07C +016_002_00E_0_002_00E_053_053 +016_002_00E_0_002_00E_09E_09E +016_002_00E_0_002_00E_0FB_0FB +016_002_00E_0_002_00E_013_013 +016_002_00E_0_002_00E_06D_06D +016_002_00E_0_002_00E_0EA_0EA +016_002_00E_0_002_00E_086_086 +016_002_00E_0_002_00E_068_068 +016_002_00E_0_002_00E_0CE_0CE +016_002_00E_0_002_00E_0EA_0EA +016_002_00E_0_002_00E_059_059 +016_002_00E_0_002_00E_0B7_0B7 +016_002_00E_0_002_00E_0CB_0CB +016_002_00E_0_002_00E_072_072 +016_002_00E_0_002_00E_08B_08B +016_002_00E_0_002_00E_00A_00A +016_002_00E_0_002_00E_05C_05C +016_002_00E_0_002_00E_066_066 +016_002_00E_0_002_00E_0FA_0FA +016_002_00E_0_002_00E_015_015 +016_002_00E_0_002_00E_071_071 +016_002_00E_0_002_00E_0C5_0C5 +016_002_00E_0_002_00E_040_040 +016_002_00E_0_002_00E_05E_05E +016_002_00E_0_002_00E_089_089 +016_002_00E_0_002_00E_0E6_0E6 +016_002_00E_0_002_00E_0E2_0E2 +016_002_00E_0_002_00E_0A1_0A1 +016_002_00E_0_002_00E_080_080 +016_002_00E_0_002_00E_002_002 +016_002_00E_0_002_00E_0CB_0CB +016_002_00E_0_002_00E_072_072 +016_002_00E_0_002_00E_0A8_0A8 +016_002_00E_0_002_00E_0F3_0F3 +016_002_00E_0_002_00E_0F9_0F9 +016_002_00E_0_002_00E_024_024 +016_002_00E_0_002_00E_01C_01C +016_002_00E_0_002_00E_03B_03B +016_002_00E_0_002_00E_077_077 +016_002_00E_0_002_00E_000_0EA +016_002_00E_0_002_00E_051_051 +016_002_00E_0_002_00E_048_048 +016_002_00E_0_002_00E_08B_08B +016_002_00E_0_002_00E_03C_03C +016_002_00E_0_002_00E_0EE_0EE +016_002_00E_0_002_00E_0F7_0F7 +016_002_00E_0_002_00E_030_030 +016_002_00E_0_002_00E_07C_07C +016_002_00E_0_002_00E_0DE_0DE +016_002_00E_0_002_00E_056_056 +016_002_00E_0_002_00E_0C6_0C6 +016_002_00E_0_002_00E_0DA_0DA +016_002_00E_0_002_00E_0A3_0A3 +016_002_00E_0_002_00E_0AE_0AE +016_002_00E_0_002_00E_009_009 +016_002_00E_0_002_00E_075_075 +016_002_00E_0_002_00E_0ED_0ED +016_002_00E_0_002_00E_000_0C1 +016_002_00E_0_002_00E_040_040 +016_002_00E_0_002_00E_0C2_0C2 +016_002_00E_0_002_00E_06B_06B +016_002_00E_0_002_00E_050_050 +016_002_00E_0_002_00E_0B6_0B6 +016_002_00E_0_002_00E_032_032 +016_002_00E_0_002_00E_0E1_0E1 +016_002_00E_0_002_00E_0E0_0E0 +016_002_00E_0_002_00E_06E_06E +016_002_00E_0_002_00E_00F_00F +016_002_00E_0_002_00E_07B_07B +016_002_00E_0_002_00E_0BE_0BE +016_002_00E_0_002_00E_013_013 +016_002_00E_0_002_00E_0A7_0A7 +016_002_00E_0_002_00E_061_061 +016_002_00E_0_002_00E_041_041 +016_002_00E_0_002_00E_02E_02E +016_002_00E_0_002_00E_0AD_0AD +016_002_00E_0_002_00E_08B_08B +016_002_00E_0_002_00E_04F_04F +016_002_00E_0_002_00E_09C_09C +016_002_00E_0_002_00E_0DC_0DC +016_002_00E_0_002_00E_0D7_0D7 +016_002_00E_0_002_00E_022_022 +016_002_00E_0_002_00E_03E_03E +016_002_00E_0_002_00E_0DD_0DD +016_002_00E_0_002_00E_058_058 +016_002_00E_0_002_00E_04C_04C +016_002_00E_0_002_00E_0F2_0F2 +016_002_00E_0_002_00E_06B_06B +016_002_00E_0_002_00E_0F1_0F1 +016_002_00E_0_002_00E_0F9_0F9 +016_002_00E_0_002_00E_0C2_0C2 +016_002_00E_0_002_00E_000_0B5 +016_002_00E_0_002_00E_023_023 +016_002_00E_0_002_00E_075_075 +016_002_00E_0_002_00E_05C_05C +016_002_00E_0_002_00E_004_004 +016_002_00E_0_002_00E_024_024 +016_002_00E_0_002_00E_0DC_0DC +016_002_00E_0_002_00E_073_073 +016_002_00E_0_002_00E_045_045 +016_002_00E_0_002_00E_0E6_0E6 +016_002_00E_0_002_00E_0E2_0E2 +016_002_00E_0_002_00E_0A7_0A7 +016_002_00E_0_002_00E_0AD_0AD +016_002_00E_0_002_00E_038_038 +016_002_00E_0_002_00E_0B1_0B1 +016_002_00E_0_002_00E_0D5_0D5 +016_002_00E_0_002_00E_02B_02B +016_002_00E_0_002_00E_075_075 +016_002_00E_0_002_00E_091_091 +016_002_00E_0_002_00E_082_082 +016_002_00E_0_002_00E_03A_03A +016_002_00E_0_002_00E_042_042 +016_002_00E_0_002_00E_084_084 +016_002_00E_0_002_00E_03B_03B +016_002_00E_0_002_00E_059_059 +016_002_00E_0_002_00E_030_030 +016_002_00E_0_002_00E_02A_02A +016_002_00E_0_002_00E_077_077 +// WORD Number: 2 +016_001_00A_0_001_00A_071_071 +016_001_00A_0_001_00A_06F_06F +016_001_00A_0_001_00A_005_005 +016_001_00A_0_001_00A_07E_07E +016_001_00A_0_001_00A_098_098 +016_001_00A_0_001_00A_02E_02E +016_001_00A_0_001_00A_071_071 +016_001_00A_0_001_00A_088_088 +016_001_00A_0_001_00A_0CF_0CF +016_001_00A_0_001_00A_0C3_0C3 +016_001_00A_0_001_00A_03D_03D +016_001_00A_0_001_00A_0C3_0C3 +016_001_00A_0_001_00A_082_082 +016_001_00A_0_001_00A_0BF_0BF +016_001_00A_0_001_00A_047_047 +016_001_00A_0_001_00A_0E4_0E4 +016_001_00A_0_001_00A_09F_09F +016_001_00A_0_001_00A_027_027 +016_001_00A_0_001_00A_014_014 +016_001_00A_0_001_00A_0AF_0AF +016_001_00A_0_001_00A_0ED_0ED +016_001_00A_0_001_00A_076_076 +016_001_00A_0_001_00A_0C2_0C2 +016_001_00A_0_001_00A_017_017 +016_001_00A_0_001_00A_09E_09E +016_001_00A_0_001_00A_0E2_0E2 +016_001_00A_0_001_00A_03D_03D +016_001_00A_0_001_00A_0A7_0A7 +016_001_00A_0_001_00A_027_027 +016_001_00A_0_001_00A_0E0_0E0 +016_001_00A_0_001_00A_0B6_0B6 +016_001_00A_0_001_00A_020_020 +016_001_00A_0_001_00A_04F_04F +016_001_00A_0_001_00A_0EA_0EA +016_001_00A_0_001_00A_051_051 +016_001_00A_0_001_00A_064_064 +016_001_00A_0_001_00A_086_086 +016_001_00A_0_001_00A_080_080 +016_001_00A_0_001_00A_01E_01E +016_001_00A_0_001_00A_092_092 +016_001_00A_0_001_00A_079_079 +016_001_00A_0_001_00A_06D_06D +016_001_00A_0_001_00A_04B_04B +016_001_00A_0_001_00A_073_073 +016_001_00A_0_001_00A_0E3_0E3 +016_001_00A_0_001_00A_04B_04B +016_001_00A_0_001_00A_098_098 +016_001_00A_0_001_00A_015_015 +016_001_00A_0_001_00A_0A6_0A6 +016_001_00A_0_001_00A_049_049 +016_001_00A_0_001_00A_00A_00A +016_001_00A_0_001_00A_0B5_0B5 +016_001_00A_0_001_00A_01A_01A +016_001_00A_0_001_00A_02C_02C +016_001_00A_0_001_00A_0E4_0E4 +016_001_00A_0_001_00A_0E2_0E2 +016_001_00A_0_001_00A_0A5_0A5 +016_001_00A_0_001_00A_094_094 +016_001_00A_0_001_00A_0D3_0D3 +016_001_00A_0_001_00A_0E0_0E0 +016_001_00A_0_001_00A_08C_08C +016_001_00A_0_001_00A_081_081 +016_001_00A_0_001_00A_069_069 +016_001_00A_0_001_00A_04B_04B +016_001_00A_0_001_00A_008_008 +016_001_00A_0_001_00A_015_015 +016_001_00A_0_001_00A_0CC_0CC +016_001_00A_0_001_00A_0FC_0FC +016_001_00A_0_001_00A_09D_09D +016_001_00A_0_001_00A_09C_09C +016_001_00A_0_001_00A_0B0_0B0 +016_001_00A_0_001_00A_031_031 +016_001_00A_0_001_00A_0A7_0A7 +016_001_00A_0_001_00A_0C9_0C9 +016_001_00A_0_001_00A_082_082 +016_001_00A_0_001_00A_0E7_0E7 +016_001_00A_0_001_00A_036_036 +016_001_00A_0_001_00A_042_042 +016_001_00A_0_001_00A_0E6_0E6 +016_001_00A_0_001_00A_08B_08B +016_001_00A_0_001_00A_01B_01B +016_001_00A_0_001_00A_060_060 +016_001_00A_0_001_00A_064_064 +016_001_00A_0_001_00A_0D2_0D2 +016_001_00A_0_001_00A_043_043 +016_001_00A_0_001_00A_02F_02F +016_001_00A_0_001_00A_05E_05E +016_001_00A_0_001_00A_0E6_0E6 +016_001_00A_0_001_00A_044_044 +016_001_00A_0_001_00A_0BD_0BD +016_001_00A_0_001_00A_046_046 +016_001_00A_0_001_00A_0C2_0C2 +016_001_00A_0_001_00A_036_036 +016_001_00A_0_001_00A_000_091 +016_001_00A_0_001_00A_00E_00E +016_001_00A_0_001_00A_0DF_0DF +016_001_00A_0_001_00A_0C4_0C4 +016_001_00A_0_001_00A_079_079 +016_001_00A_0_001_00A_0DF_0DF +016_001_00A_0_001_00A_010_010 +016_001_00A_0_001_00A_082_082 +016_001_00A_0_001_00A_000_089 +016_001_00A_0_001_00A_00D_00D +016_001_00A_0_001_00A_0AA_0AA +016_001_00A_0_001_00A_082_082 +016_001_00A_0_001_00A_060_060 +016_001_00A_0_001_00A_04B_04B +016_001_00A_0_001_00A_0E9_0E9 +016_001_00A_0_001_00A_022_022 +016_001_00A_0_001_00A_0AD_0AD +016_001_00A_0_001_00A_01B_01B +016_001_00A_0_001_00A_08F_08F +016_001_00A_0_001_00A_027_027 +016_001_00A_0_001_00A_0F2_0F2 +016_001_00A_0_001_00A_089_089 +016_001_00A_0_001_00A_0CE_0CE +016_001_00A_0_001_00A_010_010 +016_001_00A_0_001_00A_088_088 +016_001_00A_0_001_00A_019_019 +016_001_00A_0_001_00A_068_068 +016_001_00A_0_001_00A_0A4_0A4 +016_001_00A_0_001_00A_0E4_0E4 +016_001_00A_0_001_00A_0FE_0FE +016_001_00A_0_001_00A_015_015 +016_001_00A_0_001_00A_0CE_0CE +016_001_00A_0_001_00A_018_018 +016_001_00A_0_001_00A_08C_08C +016_001_00A_0_001_00A_025_025 +016_001_00A_0_001_00A_0AA_0AA +016_001_00A_0_001_00A_09C_09C +016_001_00A_0_001_00A_000_0F0 +016_001_00A_0_001_00A_066_066 +016_001_00A_0_001_00A_0E0_0E0 +016_001_00A_0_001_00A_04F_04F +016_001_00A_0_001_00A_01F_01F +016_001_00A_0_001_00A_048_048 +016_001_00A_0_001_00A_031_031 +016_001_00A_0_001_00A_0B9_0B9 +016_001_00A_0_001_00A_00C_00C +016_001_00A_0_001_00A_03F_03F +016_001_00A_0_001_00A_04F_04F +016_001_00A_0_001_00A_093_093 +016_001_00A_0_001_00A_01E_01E +016_001_00A_0_001_00A_069_069 +016_001_00A_0_001_00A_0F2_0F2 +016_001_00A_0_001_00A_089_089 +016_001_00A_0_001_00A_0E1_0E1 +016_001_00A_0_001_00A_071_071 +016_001_00A_0_001_00A_028_028 +016_001_00A_0_001_00A_03E_03E +016_001_00A_0_001_00A_0FC_0FC +016_001_00A_0_001_00A_0B3_0B3 +016_001_00A_0_001_00A_0EC_0EC +016_001_00A_0_001_00A_091_091 +016_001_00A_0_001_00A_063_063 +016_001_00A_0_001_00A_0A1_0A1 +016_001_00A_0_001_00A_000_0FB +016_001_00A_0_001_00A_01F_01F +016_001_00A_0_001_00A_0CD_0CD +016_001_00A_0_001_00A_065_065 +016_001_00A_0_001_00A_0E3_0E3 +016_001_00A_0_001_00A_008_008 +016_001_00A_0_001_00A_069_069 +016_001_00A_0_001_00A_000_0C8 +016_001_00A_0_001_00A_05D_05D +016_001_00A_0_001_00A_0F7_0F7 +016_001_00A_0_001_00A_0CC_0CC +016_001_00A_0_001_00A_052_052 +016_001_00A_0_001_00A_0DC_0DC +016_001_00A_0_001_00A_05C_05C +016_001_00A_0_001_00A_02E_02E +016_001_00A_0_001_00A_0B2_0B2 +016_001_00A_0_001_00A_066_066 +016_001_00A_0_001_00A_0FC_0FC +016_001_00A_0_001_00A_0D7_0D7 +016_001_00A_0_001_00A_061_061 +016_001_00A_0_001_00A_0A3_0A3 +016_001_00A_0_001_00A_039_0AC +016_001_00A_0_001_00A_0D4_0D4 +016_001_00A_0_001_00A_083_083 +016_001_00A_0_001_00A_034_034 +016_001_00A_0_001_00A_059_059 +016_001_00A_0_001_00A_0EE_0EE +016_001_00A_0_001_00A_00E_00E +016_001_00A_0_001_00A_045_045 +016_001_00A_0_001_00A_04C_04C +016_001_00A_0_001_00A_0DD_0DD +016_001_00A_0_001_00A_02D_02D +016_001_00A_0_001_00A_066_066 +016_001_00A_0_001_00A_0AC_0AC +016_001_00A_0_001_00A_0B8_0B8 +016_001_00A_0_001_00A_0E7_0E7 +016_001_00A_0_001_00A_096_096 +016_001_00A_0_001_00A_045_045 +016_001_00A_0_001_00A_0B0_0B0 +016_001_00A_0_001_00A_0FC_0FC +016_001_00A_0_001_00A_000_0A1 +016_001_00A_0_001_00A_087_087 +016_001_00A_0_001_00A_0FE_0FE +016_001_00A_0_001_00A_00F_00F +016_001_00A_0_001_00A_0AD_0AD +016_001_00A_0_001_00A_0D2_0D2 +016_001_00A_0_001_00A_01A_01A +016_001_00A_0_001_00A_00A_00A +016_001_00A_0_001_00A_00F_00F +016_001_00A_0_001_00A_0F1_0F1 +016_001_00A_0_001_00A_02E_02E +016_001_00A_0_001_00A_0BF_0BF +016_001_00A_0_001_00A_063_063 +016_001_00A_0_001_00A_0E4_0E4 +016_001_00A_0_001_00A_0CA_0CA +016_001_00A_0_001_00A_000_0CB +016_001_00A_0_001_00A_0DB_0DB +016_001_00A_0_001_00A_000_0E2 +016_001_00A_0_001_00A_0D9_0D9 +016_001_00A_0_001_00A_0C0_0C0 +016_001_00A_0_001_00A_0D7_0D7 +016_001_00A_0_001_00A_09E_09E +016_001_00A_0_001_00A_0D4_0D4 +016_001_00A_0_001_00A_083_083 +016_001_00A_0_001_00A_0B6_0B6 +016_001_00A_0_001_00A_0CA_0CA +016_001_00A_0_001_00A_035_035 +016_001_00A_0_001_00A_0F2_0F2 +016_001_00A_0_001_00A_0EC_0EC +016_001_00A_0_001_00A_0D9_0D9 +016_001_00A_0_001_00A_02F_02F +016_001_00A_0_001_00A_0CA_0CA +016_001_00A_0_001_00A_055_055 +016_001_00A_0_001_00A_00A_00A +016_001_00A_0_001_00A_09C_09C +016_001_00A_0_001_00A_0C8_0C8 +016_001_00A_0_001_00A_0CA_0CA +016_001_00A_0_001_00A_03F_03F +016_001_00A_0_001_00A_0A6_0A6 +016_001_00A_0_001_00A_075_075 +016_001_00A_0_001_00A_0CB_0CB +016_001_00A_0_001_00A_07D_07D +016_001_00A_0_001_00A_0F5_0F5 +016_001_00A_0_001_00A_03A_03A +016_001_00A_0_001_00A_05C_05C +016_001_00A_0_001_00A_043_043 +016_001_00A_0_001_00A_020_020 +016_001_00A_0_001_00A_000_053 +016_001_00A_0_001_00A_08B_08B +016_001_00A_0_001_00A_0F0_0F0 +016_001_00A_0_001_00A_048_048 +016_001_00A_0_001_00A_058_058 +016_001_00A_0_001_00A_0FD_0FD +016_001_00A_0_001_00A_0BF_0BF +016_001_00A_0_001_00A_036_036 +016_001_00A_0_001_00A_0EA_0EA +016_001_00A_0_001_00A_0E6_0E6 +016_001_00A_0_001_00A_03D_03D +016_001_00A_0_001_00A_016_016 +// WORD Number: 3 +016_001_009_0_001_009_0C3_0C3 +016_001_009_0_001_009_01C_01C +016_001_009_0_001_009_090_090 +016_001_009_0_001_009_0AA_0AA +016_001_009_0_001_009_029_029 +016_001_009_0_001_009_0B8_0B8 +016_001_009_0_001_009_094_094 +016_001_009_0_001_009_057_057 +016_001_009_0_001_009_039_039 +016_001_009_0_001_009_07F_07F +016_001_009_0_001_009_09D_09D +016_001_009_0_001_009_064_064 +016_001_009_0_001_009_0D8_0D8 +016_001_009_0_001_009_091_091 +016_001_009_0_001_009_0D9_0D9 +016_001_009_0_001_009_09B_09B +016_001_009_0_001_009_0B8_0B8 +016_001_009_0_001_009_0AB_0AB +016_001_009_0_001_009_0A2_0A2 +016_001_009_0_001_009_000_03A +016_001_009_0_001_009_029_029 +016_001_009_0_001_009_0A8_0A8 +016_001_009_0_001_009_0F6_0F6 +016_001_009_0_001_009_09B_09B +016_001_009_0_001_009_032_032 +016_001_009_0_001_009_048_048 +016_001_009_0_001_009_027_027 +016_001_009_0_001_009_014_014 +016_001_009_0_001_009_0E0_0E0 +016_001_009_0_001_009_031_031 +016_001_009_0_001_009_0D3_0D3 +016_001_009_0_001_009_01D_01D +016_001_009_0_001_009_0DE_0DE +016_001_009_0_001_009_033_033 +016_001_009_0_001_009_017_017 +016_001_009_0_001_009_0B0_0B0 +016_001_009_0_001_009_046_046 +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_000_000 +016_001_009_0_001_009_0F6_0F6 +016_001_009_0_001_009_0B7_0B7 +016_001_009_0_001_009_0FC_0FC +016_001_009_0_001_009_042_042 +016_001_009_0_001_009_01F_01F +016_001_009_0_001_009_0A8_0A8 +016_001_009_0_001_009_021_021 +016_001_009_0_001_009_02D_02D +016_001_009_0_001_009_091_091 +016_001_009_0_001_009_0FB_0FB +016_001_009_0_001_009_066_066 +016_001_009_0_001_009_0DC_0DC +016_001_009_0_001_009_046_046 +016_001_009_0_001_009_0D5_0D5 +016_001_009_0_001_009_031_031 +016_001_009_0_001_009_0B0_0B0 +016_001_009_0_001_009_06F_06F +016_001_009_0_001_009_000_0AE +016_001_009_0_001_009_0EA_0EA +016_001_009_0_001_009_0FD_0FD +016_001_009_0_001_009_05E_05E +016_001_009_0_001_009_0A4_0A4 +016_001_009_0_001_009_003_003 +016_001_009_0_001_009_002_002 +016_001_009_0_001_009_000_0A2 +016_001_009_0_001_009_015_015 +016_001_009_0_001_009_035_035 +016_001_009_0_001_009_01F_01F +016_001_009_0_001_009_074_074 +016_001_009_0_001_009_06C_06C +016_001_009_0_001_009_00C_00C +016_001_009_0_001_009_042_042 +016_001_009_0_001_009_052_052 +016_001_009_0_001_009_03B_03B +016_001_009_0_001_009_0A5_0A5 +016_001_009_0_001_009_0A3_0A3 +016_001_009_0_001_009_0E9_0E9 +016_001_009_0_001_009_08B_08B +016_001_009_0_001_009_0B7_0B7 +016_001_009_0_001_009_0B1_0B1 +016_001_009_0_001_009_038_038 +016_001_009_0_001_009_070_070 +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_04B_04B +016_001_009_0_001_009_0F3_0F3 +016_001_009_0_001_009_0E0_0E0 +016_001_009_0_001_009_0E1_0E1 +016_001_009_0_001_009_034_034 +016_001_009_0_001_009_025_025 +016_001_009_0_001_009_0C4_0C4 +016_001_009_0_001_009_0FD_0FD +016_001_009_0_001_009_0C1_0C1 +016_001_009_0_001_009_01A_01A +016_001_009_0_001_009_000_050 +016_001_009_0_001_009_05E_05E +016_001_009_0_001_009_0D5_0D5 +016_001_009_0_001_009_07C_07C +016_001_009_0_001_009_090_090 +016_001_009_0_001_009_0A9_0A9 +016_001_009_0_001_009_00F_00F +016_001_009_0_001_009_0BC_0BC +016_001_009_0_001_009_044_044 +016_001_009_0_001_009_072_072 +016_001_009_0_001_009_042_042 +016_001_009_0_001_009_0B3_0B3 +016_001_009_0_001_009_0EE_0EE +016_001_009_0_001_009_003_003 +016_001_009_0_001_009_026_026 +016_001_009_0_001_009_08A_08A +016_001_009_0_001_009_029_029 +016_001_009_0_001_009_059_059 +016_001_009_0_001_009_04D_04D +016_001_009_0_001_009_0D7_0D7 +016_001_009_0_001_009_03C_03C +016_001_009_0_001_009_070_070 +016_001_009_0_001_009_058_058 +016_001_009_0_001_009_008_008 +016_001_009_0_001_009_0EF_0EF +016_001_009_0_001_009_0C1_0C1 +016_001_009_0_001_009_06A_06A +016_001_009_0_001_009_005_005 +016_001_009_0_001_009_09E_09E +016_001_009_0_001_009_008_008 +016_001_009_0_001_009_000_0DD +016_001_009_0_001_009_011_011 +016_001_009_0_001_009_08B_08B +016_001_009_0_001_009_04A_04A +016_001_009_0_001_009_034_034 +016_001_009_0_001_009_0F1_0F1 +016_001_009_0_001_009_078_078 +016_001_009_0_001_009_017_017 +016_001_009_0_001_009_051_051 +016_001_009_0_001_009_051_051 +016_001_009_0_001_009_076_076 +016_001_009_0_001_009_00D_00D +016_001_009_0_001_009_0E9_0E9 +016_001_009_0_001_009_063_063 +016_001_009_0_001_009_0F8_0F8 +016_001_009_0_001_009_09D_09D +016_001_009_0_001_009_034_034 +016_001_009_0_001_009_0C9_0C9 +016_001_009_0_001_009_02B_02B +016_001_009_0_001_009_012_012 +016_001_009_0_001_009_0E9_0E9 +016_001_009_0_001_009_0B5_0B5 +016_001_009_0_001_009_08A_08A +016_001_009_0_001_009_0CE_0CE +016_001_009_0_001_009_069_069 +016_001_009_0_001_009_04F_04F +016_001_009_0_001_009_0AD_0AD +016_001_009_0_001_009_0D7_0D7 +016_001_009_0_001_009_037_03A +016_001_009_0_001_009_057_057 +016_001_009_0_001_009_061_061 +016_001_009_0_001_009_093_093 +016_001_009_0_001_009_0B8_0B8 +016_001_009_0_001_009_00B_00B +016_001_009_0_001_009_0FE_0FE +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_007_007 +016_001_009_0_001_009_04B_04B +016_001_009_0_001_009_0F5_0F5 +016_001_009_0_001_009_007_007 +016_001_009_0_001_009_04C_04C +016_001_009_0_001_009_0FB_0FB +016_001_009_0_001_009_0A9_0A9 +016_001_009_0_001_009_000_0E2 +016_001_009_0_001_009_01D_01D +016_001_009_0_001_009_0A9_0A9 +016_001_009_0_001_009_080_080 +016_001_009_0_001_009_0FB_0FB +016_001_009_0_001_009_036_036 +016_001_009_0_001_009_06F_06F +016_001_009_0_001_009_039_039 +016_001_009_0_001_009_0E7_0E7 +016_001_009_0_001_009_06D_06D +016_001_009_0_001_009_01B_01B +016_001_009_0_001_009_080_080 +016_001_009_0_001_009_073_073 +016_001_009_0_001_009_0E8_0E8 +016_001_009_0_001_009_08E_08E +016_001_009_0_001_009_0BF_0BF +016_001_009_0_001_009_02D_02D +016_001_009_0_001_009_08D_08D +016_001_009_0_001_009_062_062 +016_001_009_0_001_009_038_038 +016_001_009_0_001_009_027_027 +016_001_009_0_001_009_0BA_0BA +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_051_051 +016_001_009_0_001_009_0F7_0F7 +016_001_009_0_001_009_036_036 +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_02E_02E +016_001_009_0_001_009_002_002 +016_001_009_0_001_009_068_068 +016_001_009_0_001_009_081_081 +016_001_009_0_001_009_085_085 +016_001_009_0_001_009_0FB_0FB +016_001_009_0_001_009_0C7_0C7 +016_001_009_0_001_009_0CC_0CC +016_001_009_0_001_009_0AE_0AE +016_001_009_0_001_009_0A6_0A6 +016_001_009_0_001_009_092_092 +016_001_009_0_001_009_044_044 +016_001_009_0_001_009_000_0FA +016_001_009_0_001_009_0E2_0E2 +016_001_009_0_001_009_0C1_0C1 +016_001_009_0_001_009_051_051 +016_001_009_0_001_009_046_046 +016_001_009_0_001_009_0E6_0E6 +016_001_009_0_001_009_03B_03B +016_001_009_0_001_009_08E_08E +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_098_0CB +016_001_009_0_001_009_049_049 +016_001_009_0_001_009_06F_06F +016_001_009_0_001_009_049_049 +016_001_009_0_001_009_04B_04B +016_001_009_0_001_009_04B_04B +016_001_009_0_001_009_027_027 +016_001_009_0_001_009_02B_02B +016_001_009_0_001_009_0C8_0C8 +016_001_009_0_001_009_0AA_0AA +016_001_009_0_001_009_0C9_0C9 +016_001_009_0_001_009_04C_04C +016_001_009_0_001_009_08F_08F +016_001_009_0_001_009_00D_00D +016_001_009_0_001_009_0AD_0AD +016_001_009_0_001_009_0B4_0B4 +016_001_009_0_001_009_05F_05F +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_015_015 +016_001_009_0_001_009_0AB_0AB +016_001_009_0_001_009_04B_04B +016_001_009_0_001_009_015_015 +016_001_009_0_001_009_08E_08E +016_001_009_0_001_009_082_082 +016_001_009_0_001_009_000_06E +016_001_009_0_001_009_059_059 +016_001_009_0_001_009_019_019 +016_001_009_0_001_009_046_046 +016_001_009_0_001_009_0C7_0C7 +016_001_009_0_001_009_033_033 +016_001_009_0_001_009_0FD_0FD +016_001_009_0_001_009_0B3_0B3 +016_001_009_0_001_009_020_020 +016_001_009_0_001_009_004_004 +016_001_009_0_001_009_023_023 +016_001_009_0_001_009_09A_09A +016_001_009_0_001_009_088_088 +016_001_009_0_001_009_074_074 +016_001_009_0_001_009_057_057 +016_001_009_0_001_009_0EE_0EE +016_001_009_0_001_009_045_045 +016_001_009_0_001_009_016_016 +// WORD Number: 4 +016_002_008_0_002_008_05F_05F +016_002_008_0_002_008_000_0CB +016_002_008_0_002_008_06D_06D +016_002_008_0_002_008_008_008 +016_002_008_0_002_008_01E_01E +016_002_008_0_002_008_0D9_0D9 +016_002_008_0_002_008_0A3_0A3 +016_002_008_0_002_008_083_083 +016_002_008_0_002_008_09F_09F +016_002_008_0_002_008_0C5_0C5 +016_002_008_0_002_008_0D3_0D3 +016_002_008_0_002_008_059_059 +016_002_008_0_002_008_025_025 +016_002_008_0_002_008_058_058 +016_002_008_0_002_008_0ED_0ED +016_002_008_0_002_008_0D0_0D0 +016_002_008_0_002_008_0B3_0B3 +016_002_008_0_002_008_000_015 +016_002_008_0_002_008_0BD_0BD +016_002_008_0_002_008_092_092 +016_002_008_0_002_008_018_018 +016_002_008_0_002_008_026_026 +016_002_008_0_002_008_010_010 +016_002_008_0_002_008_048_048 +016_002_008_0_002_008_029_029 +016_002_008_0_002_008_095_095 +016_002_008_0_002_008_018_018 +016_002_008_0_002_008_06B_06B +016_002_008_0_002_008_04E_04E +016_002_008_0_002_008_0BF_0BF +016_002_008_0_002_008_011_011 +016_002_008_0_002_008_057_057 +016_002_008_0_002_008_000_040 +016_002_008_0_002_008_006_006 +016_002_008_0_002_008_025_025 +016_002_008_0_002_008_0A2_0A2 +016_002_008_0_002_008_010_010 +016_002_008_0_002_008_0C7_0C7 +016_002_008_0_002_008_08D_08D +016_002_008_0_002_008_000_0AB +016_002_008_0_002_008_06C_06C +016_002_008_0_002_008_08C_08C +016_002_008_0_002_008_0FA_0FA +016_002_008_0_002_008_076_076 +016_002_008_0_002_008_01E_01E +016_002_008_0_002_008_000_082 +016_002_008_0_002_008_033_033 +016_002_008_0_002_008_0B7_0B7 +016_002_008_0_002_008_000_0D5 +016_002_008_0_002_008_02D_02D +016_002_008_0_002_008_0FF_0FF +016_002_008_0_002_008_000_02C +016_002_008_0_002_008_028_028 +016_002_008_0_002_008_05A_05A +016_002_008_0_002_008_045_045 +016_002_008_0_002_008_030_030 +016_002_008_0_002_008_0D8_0D8 +016_002_008_0_002_008_055_055 +016_002_008_0_002_008_072_072 +016_002_008_0_002_008_08E_08E +016_002_008_0_002_008_055_055 +016_002_008_0_002_008_05D_05D +016_002_008_0_002_008_01B_01B +016_002_008_0_002_008_093_093 +016_002_008_0_002_008_084_084 +016_002_008_0_002_008_055_055 +016_002_008_0_002_008_0E4_0E4 +016_002_008_0_002_008_067_067 +016_002_008_0_002_008_0C0_0C0 +016_002_008_0_002_008_0BC_0BC +016_002_008_0_002_008_0A0_0A0 +016_002_008_0_002_008_09D_09D +016_002_008_0_002_008_01F_01F +016_002_008_0_002_008_0DF_0DF +016_002_008_0_002_008_000_0B9 +016_002_008_0_002_008_008_008 +016_002_008_0_002_008_0F6_0F6 +016_002_008_0_002_008_04D_04D +016_002_008_0_002_008_0D2_0D2 +016_002_008_0_002_008_0D0_0D0 +016_002_008_0_002_008_09F_09F +016_002_008_0_002_008_08C_08C +016_002_008_0_002_008_0AC_0AC +016_002_008_0_002_008_0C6_0C6 +016_002_008_0_002_008_079_079 +016_002_008_0_002_008_00A_00A +016_002_008_0_002_008_046_046 +016_002_008_0_002_008_0F5_0F5 +016_002_008_0_002_008_031_031 +016_002_008_0_002_008_000_056 +016_002_008_0_002_008_049_049 +016_002_008_0_002_008_079_079 +016_002_008_0_002_008_040_040 +016_002_008_0_002_008_090_090 +016_002_008_0_002_008_0A2_0A2 +016_002_008_0_002_008_095_095 +016_002_008_0_002_008_0B5_0B5 +016_002_008_0_002_008_01F_01F +016_002_008_0_002_008_071_071 +016_002_008_0_002_008_0FF_0FF +016_002_008_0_002_008_035_035 +016_002_008_0_002_008_0A1_0A1 +016_002_008_0_002_008_000_022 +016_002_008_0_002_008_07E_07E +016_002_008_0_002_008_040_040 +016_002_008_0_002_008_028_028 +016_002_008_0_002_008_0D9_0D9 +016_002_008_0_002_008_000_0B7 +016_002_008_0_002_008_0B5_0B5 +016_002_008_0_002_008_0A3_0A3 +016_002_008_0_002_008_014_014 +016_002_008_0_002_008_044_044 +016_002_008_0_002_008_099_099 +016_002_008_0_002_008_09A_09A +016_002_008_0_002_008_08C_08C +016_002_008_0_002_008_007_007 +016_002_008_0_002_008_014_014 +016_002_008_0_002_008_01F_01F +016_002_008_0_002_008_05C_05C +016_002_008_0_002_008_0BE_0BE +016_002_008_0_002_008_0BC_0BC +016_002_008_0_002_008_001_001 +016_002_008_0_002_008_064_064 +016_002_008_0_002_008_0D7_0D7 +016_002_008_0_002_008_017_017 +016_002_008_0_002_008_042_042 +016_002_008_0_002_008_0F0_0F0 +016_002_008_0_002_008_085_085 +016_002_008_0_002_008_05A_05A +016_002_008_0_002_008_0CB_0CB +016_002_008_0_002_008_095_095 +016_002_008_0_002_008_013_013 +016_002_008_0_002_008_077_077 +016_002_008_0_002_008_05F_05F +016_002_008_0_002_008_05C_05C +016_002_008_0_002_008_079_079 +016_002_008_0_002_008_057_057 +016_002_008_0_002_008_0CE_0CE +016_002_008_0_002_008_023_023 +016_002_008_0_002_008_02D_02D +016_002_008_0_002_008_064_064 +016_002_008_0_002_008_06B_06B +016_002_008_0_002_008_03F_03F +016_002_008_0_002_008_03B_03B +016_002_008_0_002_008_04B_04B +016_002_008_0_002_008_0BF_0BF +016_002_008_0_002_008_066_066 +016_002_008_0_002_008_098_098 +016_002_008_0_002_008_000_000 +016_002_008_0_002_008_07F_07F +016_002_008_0_002_008_0CD_0CD +016_002_008_0_002_008_0B3_0B3 +016_002_008_0_002_008_002_002 +016_002_008_0_002_008_0BC_0BC +016_002_008_0_002_008_08D_08D +016_002_008_0_002_008_04E_04E +016_002_008_0_002_008_0E0_0E0 +016_002_008_0_002_008_05A_05A +016_002_008_0_002_008_04B_04B +016_002_008_0_002_008_08C_08C +016_002_008_0_002_008_0FC_0FC +016_002_008_0_002_008_0C3_0C3 +016_002_008_0_002_008_018_018 +016_002_008_0_002_008_04B_04B +016_002_008_0_002_008_08F_08F +016_002_008_0_002_008_0DC_0DC +016_002_008_0_002_008_096_096 +016_002_008_0_002_008_0B3_0B3 +016_002_008_0_002_008_0ED_0ED +016_002_008_0_002_008_039_039 +016_002_008_0_002_008_05C_05C +016_002_008_0_002_008_00F_00F +016_002_008_0_002_008_00B_00B +016_002_008_0_002_008_08D_08D +016_002_008_0_002_008_09C_09C +016_002_008_0_002_008_0DC_0DC +016_002_008_0_002_008_03E_03E +016_002_008_0_002_008_064_064 +016_002_008_0_002_008_003_003 +016_002_008_0_002_008_020_020 +016_002_008_0_002_008_045_045 +016_002_008_0_002_008_014_014 +016_002_008_0_002_008_0E1_0E1 +016_002_008_0_002_008_0FE_0FE +016_002_008_0_002_008_08A_08A +016_002_008_0_002_008_000_0F0 +016_002_008_0_002_008_08A_08A +016_002_008_0_002_008_086_086 +016_002_008_0_002_008_0A5_0A5 +016_002_008_0_002_008_0C0_0C0 +016_002_008_0_002_008_0FC_0FC +016_002_008_0_002_008_0D2_0D2 +016_002_008_0_002_008_022_022 +016_002_008_0_002_008_06E_06E +016_002_008_0_002_008_0C2_0C2 +016_002_008_0_002_008_04E_04E +016_002_008_0_002_008_084_084 +016_002_008_0_002_008_002_002 +016_002_008_0_002_008_018_018 +016_002_008_0_002_008_057_057 +016_002_008_0_002_008_089_089 +016_002_008_0_002_008_0D0_0D0 +016_002_008_0_002_008_04F_04F +016_002_008_0_002_008_008_008 +016_002_008_0_002_008_0B0_0B0 +016_002_008_0_002_008_0F0_0F0 +016_002_008_0_002_008_073_073 +016_002_008_0_002_008_050_050 +016_002_008_0_002_008_0F9_0F9 +016_002_008_0_002_008_0EF_0EF +016_002_008_0_002_008_02C_02C +016_002_008_0_002_008_048_048 +016_002_008_0_002_008_0EC_0EC +016_002_008_0_002_008_0C4_0C4 +016_002_008_0_002_008_0E2_0E2 +016_002_008_0_002_008_0C4_0C4 +016_002_008_0_002_008_0DC_0DC +016_002_008_0_002_008_006_006 +016_002_008_0_002_008_024_024 +016_002_008_0_002_008_029_029 +016_002_008_0_002_008_06D_06D +016_002_008_0_002_008_05C_05C +016_002_008_0_002_008_000_04B +016_002_008_0_002_008_07E_07E +016_002_008_0_002_008_054_054 +016_002_008_0_002_008_034_034 +016_002_008_0_002_008_05A_05A +016_002_008_0_002_008_0C5_0C5 +016_002_008_0_002_008_05E_05E +016_002_008_0_002_008_0B8_0B8 +016_002_008_0_002_008_029_029 +016_002_008_0_002_008_08B_08B +016_002_008_0_002_008_0B4_0B4 +016_002_008_0_002_008_060_060 +016_002_008_0_002_008_019_019 +016_002_008_0_002_008_020_020 +016_002_008_0_002_008_065_065 +016_002_008_0_002_008_0B8_0B8 +016_002_008_0_002_008_0E4_0E4 +016_002_008_0_002_008_00D_00D +016_002_008_0_002_008_0EA_0EA +016_002_008_0_002_008_0A0_0A0 +016_002_008_0_002_008_01D_01D +016_002_008_0_002_008_097_097 +016_002_008_0_002_008_097_097 +016_002_008_0_002_008_0EB_0EB +016_002_008_0_002_008_052_052 +016_002_008_0_002_008_0C7_0C7 +016_002_008_0_002_008_0D0_0D0 +016_002_008_0_002_008_0CE_0CE +016_002_008_0_002_008_01B_01B +016_002_008_0_002_008_0A3_0A3 +016_002_008_0_002_008_06A_06A +016_002_008_0_002_008_0FE_0FE +016_002_008_0_002_008_0C7_0C7 +// WORD Number: 5 +016_000_00D_0_000_00D_017_017 +016_000_00D_0_000_00D_000_077 +016_000_00D_0_000_00D_07E_07E +016_000_00D_0_000_00D_0EA_0EA +016_000_00D_0_000_00D_050_050 +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_036_036 +016_000_00D_0_000_00D_00E_00E +016_000_00D_0_000_00D_041_041 +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_0F2_0F2 +016_000_00D_0_000_00D_0D5_0D5 +016_000_00D_0_000_00D_035_035 +016_000_00D_0_000_00D_06D_06D +016_000_00D_0_000_00D_06D_06D +016_000_00D_0_000_00D_063_063 +016_000_00D_0_000_00D_0D1_0D1 +016_000_00D_0_000_00D_006_006 +016_000_00D_0_000_00D_09D_09D +016_000_00D_0_000_00D_021_021 +016_000_00D_0_000_00D_0EB_0EB +016_000_00D_0_000_00D_000_0FB +016_000_00D_0_000_00D_02E_02E +016_000_00D_0_000_00D_060_060 +016_000_00D_0_000_00D_0A0_0A0 +016_000_00D_0_000_00D_0CD_0CD +016_000_00D_0_000_00D_02E_02E +016_000_00D_0_000_00D_03F_03F +016_000_00D_0_000_00D_0A0_0A0 +016_000_00D_0_000_00D_032_032 +016_000_00D_0_000_00D_00A_00A +016_000_00D_0_000_00D_0CE_0CE +016_000_00D_0_000_00D_000_0CD +016_000_00D_0_000_00D_05C_05C +016_000_00D_0_000_00D_0B9_0B9 +016_000_00D_0_000_00D_073_073 +016_000_00D_0_000_00D_005_005 +016_000_00D_0_000_00D_000_07E +016_000_00D_0_000_00D_037_037 +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_03B_03B +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_035_035 +016_000_00D_0_000_00D_058_058 +016_000_00D_0_000_00D_0CD_0CD +016_000_00D_0_000_00D_044_044 +016_000_00D_0_000_00D_00F_00F +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_06A_06A +016_000_00D_0_000_00D_0FE_0FE +016_000_00D_0_000_00D_05A_05A +016_000_00D_0_000_00D_031_031 +016_000_00D_0_000_00D_057_057 +016_000_00D_0_000_00D_08F_08F +016_000_00D_0_000_00D_0DF_0DF +016_000_00D_0_000_00D_03A_03A +016_000_00D_0_000_00D_0B5_0B5 +016_000_00D_0_000_00D_053_053 +016_000_00D_0_000_00D_03A_03A +016_000_00D_0_000_00D_06F_06F +016_000_00D_0_000_00D_084_084 +016_000_00D_0_000_00D_0D8_0D8 +016_000_00D_0_000_00D_014_014 +016_000_00D_0_000_00D_0E3_0E3 +016_000_00D_0_000_00D_060_060 +016_000_00D_0_000_00D_0D9_0D9 +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_0B2_0B2 +016_000_00D_0_000_00D_0DE_0DE +016_000_00D_0_000_00D_000_000 +016_000_00D_0_000_00D_016_016 +016_000_00D_0_000_00D_016_016 +016_000_00D_0_000_00D_03D_03D +016_000_00D_0_000_00D_07D_07D +016_000_00D_0_000_00D_013_013 +016_000_00D_0_000_00D_004_004 +016_000_00D_0_000_00D_002_002 +016_000_00D_0_000_00D_0C7_0C7 +016_000_00D_0_000_00D_0B0_0B0 +016_000_00D_0_000_00D_0F7_0F7 +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_000_059 +016_000_00D_0_000_00D_04E_04E +016_000_00D_0_000_00D_05E_05E +016_000_00D_0_000_00D_054_054 +016_000_00D_0_000_00D_033_033 +016_000_00D_0_000_00D_0C1_0C1 +016_000_00D_0_000_00D_04B_04B +016_000_00D_0_000_00D_0FC_0FC +016_000_00D_0_000_00D_02A_02A +016_000_00D_0_000_00D_053_053 +016_000_00D_0_000_00D_06F_06F +016_000_00D_0_000_00D_042_042 +016_000_00D_0_000_00D_082_082 +016_000_00D_0_000_00D_00B_00B +016_000_00D_0_000_00D_046_046 +016_000_00D_0_000_00D_000_000 +016_000_00D_0_000_00D_0BE_0BE +016_000_00D_0_000_00D_02F_02F +016_000_00D_0_000_00D_08F_08F +016_000_00D_0_000_00D_04A_04A +016_000_00D_0_000_00D_0B7_0B7 +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_0FF_0FF +016_000_00D_0_000_00D_04E_04E +016_000_00D_0_000_00D_0EC_0EC +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_036_036 +016_000_00D_0_000_00D_07E_07E +016_000_00D_0_000_00D_019_019 +016_000_00D_0_000_00D_061_061 +016_000_00D_0_000_00D_0F2_0F2 +016_000_00D_0_000_00D_000_0F2 +016_000_00D_0_000_00D_00B_00B +016_000_00D_0_000_00D_0E9_0E9 +016_000_00D_0_000_00D_083_083 +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_0B2_0B2 +016_000_00D_0_000_00D_000_079 +016_000_00D_0_000_00D_07F_07F +016_000_00D_0_000_00D_04D_04D +016_000_00D_0_000_00D_078_078 +016_000_00D_0_000_00D_0A7_0A7 +016_000_00D_0_000_00D_0B6_0B6 +016_000_00D_0_000_00D_0A0_0A0 +016_000_00D_0_000_00D_000_0D1 +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_068_068 +016_000_00D_0_000_00D_094_094 +016_000_00D_0_000_00D_013_013 +016_000_00D_0_000_00D_0FE_0FE +016_000_00D_0_000_00D_0B6_0B6 +016_000_00D_0_000_00D_017_017 +016_000_00D_0_000_00D_089_089 +016_000_00D_0_000_00D_0E9_0E9 +016_000_00D_0_000_00D_057_057 +016_000_00D_0_000_00D_051_051 +016_000_00D_0_000_00D_0C2_0C2 +016_000_00D_0_000_00D_0BE_0BE +016_000_00D_0_000_00D_08C_08C +016_000_00D_0_000_00D_0CF_0CF +016_000_00D_0_000_00D_02F_02F +016_000_00D_0_000_00D_004_004 +016_000_00D_0_000_00D_056_056 +016_000_00D_0_000_00D_0E1_0E1 +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_02F_02F +016_000_00D_0_000_00D_0E6_0E6 +016_000_00D_0_000_00D_040_040 +016_000_00D_0_000_00D_0E0_0E0 +016_000_00D_0_000_00D_066_066 +016_000_00D_0_000_00D_055_055 +016_000_00D_0_000_00D_0F4_0F4 +016_000_00D_0_000_00D_001_001 +016_000_00D_0_000_00D_089_089 +016_000_00D_0_000_00D_095_095 +016_000_00D_0_000_00D_075_075 +016_000_00D_0_000_00D_0F9_0F9 +016_000_00D_0_000_00D_073_073 +016_000_00D_0_000_00D_0A8_0A8 +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_07C_07C +016_000_00D_0_000_00D_00F_00F +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_000_09D +016_000_00D_0_000_00D_042_042 +016_000_00D_0_000_00D_000_086 +016_000_00D_0_000_00D_00F_00F +016_000_00D_0_000_00D_0A9_0A9 +016_000_00D_0_000_00D_0AA_0AA +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_03C_03C +016_000_00D_0_000_00D_032_032 +016_000_00D_0_000_00D_021_021 +016_000_00D_0_000_00D_08B_08B +016_000_00D_0_000_00D_09D_09D +016_000_00D_0_000_00D_0AA_0AA +016_000_00D_0_000_00D_000_028 +016_000_00D_0_000_00D_06F_06F +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_00F_00F +016_000_00D_0_000_00D_036_036 +016_000_00D_0_000_00D_0BB_0BB +016_000_00D_0_000_00D_06E_06E +016_000_00D_0_000_00D_000_000 +016_000_00D_0_000_00D_0F4_0F4 +016_000_00D_0_000_00D_00B_00B +016_000_00D_0_000_00D_021_021 +016_000_00D_0_000_00D_040_040 +016_000_00D_0_000_00D_000_06C +016_000_00D_0_000_00D_03E_03E +016_000_00D_0_000_00D_0F6_0F6 +016_000_00D_0_000_00D_0B2_0B2 +016_000_00D_0_000_00D_083_083 +016_000_00D_0_000_00D_0F6_0F6 +016_000_00D_0_000_00D_01C_01C +016_000_00D_0_000_00D_09D_09D +016_000_00D_0_000_00D_0F4_0F4 +016_000_00D_0_000_00D_050_050 +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_0AE_0AE +016_000_00D_0_000_00D_044_044 +016_000_00D_0_000_00D_00C_00C +016_000_00D_0_000_00D_04A_04A +016_000_00D_0_000_00D_041_041 +016_000_00D_0_000_00D_0F9_0F9 +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_0E8_0E8 +016_000_00D_0_000_00D_0DC_0DC +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_063_063 +016_000_00D_0_000_00D_0E7_0E7 +016_000_00D_0_000_00D_0FC_0FC +016_000_00D_0_000_00D_08B_08B +016_000_00D_0_000_00D_068_068 +016_000_00D_0_000_00D_067_067 +016_000_00D_0_000_00D_015_015 +016_000_00D_0_000_00D_0BB_0BB +016_000_00D_0_000_00D_000_0A8 +016_000_00D_0_000_00D_072_072 +016_000_00D_0_000_00D_0D4_0D4 +016_000_00D_0_000_00D_01D_01D +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_0D4_0D4 +016_000_00D_0_000_00D_0A7_0A7 +016_000_00D_0_000_00D_0F8_0F8 +016_000_00D_0_000_00D_098_098 +016_000_00D_0_000_00D_02D_02D +016_000_00D_0_000_00D_042_042 +016_000_00D_0_000_00D_084_084 +016_000_00D_0_000_00D_018_018 +016_000_00D_0_000_00D_0A0_0A0 +016_000_00D_0_000_00D_01B_01B +016_000_00D_0_000_00D_0B0_0B0 +016_000_00D_0_000_00D_0DF_0DF +016_000_00D_0_000_00D_0A5_0A5 +016_000_00D_0_000_00D_062_062 +016_000_00D_0_000_00D_0BD_0BD +016_000_00D_0_000_00D_04F_04F +016_000_00D_0_000_00D_06D_06D +016_000_00D_0_000_00D_004_004 +016_000_00D_0_000_00D_0FD_0FD +016_000_00D_0_000_00D_02C_02C +016_000_00D_0_000_00D_07F_07F +016_000_00D_0_000_00D_0FC_0FC +016_000_00D_0_000_00D_0C8_0C8 +016_000_00D_0_000_00D_0B4_0B4 +016_000_00D_0_000_00D_057_057 +016_000_00D_0_000_00D_093_093 +016_000_00D_0_000_00D_0EF_0EF +// WORD Number: 6 +016_000_00D_0_000_00D_0F5_0F5 +016_000_00D_0_000_00D_09F_09F +016_000_00D_0_000_00D_092_092 +016_000_00D_0_000_00D_098_098 +016_000_00D_0_000_00D_0D5_0D5 +016_000_00D_0_000_00D_060_060 +016_000_00D_0_000_00D_069_069 +016_000_00D_0_000_00D_000_001 +016_000_00D_0_000_00D_010_010 +016_000_00D_0_000_00D_08E_08E +016_000_00D_0_000_00D_083_083 +016_000_00D_0_000_00D_007_007 +016_000_00D_0_000_00D_044_044 +016_000_00D_0_000_00D_05E_05E +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_0A3_0A3 +016_000_00D_0_000_00D_0D9_0D9 +016_000_00D_0_000_00D_0A7_0A7 +016_000_00D_0_000_00D_05B_05B +016_000_00D_0_000_00D_092_092 +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_03C_03C +016_000_00D_0_000_00D_0BE_0BE +016_000_00D_0_000_00D_04E_04E +016_000_00D_0_000_00D_04B_04B +016_000_00D_0_000_00D_078_078 +016_000_00D_0_000_00D_0F0_0F0 +016_000_00D_0_000_00D_03C_03C +016_000_00D_0_000_00D_02B_02B +016_000_00D_0_000_00D_01A_01A +016_000_00D_0_000_00D_08C_08C +016_000_00D_0_000_00D_027_027 +016_000_00D_0_000_00D_076_076 +016_000_00D_0_000_00D_053_053 +016_000_00D_0_000_00D_0CA_0CA +016_000_00D_0_000_00D_0ED_0ED +016_000_00D_0_000_00D_0E1_0E1 +016_000_00D_0_000_00D_01E_01E +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_078_078 +016_000_00D_0_000_00D_0FD_0FD +016_000_00D_0_000_00D_0D0_0D0 +016_000_00D_0_000_00D_0A4_0A4 +016_000_00D_0_000_00D_0F0_0F0 +016_000_00D_0_000_00D_0A3_0A3 +016_000_00D_0_000_00D_0F0_0F0 +016_000_00D_0_000_00D_049_049 +016_000_00D_0_000_00D_02F_02F +016_000_00D_0_000_00D_041_096 +016_000_00D_0_000_00D_048_048 +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_076_076 +016_000_00D_0_000_00D_064_064 +016_000_00D_0_000_00D_03C_03C +016_000_00D_0_000_00D_03A_03A +016_000_00D_0_000_00D_05E_05E +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_05B_05B +016_000_00D_0_000_00D_04E_04E +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_0E7_0E7 +016_000_00D_0_000_00D_034_034 +016_000_00D_0_000_00D_04C_04C +016_000_00D_0_000_00D_0B9_0B9 +016_000_00D_0_000_00D_041_041 +016_000_00D_0_000_00D_06B_06B +016_000_00D_0_000_00D_01A_01A +016_000_00D_0_000_00D_039_039 +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_00C_00C +016_000_00D_0_000_00D_063_063 +016_000_00D_0_000_00D_01C_01C +016_000_00D_0_000_00D_0A6_0A6 +016_000_00D_0_000_00D_01E_01E +016_000_00D_0_000_00D_0DF_0DF +016_000_00D_0_000_00D_0CA_0CA +016_000_00D_0_000_00D_070_070 +016_000_00D_0_000_00D_07C_07C +016_000_00D_0_000_00D_0D5_0D5 +016_000_00D_0_000_00D_000_002 +016_000_00D_0_000_00D_0C1_0C1 +016_000_00D_0_000_00D_0E0_0E0 +016_000_00D_0_000_00D_0DE_0DE +016_000_00D_0_000_00D_084_084 +016_000_00D_0_000_00D_0A3_0A3 +016_000_00D_0_000_00D_041_041 +016_000_00D_0_000_00D_0EB_0EB +016_000_00D_0_000_00D_00E_00E +016_000_00D_0_000_00D_02F_02F +016_000_00D_0_000_00D_05F_05F +016_000_00D_0_000_00D_089_089 +016_000_00D_0_000_00D_08A_08A +016_000_00D_0_000_00D_0F5_0F5 +016_000_00D_0_000_00D_09C_09C +016_000_00D_0_000_00D_064_064 +016_000_00D_0_000_00D_086_086 +016_000_00D_0_000_00D_09E_09E +016_000_00D_0_000_00D_00D_00D +016_000_00D_0_000_00D_00A_00A +016_000_00D_0_000_00D_0E4_0E4 +016_000_00D_0_000_00D_0D0_0D0 +016_000_00D_0_000_00D_0D1_0D1 +016_000_00D_0_000_00D_0F2_0F2 +016_000_00D_0_000_00D_0D3_0D3 +016_000_00D_0_000_00D_052_052 +016_000_00D_0_000_00D_0A1_0A1 +016_000_00D_0_000_00D_0BD_0BD +016_000_00D_0_000_00D_0FE_0FE +016_000_00D_0_000_00D_071_071 +016_000_00D_0_000_00D_0A9_0A9 +016_000_00D_0_000_00D_0BB_0BB +016_000_00D_0_000_00D_003_003 +016_000_00D_0_000_00D_0A2_0A2 +016_000_00D_0_000_00D_096_096 +016_000_00D_0_000_00D_0B1_0B1 +016_000_00D_0_000_00D_026_026 +016_000_00D_0_000_00D_068_068 +016_000_00D_0_000_00D_0F1_0F1 +016_000_00D_0_000_00D_0DA_0DA +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_078_078 +016_000_00D_0_000_00D_0AB_0AB +016_000_00D_0_000_00D_02B_02B +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_01C_01C +016_000_00D_0_000_00D_0F9_0F9 +016_000_00D_0_000_00D_0DB_0DB +016_000_00D_0_000_00D_075_075 +016_000_00D_0_000_00D_0D5_0D5 +016_000_00D_0_000_00D_062_062 +016_000_00D_0_000_00D_023_023 +016_000_00D_0_000_00D_056_056 +016_000_00D_0_000_00D_044_044 +016_000_00D_0_000_00D_015_015 +016_000_00D_0_000_00D_043_043 +016_000_00D_0_000_00D_000_086 +016_000_00D_0_000_00D_04A_04A +016_000_00D_0_000_00D_081_081 +016_000_00D_0_000_00D_0C5_0C5 +016_000_00D_0_000_00D_0F2_0F2 +016_000_00D_0_000_00D_06F_06F +016_000_00D_0_000_00D_000_020 +016_000_00D_0_000_00D_005_005 +016_000_00D_0_000_00D_019_019 +016_000_00D_0_000_00D_080_080 +016_000_00D_0_000_00D_093_093 +016_000_00D_0_000_00D_0F1_0F1 +016_000_00D_0_000_00D_000_0C3 +016_000_00D_0_000_00D_07C_07C +016_000_00D_0_000_00D_0F4_0F4 +016_000_00D_0_000_00D_00E_00E +016_000_00D_0_000_00D_0EF_0EF +016_000_00D_0_000_00D_0B2_0B2 +016_000_00D_0_000_00D_068_068 +016_000_00D_0_000_00D_0BC_0BC +016_000_00D_0_000_00D_00D_00D +016_000_00D_0_000_00D_023_023 +016_000_00D_0_000_00D_0F3_0F3 +016_000_00D_0_000_00D_0BA_0BA +016_000_00D_0_000_00D_06D_06D +016_000_00D_0_000_00D_02D_02D +016_000_00D_0_000_00D_091_091 +016_000_00D_0_000_00D_0EC_0EC +016_000_00D_0_000_00D_0F8_0F8 +016_000_00D_0_000_00D_06B_06B +016_000_00D_0_000_00D_082_082 +016_000_00D_0_000_00D_05C_05C +016_000_00D_0_000_00D_01E_01E +016_000_00D_0_000_00D_0D7_0D7 +016_000_00D_0_000_00D_0E5_0E5 +016_000_00D_0_000_00D_080_080 +016_000_00D_0_000_00D_00F_00F +016_000_00D_0_000_00D_031_031 +016_000_00D_0_000_00D_088_088 +016_000_00D_0_000_00D_0BB_0BB +016_000_00D_0_000_00D_02E_02E +016_000_00D_0_000_00D_0A5_0A5 +016_000_00D_0_000_00D_0FF_0FF +016_000_00D_0_000_00D_025_025 +016_000_00D_0_000_00D_0C2_0C2 +016_000_00D_0_000_00D_0A8_0A8 +016_000_00D_0_000_00D_0F3_0F3 +016_000_00D_0_000_00D_08F_08F +016_000_00D_0_000_00D_0EF_0EF +016_000_00D_0_000_00D_000_023 +016_000_00D_0_000_00D_0BD_0BD +016_000_00D_0_000_00D_0C2_0C2 +016_000_00D_0_000_00D_0E6_0E6 +016_000_00D_0_000_00D_0D3_0D3 +016_000_00D_0_000_00D_033_033 +016_000_00D_0_000_00D_008_008 +016_000_00D_0_000_00D_000_058 +016_000_00D_0_000_00D_0EF_0EF +016_000_00D_0_000_00D_0C2_0C2 +016_000_00D_0_000_00D_0EE_0EE +016_000_00D_0_000_00D_030_030 +016_000_00D_0_000_00D_00C_00C +016_000_00D_0_000_00D_0BE_0BE +016_000_00D_0_000_00D_047_047 +016_000_00D_0_000_00D_081_081 +016_000_00D_0_000_00D_03F_03F +016_000_00D_0_000_00D_0F5_0F5 +016_000_00D_0_000_00D_074_074 +016_000_00D_0_000_00D_0BD_0BD +016_000_00D_0_000_00D_081_081 +016_000_00D_0_000_00D_08A_08A +016_000_00D_0_000_00D_0E3_0E3 +016_000_00D_0_000_00D_029_029 +016_000_00D_0_000_00D_057_057 +016_000_00D_0_000_00D_001_001 +016_000_00D_0_000_00D_0D6_0D6 +016_000_00D_0_000_00D_08D_08D +016_000_00D_0_000_00D_0B2_0B2 +016_000_00D_0_000_00D_096_096 +016_000_00D_0_000_00D_066_066 +016_000_00D_0_000_00D_030_030 +016_000_00D_0_000_00D_013_013 +016_000_00D_0_000_00D_000_0D3 +016_000_00D_0_000_00D_0C7_0C7 +016_000_00D_0_000_00D_003_003 +016_000_00D_0_000_00D_0F4_0F4 +016_000_00D_0_000_00D_061_061 +016_000_00D_0_000_00D_0CD_0CD +016_000_00D_0_000_00D_01D_01D +016_000_00D_0_000_00D_064_064 +016_000_00D_0_000_00D_01F_01F +016_000_00D_0_000_00D_0AF_0AF +016_000_00D_0_000_00D_067_067 +016_000_00D_0_000_00D_0F1_0F1 +016_000_00D_0_000_00D_071_071 +016_000_00D_0_000_00D_00C_00C +016_000_00D_0_000_00D_099_099 +016_000_00D_0_000_00D_0CA_0CA +016_000_00D_0_000_00D_06E_06E +016_000_00D_0_000_00D_099_099 +016_000_00D_0_000_00D_0FC_0FC +016_000_00D_0_000_00D_0C7_0C7 +016_000_00D_0_000_00D_04E_04E +016_000_00D_0_000_00D_016_016 +016_000_00D_0_000_00D_01A_01A +016_000_00D_0_000_00D_0F8_0F8 +016_000_00D_0_000_00D_07C_07C +016_000_00D_0_000_00D_083_083 +016_000_00D_0_000_00D_0A6_0A6 +016_000_00D_0_000_00D_09C_09C +016_000_00D_0_000_00D_07C_07C +016_000_00D_0_000_00D_048_048 +016_000_00D_0_000_00D_063_063 +016_000_00D_0_000_00D_0DC_0DC +016_000_00D_0_000_00D_049_049 +016_000_00D_0_000_00D_011_011 +016_000_00D_0_000_00D_085_085 +016_000_00D_0_000_00D_0F6_0F6 +016_000_00D_0_000_00D_074_074 +016_000_00D_0_000_00D_090_090 +// WORD Number: 7 +016_001_008_0_001_008_00D_00D +016_001_008_0_001_008_09A_09A +016_001_008_0_001_008_056_056 +016_001_008_0_001_008_0AC_0AC +016_001_008_0_001_008_0F9_0F9 +016_001_008_0_001_008_05B_05B +016_001_008_0_001_008_0C8_0C8 +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_075_075 +016_001_008_0_001_008_086_086 +016_001_008_0_001_008_0A3_0A3 +016_001_008_0_001_008_00A_00A +016_001_008_0_001_008_08D_08D +016_001_008_0_001_008_00B_00B +016_001_008_0_001_008_0EC_0EC +016_001_008_0_001_008_0EB_0EB +016_001_008_0_001_008_0FE_0FE +016_001_008_0_001_008_0C5_0C5 +016_001_008_0_001_008_0E0_0E0 +016_001_008_0_001_008_0EE_0EE +016_001_008_0_001_008_098_098 +016_001_008_0_001_008_04E_04E +016_001_008_0_001_008_07D_07D +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_0E6_0E6 +016_001_008_0_001_008_000_017 +016_001_008_0_001_008_000_044 +016_001_008_0_001_008_02D_02D +016_001_008_0_001_008_011_011 +016_001_008_0_001_008_0B8_0B8 +016_001_008_0_001_008_03E_03E +016_001_008_0_001_008_0EF_0EF +016_001_008_0_001_008_002_002 +016_001_008_0_001_008_084_084 +016_001_008_0_001_008_03D_03D +016_001_008_0_001_008_005_005 +016_001_008_0_001_008_0C7_0C7 +016_001_008_0_001_008_061_061 +016_001_008_0_001_008_064_064 +016_001_008_0_001_008_097_097 +016_001_008_0_001_008_038_038 +016_001_008_0_001_008_0D7_0D7 +016_001_008_0_001_008_0E9_0E9 +016_001_008_0_001_008_094_094 +016_001_008_0_001_008_0DA_0DA +016_001_008_0_001_008_066_066 +016_001_008_0_001_008_01A_01A +016_001_008_0_001_008_0A4_0A4 +016_001_008_0_001_008_003_003 +016_001_008_0_001_008_01D_01D +016_001_008_0_001_008_09E_09E +016_001_008_0_001_008_05F_05F +016_001_008_0_001_008_000_03F +016_001_008_0_001_008_068_068 +016_001_008_0_001_008_0FE_0FE +016_001_008_0_001_008_0BC_0BC +016_001_008_0_001_008_0F3_0F3 +016_001_008_0_001_008_02A_02A +016_001_008_0_001_008_064_064 +016_001_008_0_001_008_0CC_0CC +016_001_008_0_001_008_040_040 +016_001_008_0_001_008_00B_00B +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_0A8_0A8 +016_001_008_0_001_008_02A_02A +016_001_008_0_001_008_014_014 +016_001_008_0_001_008_075_075 +016_001_008_0_001_008_0A8_0A8 +016_001_008_0_001_008_0FA_0FA +016_001_008_0_001_008_079_079 +016_001_008_0_001_008_00B_00B +016_001_008_0_001_008_0D5_0D5 +016_001_008_0_001_008_0E0_0E0 +016_001_008_0_001_008_0B5_0B5 +016_001_008_0_001_008_0C4_0C4 +016_001_008_0_001_008_0A1_0A1 +016_001_008_0_001_008_0DD_0DD +016_001_008_0_001_008_0DC_0DC +016_001_008_0_001_008_036_036 +016_001_008_0_001_008_0D6_0D6 +016_001_008_0_001_008_0E0_0E0 +016_001_008_0_001_008_02D_02D +016_001_008_0_001_008_073_073 +016_001_008_0_001_008_0CD_0CD +016_001_008_0_001_008_030_030 +016_001_008_0_001_008_0E7_0E7 +016_001_008_0_001_008_089_08E +016_001_008_0_001_008_0E0_0E0 +016_001_008_0_001_008_009_009 +016_001_008_0_001_008_05F_05F +016_001_008_0_001_008_05B_05B +016_001_008_0_001_008_021_021 +016_001_008_0_001_008_08A_08A +016_001_008_0_001_008_000_04E +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_04D_04D +016_001_008_0_001_008_0CF_0CF +016_001_008_0_001_008_06F_06F +016_001_008_0_001_008_088_088 +016_001_008_0_001_008_0FB_0FB +016_001_008_0_001_008_05A_05A +016_001_008_0_001_008_04A_04A +016_001_008_0_001_008_0C6_0C6 +016_001_008_0_001_008_019_019 +016_001_008_0_001_008_0B7_0B7 +016_001_008_0_001_008_04A_04A +016_001_008_0_001_008_0BB_0BB +016_001_008_0_001_008_099_099 +016_001_008_0_001_008_05F_05F +016_001_008_0_001_008_000_016 +016_001_008_0_001_008_046_046 +016_001_008_0_001_008_068_068 +016_001_008_0_001_008_0DE_0DE +016_001_008_0_001_008_01E_01E +016_001_008_0_001_008_000_0E6 +016_001_008_0_001_008_0A0_0A0 +016_001_008_0_001_008_031_031 +016_001_008_0_001_008_074_074 +016_001_008_0_001_008_035_035 +016_001_008_0_001_008_0FE_0FE +016_001_008_0_001_008_072_072 +016_001_008_0_001_008_0DE_0DE +016_001_008_0_001_008_0B3_0B3 +016_001_008_0_001_008_096_096 +016_001_008_0_001_008_0B7_0B7 +016_001_008_0_001_008_029_029 +016_001_008_0_001_008_0C5_0C5 +016_001_008_0_001_008_0C5_0C5 +016_001_008_0_001_008_037_037 +016_001_008_0_001_008_0C0_0C0 +016_001_008_0_001_008_0FE_0FE +016_001_008_0_001_008_068_068 +016_001_008_0_001_008_0AE_0AE +016_001_008_0_001_008_07D_07D +016_001_008_0_001_008_09C_09C +016_001_008_0_001_008_04B_04B +016_001_008_0_001_008_003_003 +016_001_008_0_001_008_0BE_0BE +016_001_008_0_001_008_056_056 +016_001_008_0_001_008_0E5_0E5 +016_001_008_0_001_008_028_028 +016_001_008_0_001_008_0BC_0BC +016_001_008_0_001_008_055_055 +016_001_008_0_001_008_042_042 +016_001_008_0_001_008_043_043 +016_001_008_0_001_008_018_018 +016_001_008_0_001_008_080_080 +016_001_008_0_001_008_040_040 +016_001_008_0_001_008_00B_00B +016_001_008_0_001_008_000_0B7 +016_001_008_0_001_008_0FC_0FC +016_001_008_0_001_008_0FE_0FE +016_001_008_0_001_008_074_074 +016_001_008_0_001_008_0D0_0D0 +016_001_008_0_001_008_0F3_0F3 +016_001_008_0_001_008_092_092 +016_001_008_0_001_008_08E_08E +016_001_008_0_001_008_043_043 +016_001_008_0_001_008_095_095 +016_001_008_0_001_008_0FA_0FA +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_02D_02D +016_001_008_0_001_008_05D_05D +016_001_008_0_001_008_055_055 +016_001_008_0_001_008_0C0_0C0 +016_001_008_0_001_008_0B9_0B9 +016_001_008_0_001_008_096_096 +016_001_008_0_001_008_054_054 +016_001_008_0_001_008_00D_00D +016_001_008_0_001_008_039_039 +016_001_008_0_001_008_01D_01D +016_001_008_0_001_008_0EB_0EB +016_001_008_0_001_008_000_000 +016_001_008_0_001_008_075_075 +016_001_008_0_001_008_068_068 +016_001_008_0_001_008_04C_04C +016_001_008_0_001_008_057_057 +016_001_008_0_001_008_042_042 +016_001_008_0_001_008_0C7_0C7 +016_001_008_0_001_008_015_015 +016_001_008_0_001_008_086_086 +016_001_008_0_001_008_057_057 +016_001_008_0_001_008_0EA_0EA +016_001_008_0_001_008_0C8_0C8 +016_001_008_0_001_008_058_058 +016_001_008_0_001_008_05D_05D +016_001_008_0_001_008_0A4_0A4 +016_001_008_0_001_008_07D_07D +016_001_008_0_001_008_0D8_0D8 +016_001_008_0_001_008_045_045 +016_001_008_0_001_008_0EE_0EE +016_001_008_0_001_008_0D3_0D3 +016_001_008_0_001_008_072_072 +016_001_008_0_001_008_0DE_0DE +016_001_008_0_001_008_02F_02F +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_056_056 +016_001_008_0_001_008_0A7_0A7 +016_001_008_0_001_008_0BB_0BB +016_001_008_0_001_008_01A_01A +016_001_008_0_001_008_01D_01D +016_001_008_0_001_008_0E2_0E2 +016_001_008_0_001_008_099_099 +016_001_008_0_001_008_014_014 +016_001_008_0_001_008_0AF_0AF +016_001_008_0_001_008_0E9_0E9 +016_001_008_0_001_008_089_089 +016_001_008_0_001_008_06E_06E +016_001_008_0_001_008_064_064 +016_001_008_0_001_008_0C5_0C5 +016_001_008_0_001_008_045_045 +016_001_008_0_001_008_088_088 +016_001_008_0_001_008_069_069 +016_001_008_0_001_008_0FD_0FD +016_001_008_0_001_008_008_008 +016_001_008_0_001_008_045_045 +016_001_008_0_001_008_066_066 +016_001_008_0_001_008_0AC_0AC +016_001_008_0_001_008_04D_04D +016_001_008_0_001_008_0BE_0BE +016_001_008_0_001_008_05D_05D +016_001_008_0_001_008_0D6_0D6 +016_001_008_0_001_008_0D9_0D9 +016_001_008_0_001_008_038_038 +016_001_008_0_001_008_0D6_0D6 +016_001_008_0_001_008_0FC_0FC +016_001_008_0_001_008_0FB_0FB +016_001_008_0_001_008_054_054 +016_001_008_0_001_008_039_039 +016_001_008_0_001_008_0EE_0EE +016_001_008_0_001_008_013_013 +016_001_008_0_001_008_086_086 +016_001_008_0_001_008_07B_07B +016_001_008_0_001_008_06F_06F +016_001_008_0_001_008_088_088 +016_001_008_0_001_008_031_031 +016_001_008_0_001_008_058_058 +016_001_008_0_001_008_0D0_0D0 +016_001_008_0_001_008_090_090 +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_0BC_0BC +016_001_008_0_001_008_018_018 +016_001_008_0_001_008_053_053 +016_001_008_0_001_008_0A7_0A7 +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_08E_08E +016_001_008_0_001_008_0E9_0E9 +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_000_010 +016_001_008_0_001_008_092_092 +016_001_008_0_001_008_0FD_0FD +016_001_008_0_001_008_098_098 +016_001_008_0_001_008_026_026 +016_001_008_0_001_008_02F_02F +016_001_008_0_001_008_061_061 +// WORD Number: 8 +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_055_055 +016_001_008_0_001_008_05C_05C +016_001_008_0_001_008_000_06E +016_001_008_0_001_008_0B2_0B2 +016_001_008_0_001_008_0A8_0A8 +016_001_008_0_001_008_0F4_0F4 +016_001_008_0_001_008_039_039 +016_001_008_0_001_008_0DD_0DD +016_001_008_0_001_008_0CB_0CB +016_001_008_0_001_008_0E2_0E2 +016_001_008_0_001_008_0A5_0A5 +016_001_008_0_001_008_033_033 +016_001_008_0_001_008_039_039 +016_001_008_0_001_008_08B_08B +016_001_008_0_001_008_018_018 +016_001_008_0_001_008_0D5_0D5 +016_001_008_0_001_008_09E_09E +016_001_008_0_001_008_0B4_0B4 +016_001_008_0_001_008_0CE_0CE +016_001_008_0_001_008_062_062 +016_001_008_0_001_008_032_032 +016_001_008_0_001_008_08C_08C +016_001_008_0_001_008_0CB_0CB +016_001_008_0_001_008_018_018 +016_001_008_0_001_008_046_046 +016_001_008_0_001_008_0ED_0ED +016_001_008_0_001_008_014_014 +016_001_008_0_001_008_03C_03C +016_001_008_0_001_008_01C_01C +016_001_008_0_001_008_0DF_0DF +016_001_008_0_001_008_01E_01E +016_001_008_0_001_008_0BC_0BC +016_001_008_0_001_008_0FC_0FC +016_001_008_0_001_008_05E_05E +016_001_008_0_001_008_087_087 +016_001_008_0_001_008_014_014 +016_001_008_0_001_008_000_084 +016_001_008_0_001_008_05D_05D +016_001_008_0_001_008_004_004 +016_001_008_0_001_008_06E_06E +016_001_008_0_001_008_040_040 +016_001_008_0_001_008_00A_00A +016_001_008_0_001_008_000_09B +016_001_008_0_001_008_00D_00D +016_001_008_0_001_008_07B_07B +016_001_008_0_001_008_054_054 +016_001_008_0_001_008_012_012 +016_001_008_0_001_008_0EB_0EB +016_001_008_0_001_008_054_054 +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_0A7_0A7 +016_001_008_0_001_008_0A1_0A1 +016_001_008_0_001_008_014_014 +016_001_008_0_001_008_006_006 +016_001_008_0_001_008_001_001 +016_001_008_0_001_008_088_088 +016_001_008_0_001_008_0BE_0BE +016_001_008_0_001_008_02B_02B +016_001_008_0_001_008_067_067 +016_001_008_0_001_008_01E_01E +016_001_008_0_001_008_0E8_0E8 +016_001_008_0_001_008_02B_02B +016_001_008_0_001_008_030_030 +016_001_008_0_001_008_0AB_0AB +016_001_008_0_001_008_0CA_0CA +016_001_008_0_001_008_02B_02B +016_001_008_0_001_008_07A_07A +016_001_008_0_001_008_024_024 +016_001_008_0_001_008_095_095 +016_001_008_0_001_008_06A_06A +016_001_008_0_001_008_01F_01F +016_001_008_0_001_008_04F_04F +016_001_008_0_001_008_006_006 +016_001_008_0_001_008_080_080 +016_001_008_0_001_008_0E5_0E5 +016_001_008_0_001_008_028_028 +016_001_008_0_001_008_03A_03A +016_001_008_0_001_008_0E4_0E4 +016_001_008_0_001_008_0F5_0F5 +016_001_008_0_001_008_084_084 +016_001_008_0_001_008_0C4_0C4 +016_001_008_0_001_008_0B1_0B1 +016_001_008_0_001_008_08F_08F +016_001_008_0_001_008_0F4_0F4 +016_001_008_0_001_008_0FD_0FD +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_0FB_0FB +016_001_008_0_001_008_0EC_0EC +016_001_008_0_001_008_09B_09B +016_001_008_0_001_008_07B_07B +016_001_008_0_001_008_0C3_0C3 +016_001_008_0_001_008_024_024 +016_001_008_0_001_008_085_085 +016_001_008_0_001_008_042_042 +016_001_008_0_001_008_01F_01F +016_001_008_0_001_008_03F_03F +016_001_008_0_001_008_0E6_0E6 +016_001_008_0_001_008_04D_04D +016_001_008_0_001_008_0B1_0B1 +016_001_008_0_001_008_0AB_0AB +016_001_008_0_001_008_080_080 +016_001_008_0_001_008_025_025 +016_001_008_0_001_008_072_072 +016_001_008_0_001_008_0C8_0C8 +016_001_008_0_001_008_044_044 +016_001_008_0_001_008_0CC_0CC +016_001_008_0_001_008_0ED_0ED +016_001_008_0_001_008_04C_04C +016_001_008_0_001_008_01F_01F +016_001_008_0_001_008_000_044 +016_001_008_0_001_008_0AB_0AB +016_001_008_0_001_008_0E6_0E6 +016_001_008_0_001_008_016_016 +016_001_008_0_001_008_050_050 +016_001_008_0_001_008_0EE_0EE +016_001_008_0_001_008_021_021 +016_001_008_0_001_008_095_095 +016_001_008_0_001_008_07F_07F +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_08C_08C +016_001_008_0_001_008_004_004 +016_001_008_0_001_008_065_065 +016_001_008_0_001_008_090_090 +016_001_008_0_001_008_018_018 +016_001_008_0_001_008_09C_09C +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_0D5_0D5 +016_001_008_0_001_008_0C1_0C1 +016_001_008_0_001_008_079_079 +016_001_008_0_001_008_04C_04C +016_001_008_0_001_008_092_092 +016_001_008_0_001_008_070_070 +016_001_008_0_001_008_0F0_0F0 +016_001_008_0_001_008_096_096 +016_001_008_0_001_008_0E6_0E6 +016_001_008_0_001_008_020_020 +016_001_008_0_001_008_022_022 +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_019_019 +016_001_008_0_001_008_000_040 +016_001_008_0_001_008_0D1_0D1 +016_001_008_0_001_008_07B_07B +016_001_008_0_001_008_01A_01A +016_001_008_0_001_008_059_059 +016_001_008_0_001_008_073_073 +016_001_008_0_001_008_010_010 +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_0F1_0F1 +016_001_008_0_001_008_085_085 +016_001_008_0_001_008_08D_08D +016_001_008_0_001_008_0DC_0DC +016_001_008_0_001_008_0AF_0AF +016_001_008_0_001_008_000_022 +016_001_008_0_001_008_072_072 +016_001_008_0_001_008_036_036 +016_001_008_0_001_008_0C0_0C0 +016_001_008_0_001_008_0D4_0D4 +016_001_008_0_001_008_0F1_0F1 +016_001_008_0_001_008_038_038 +016_001_008_0_001_008_078_078 +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_0AE_0AE +016_001_008_0_001_008_087_087 +016_001_008_0_001_008_03D_03D +016_001_008_0_001_008_08B_08B +016_001_008_0_001_008_0C4_0C4 +016_001_008_0_001_008_061_061 +016_001_008_0_001_008_0A1_0A1 +016_001_008_0_001_008_0C9_0C9 +016_001_008_0_001_008_008_008 +016_001_008_0_001_008_0D3_0D3 +016_001_008_0_001_008_0CE_0CE +016_001_008_0_001_008_0F9_0F9 +016_001_008_0_001_008_091_091 +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_027_027 +016_001_008_0_001_008_003_003 +016_001_008_0_001_008_078_078 +016_001_008_0_001_008_0B1_0B1 +016_001_008_0_001_008_02C_02C +016_001_008_0_001_008_075_075 +016_001_008_0_001_008_0DC_0DC +016_001_008_0_001_008_092_092 +016_001_008_0_001_008_09E_09E +016_001_008_0_001_008_01D_01D +016_001_008_0_001_008_029_029 +016_001_008_0_001_008_01D_01D +016_001_008_0_001_008_0E4_0E4 +016_001_008_0_001_008_0D6_0D6 +016_001_008_0_001_008_09A_09A +016_001_008_0_001_008_032_032 +016_001_008_0_001_008_0AE_0AE +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_0FD_0FD +016_001_008_0_001_008_0F7_0F7 +016_001_008_0_001_008_0D8_0D8 +016_001_008_0_001_008_0F9_0F9 +016_001_008_0_001_008_0B7_0B7 +016_001_008_0_001_008_0CC_0CC +016_001_008_0_001_008_000_091 +016_001_008_0_001_008_061_061 +016_001_008_0_001_008_007_007 +016_001_008_0_001_008_082_082 +016_001_008_0_001_008_00C_0BC +016_001_008_0_001_008_03F_03F +016_001_008_0_001_008_08F_08F +016_001_008_0_001_008_0C7_0C7 +016_001_008_0_001_008_096_096 +016_001_008_0_001_008_0ED_0ED +016_001_008_0_001_008_010_010 +016_001_008_0_001_008_0E5_0E5 +016_001_008_0_001_008_09A_09A +016_001_008_0_001_008_00C_00C +016_001_008_0_001_008_075_075 +016_001_008_0_001_008_000_0AD +016_001_008_0_001_008_0A2_0A2 +016_001_008_0_001_008_01C_01C +016_001_008_0_001_008_013_013 +016_001_008_0_001_008_0AD_0AD +016_001_008_0_001_008_000_04E +016_001_008_0_001_008_04A_04A +016_001_008_0_001_008_02F_02F +016_001_008_0_001_008_0AA_0AA +016_001_008_0_001_008_0A9_0A9 +016_001_008_0_001_008_088_088 +016_001_008_0_001_008_0C0_0C0 +016_001_008_0_001_008_04A_04A +016_001_008_0_001_008_00A_00A +016_001_008_0_001_008_0E3_0E3 +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_010_010 +016_001_008_0_001_008_039_039 +016_001_008_0_001_008_05D_05D +016_001_008_0_001_008_091_091 +016_001_008_0_001_008_011_011 +016_001_008_0_001_008_0F5_0F5 +016_001_008_0_001_008_089_089 +016_001_008_0_001_008_008_008 +016_001_008_0_001_008_011_011 +016_001_008_0_001_008_0FF_0FF +016_001_008_0_001_008_0FD_0FD +016_001_008_0_001_008_05B_05B +016_001_008_0_001_008_0BA_0BA +016_001_008_0_001_008_04E_04E +016_001_008_0_001_008_077_077 +016_001_008_0_001_008_0A4_0A4 +016_001_008_0_001_008_00D_00D +016_001_008_0_001_008_0F1_0F1 +016_001_008_0_001_008_050_050 +016_001_008_0_001_008_0F6_0F6 +016_001_008_0_001_008_0ED_0ED +016_001_008_0_001_008_058_058 +016_001_008_0_001_008_013_013 +016_001_008_0_001_008_073_073 +// WORD Number: 9 +016_001_009_0_001_009_0E1_0E1 +016_001_009_0_001_009_0A3_0A3 +016_001_009_0_001_009_0B0_0B0 +016_001_009_0_001_009_03B_03B +016_001_009_0_001_009_073_073 +016_001_009_0_001_009_072_072 +016_001_009_0_001_009_0ED_0ED +016_001_009_0_001_009_0CA_0CA +016_001_009_0_001_009_03B_03B +016_001_009_0_001_009_001_001 +016_001_009_0_001_009_0D1_0D1 +016_001_009_0_001_009_0A6_0A6 +016_001_009_0_001_009_04A_04A +016_001_009_0_001_009_025_025 +016_001_009_0_001_009_0B1_0B1 +016_001_009_0_001_009_064_064 +016_001_009_0_001_009_037_037 +016_001_009_0_001_009_02D_02D +016_001_009_0_001_009_06D_06D +016_001_009_0_001_009_0F5_0F5 +016_001_009_0_001_009_07B_07B +016_001_009_0_001_009_0BB_0BB +016_001_009_0_001_009_0F2_0F2 +016_001_009_0_001_009_0EE_01C +016_001_009_0_001_009_01C_01C +016_001_009_0_001_009_0D2_0D2 +016_001_009_0_001_009_003_003 +016_001_009_0_001_009_025_025 +016_001_009_0_001_009_089_089 +016_001_009_0_001_009_02F_02F +016_001_009_0_001_009_03A_03A +016_001_009_0_001_009_0D5_0D5 +016_001_009_0_001_009_0C5_0C5 +016_001_009_0_001_009_0DD_0DD +016_001_009_0_001_009_049_049 +016_001_009_0_001_009_09D_09D +016_001_009_0_001_009_0C8_0C8 +016_001_009_0_001_009_004_004 +016_001_009_0_001_009_086_086 +016_001_009_0_001_009_012_012 +016_001_009_0_001_009_023_023 +016_001_009_0_001_009_002_002 +016_001_009_0_001_009_0A7_0A7 +016_001_009_0_001_009_0A2_0A2 +016_001_009_0_001_009_0E2_0E2 +016_001_009_0_001_009_0BC_0BC +016_001_009_0_001_009_0C9_0C9 +016_001_009_0_001_009_07F_07F +016_001_009_0_001_009_0B6_0B6 +016_001_009_0_001_009_036_036 +016_001_009_0_001_009_0B8_0B8 +016_001_009_0_001_009_0E0_0E0 +016_001_009_0_001_009_000_054 +016_001_009_0_001_009_062_062 +016_001_009_0_001_009_06A_06A +016_001_009_0_001_009_000_069 +016_001_009_0_001_009_018_018 +016_001_009_0_001_009_036_036 +016_001_009_0_001_009_0CC_0CC +016_001_009_0_001_009_0E7_0E7 +016_001_009_0_001_009_0EE_0EE +016_001_009_0_001_009_001_001 +016_001_009_0_001_009_0C2_0C2 +016_001_009_0_001_009_041_041 +016_001_009_0_001_009_072_072 +016_001_009_0_001_009_0FF_0FF +016_001_009_0_001_009_068_068 +016_001_009_0_001_009_0AC_0AC +016_001_009_0_001_009_056_056 +016_001_009_0_001_009_02B_02B +016_001_009_0_001_009_09F_09F +016_001_009_0_001_009_000_01D +016_001_009_0_001_009_004_004 +016_001_009_0_001_009_054_054 +016_001_009_0_001_009_0C5_0C5 +016_001_009_0_001_009_004_004 +016_001_009_0_001_009_085_085 +016_001_009_0_001_009_073_073 +016_001_009_0_001_009_0C3_0C3 +016_001_009_0_001_009_037_037 +016_001_009_0_001_009_0A2_0A2 +016_001_009_0_001_009_03C_03C +016_001_009_0_001_009_04D_04D +016_001_009_0_001_009_02C_02C +016_001_009_0_001_009_049_049 +016_001_009_0_001_009_0F3_0F3 +016_001_009_0_001_009_065_065 +016_001_009_0_001_009_06C_06C +016_001_009_0_001_009_032_032 +016_001_009_0_001_009_081_081 +016_001_009_0_001_009_021_021 +016_001_009_0_001_009_044_044 +016_001_009_0_001_009_0C1_0C1 +016_001_009_0_001_009_0C7_0C7 +016_001_009_0_001_009_000_0AF +016_001_009_0_001_009_0BE_0BE +016_001_009_0_001_009_02F_02F +016_001_009_0_001_009_032_032 +016_001_009_0_001_009_096_096 +016_001_009_0_001_009_0D0_0D0 +016_001_009_0_001_009_0E5_0E5 +016_001_009_0_001_009_090_090 +016_001_009_0_001_009_03E_03E +016_001_009_0_001_009_0D2_0D2 +016_001_009_0_001_009_028_028 +016_001_009_0_001_009_022_022 +016_001_009_0_001_009_0B3_0B3 +016_001_009_0_001_009_035_035 +016_001_009_0_001_009_0FB_0FB +016_001_009_0_001_009_0F2_0F2 +016_001_009_0_001_009_0A6_0A6 +016_001_009_0_001_009_073_073 +016_001_009_0_001_009_041_041 +016_001_009_0_001_009_066_066 +016_001_009_0_001_009_0B5_0B5 +016_001_009_0_001_009_042_042 +016_001_009_0_001_009_023_023 +016_001_009_0_001_009_016_016 +016_001_009_0_001_009_0EC_0EC +016_001_009_0_001_009_00D_00D +016_001_009_0_001_009_0B1_0B1 +016_001_009_0_001_009_0DB_0DB +016_001_009_0_001_009_08B_08B +016_001_009_0_001_009_0A4_0A4 +016_001_009_0_001_009_0CC_0CC +016_001_009_0_001_009_028_028 +016_001_009_0_001_009_009_009 +016_001_009_0_001_009_033_033 +016_001_009_0_001_009_043_043 +016_001_009_0_001_009_09E_09E +016_001_009_0_001_009_05A_05A +016_001_009_0_001_009_071_071 +016_001_009_0_001_009_03C_03C +016_001_009_0_001_009_0DA_0DA +016_001_009_0_001_009_06E_06E +016_001_009_0_001_009_019_019 +016_001_009_0_001_009_0D6_0D6 +016_001_009_0_001_009_092_092 +016_001_009_0_001_009_0FA_0FA +016_001_009_0_001_009_09E_09E +016_001_009_0_001_009_00C_00C +016_001_009_0_001_009_0E0_0E0 +016_001_009_0_001_009_000_07A +016_001_009_0_001_009_000_01B +016_001_009_0_001_009_0DD_0DD +016_001_009_0_001_009_0DD_0DD +016_001_009_0_001_009_077_077 +016_001_009_0_001_009_088_088 +016_001_009_0_001_009_000_0A9 +016_001_009_0_001_009_072_072 +016_001_009_0_001_009_005_005 +016_001_009_0_001_009_034_034 +016_001_009_0_001_009_0DF_0DF +016_001_009_0_001_009_06B_06B +016_001_009_0_001_009_091_091 +016_001_009_0_001_009_06F_06F +016_001_009_0_001_009_0D5_0D5 +016_001_009_0_001_009_000_0CD +016_001_009_0_001_009_0D9_0D9 +016_001_009_0_001_009_087_087 +016_001_009_0_001_009_0F7_0F7 +016_001_009_0_001_009_06A_06A +016_001_009_0_001_009_03C_03C +016_001_009_0_001_009_0F7_0F7 +016_001_009_0_001_009_024_024 +016_001_009_0_001_009_0B2_0B2 +016_001_009_0_001_009_034_034 +016_001_009_0_001_009_0DA_0DA +016_001_009_0_001_009_055_055 +016_001_009_0_001_009_0CC_0CC +016_001_009_0_001_009_021_021 +016_001_009_0_001_009_0A6_0A6 +016_001_009_0_001_009_080_080 +016_001_009_0_001_009_0E6_0E6 +016_001_009_0_001_009_048_048 +016_001_009_0_001_009_016_016 +016_001_009_0_001_009_0BC_0BC +016_001_009_0_001_009_0C9_0C9 +016_001_009_0_001_009_01B_01B +016_001_009_0_001_009_068_068 +016_001_009_0_001_009_0A5_0A5 +016_001_009_0_001_009_0B0_0B0 +016_001_009_0_001_009_0BB_0BB +016_001_009_0_001_009_0C9_0C9 +016_001_009_0_001_009_002_002 +016_001_009_0_001_009_05A_05A +016_001_009_0_001_009_0BB_0BB +016_001_009_0_001_009_00E_00E +016_001_009_0_001_009_0A5_0A5 +016_001_009_0_001_009_05E_05E +016_001_009_0_001_009_027_027 +016_001_009_0_001_009_0A4_0A4 +016_001_009_0_001_009_093_093 +016_001_009_0_001_009_0BF_0BF +016_001_009_0_001_009_000_0C4 +016_001_009_0_001_009_0CA_0CA +016_001_009_0_001_009_065_065 +016_001_009_0_001_009_0C0_0C0 +016_001_009_0_001_009_09A_09A +016_001_009_0_001_009_0FD_0FD +016_001_009_0_001_009_0EE_0EE +016_001_009_0_001_009_0F9_0F9 +016_001_009_0_001_009_0B0_0B0 +016_001_009_0_001_009_0B4_0B4 +016_001_009_0_001_009_000_01E +016_001_009_0_001_009_0AB_0AB +016_001_009_0_001_009_017_017 +016_001_009_0_001_009_04E_04E +016_001_009_0_001_009_026_026 +016_001_009_0_001_009_051_051 +016_001_009_0_001_009_029_029 +016_001_009_0_001_009_049_049 +016_001_009_0_001_009_0DD_0DD +016_001_009_0_001_009_077_077 +016_001_009_0_001_009_013_013 +016_001_009_0_001_009_0B4_0B4 +016_001_009_0_001_009_063_063 +016_001_009_0_001_009_0CF_0CF +016_001_009_0_001_009_091_091 +016_001_009_0_001_009_0E7_0E7 +016_001_009_0_001_009_004_004 +016_001_009_0_001_009_082_082 +016_001_009_0_001_009_0F9_0F9 +016_001_009_0_001_009_071_071 +016_001_009_0_001_009_05F_05F +016_001_009_0_001_009_0C4_0C4 +016_001_009_0_001_009_07B_07B +016_001_009_0_001_009_052_052 +016_001_009_0_001_009_0C7_0C7 +016_001_009_0_001_009_0AB_0AB +016_001_009_0_001_009_0A7_0A7 +016_001_009_0_001_009_06B_06B +016_001_009_0_001_009_0E9_0E9 +016_001_009_0_001_009_046_046 +016_001_009_0_001_009_0DC_0DC +016_001_009_0_001_009_03F_03F +016_001_009_0_001_009_02B_02B +016_001_009_0_001_009_074_074 +016_001_009_0_001_009_0A7_0A7 +016_001_009_0_001_009_0C8_0C8 +016_001_009_0_001_009_018_018 +016_001_009_0_001_009_026_026 +016_001_009_0_001_009_036_036 +016_001_009_0_001_009_04D_04D +016_001_009_0_001_009_0A4_0A4 +016_001_009_0_001_009_0BB_0BB +016_001_009_0_001_009_0B6_0B6 +016_001_009_0_001_009_020_020 +016_001_009_0_001_009_0B3_0B3 +016_001_009_0_001_009_0B3_0B3 +016_001_009_0_001_009_0A0_0A0 +016_001_009_0_001_009_070_070 +016_001_009_0_001_009_0A6_0A6 +016_001_009_0_001_009_000_0E6 +016_001_009_0_001_009_0A0_0A0 Index: trunk/example/sim =================================================================== --- trunk/example/sim (nonexistent) +++ trunk/example/sim (revision 4)
trunk/example/sim Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: trunk/example =================================================================== --- trunk/example (nonexistent) +++ trunk/example (revision 4)
trunk/example Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.