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URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

Subversion Repositories robust_axi_fabric

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/robust_axi_fabric/trunk/src/base/def_ic.txt
1,23 → 1,22
INCLUDE def_ic_static.txt
 
SWAP #FFD #1 ##flip-flop delay
SWAP #FFD #1 ##flip-flop delay
 
SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
 
##fabric 0
BUILD
SWAP MASTER_NUM 3 ##number of masters
SWAP SLAVE_NUM 8 ##number of slaves
SWAP SLAVE_NUM 6 ##number of slaves
 
##DEFINE DEF_DECERR_SLV ##use interanl decode slave error
DEFINE DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP ID_BITS 2 ##AXI ID bits
LOOP M0_IDX 1 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
SWAP ID_BITS 3 ##AXI ID bits
LOOP M0_IDX 2 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b000 ##master 0 ID0
SWAP ID_M0_ID1 ID_BITS'b001 ##master 0 ID1
LOOP M1_IDX 1 ##number of IDs for master 1
SWAP ID_M1_ID0 ID_BITS'b01 ##master 1 ID0
SWAP ID_M1_ID0 ID_BITS'b011 ##master 1 ID0
LOOP M2_IDX 1 ##number of IDs for master 2
SWAP ID_M2_ID0 ID_BITS'b10 ##master 2 ID0
SWAP ID_M2_ID0 ID_BITS'b101 ##master 2 ID0
SWAP CMD_DEPTH 8 ##AXI command depth for read and write
 
25,26 → 24,3
SWAP ADDR_BITS 32 ##AXI address bits
 
SWAP USER_BITS 4 ##AXI user bits
ENDBUILD
 
##fabric 1
BUILD
SWAP MASTER_NUM 1 ##number of masters
SWAP SLAVE_NUM 3 ##number of slaves
 
DEFINE DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP ID_BITS 2 ##AXI ID bits
LOOP M0_IDX 3 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
SWAP ID_M0_ID1 ID_BITS'b01 ##master 0 ID1
SWAP ID_M0_ID2 ID_BITS'b11 ##master 0 ID2
SWAP CMD_DEPTH 4 ##AXI command depth for read and write
 
SWAP DATA_BITS 32 ##AXI data bits
SWAP ADDR_BITS 24 ##AXI address bits
 
SWAP USER_BITS 0 ##AXI user bits
ENDBUILD
 

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