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URL https://opencores.org/ocsvn/robust_axi_fabric/robust_axi_fabric/trunk

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Rev 1 → Rev 2

/trunk/run/run.sh
0,0 → 1,9
#!/bin/bash
 
echo Starting RobustVerilog fabric run
rm -rf out
mkdir out
 
../../../robust ../src/base/ic.v -od out -I ../src/gen -list iclist.txt -listpath -header
 
echo Completed RobustVerilog fabric run - results in examples/fabric/run/out/
/trunk/src/gen/prgen_fifo.v
0,0 → 1,127
 
OUTFILE prgen_fifo.v
 
module prgen_fifo(PORTS);
 
parameter WIDTH = 8;
parameter DEPTH_FULL = 8;
 
parameter SINGLE = DEPTH_FULL == 1;
parameter DEPTH = SINGLE ? 1 : DEPTH_FULL -1;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 : 0; //0 is ilegal
 
parameter LAST_LINE = DEPTH-1;
 
input clk;
input reset;
 
input push;
input pop;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
//output next;
output empty;
output full;
 
wire reg_push;
wire reg_pop;
wire fifo_push;
wire fifo_pop;
reg [DEPTH-1:0] fullness_in;
reg [DEPTH-1:0] fullness_out;
reg [DEPTH-1:0] fullness;
reg [WIDTH-1:0] fifo [DEPTH-1:0];
wire fifo_empty;
wire next;
reg [WIDTH-1:0] dout;
reg dout_empty;
reg [DEPTH_BITS-1:0] ptr_in;
reg [DEPTH_BITS-1:0] ptr_out;
 
 
assign reg_push = push & fifo_empty & (dout_empty | pop);
assign reg_pop = pop & fifo_empty;
assign fifo_push = !SINGLE & push & (~reg_push);
assign fifo_pop = !SINGLE & pop & (~reg_pop);
always @(posedge clk or posedge reset)
if (reset)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (reg_push)
begin
dout <= #FFD din;
dout_empty <= #FFD 1'b0;
end
else if (reg_pop)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (fifo_pop)
begin
dout <= #FFD fifo[ptr_out];
dout_empty <= #FFD 1'b0;
end
always @(posedge clk or posedge reset)
if (reset)
ptr_in <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_push)
ptr_in <= #FFD ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
 
always @(posedge clk or posedge reset)
if (reset)
ptr_out <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_pop)
ptr_out <= #FFD ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
 
always @(posedge clk)
if (fifo_push)
fifo[ptr_in] <= #FFD din;
 
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
fullness_in = {DEPTH{1'b0}};
fullness_in[ptr_in] = fifo_push;
end
always @(/*AUTOSENSE*/fifo_pop or ptr_out)
begin
fullness_out = {DEPTH{1'b0}};
fullness_out[ptr_out] = fifo_pop;
end
always @(posedge clk or posedge reset)
if (reset)
fullness <= #FFD {DEPTH{1'b0}};
else if (fifo_push | fifo_pop)
fullness <= #FFD (fullness & (~fullness_out)) | fullness_in;
 
 
assign next = |fullness;
assign fifo_empty = ~next;
assign empty = fifo_empty & dout_empty;
assign full = SINGLE ? !dout_empty : &fullness;
 
endmodule
 
 
/trunk/src/base/ic.v
0,0 → 1,114
OUTFILE PREFIX_ic.v
INCLUDE def_ic.txt
ITER MX
 
ITER SX SLAVE_NUM ##external slave ports don't include decerr slave
 
module PREFIX_ic (PORTS);
 
input clk;
input reset;
 
port MMX_GROUP_IC_AXI;
revport SSX_GROUP_IC_AXI;
ENDITER SX
ITER SX ##use global iterator
wire [EXPR(SLV_BITS-1):0] MMX_AWSLV;
wire [EXPR(SLV_BITS-1):0] MMX_ARSLV;
wire [EXPR(MSTR_BITS-1):0] SSX_AWMSTR;
wire [EXPR(MSTR_BITS-1):0] SSX_ARMSTR;
wire SSX_AWIDOK;
wire SSX_ARIDOK;
 
CREATE ic_addr.v def_ic.txt
PREFIX_ic_addr
PREFIX_ic_addr_rd (.clk(clk),
.reset(reset),
.MMX_ASLV(MMX_ARSLV),
.MMX_AGROUP_IC_AXI_A(MMX_ARGROUP_IC_AXI_A),
.SSX_AMSTR(SSX_ARMSTR),
.SSX_AIDOK(SSX_ARIDOK),
.SSX_AGROUP_IC_AXI_A(SSX_ARGROUP_IC_AXI_A),
STOMP ,
);
 
PREFIX_ic_addr
PREFIX_ic_addr_wr (
.clk(clk),
.reset(reset),
.MMX_ASLV(MMX_AWSLV),
.MMX_AGROUP_IC_AXI_A(MMX_AWGROUP_IC_AXI_A),
.SSX_AMSTR(SSX_AWMSTR),
.SSX_AIDOK(SSX_AWIDOK),
.SSX_AGROUP_IC_AXI_A(SSX_AWGROUP_IC_AXI_A),
STOMP ,
);
 
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) R)
PREFIX_ic_resp
PREFIX_ic_rresp (
.clk(clk),
.reset(reset),
.MMX_AGROUP_IC_AXI_CMD(MMX_ARGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_R(MMX_RGROUP_IC_AXI_R),
.SSX_GROUP_IC_AXI_R(SSX_RGROUP_IC_AXI_R),
STOMP ,
);
 
CREATE ic_wdata.v def_ic.txt
PREFIX_ic_wdata
PREFIX_ic_wdata (
.clk(clk),
.reset(reset),
.MMX_AWGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD),
.MMX_WGROUP_IC_AXI_W(MMX_WGROUP_IC_AXI_W),
.SSX_WGROUP_IC_AXI_W(SSX_WGROUP_IC_AXI_W),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWMSTR(SSX_AWMSTR),
STOMP ,
);
 
CREATE ic_resp.v def_ic.txt DEFCMD(SWAP CONST(RW) W)
PREFIX_ic_resp
PREFIX_ic_bresp (
.clk(clk),
.reset(reset),
.MMX_AGROUP_IC_AXI_CMD(MMX_AWGROUP_IC_AXI_CMD),
.MMX_GROUP_IC_AXI_B(MMX_BGROUP_IC_AXI_B),
.MMX_DATA(),
.MMX_LAST(),
.SSX_GROUP_IC_AXI_B(SSX_BGROUP_IC_AXI_B),
.SSX_DATA({DATA_BITS{1'b0}}),
.SSX_LAST(1'b1),
STOMP ,
);
IFDEF DEF_DECERR_SLV
wire SSERR_GROUP_IC_AXI;
CREATE ic_decerr.v def_ic.txt
PREFIX_ic_decerr
PREFIX_ic_decerr (
.clk(clk),
.reset(reset),
.AWIDOK(SSERR_AWIDOK),
.ARIDOK(SSERR_ARIDOK),
.GROUP_IC_AXI(SSERR_GROUP_IC_AXI),
STOMP ,
);
ENDIF DEF_DECERR_SLV
endmodule
 
 
 
/trunk/src/base/ic_registry_wr.v
0,0 → 1,136
OUTFILE PREFIX_ic_registry_wr.v
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
module PREFIX_ic_registry_wr(PORTS);
 
input clk;
input reset;
 
port MMX_AWGROUP_IC_AXI_CMD;
input [ID_BITS-1:0] MMX_WID;
input MMX_WVALID;
input MMX_WREADY;
input MMX_WLAST;
output [SLV_BITS-1:0] MMX_WSLV;
output MMX_WOK;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
input SSX_WVALID;
input SSX_WREADY;
input SSX_WLAST;
wire AWmatch_MMX_IDMMX_IDX;
wire Wmatch_MMX_IDMMX_IDX;
 
wire cmd_push_MMX;
wire cmd_push_MMX_IDMMX_IDX;
wire cmd_pop_MMX;
wire cmd_pop_MMX_IDMMX_IDX;
 
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX;
wire slave_empty_MMX_IDMMX_IDX;
wire slave_full_MMX_IDMMX_IDX;
 
wire cmd_push_SSX;
wire cmd_pop_SSX;
wire [MSTR_BITS-1:0] master_in_SSX;
wire [MSTR_BITS-1:0] master_out_SSX;
wire master_empty_SSX;
wire master_full_SSX;
reg [SLV_BITS-1:0] MMX_WSLV;
reg MMX_WOK;
 
assign AWmatch_MMX_IDMMX_IDX = MMX_AWID == ID_MMX_IDMMX_IDX;
assign Wmatch_MMX_IDMMX_IDX = MMX_WID == ID_MMX_IDMMX_IDX;
assign cmd_push_MMX = MMX_AWVALID & MMX_AWREADY;
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & AWmatch_MMX_IDMMX_IDX;
assign cmd_pop_MMX = MMX_WVALID & MMX_WREADY & MMX_WLAST;
assign cmd_pop_MMX_IDMMX_IDX = cmd_pop_MMX & Wmatch_MMX_IDMMX_IDX;
 
assign cmd_push_SSX = SSX_AWVALID & SSX_AWREADY;
assign cmd_pop_SSX = SSX_WVALID & SSX_WREADY & SSX_WLAST;
assign master_in_SSX = SSX_AWMSTR;
assign slave_in_MMX_IDMMX_IDX = MMX_AWSLV;
 
LOOP MX
always @(MMX_WID
or slave_out_MMX_IDMMX_IDX
)
begin
case (MMX_WID)
ID_MMX_IDMMX_IDX : MMX_WSLV = slave_out_MMX_IDMMX_IDX;
default : MMX_WSLV = SERR;
endcase
end
 
always @(MMX_WSLV
or master_out_SSX
)
begin
case (MMX_WSLV)
'dSX : MMX_WOK = master_out_SSX == 'dMX;
default : MMX_WOK = 1'b0;
endcase
end
 
ENDLOOP MX
LOOP MX
LOOP MMX_IDX
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDMMX_IDX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDMMX_IDX),
.pop(cmd_pop_MMX_IDMMX_IDX),
.din(slave_in_MMX_IDMMX_IDX),
.dout(slave_out_MMX_IDMMX_IDX),
.empty(slave_empty_MMX_IDMMX_IDX),
.full(slave_full_MMX_IDMMX_IDX)
);
 
ENDLOOP MMX_IDX
ENDLOOP MX
 
LOOP SX
prgen_fifo #(MSTR_BITS, 32)
master_fifo_SSX(
.clk(clk),
.reset(reset),
.push(cmd_push_SSX),
.pop(cmd_pop_SSX),
.din(master_in_SSX),
.dout(master_out_SSX),
.empty(master_empty_SSX),
.full(master_full_SSX)
);
 
ENDLOOP SX
endmodule
 
/trunk/src/base/ic_wdata.v
0,0 → 1,80
OUTFILE PREFIX_ic_wdata.v
 
ITER MX
ITER SX
 
module PREFIX_ic_wdata (PORTS);
 
parameter STRB_BITS = DATA_BITS/8;
input clk;
input reset;
port MMX_AWGROUP_IC_AXI_CMD;
port MMX_WGROUP_IC_AXI_W;
revport SSX_WGROUP_IC_AXI_W;
input SSX_AWVALID;
input SSX_AWREADY;
input [MSTR_BITS-1:0] SSX_AWMSTR;
 
 
parameter WBUS_WIDTH = GONCAT(GROUP_IC_AXI_W.IN.WIDTH +);
 
wire [WBUS_WIDTH-1:0] SSX_WBUS;
wire [WBUS_WIDTH-1:0] MMX_WBUS;
wire [SLV_BITS-1:0] MMX_WSLV;
wire MMX_WOK;
wire SSX_MMX;
 
 
 
CREATE ic_registry_wr.v def_ic.txt
PREFIX_ic_registry_wr
PREFIX_ic_registry_wr (
.clk(clk),
.reset(reset),
.MMX_AWSLV(MMX_AWSLV),
.MMX_AWID(MMX_AWID),
.MMX_AWVALID(MMX_AWVALID),
.MMX_AWREADY(MMX_AWREADY),
.MMX_WID(MMX_WID),
.MMX_WVALID(MMX_WVALID),
.MMX_WREADY(MMX_WREADY),
.MMX_WLAST(MMX_WLAST),
.MMX_WSLV(MMX_WSLV),
.MMX_WOK(MMX_WOK),
.SSX_AWVALID(SSX_AWVALID),
.SSX_AWREADY(SSX_AWREADY),
.SSX_AWMSTR(SSX_AWMSTR),
.SSX_WVALID(SSX_WVALID),
.SSX_WREADY(SSX_WREADY),
.SSX_WLAST(SSX_WLAST),
STOMP ,
);
 
 
assign SSX_MMX = (MMX_WSLV == 'dSX) & MMX_WOK & MMX_WVALID;
assign MMX_WBUS = {GONCAT(MMX_WGROUP_IC_AXI_W.IN ,)};
 
assign SSX_WBUS = CONCAT((MMX_WBUS & {WBUS_WIDTH{SSX_MMX}}) |);
 
assign {GONCAT(SSX_WGROUP_IC_AXI_W.IN ,)} = SSX_WBUS;
LOOP MX
assign MMX_WREADY =
SSX_MMX ? SSX_WREADY :
1'b0;
ENDLOOP MX
endmodule
 
 
 
/trunk/src/base/ic_registry_resp.v
0,0 → 1,134
OUTFILE PREFIX_ic_registry_resp.v
 
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
module PREFIX_ic_registry_resp(PORTS);
input clk;
input reset;
 
port MMX_AGROUP_IC_AXI_CMD;
input [ID_BITS-1:0] SSX_ID;
input SSX_VALID;
input SSX_READY;
input SSX_LAST;
output [MSTR_BITS-1:0] SSX_MSTR;
output SSX_OK;
 
wire Amatch_MMX_IDMMX_IDX;
wire match_MMX_IDMMX_IDX;
wire no_Amatch_MMX;
wire cmd_push_MMX;
wire cmd_push_MMX_IDMMX_IDX;
wire cmd_pop_SSX;
LOOP MX
wire cmd_pop_MMX_IDMMX_IDX;
ENDLOOP MX
 
wire [SLV_BITS-1:0] slave_in_MMX_IDMMX_IDX;
wire [SLV_BITS-1:0] slave_out_MMX_IDMMX_IDX;
wire slave_empty_MMX_IDMMX_IDX;
wire slave_full_MMX_IDMMX_IDX;
 
reg [MSTR_BITS-1:0] ERR_MSTR_reg;
wire [MSTR_BITS-1:0] ERR_MSTR;
reg [MSTR_BITS-1:0] SSX_MSTR;
reg SSX_OK;
 
assign Amatch_MMX_IDMMX_IDX = MMX_AID == ID_MMX_IDMMX_IDX;
assign match_MMX_IDMMX_IDX = SSX_ID == ID_MMX_IDMMX_IDX;
 
assign cmd_push_MMX = MMX_AVALID & MMX_AREADY;
assign cmd_push_MMX_IDMMX_IDX = cmd_push_MMX & Amatch_MMX_IDMMX_IDX;
assign cmd_pop_SSX = SSX_VALID & SSX_READY & SSX_LAST;
LOOP MX
assign cmd_pop_MMX_IDMMX_IDX = CONCAT((cmd_pop_SSX & (SSX_ID == ID_MMX_IDMMX_IDX)) |);
ENDLOOP MX
assign slave_in_MMX_IDMMX_IDX = MMX_ASLV;
 
 
 
 
IFDEF DEF_DECERR_SLV
LOOP MX
assign no_Amatch_MMX = CONCAT((~Amatch_MMX_IDMMX_IDX) &);
ENDLOOP MX
 
always @(posedge clk or posedge reset)
if (reset)
ERR_MSTR_reg <= #FFD {MSTR_BITS{1'b0}};
LOOP MX
else if (cmd_push_MMX & no_Amatch_MMX)
ERR_MSTR_reg <= #FFD 'dMX;
ENDLOOP MX
assign ERR_MSTR = ERR_MSTR_reg;
ELSE DEF_DECERR_SLV
assign ERR_MSTR = 'd0;
ENDIF DEF_DECERR_SLV
LOOP SX
always @(SSX_ID or ERR_MSTR)
begin
case (SSX_ID)
LOOP MX
ID_MMX_IDMMX_IDX : SSX_MSTR = 'dMX;
ENDLOOP MX
default : SSX_MSTR = ERR_MSTR;
endcase
end
always @(*)
begin
case (SSX_ID)
LOOP MX
ID_MMX_IDMMX_IDX : SSX_OK = slave_out_MMX_IDMMX_IDX == 'dSX;
ENDLOOP MX
default : SSX_OK = 1'b1; //SLVERR
endcase
end
ENDLOOP SX
 
CREATE prgen_fifo.v DEFCMD(SWAP CONST(#FFD) #FFD)
LOOP MX
LOOP MMX_IDX
prgen_fifo #(SLV_BITS, CMD_DEPTH)
slave_fifo_MMX_IDMMX_IDX(
.clk(clk),
.reset(reset),
.push(cmd_push_MMX_IDMMX_IDX),
.pop(cmd_pop_MMX_IDMMX_IDX),
.din(slave_in_MMX_IDMMX_IDX),
.dout(slave_out_MMX_IDMMX_IDX),
.empty(slave_empty_MMX_IDMMX_IDX),
.full(slave_full_MMX_IDMMX_IDX)
);
ENDLOOP MMX_IDX
ENDLOOP MX
 
endmodule
 
/trunk/src/base/ic_decerr.v
0,0 → 1,111
OUTFILE PREFIX_ic_decerr.v
 
module PREFIX_ic_decerr(PORTS);
 
input clk;
input reset;
 
input AWIDOK;
input ARIDOK;
port GROUP_IC_AXI;
 
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
reg AWREADY;
reg [ID_BITS-1:0] BID;
reg [1:0] BRESP;
reg BVALID;
reg ARREADY;
reg [ID_BITS-1:0] RID;
reg [1:0] RRESP;
reg RVALID;
reg [4-1:0] rvalid_cnt;
 
assign BUSER = 'd0;
assign RUSER = 'd0;
assign RDATA = {DATA_BITS{1'b0}};
 
 
//WRITE
assign WREADY = 1'b1;
always @(posedge clk or posedge reset)
if (reset)
begin
AWREADY <= #FFD 1'b1;
BID <= #FFD {ID_BITS{1'b0}};
BRESP <= #FFD 2'b00;
end
else if (BVALID & BREADY)
begin
AWREADY <= #FFD 1'b1;
end
else if (AWVALID & AWREADY)
begin
AWREADY <= #FFD 1'b0;
BID <= #FFD AWID;
BRESP <= #FFD AWIDOK ? RESP_DECERR : RESP_SLVERR;
end
always @(posedge clk or posedge reset)
if (reset)
BVALID <= #FFD 1'b0;
else if (WVALID & WREADY & WLAST)
BVALID <= #FFD 1'b1;
else if (BVALID & BREADY)
BVALID <= #FFD 1'b0;
 
//READ
always @(posedge clk or posedge reset)
if (reset)
begin
ARREADY <= #FFD 1'b1;
RID <= #FFD {ID_BITS{1'b0}};
RRESP <= #FFD 2'b00;
end
else if (RVALID & RREADY & RLAST)
begin
ARREADY <= #FFD 1'b1;
end
else if (ARVALID & ARREADY)
begin
ARREADY <= #FFD 1'b0;
RID <= #FFD ARID;
RRESP <= #FFD ARIDOK ? RESP_DECERR : RESP_SLVERR;
end
 
 
always @(posedge clk or posedge reset)
if (reset)
rvalid_cnt <= #FFD {4{1'b0}};
else if (RVALID & RREADY & RLAST)
rvalid_cnt <= #FFD {4{1'b0}};
else if (RVALID & RREADY)
rvalid_cnt <= #FFD rvalid_cnt - 1'b1;
else if (ARVALID & ARREADY)
rvalid_cnt <= #FFD ARLEN;
 
always @(posedge clk or posedge reset)
if (reset)
RVALID <= #FFD 1'b0;
else if (RVALID & RREADY & RLAST)
RVALID <= #FFD 1'b0;
else if (ARVALID & ARREADY)
RVALID <= #FFD 1'b1;
assign RLAST = (rvalid_cnt == 'd0) & RVALID;
endmodule
 
/trunk/src/base/def_ic.txt
0,0 → 1,50
INCLUDE def_ic_static.txt
 
SWAP #FFD #1 ##flip-flop delay
 
SWAP PREFIX fabric_MASTER_NUM_SLAVE_NUM ##prefix for all module and file names
 
##fabric 0
BUILD
SWAP MASTER_NUM 3 ##number of masters
SWAP SLAVE_NUM 8 ##number of slaves
 
##DEFINE DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP ID_BITS 2 ##AXI ID bits
LOOP M0_IDX 1 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
LOOP M1_IDX 1 ##number of IDs for master 1
SWAP ID_M1_ID0 ID_BITS'b01 ##master 1 ID0
LOOP M2_IDX 1 ##number of IDs for master 2
SWAP ID_M2_ID0 ID_BITS'b10 ##master 2 ID0
SWAP CMD_DEPTH 8 ##AXI command depth for read and write
 
SWAP DATA_BITS 64 ##AXI data bits
SWAP ADDR_BITS 32 ##AXI address bits
 
SWAP USER_BITS 4 ##AXI user bits
ENDBUILD
 
##fabric 1
BUILD
SWAP MASTER_NUM 1 ##number of masters
SWAP SLAVE_NUM 3 ##number of slaves
 
DEFINE DEF_DECERR_SLV ##use interanl decode slave error
 
SWAP ID_BITS 2 ##AXI ID bits
LOOP M0_IDX 3 ##number of IDs for master 0
SWAP ID_M0_ID0 ID_BITS'b00 ##master 0 ID0
SWAP ID_M0_ID1 ID_BITS'b01 ##master 0 ID1
SWAP ID_M0_ID2 ID_BITS'b11 ##master 0 ID2
SWAP CMD_DEPTH 4 ##AXI command depth for read and write
 
SWAP DATA_BITS 32 ##AXI data bits
SWAP ADDR_BITS 24 ##AXI address bits
 
SWAP USER_BITS 0 ##AXI user bits
ENDBUILD
 
/trunk/src/base/ic_arbiter.v
0,0 → 1,97
OUTFILE PREFIX_ic_MSTR_SLV_arbiter.v
 
ITER MX MSTRNUM
ITER SX SLVNUM
module PREFIX_ic_MSTR_SLV_arbiter(PORTS);
 
input clk;
input reset;
 
input [MSTRNUM-1:0] M_last;
input [MSTRNUM-1:0] M_req;
input [MSTRNUM-1:0] M_grant;
input [LOG2(SLVNUM)-1:0] MMX_slave;
output [MSTRNUM-1:0] SSX_master;
 
 
reg [MSTRNUM:0] SSX_master_prio_reg;
wire [MSTRNUM-1:0] SSX_master_prio;
reg [MSTRNUM-1:0] SSX_master_d;
wire [MSTRNUM-1:0] M_SSX;
wire [MSTRNUM-1:0] M_SSX_valid;
wire [MSTRNUM-1:0] M_SSX_prio;
reg [MSTRNUM-1:0] M_SSX_burst;
 
 
parameter MASTER_NONE = BIN(0 MSTRNUM);
parameter MASTERMX = BIN(EXPR(2^MX) MSTRNUM);
 
IFDEF DEF_PRIO
always @(posedge clk or posedge reset)
if (reset)
begin
SSX_master_prio_reg[MSTRNUM:1] <= #FFD {MSTRNUM{1'b0}};
SSX_master_prio_reg[0] <= #FFD 1'b1;
end
else if (|(M_req & M_grant & M_last))
begin
SSX_master_prio_reg[MSTRNUM:1] <= #FFD SSX_master_prio_reg[MSTRNUM-1:0];
SSX_master_prio_reg[0] <= #FFD SSX_master_prio_reg[MSTRNUM-1];
end
 
assign SSX_master_prio = SSX_master_prio_reg[MSTRNUM-1:0];
assign M_SSX_prio = M_SSX_valid & SSX_master_prio;
ENDIF DEF_PRIO
 
 
always @(posedge clk or posedge reset)
if (reset)
begin
SSX_master_d <= #FFD {MSTRNUM{1'b0}};
end
else
begin
SSX_master_d <= #FFD SSX_master;
end
 
LOOP MX MSTRNUM
always @(posedge clk or posedge reset)
if (reset)
begin
M_SSX_burst[MX] <= #FFD 1'b0;
end
else if (M_req[MX])
begin
M_SSX_burst[MX] <= #FFD SSX_master[MX] & (M_grant[MX] ? (~M_last[MX]) : 1'b1);
end
ENDLOOP MX
assign M_SSX = {CONCAT(MMX_slave == 'dSX ,)};
assign M_SSX_valid = M_SSX & M_req;
LOOP SX SLVNUM
assign SSX_master =
M_SSX_burst[MX] ? SSX_master_d :
IF DEF_PRIO M_SSX_prio[MX] ? MASTERMX :
M_SSX_valid[MX] ? MASTERMX :
MASTER_NONE;
ENDLOOP SX
endmodule
 
/trunk/src/base/ic_resp.v
0,0 → 1,95
OUTFILE PREFIX_ic_resp.v
 
ITER MX
ITER SX
 
module PREFIX_ic_resp (PORTS);
 
parameter STRB_BITS = DATA_BITS/8;
input clk;
input reset;
port MMX_AGROUP_IC_AXI_CMD;
port MMX_GROUP_IC_AXI_R;
revport SSX_GROUP_IC_AXI_R;
parameter RBUS_WIDTH = GONCAT(GROUP_IC_AXI_R.OUT.WIDTH +);
wire SSX_req;
wire [RBUS_WIDTH-1:0] SSX_RBUS;
wire [RBUS_WIDTH-1:0] MMX_RBUS;
wire SSX_MMX;
 
wire [MSTR_BITS-1:0] SSX_MSTR;
wire SSX_OK;
wire [SLVS-1:0] MMX_slave;
 
 
 
 
CREATE ic_registry_resp.v def_ic.txt
PREFIX_ic_registry_resp
PREFIX_ic_registry_resp (
.clk(clk),
.reset(reset),
.MMX_ASLV(MMX_ASLV),
.MMX_AID(MMX_AID),
.MMX_AVALID(MMX_AVALID),
.MMX_AREADY(MMX_AREADY),
.SSX_ID(SSX_ID),
.SSX_VALID(SSX_VALID),
.SSX_READY(SSX_READY),
.SSX_LAST(SSX_LAST),
.SSX_MSTR(SSX_MSTR),
.SSX_OK(SSX_OK),
STOMP ,
);
 
CREATE ic_arbiter.v def_ic.txt DEFCMD(SWAP MSTR_SLV slv) DEFCMD(SWAP MSTRNUM SLVS) DEFCMD(SWAP SLVNUM MSTRS) DEFCMD(DEFINE DEF_PRIO)
PREFIX_ic_slv_arbiter
PREFIX_ic_slv_arbiter(
.clk(clk),
.reset(reset),
.MSX_slave(SSX_MSTR),
.SMX_master(MMX_slave),
.M_last({CONCAT(SSX_LAST ,)}),
.M_req({CONCAT(SSX_req ,)}),
.M_grant({CONCAT(SSX_READY ,)})
);
 
assign SSX_req = SSX_VALID & SSX_OK;
assign SSX_MMX = MMX_slave[SX];
assign SSX_RBUS = {GONCAT(SSX_GROUP_IC_AXI_R.OUT ,)};
 
assign {GONCAT(MMX_GROUP_IC_AXI_R.OUT ,)} = MMX_RBUS;
 
LOOP MX
assign MMX_RBUS = CONCAT((SSX_RBUS & {RBUS_WIDTH{SSX_MMX}}) |);
ENDLOOP MX
 
LOOP SX
assign SSX_READY = CONCAT((SSX_MMX & MMX_READY) |);
ENDLOOP SX
endmodule
 
 
/trunk/src/base/ic_addr.v
0,0 → 1,98
OUTFILE PREFIX_ic_addr.v
 
ITER MX
ITER SX
 
module PREFIX_ic_addr (PORTS);
 
input clk;
input reset;
output [EXPR(SLV_BITS-1):0] MMX_ASLV;
port MMX_AGROUP_IC_AXI_A;
output [EXPR(MSTR_BITS-1):0] SSX_AMSTR;
output SSX_AIDOK;
revport SSX_AGROUP_IC_AXI_A;
parameter MASTER_NONE = 0;
parameter MASTERMX = 1 << MX;
 
parameter ABUS_WIDTH = GONCAT(GROUP_IC_AXI_A.IN.WIDTH +);
 
wire [ABUS_WIDTH-1:0] SSX_ABUS;
wire [ABUS_WIDTH-1:0] MMX_ABUS;
wire SSX_MMX;
wire [EXPR(SLV_BITS-1):0] MMX_ASLV;
wire MMX_AIDOK;
wire [EXPR(MSTRS-1):0] SSX_master;
 
reg [EXPR(MSTR_BITS-1):0] SSX_AMSTR;
 
wire SSX_AIDOK;
CREATE ic_dec.v def_ic.txt
PREFIX_ic_dec #(ADDR_BITS)
PREFIX_ic_dec (
.MMX_AADDR(MMX_AADDR),
.MMX_AID(MMX_AID),
.MMX_ASLV(MMX_ASLV),
.MMX_AIDOK(MMX_AIDOK),
STOMP ,
);
 
CREATE ic_arbiter.v def_ic.txt DEFCMD(SWAP MSTR_SLV mstr) DEFCMD(SWAP MSTRNUM MSTRS) DEFCMD(SWAP SLVNUM SLVS) DEFCMD(DEFINE DEF_PRIO)
PREFIX_ic_mstr_arbiter
PREFIX_ic_mstr_arbiter(
.clk(clk),
.reset(reset),
.MMX_slave(MMX_ASLV),
.SSX_master(SSX_master),
.M_last({MSTRS{1'b1}}),
.M_req({CONCAT(MMX_AVALID ,)}),
.M_grant({CONCAT(MMX_AREADY ,)})
);
LOOP SX
always @(/*AUTOSENSE*/SSX_master)
begin
case (SSX_master)
MASTERMX : SSX_AMSTR = MX;
default : SSX_AMSTR = MASTER_NONE;
endcase
end
ENDLOOP SX
assign SSX_MMX = SSX_master[MX];
assign MMX_ABUS = {GONCAT(MMX_AGROUP_IC_AXI_A.IN ,)};
 
assign {GONCAT(SSX_AGROUP_IC_AXI_A.IN ,)} = SSX_ABUS;
LOOP SX
assign SSX_ABUS = CONCAT((MMX_ABUS & {ABUS_WIDTH{SSX_MMX}}) |);
assign SSX_AIDOK = CONCAT((SSX_MMX & MMX_AIDOK) |);
ENDLOOP SX
LOOP MX
assign MMX_AREADY =
SSX_MMX ? SSX_AREADY :
~MMX_AVALID;
ENDLOOP MX
endmodule
 
 
 
/trunk/src/base/ic_dec.v
0,0 → 1,45
OUTFILE PREFIX_ic_dec.v
 
ITER MX
ITER SX
 
LOOP MX
ITER MMX_IDX
ENDLOOP MX
module PREFIX_ic_dec (PORTS);
 
input [ADDR_BITS-1:0] MMX_AADDR;
input [ID_BITS-1:0] MMX_AID;
output [SLV_BITS-1:0] MMX_ASLV;
output MMX_AIDOK;
 
parameter DEC_MSB = ADDR_BITS - 1;
parameter DEC_LSB = ADDR_BITS - MSTR_BITS;
reg [SLV_BITS-1:0] MMX_ASLV;
reg MMX_AIDOK;
LOOP MX
always @(MMX_AADDR or MMX_AIDOK)
begin
case ({MMX_AIDOK, MMX_AADDR[DEC_MSB:DEC_LSB]})
{1'b1, BIN(MX MSTR_BITS)} : MMX_ASLV = 'dSX;
default : MMX_ASLV = SERR;
endcase
end
 
always @(MMX_AID)
begin
case (MMX_AID)
ID_MMX_IDMMX_IDX : MMX_AIDOK = 1'b1;
default : MMX_AIDOK = 1'b0;
endcase
end
ENDLOOP MX
endmodule
 
 
 
/trunk/src/base/ic_defines.v
0,0 → 1,3
 
`define LEN_BITS 4
`define SIZE_BITS 3
/trunk/src/base/def_ic_static.txt
0,0 → 1,69
 
##Static defines
SWAP MSTRS MASTER_NUM
SWAP SLVS EXPR(SLAVE_NUM+DVAL(DECERR_SLV))
 
LOOP MX MSTRS
LOOP SX SLVS
 
SWAP MSTR_BITS LOG2(MSTRS)
SWAP SLV_BITS LOG2(SLVS)
 
SWAP SERR SLAVE_NUM
 
GROUP IC_AXI_A is {
ID ID_BITS input
ADDR ADDR_BITS input
LEN 4 input
SIZE 2 input
BURST 2 input
CACHE 4 input
PROT 3 input
LOCK 2 input
USER USER_BITS input
VALID 1 input
READY 1 output
}
 
GROUP IC_AXI_W is {
ID ID_BITS input
DATA DATA_BITS input
STRB DATA_BITS/8 input
LAST 1 input
USER USER_BITS input
VALID 1 input
READY 1 output
}
 
GROUP IC_AXI_B is {
ID ID_BITS output
RESP 2 output
USER USER_BITS output
VALID 1 output
READY 1 input
}
 
GROUP IC_AXI_R is {
ID ID_BITS output
DATA DATA_BITS output
RESP 2 output
LAST 1 output
USER USER_BITS output
VALID 1 output
READY 1 input
}
 
GROUP IC_AXI joins {
GROUP IC_AXI_A prefix_AW
GROUP IC_AXI_W prefix_W
GROUP IC_AXI_B prefix_B
GROUP IC_AXI_A prefix_AR
GROUP IC_AXI_R prefix_R
}
 
GROUP IC_AXI_CMD is {
SLV SLV_BITS input
ID ID_BITS input
VALID 1 input
READY 1 input
}
/trunk/README.txt
0,0 → 1,22
 
------------------------------ Remark ----------------------------------------
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
------------------------------------------------------------------------------
 
RobustVerilog generic AXI interconnect fabric
 
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
 
The RobustVerilog top source file is ic.v, it calls the top definition file named def_ic.txt.
 
The default definition file def_ic.txt generates 2 fabrics, the first with 3 masters and 8 slaves,
 
the second with 1 master, 3 slaves and an internal decode error slave.
 
Changing the interconnect parameters should be made only in def_ic.txt in the src/base directory (changing master num, slave num etc.).
 
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
 
 
 

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