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Rev 15 → Rev 16

/robust_fir/trunk/src/gen/prgen_bintree_adder.v
26,7 → 26,6
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE prgen_bintree_adder_INPUT_NUM.v
 
STARTDEF
55,9 → 54,9
ENDLOOP EX
STOMP LINE
 
LOOP TX EXPR(2^LOG2(INPUT_NUM)) ##round up
wire [BITS-1:0] sum_stageADD_STAGES_TX;
 
LOOP TX EXPR(2^LOG2(INPUT_NUM))
assign sum_stageADD_STAGES_TX = data_inTX;
ENDLOOP TX
/robust_fir/trunk/src/gen/prgen_delayN.v
1,31 → 1,31
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
 
OUTFILE prgen_NAME.v
/robust_fir/trunk/src/base/fir_parallel.v
1,88 → 1,88
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE fir_parallel_TOPO.v
 
ITER OX ORDER
ITER CX COEFF_NUM
ITER SX ADD_STAGES
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
// Number of multiplayers = COEFF_NUM
 
module fir_parallel_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid_out;
 
wire [EXPR(DIN_BITS-1):0] data_in_d0;
wire [EXPR(DIN_BITS-1):0] data_in_dEXPR(OX+1);
reg [EXPR(MULT_BITS-1):0] multCX;
//delay inputs per multiplayer
assign data_in_d0 = data_in;
CREATE prgen_delayN.v DEFCMD(SWAP DELAY 1) DEFCMD(DEFINE CLKEN)
prgen_delay1_en #(DIN_BITS) delay_dinOX (clk, reset, clken, data_in_dOX, data_in_dEXPR(OX+1));
always @(posedge clk or posedge reset)
if (reset)
begin
multCX <= #FFD {MULT_BITS{1'b0}};
end
else if (clken)
begin
multCX <= #FFD kCX * data_in_dCX;
end
 
//Pipline the output additions
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM COEFF_NUM)
prgen_bintree_adder_COEFF_NUM #(MULT_BITS) prgen_bintree_adder(
.clk(clk),
.reset(reset),
.data_inCX(multCX),
.data_out(data_out),
.valid_in(clken),
.valid_out(valid_out)
);
 
endmodule
 
 
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_parallel_TOPO.v
 
ITER OX ORDER
ITER CX COEFF_NUM
ITER SX ADD_STAGES
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
// Number of multiplayers = COEFF_NUM
 
module PREFIX_parallel_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid_out;
 
wire [EXPR(DIN_BITS-1):0] data_in_d0;
wire [EXPR(DIN_BITS-1):0] data_in_dEXPR(OX+1);
reg [EXPR(MULT_BITS-1):0] multCX;
//delay inputs per multiplayer
assign data_in_d0 = data_in;
CREATE prgen_delayN.v DEFCMD(SWAP DELAY 1) DEFCMD(DEFINE CLKEN)
prgen_delay1_en #(DIN_BITS) delay_dinOX (clk, reset, clken, data_in_dOX, data_in_dEXPR(OX+1));
always @(posedge clk or posedge reset)
if (reset)
begin
multCX <= #FFD {MULT_BITS{1'b0}};
end
else if (clken)
begin
multCX <= #FFD kCX * data_in_dCX;
end
 
//Pipline the output additions
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM COEFF_NUM)
prgen_bintree_adder_COEFF_NUM #(MULT_BITS) prgen_bintree_adder(
.clk(clk),
.reset(reset),
.data_inCX(multCX),
.data_out(data_out),
.valid_in(clken),
.valid_out(valid_out)
);
 
endmodule
 
 
/robust_fir/trunk/src/base/fir_Nserial.v
1,105 → 1,105
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE fir_MAC_NUMserial_TOPO.v
 
ITER CX COEFF_NUM
ITER MX MAC_NUM
ITER DX SON_DELAY
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
// Number of serial FIR sons = MAC_NUM
// Number of multiplayers = MAC_NUM
 
 
module fir_MAC_NUMserial_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid;
 
wire [EXPR(DIN_BITS-1):0] data_inMX;
wire [EXPR(SON_DOUT-1):0] data_outMX;
wire validMX;
wire null;
//delay inputs per son
assign data_in0 = data_in;
CREATE prgen_delayN.v DEFCMD(SWAP CONST(DELAY) SON_DELAY) DEFCMD(DEFINE CLKEN)
prgen_delaySON_DELAY_en #(DIN_BITS) delay_dinMX (clk, reset, clken, data_inMX, data_inEXPR(MX+1));
STOMP LINE
 
//the FIR sons
LOOP MX MAC_NUM
CREATE fir_serial.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) EXPR(SON_DELAY-1)) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
fir_serial_EXPR(SON_DELAY-1)_INPUT_BITS firMX
(
.clk(clk),
.reset(reset),
.clken(clken),
.kDX(kEXPR((MX*SON_DELAY)+DX)) ,
.data_in(data_inMX),
.data_out(data_outMX),
.valid(validMX)
);
ENDLOOP MX
 
//Pipline the output additions
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM MAC_NUM)
prgen_bintree_adder_MAC_NUM #(SON_DOUT) prgen_bintree_adder
(
.clk(clk),
.reset(reset),
.data_inMX(data_outMX),
IF TRUE(ADD_DOUT!=DOUT_BITS) .data_out({null, data_out}),
IF TRUE(ADD_DOUT==DOUT_BITS) .data_out(data_out),
.valid_in(valid0),
.valid_out(valid)
);
endmodule
 
 
 
 
 
 
 
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_MAC_NUMserial_TOPO.v
 
ITER CX COEFF_NUM
ITER MX MAC_NUM
ITER DX SON_DELAY
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
// Number of serial FIR sons = MAC_NUM
// Number of multiplayers = MAC_NUM
 
 
module PREFIX_MAC_NUMserial_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid;
 
wire [EXPR(DIN_BITS-1):0] data_inMX;
wire [EXPR(SON_DOUT-1):0] data_outMX;
wire validMX;
wire null;
//delay inputs per son
assign data_in0 = data_in;
CREATE prgen_delayN.v DEFCMD(SWAP CONST(DELAY) SON_DELAY) DEFCMD(DEFINE CLKEN)
prgen_delaySON_DELAY_en #(DIN_BITS) delay_dinMX (clk, reset, clken, data_inMX, data_inEXPR(MX+1));
STOMP LINE
 
//the FIR sons
LOOP MX MAC_NUM
CREATE fir_serial.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) EXPR(SON_DELAY-1)) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
PREFIX_serial_EXPR(SON_DELAY-1)_INPUT_BITS PREFIXMX
(
.clk(clk),
.reset(reset),
.clken(clken),
.kDX(kEXPR((MX*SON_DELAY)+DX)) ,
.data_in(data_inMX),
.data_out(data_outMX),
.valid(validMX)
);
ENDLOOP MX
 
//Pipline the output additions
CREATE prgen_bintree_adder.v DEFCMD(SWAP INPUT_NUM MAC_NUM)
prgen_bintree_adder_MAC_NUM #(SON_DOUT) prgen_bintree_adder
(
.clk(clk),
.reset(reset),
.data_inMX(data_outMX),
IF TRUE(ADD_DOUT!=DOUT_BITS) .data_out({null, data_out}),
IF TRUE(ADD_DOUT==DOUT_BITS) .data_out(data_out),
.valid_in(valid0),
.valid_out(valid)
);
endmodule
 
 
 
 
 
 
 
/robust_fir/trunk/src/base/fir_serial.v
1,164 → 1,164
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE fir_serial_TOPO.v
 
ITER OX ORDER
ITER CX COEFF_NUM
ITER SX ADD_STAGES
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
 
module fir_serial_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid;
 
wire [EXPR(COEFF_BITS-1):0] k;
wire [EXPR(MULT_BITS-1):0] mult;
reg [EXPR(DOUT_BITS-1):0] multCX;
wire [EXPR(DOUT_BITS-1):0] add;
wire addCX;
reg [EXPR(DOUT_BITS-1):0] mult_sum;
reg [EXPR(DOUT_BITS-1):0] data_out;
reg valid;
reg active;
reg [EXPR(ADD_STAGES-1):0] phase;
reg [EXPR(ADD_STAGES-1):0] cycle;
wire phaseCX;
wire cycleCX;
assign phaseCX = phase == 'dCX;
assign cycleCX = cycle == 'dCX;
assign k =
phaseOX ? kOX :
kORDER;
//a single multiplayer and a single adder
assign mult = k * data_in;
assign add = mult + (
addOX ? multOX :
multORDER);
always @(posedge clk or posedge reset)
if (reset)
active <= #FFD 1'b0;
else if (clken)
active <= #FFD 1'b1;
else if (phase == 'dORDER)
active <= #FFD 1'b0;
always @(posedge clk or posedge reset)
if (reset)
phase <= #FFD {ADD_STAGES{1'b0}};
else if (phase == 'dORDER)
phase <= #FFD {ADD_STAGES{1'b0}};
else if (active)
phase <= #FFD phase + 1'b1;
always @(posedge clk or posedge reset)
if (reset)
cycle <= #FFD {ADD_STAGES{1'b0}};
else if (phase == 'dORDER)
begin
if (cycle == 'dORDER)
cycle <= #FFD {ADD_STAGES{1'b0}};
else
cycle <= cycle + 1'b1;
end
LOOP PX COEFF_NUM
assign addPX = active & (
(phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) ||
STOMP || );
always @(posedge clk or posedge reset)
if (reset)
multPX <= #FFD {MULT_BITS{1'b0}};
else if (phase1 && cyclePX)
multPX <= #FFD {MULT_BITS{1'b0}};
else if (addPX)
multPX <= #FFD add;
ENDLOOP PX
 
//sample when valid
always @(posedge clk or posedge reset)
if (reset)
mult_sum <= #FFD {DOUT_BITS{1'b0}};
else if (phase1)
begin
LOOP CX COEFF_NUM
if (cycleCX)
mult_sum <= #FFD multCX;
else
STOMP NEWLINE
ENDLOOP CX
STOMP else
end
 
//sync to clock enable
always @(posedge clk or posedge reset)
if (reset)
begin
data_out <= #FFD {DOUT_BITS{1'b0}};
valid <= #FFD 1'b0;
end
else if (clken)
begin
data_out <= #FFD mult_sum;
valid <= #FFD 1'b1;
end
else
begin
valid <= #FFD 1'b0;
end
endmodule
 
 
 
 
 
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE PREFIX_serial_TOPO.v
 
ITER OX ORDER
ITER CX COEFF_NUM
ITER SX ADD_STAGES
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Sum of Products Latency = LATENCY
 
module PREFIX_serial_TOPO (PORTS);
input clk;
input reset;
input clken;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
output valid;
 
wire [EXPR(COEFF_BITS-1):0] k;
wire [EXPR(MULT_BITS-1):0] mult;
reg [EXPR(DOUT_BITS-1):0] multCX;
wire [EXPR(DOUT_BITS-1):0] add;
wire addCX;
reg [EXPR(DOUT_BITS-1):0] mult_sum;
reg [EXPR(DOUT_BITS-1):0] data_out;
reg valid;
reg active;
reg [EXPR(ADD_STAGES-1):0] phase;
reg [EXPR(ADD_STAGES-1):0] cycle;
wire phaseCX;
wire cycleCX;
assign phaseCX = phase == 'dCX;
assign cycleCX = cycle == 'dCX;
assign k =
phaseOX ? kOX :
kORDER;
//a single multiplayer and a single adder
assign mult = k * data_in;
assign add = mult + (
addOX ? multOX :
multORDER);
always @(posedge clk or posedge reset)
if (reset)
active <= #FFD 1'b0;
else if (clken)
active <= #FFD 1'b1;
else if (phase == 'dORDER)
active <= #FFD 1'b0;
always @(posedge clk or posedge reset)
if (reset)
phase <= #FFD {ADD_STAGES{1'b0}};
else if (phase == 'dORDER)
phase <= #FFD {ADD_STAGES{1'b0}};
else if (active)
phase <= #FFD phase + 1'b1;
always @(posedge clk or posedge reset)
if (reset)
cycle <= #FFD {ADD_STAGES{1'b0}};
else if (phase == 'dORDER)
begin
if (cycle == 'dORDER)
cycle <= #FFD {ADD_STAGES{1'b0}};
else
cycle <= cycle + 1'b1;
end
LOOP PX COEFF_NUM
assign addPX = active & (
(phaseEXPR((COEFF_NUM+PX-CX)%COEFF_NUM) && cycleCX) ||
STOMP || );
always @(posedge clk or posedge reset)
if (reset)
multPX <= #FFD {MULT_BITS{1'b0}};
else if (phase1 && cyclePX)
multPX <= #FFD {MULT_BITS{1'b0}};
else if (addPX)
multPX <= #FFD add;
ENDLOOP PX
 
//sample when valid
always @(posedge clk or posedge reset)
if (reset)
mult_sum <= #FFD {DOUT_BITS{1'b0}};
else if (phase1)
begin
LOOP CX COEFF_NUM
if (cycleCX)
mult_sum <= #FFD multCX;
else
STOMP NEWLINE
ENDLOOP CX
STOMP else
end
 
//sync to clock enable
always @(posedge clk or posedge reset)
if (reset)
begin
data_out <= #FFD {DOUT_BITS{1'b0}};
valid <= #FFD 1'b0;
end
else if (clken)
begin
data_out <= #FFD mult_sum;
valid <= #FFD 1'b1;
end
else
begin
valid <= #FFD 1'b0;
end
endmodule
 
 
 
 
 
/robust_fir/trunk/src/base/fir.v
1,83 → 1,83
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTDIR fir_NAME
OUTFILE fir_NAME.v
INCLUDE def_fir.txt
 
LIST firlist_NAME.txt
 
ITER CX COEFF_NUM
 
## Expected RobustVerilog parameters:
## SWAP ORDER val - order of FIR
## SWAP COEFF_BITS val - precision of coeeficients (bit num)
## SWAP DIN_BITS val - precision of input data (bit num)
## SWAP MAC_NUM val - number of multiplayers (determines architecture)
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Number of serial FIR sons = MAC_NUM
// Number of multiplayers = MAC_NUM
// Architecture = ARCH
// Sum of Products Latency = LATENCY
 
 
module fir_NAME (PORTS);
input clk;
input reset;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
input valid_in;
output valid_out;
IFDEF MAC_EQ(1)
CREATE fir_serial.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
fir_serial_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ELSE MAC_EQ(1)
IFDEF MAC_EQ(COEFF_NUM)
CREATE fir_parallel.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
fir_parallel_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ELSE MAC_EQ(COEFF_NUM)
CREATE fir_Nserial.v def_fir_Nserial.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS) DEFCMD(SWAP CONST(MAC_NUM) MAC_NUM)
fir_MAC_NUMserial_TOPO fir(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ENDIF MAC_EQ(COEFF_NUM)
ENDIF MAC_EQ(1)
endmodule
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTDIR PREFIX_NAME
OUTFILE PREFIX_NAME.v
INCLUDE def_fir.txt
 
LIST firlist_NAME.txt
 
ITER CX COEFF_NUM
 
## Expected RobustVerilog parameters:
## SWAP ORDER val - order of FIR
## SWAP COEFF_BITS val - precision of coeeficients (bit num)
## SWAP DIN_BITS val - precision of input data (bit num)
## SWAP MAC_NUM val - number of multiplayers (determines architecture)
 
// Built In Parameters:
//
// Filter Order = ORDER
// Input Precision = DIN_BITS
// Coefficient Precision = COEFF_BITS
// Number of serial FIR sons = MAC_NUM
// Number of multiplayers = MAC_NUM
// Architecture = ARCH
// Sum of Products Latency = LATENCY
 
 
module PREFIX_NAME (PORTS);
input clk;
input reset;
input [EXPR(COEFF_BITS-1):0] kCX;
input [EXPR(DIN_BITS-1):0] data_in;
output [EXPR(DOUT_BITS-1):0] data_out;
input valid_in;
output valid_out;
IFDEF MAC_EQ(1)
CREATE fir_serial.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
PREFIX_serial_TOPO PREFIX(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ELSE MAC_EQ(1)
IFDEF MAC_EQ(COEFF_NUM)
CREATE fir_parallel.v def_fir_basic.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS)
PREFIX_parallel_TOPO PREFIX(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ELSE MAC_EQ(COEFF_NUM)
CREATE fir_Nserial.v def_fir_Nserial.txt DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS) DEFCMD(SWAP CONST(MAC_NUM) MAC_NUM)
PREFIX_MAC_NUMserial_TOPO PREFIX(clk, reset, valid_in, CONCAT.REV(kCX ,), data_in, data_out, valid_out);
ENDIF MAC_EQ(COEFF_NUM)
ENDIF MAC_EQ(1)
endmodule
/robust_fir/trunk/src/base/fir_top.v
1,11 → 1,48
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
OUTFILE NULL
 
DEFLINE SWAP FIR(WW,XX,YY,ZZ) CREATE.USER fir.v DEFCMD(SWAP.USER ORDER WW) DEFCMD(SWAP.USER COEFF_BITS XX) DEFCMD(SWAP.USER DIN_BITS YY) DEFCMD(SWAP.USER MAC_NUM ZZ)
STARTDEF
 
SWAP.GLOBAL MODEL_NAME FIR
 
##FIR(ORDER, COEFF_BITS, DIN_BITS, MAC_NUM)
FIR(3, 12, 8, 4) ##parallel
FIR(3, 16, 24, 2) ##Nserial
FIR(7, 8, 32, 1) ##Serial
STARTUSER
 
SWAP.GLOBAL.USER PREFIX fir
SWAP.USER FIR(ORDER,COEFF_BITS,DIN_BITS,MAC_NUM) SRCLINE CREATE fir.v DEFCMD(SWAP CONST(ORDER) ORDER) DEFCMD(SWAP CONST(COEFF_BITS) COEFF_BITS) DEFCMD(SWAP CONST(DIN_BITS) DIN_BITS) DEFCMD(SWAP CONST(MAC_NUM) MAC_NUM) ##FIR Filters
 
FIR(3, 12, 8, 4) ##parallel
FIR(3, 16, 24, 2) ##Nserial
FIR(8, 5, 32, 3) ##Nserial
FIR(7, 8, 32, 1) ##Serial
 
ENDDEF
 
/robust_fir/trunk/src/base/def_fir.txt
27,12 → 27,10
//// ////
//////////////////////////////////////////////////////////////////##>
 
REQUIRE(1.4)
REQUIRE(1.5)
 
INCLUDE def_fir_basic.txt
 
STARTUSER
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
##check all input parameters have been given

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