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https://opencores.org/ocsvn/rsa/rsa/trunk
Subversion Repositories rsa
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/tags/Test/rtl/vhdl/rsacypher.vhd
File deleted
/tags/Test/rtl/vhdl/modmult.vhd
File deleted
/tags/work/rtl/vhdl/rsacypher.vhd
File deleted
/tags/work/rtl/vhdl/modmult.vhd
File deleted
/trunk/rtl/vhdl/rsacypher.vhd
File deleted
/rsa/trunk/rtl/vhdl/rsacypher.vhd
0,0 → 1,209
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
-- Uncomment the following lines to use the declarations that are |
-- provided for instantiating Xilinx primitive components. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity RSACypher is |
Generic (KEYSIZE: integer := 1024); |
Port (indata: in std_logic_vector(KEYSIZE-1 downto 0); |
inExp: in std_logic_vector(KEYSIZE-1 downto 0); |
inMod: in std_logic_vector(KEYSIZE-1 downto 0); |
cypher: out std_logic_vector(KEYSIZE-1 downto 0); |
clk: in std_logic; |
ds: in std_logic; |
reset: in std_logic; |
ready: out std_logic |
); |
end RSACypher; |
|
architecture Behavioral of RSACypher is |
attribute keep: string; |
|
component modmult32 is |
Generic (MPWID: integer); |
Port ( mpand : in std_logic_vector(MPWID-1 downto 0); |
mplier : in std_logic_vector(MPWID-1 downto 0); |
modulus : in std_logic_vector(MPWID-1 downto 0); |
product : out std_logic_vector(MPWID-1 downto 0); |
clk : in std_logic; |
ds : in std_logic; |
reset : in std_logic; |
ready: out std_logic); |
end component; |
|
--signal message: std_logic_vector(KEYSIZE-1 downto 0); |
--signal exponent: std_logic_vector(KEYSIZE-1 downto 0); |
signal modreg: std_logic_vector(KEYSIZE-1 downto 0); |
signal root: std_logic_vector(KEYSIZE-1 downto 0); |
signal square: std_logic_vector(KEYSIZE-1 downto 0); |
signal sqrin: std_logic_vector(KEYSIZE-1 downto 0); |
signal tempin: std_logic_vector(KEYSIZE-1 downto 0); |
signal tempout: std_logic_vector(KEYSIZE-1 downto 0); |
--signal cypher: std_logic_vector(KEYSIZE-1 downto 0); |
signal count: std_logic_vector(KEYSIZE-1 downto 0); |
|
signal multrdy, sqrrdy, bothrdy: std_logic; |
signal multgo, sqrgo: std_logic; |
--signal multds, sqrds: std_logic; |
signal done: std_logic; |
|
attribute keep of multrdy: signal is "true"; |
attribute keep of sqrrdy: signal is "true"; |
attribute keep of bothrdy: signal is "true"; |
attribute keep of multgo: signal is "true"; |
attribute keep of sqrgo: signal is "true"; |
|
|
begin |
|
ready <= done; |
bothrdy <= multrdy and sqrrdy; |
|
modmult: modmult32 |
Generic Map(MPWID => KEYSIZE) |
Port Map(mpand => tempin, |
mplier => sqrin, |
modulus => modreg, |
product => tempout, |
clk => clk, |
ds => multgo, |
reset => reset, |
ready => multrdy); |
|
modsqr: modmult32 |
Generic Map(MPWID => KEYSIZE) |
Port Map(mpand => root, |
mplier => root, |
modulus => modreg, |
product => square, |
clk => clk, |
ds => multgo, |
reset => reset, |
ready =>sqrrdy); |
|
mngcount: process (clk, reset, done, ds, count, bothrdy) is |
begin |
-- handles DONE and COUNT signals |
|
if reset = '1' then |
count <= (others => '0'); |
done <= '1'; |
elsif rising_edge(clk) then |
if done = '1' then |
if ds = '1' then |
-- first time through |
count <= '0' & inExp(KEYSIZE-1 downto 1); |
done <= '0'; |
end if; |
-- after first time |
elsif count = 0 then |
if bothrdy = '1' and multgo = '0' then |
cypher <= tempout; -- set output value |
-- if ds = '0' then |
done <= '1'; |
end if; |
-- elsif sqrrdy = '1' and multrdy = '1' then |
elsif bothrdy = '1' then |
if multgo = '0' then |
count <= '0' & count(KEYSIZE-1 downto 1); |
end if; |
end if; |
end if; |
|
end process mngcount; |
|
|
setupsqr: process (clk, reset, done, ds) is |
begin |
|
if reset = '1' then |
root <= (others => '0'); |
modreg <= (others => '0'); |
elsif rising_edge(clk) then |
if done = '1' then |
if ds = '1' then |
---- first time through |
modreg <= inMod; |
root <= indata; |
end if; |
---- after first time |
else |
root <= square; |
end if; |
end if; |
|
end process setupsqr; |
|
setupmult: process (clk, reset, done, ds) is |
begin |
|
if reset = '1' then |
tempin <= (others => '0'); |
sqrin <= (others => '0'); |
modreg <= (others => '0'); |
elsif rising_edge(clk) then |
if done = '1' then |
if ds = '1' then |
-- first time through |
if inExp(0) = '1' then |
tempin <= indata; |
else |
tempin(KEYSIZE-1 downto 1) <= (others => '0'); |
tempin(0) <= '1'; |
end if; |
modreg <= inMod; |
sqrin(KEYSIZE-1 downto 1) <= (others => '0'); |
sqrin(0) <= '1'; |
end if; |
-- after first time |
else |
tempin <= tempout; |
if count(0) = '1' then |
sqrin <= square; |
else |
sqrin(KEYSIZE-1 downto 1) <= (others => '0'); |
sqrin(0) <= '1'; |
end if; |
end if; |
end if; |
|
end process setupmult; |
|
crypto: process (clk, reset, done, ds, count, bothrdy) is |
begin |
|
if reset = '1' then |
multgo <= '0'; |
-- sqrgo <= '0'; |
elsif rising_edge(clk) then |
if done = '1' then |
if ds = '1' then |
-- first time through |
multgo <= '1'; |
-- sqrgo <= '1'; |
end if; |
-- after first time |
elsif count /= 0 then |
if bothrdy = '1' then |
multgo <= '1'; |
-- sqrgo <= '1'; |
end if; |
-- else |
end if; |
if multgo = '1' then |
multgo <= '0'; |
end if; |
-- if sqrgo = '1' then |
-- sqrgo <= '0'; |
-- end if; |
-- end if; |
end if; |
|
end process crypto; |
|
end Behavioral; |
rsa/trunk
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: rsa/web_uploads
===================================================================
--- rsa/web_uploads (nonexistent)
+++ rsa/web_uploads (revision 6)
rsa/web_uploads
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: rsa/branches
===================================================================
--- rsa/branches (nonexistent)
+++ rsa/branches (revision 6)
rsa/branches
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: rsa/tags/work/rtl/vhdl/rsacypher.vhd
===================================================================
--- rsa/tags/work/rtl/vhdl/rsacypher.vhd (nonexistent)
+++ rsa/tags/work/rtl/vhdl/rsacypher.vhd (revision 6)
@@ -0,0 +1,209 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity RSACypher is
+ Generic (KEYSIZE: integer := 1024);
+ Port (indata: in std_logic_vector(KEYSIZE-1 downto 0);
+ inExp: in std_logic_vector(KEYSIZE-1 downto 0);
+ inMod: in std_logic_vector(KEYSIZE-1 downto 0);
+ cypher: out std_logic_vector(KEYSIZE-1 downto 0);
+ clk: in std_logic;
+ ds: in std_logic;
+ reset: in std_logic;
+ ready: out std_logic
+ );
+end RSACypher;
+
+architecture Behavioral of RSACypher is
+attribute keep: string;
+
+component modmult32 is
+ Generic (MPWID: integer);
+ Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
+ mplier : in std_logic_vector(MPWID-1 downto 0);
+ modulus : in std_logic_vector(MPWID-1 downto 0);
+ product : out std_logic_vector(MPWID-1 downto 0);
+ clk : in std_logic;
+ ds : in std_logic;
+ reset : in std_logic;
+ ready: out std_logic);
+end component;
+
+--signal message: std_logic_vector(KEYSIZE-1 downto 0);
+--signal exponent: std_logic_vector(KEYSIZE-1 downto 0);
+signal modreg: std_logic_vector(KEYSIZE-1 downto 0);
+signal root: std_logic_vector(KEYSIZE-1 downto 0);
+signal square: std_logic_vector(KEYSIZE-1 downto 0);
+signal sqrin: std_logic_vector(KEYSIZE-1 downto 0);
+signal tempin: std_logic_vector(KEYSIZE-1 downto 0);
+signal tempout: std_logic_vector(KEYSIZE-1 downto 0);
+--signal cypher: std_logic_vector(KEYSIZE-1 downto 0);
+signal count: std_logic_vector(KEYSIZE-1 downto 0);
+
+signal multrdy, sqrrdy, bothrdy: std_logic;
+signal multgo, sqrgo: std_logic;
+--signal multds, sqrds: std_logic;
+signal done: std_logic;
+
+attribute keep of multrdy: signal is "true";
+attribute keep of sqrrdy: signal is "true";
+attribute keep of bothrdy: signal is "true";
+attribute keep of multgo: signal is "true";
+attribute keep of sqrgo: signal is "true";
+
+
+begin
+
+ ready <= done;
+ bothrdy <= multrdy and sqrrdy;
+
+ modmult: modmult32
+ Generic Map(MPWID => KEYSIZE)
+ Port Map(mpand => tempin,
+ mplier => sqrin,
+ modulus => modreg,
+ product => tempout,
+ clk => clk,
+ ds => multgo,
+ reset => reset,
+ ready => multrdy);
+
+ modsqr: modmult32
+ Generic Map(MPWID => KEYSIZE)
+ Port Map(mpand => root,
+ mplier => root,
+ modulus => modreg,
+ product => square,
+ clk => clk,
+ ds => multgo,
+ reset => reset,
+ ready =>sqrrdy);
+
+ mngcount: process (clk, reset, done, ds, count, bothrdy) is
+ begin
+ -- handles DONE and COUNT signals
+
+ if reset = '1' then
+ count <= (others => '0');
+ done <= '1';
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ count <= '0' & inExp(KEYSIZE-1 downto 1);
+ done <= '0';
+ end if;
+-- after first time
+ elsif count = 0 then
+ if bothrdy = '1' and multgo = '0' then
+ cypher <= tempout; -- set output value
+-- if ds = '0' then
+ done <= '1';
+ end if;
+-- elsif sqrrdy = '1' and multrdy = '1' then
+ elsif bothrdy = '1' then
+ if multgo = '0' then
+ count <= '0' & count(KEYSIZE-1 downto 1);
+ end if;
+ end if;
+ end if;
+
+ end process mngcount;
+
+
+ setupsqr: process (clk, reset, done, ds) is
+ begin
+
+ if reset = '1' then
+ root <= (others => '0');
+ modreg <= (others => '0');
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+---- first time through
+ modreg <= inMod;
+ root <= indata;
+ end if;
+---- after first time
+ else
+ root <= square;
+ end if;
+ end if;
+
+ end process setupsqr;
+
+ setupmult: process (clk, reset, done, ds) is
+ begin
+
+ if reset = '1' then
+ tempin <= (others => '0');
+ sqrin <= (others => '0');
+ modreg <= (others => '0');
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ if inExp(0) = '1' then
+ tempin <= indata;
+ else
+ tempin(KEYSIZE-1 downto 1) <= (others => '0');
+ tempin(0) <= '1';
+ end if;
+ modreg <= inMod;
+ sqrin(KEYSIZE-1 downto 1) <= (others => '0');
+ sqrin(0) <= '1';
+ end if;
+-- after first time
+ else
+ tempin <= tempout;
+ if count(0) = '1' then
+ sqrin <= square;
+ else
+ sqrin(KEYSIZE-1 downto 1) <= (others => '0');
+ sqrin(0) <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process setupmult;
+
+ crypto: process (clk, reset, done, ds, count, bothrdy) is
+ begin
+
+ if reset = '1' then
+ multgo <= '0';
+-- sqrgo <= '0';
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ multgo <= '1';
+-- sqrgo <= '1';
+ end if;
+-- after first time
+ elsif count /= 0 then
+ if bothrdy = '1' then
+ multgo <= '1';
+-- sqrgo <= '1';
+ end if;
+-- else
+ end if;
+ if multgo = '1' then
+ multgo <= '0';
+ end if;
+-- if sqrgo = '1' then
+-- sqrgo <= '0';
+-- end if;
+-- end if;
+ end if;
+
+ end process crypto;
+
+end Behavioral;
Index: rsa/tags/work/rtl/vhdl/modmult.vhd
===================================================================
--- rsa/tags/work/rtl/vhdl/modmult.vhd (nonexistent)
+++ rsa/tags/work/rtl/vhdl/modmult.vhd (revision 6)
@@ -0,0 +1,142 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity modmult32 is
+ Generic (MPWID: integer := 32);
+ Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
+ mplier : in std_logic_vector(MPWID-1 downto 0);
+ modulus : in std_logic_vector(MPWID-1 downto 0);
+ product : out std_logic_vector(MPWID-1 downto 0);
+ clk : in std_logic;
+ ds : in std_logic;
+ reset : in std_logic;
+ ready : out std_logic);
+end modmult32;
+
+architecture modmult of modmult32 is
+
+signal mpreg: std_logic_vector(MPWID-1 downto 0);
+signal mcreg, mcreg1, mcreg2: std_logic_vector(MPWID+1 downto 0);
+signal modreg1, modreg2: std_logic_vector(MPWID+1 downto 0);
+signal prodreg, prodreg1, prodreg2, prodreg3, prodreg4: std_logic_vector(MPWID+1 downto 0);
+
+signal count: integer;
+signal modstate: std_logic_vector(1 downto 0);
+signal first: std_logic;
+
+begin
+
+
+ product <= prodreg4(MPWID-1 downto 0);
+
+ with mpreg(0) select
+ prodreg1 <= prodreg + mcreg when '1',
+ prodreg when others;
+
+ prodreg2 <= prodreg1 - modreg1;
+ prodreg3 <= prodreg1 - modreg2;
+
+ modstate <= prodreg3(mpwid+1) & prodreg2(mpwid+1);
+
+ with modstate select
+ prodreg4 <= prodreg1 when "11",
+ prodreg2 when "10",
+ prodreg3 when others;
+
+ mcreg1 <= mcreg - modreg1;
+
+ with mcreg1(MPWID) select
+ mcreg2 <= mcreg when '1',
+ mcreg1 when others;
+
+ ready <= first;
+
+ combine: process (clk, first, ds, count, mpreg, reset) is
+
+ begin
+
+ if reset = '1' then
+ first <= '1';
+ elsif rising_edge(clk) then
+ if first = '1' then
+ if ds = '1' then
+ mpreg <= mplier;
+ mcreg <= "00" & mpand;
+ modreg1 <= "00" & modulus;
+ modreg2 <= '0' & modulus & '0';
+ prodreg <= (others => '0');
+ count <= MPWID;
+ first <= '0';
+ end if;
+ else
+ if count = 0 or mpreg = 0 then
+ first <= '1';
+ else
+ count <= count - 1;
+ mcreg <= mcreg2(MPWID downto 0) & '0';
+ mpreg <= '0' & mpreg(MPWID-1 downto 1);
+ prodreg <= prodreg4;
+ end if;
+ end if;
+ end if;
+
+ end process combine;
+
+-- combine: process (clk, reset) is
+--
+-- variable mpvar: std_logic_vector(MPWID downto 0);
+-- variable mcvar: std_logic_vector(MPWID downto 0);
+-- variable prodvar: std_logic_vector(MPWID downto 0);
+-- variable count: integer;
+--
+-- begin
+--
+-- if reset = '1' then
+-- first <= '1';
+-- elsif rising_edge(clk) then
+-- if first = '1' then
+-- if ds = '1' then
+-- mpvar := '0' & mplier;
+-- mcvar := '0' & mpand;
+-- modreg1 <= '0' & modulus;
+-- modreg2 <= modulus & '0';
+-- prodvar := (others => '0');
+-- count := MPWID;
+-- first <= '0';
+-- end if;
+-- else
+-- count := count - 1;
+--
+-- if mcvar > modreg then
+-- mcvar := mcvar - modreg;
+-- end if;
+--
+-- if mpvar(0) = '1' then
+-- prodvar1 := prodvar + mcvar;
+-- end if;
+--
+-- if prodvar > modreg then
+-- prodvar := prodvar - modreg;
+-- end if;
+--
+-- mcvar := mcvar(MPWID-1 downto 0) & '0';
+--
+-- mpvar := '0' & mpvar(MPWID downto 1);
+--
+-- if count = 0 or mpvar = 0 then
+-- first <= '1';
+-- product <= prodvar(MPWID-1 downto 0);
+-- end if;
+-- end if;
+-- end if;
+--
+-- end process combine;
+
+end modmult;
Index: rsa/tags/Test/rtl/vhdl/rsacypher.vhd
===================================================================
--- rsa/tags/Test/rtl/vhdl/rsacypher.vhd (nonexistent)
+++ rsa/tags/Test/rtl/vhdl/rsacypher.vhd (revision 6)
@@ -0,0 +1,209 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity RSACypher is
+ Generic (KEYSIZE: integer := 1024);
+ Port (indata: in std_logic_vector(KEYSIZE-1 downto 0);
+ inExp: in std_logic_vector(KEYSIZE-1 downto 0);
+ inMod: in std_logic_vector(KEYSIZE-1 downto 0);
+ cypher: out std_logic_vector(KEYSIZE-1 downto 0);
+ clk: in std_logic;
+ ds: in std_logic;
+ reset: in std_logic;
+ ready: out std_logic
+ );
+end RSACypher;
+
+architecture Behavioral of RSACypher is
+attribute keep: string;
+
+component modmult32 is
+ Generic (MPWID: integer);
+ Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
+ mplier : in std_logic_vector(MPWID-1 downto 0);
+ modulus : in std_logic_vector(MPWID-1 downto 0);
+ product : out std_logic_vector(MPWID-1 downto 0);
+ clk : in std_logic;
+ ds : in std_logic;
+ reset : in std_logic;
+ ready: out std_logic);
+end component;
+
+--signal message: std_logic_vector(KEYSIZE-1 downto 0);
+--signal exponent: std_logic_vector(KEYSIZE-1 downto 0);
+signal modreg: std_logic_vector(KEYSIZE-1 downto 0);
+signal root: std_logic_vector(KEYSIZE-1 downto 0);
+signal square: std_logic_vector(KEYSIZE-1 downto 0);
+signal sqrin: std_logic_vector(KEYSIZE-1 downto 0);
+signal tempin: std_logic_vector(KEYSIZE-1 downto 0);
+signal tempout: std_logic_vector(KEYSIZE-1 downto 0);
+--signal cypher: std_logic_vector(KEYSIZE-1 downto 0);
+signal count: std_logic_vector(KEYSIZE-1 downto 0);
+
+signal multrdy, sqrrdy, bothrdy: std_logic;
+signal multgo, sqrgo: std_logic;
+--signal multds, sqrds: std_logic;
+signal done: std_logic;
+
+attribute keep of multrdy: signal is "true";
+attribute keep of sqrrdy: signal is "true";
+attribute keep of bothrdy: signal is "true";
+attribute keep of multgo: signal is "true";
+attribute keep of sqrgo: signal is "true";
+
+
+begin
+
+ ready <= done;
+ bothrdy <= multrdy and sqrrdy;
+
+ modmult: modmult32
+ Generic Map(MPWID => KEYSIZE)
+ Port Map(mpand => tempin,
+ mplier => sqrin,
+ modulus => modreg,
+ product => tempout,
+ clk => clk,
+ ds => multgo,
+ reset => reset,
+ ready => multrdy);
+
+ modsqr: modmult32
+ Generic Map(MPWID => KEYSIZE)
+ Port Map(mpand => root,
+ mplier => root,
+ modulus => modreg,
+ product => square,
+ clk => clk,
+ ds => multgo,
+ reset => reset,
+ ready =>sqrrdy);
+
+ mngcount: process (clk, reset, done, ds, count, bothrdy) is
+ begin
+ -- handles DONE and COUNT signals
+
+ if reset = '1' then
+ count <= (others => '0');
+ done <= '1';
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ count <= '0' & inExp(KEYSIZE-1 downto 1);
+ done <= '0';
+ end if;
+-- after first time
+ elsif count = 0 then
+ if bothrdy = '1' and multgo = '0' then
+ cypher <= tempout; -- set output value
+-- if ds = '0' then
+ done <= '1';
+ end if;
+-- elsif sqrrdy = '1' and multrdy = '1' then
+ elsif bothrdy = '1' then
+ if multgo = '0' then
+ count <= '0' & count(KEYSIZE-1 downto 1);
+ end if;
+ end if;
+ end if;
+
+ end process mngcount;
+
+
+ setupsqr: process (clk, reset, done, ds) is
+ begin
+
+ if reset = '1' then
+ root <= (others => '0');
+ modreg <= (others => '0');
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+---- first time through
+ modreg <= inMod;
+ root <= indata;
+ end if;
+---- after first time
+ else
+ root <= square;
+ end if;
+ end if;
+
+ end process setupsqr;
+
+ setupmult: process (clk, reset, done, ds) is
+ begin
+
+ if reset = '1' then
+ tempin <= (others => '0');
+ sqrin <= (others => '0');
+ modreg <= (others => '0');
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ if inExp(0) = '1' then
+ tempin <= indata;
+ else
+ tempin(KEYSIZE-1 downto 1) <= (others => '0');
+ tempin(0) <= '1';
+ end if;
+ modreg <= inMod;
+ sqrin(KEYSIZE-1 downto 1) <= (others => '0');
+ sqrin(0) <= '1';
+ end if;
+-- after first time
+ else
+ tempin <= tempout;
+ if count(0) = '1' then
+ sqrin <= square;
+ else
+ sqrin(KEYSIZE-1 downto 1) <= (others => '0');
+ sqrin(0) <= '1';
+ end if;
+ end if;
+ end if;
+
+ end process setupmult;
+
+ crypto: process (clk, reset, done, ds, count, bothrdy) is
+ begin
+
+ if reset = '1' then
+ multgo <= '0';
+-- sqrgo <= '0';
+ elsif rising_edge(clk) then
+ if done = '1' then
+ if ds = '1' then
+-- first time through
+ multgo <= '1';
+-- sqrgo <= '1';
+ end if;
+-- after first time
+ elsif count /= 0 then
+ if bothrdy = '1' then
+ multgo <= '1';
+-- sqrgo <= '1';
+ end if;
+-- else
+ end if;
+ if multgo = '1' then
+ multgo <= '0';
+ end if;
+-- if sqrgo = '1' then
+-- sqrgo <= '0';
+-- end if;
+-- end if;
+ end if;
+
+ end process crypto;
+
+end Behavioral;
Index: rsa/tags/Test/rtl/vhdl/modmult.vhd
===================================================================
--- rsa/tags/Test/rtl/vhdl/modmult.vhd (nonexistent)
+++ rsa/tags/Test/rtl/vhdl/modmult.vhd (revision 6)
@@ -0,0 +1,142 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- Uncomment the following lines to use the declarations that are
+-- provided for instantiating Xilinx primitive components.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity modmult32 is
+ Generic (MPWID: integer := 32);
+ Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
+ mplier : in std_logic_vector(MPWID-1 downto 0);
+ modulus : in std_logic_vector(MPWID-1 downto 0);
+ product : out std_logic_vector(MPWID-1 downto 0);
+ clk : in std_logic;
+ ds : in std_logic;
+ reset : in std_logic;
+ ready : out std_logic);
+end modmult32;
+
+architecture modmult of modmult32 is
+
+signal mpreg: std_logic_vector(MPWID-1 downto 0);
+signal mcreg, mcreg1, mcreg2: std_logic_vector(MPWID+1 downto 0);
+signal modreg1, modreg2: std_logic_vector(MPWID+1 downto 0);
+signal prodreg, prodreg1, prodreg2, prodreg3, prodreg4: std_logic_vector(MPWID+1 downto 0);
+
+signal count: integer;
+signal modstate: std_logic_vector(1 downto 0);
+signal first: std_logic;
+
+begin
+
+
+ product <= prodreg4(MPWID-1 downto 0);
+
+ with mpreg(0) select
+ prodreg1 <= prodreg + mcreg when '1',
+ prodreg when others;
+
+ prodreg2 <= prodreg1 - modreg1;
+ prodreg3 <= prodreg1 - modreg2;
+
+ modstate <= prodreg3(mpwid+1) & prodreg2(mpwid+1);
+
+ with modstate select
+ prodreg4 <= prodreg1 when "11",
+ prodreg2 when "10",
+ prodreg3 when others;
+
+ mcreg1 <= mcreg - modreg1;
+
+ with mcreg1(MPWID) select
+ mcreg2 <= mcreg when '1',
+ mcreg1 when others;
+
+ ready <= first;
+
+ combine: process (clk, first, ds, count, mpreg, reset) is
+
+ begin
+
+ if reset = '1' then
+ first <= '1';
+ elsif rising_edge(clk) then
+ if first = '1' then
+ if ds = '1' then
+ mpreg <= mplier;
+ mcreg <= "00" & mpand;
+ modreg1 <= "00" & modulus;
+ modreg2 <= '0' & modulus & '0';
+ prodreg <= (others => '0');
+ count <= MPWID;
+ first <= '0';
+ end if;
+ else
+ if count = 0 or mpreg = 0 then
+ first <= '1';
+ else
+ count <= count - 1;
+ mcreg <= mcreg2(MPWID downto 0) & '0';
+ mpreg <= '0' & mpreg(MPWID-1 downto 1);
+ prodreg <= prodreg4;
+ end if;
+ end if;
+ end if;
+
+ end process combine;
+
+-- combine: process (clk, reset) is
+--
+-- variable mpvar: std_logic_vector(MPWID downto 0);
+-- variable mcvar: std_logic_vector(MPWID downto 0);
+-- variable prodvar: std_logic_vector(MPWID downto 0);
+-- variable count: integer;
+--
+-- begin
+--
+-- if reset = '1' then
+-- first <= '1';
+-- elsif rising_edge(clk) then
+-- if first = '1' then
+-- if ds = '1' then
+-- mpvar := '0' & mplier;
+-- mcvar := '0' & mpand;
+-- modreg1 <= '0' & modulus;
+-- modreg2 <= modulus & '0';
+-- prodvar := (others => '0');
+-- count := MPWID;
+-- first <= '0';
+-- end if;
+-- else
+-- count := count - 1;
+--
+-- if mcvar > modreg then
+-- mcvar := mcvar - modreg;
+-- end if;
+--
+-- if mpvar(0) = '1' then
+-- prodvar1 := prodvar + mcvar;
+-- end if;
+--
+-- if prodvar > modreg then
+-- prodvar := prodvar - modreg;
+-- end if;
+--
+-- mcvar := mcvar(MPWID-1 downto 0) & '0';
+--
+-- mpvar := '0' & mpvar(MPWID downto 1);
+--
+-- if count = 0 or mpvar = 0 then
+-- first <= '1';
+-- product <= prodvar(MPWID-1 downto 0);
+-- end if;
+-- end if;
+-- end if;
+--
+-- end process combine;
+
+end modmult;
Index: rsa/tags
===================================================================
--- rsa/tags (nonexistent)
+++ rsa/tags (revision 6)
rsa/tags
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##