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URL https://opencores.org/ocsvn/rtf8088/rtf8088/trunk

Subversion Repositories rtf8088

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /rtf8088
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/rtl/verilog/FETCH_DISP16.v
3,8 → 3,8
// - detch 16 bit displacement
//
//
// 2009-2012 Robert Finch
// robfinch[remove]@opencores.org
// 2009-2013 Robert Finch
// robfinch[remove]@finitron.ca
// Stratford
//
//
29,7 → 29,7
//
FETCH_DISP16:
begin
`INITIATE_CODE_READ;
code_read();
state <= FETCH_DISP16_ACK;
end
 
36,7 → 36,7
FETCH_DISP16_ACK:
if (ack_i) begin
state <= FETCH_DISP16a;
`PAUSE_CODE_READ
pause_code_read();
disp16[7:0] <= dat_i;
end
 
43,13 → 43,13
FETCH_DISP16a:
begin
state <= FETCH_DISP16a_ACK;
`INITIATE_CODE_READ
code_read();
end
 
FETCH_DISP16a_ACK:
if (ack_i) begin
state <= FETCH_DISP16b;
`TERMINATE_CODE_READ
term_code_read();
disp16[15:8] <= dat_i;
end
 
/trunk/rtl/verilog/ALU.v
3,8 → 3,8
// - perform datapath operations
//
//
// (C) 2009-2012 Robert Finch
// robfinch[remove]@opencores.org
// (C) 2009-2013 Robert Finch
// robfinch[remove]@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify
131,7 → 131,7
);
 
 
always @(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
always @* //(ir or ir2 or a or b or cf or af or al or ah or aldv10 or TTT)
begin
casex(ir)
`MOV_M2AL,`MOV_M2AX,`LDS,`LES:
156,7 → 156,7
`SCASB,`SCASW,`CMPSB,`CMPSW: alu_o <= a - b;
`INC_REG: alu_o <= a + 16'd1;
`DEC_REG: alu_o <= a - 16'd1;
`IMUL: alu_o <= w ? p : wp[15:0];
// `IMUL: alu_o <= w ? p : wp[15:0];
`ALU_I2R8:
case(TTT)
3'd0: alu_o <= a + b; // ADD
181,6 → 181,7
default: alu_o <= 16'h0000;
endcase
8'hF6,8'hF7:
begin
case(TTT)
3'd0: alu_o <= a & b; // TEST
3'd2: alu_o <= ~b; // NOT
191,6 → 192,7
3'd7: alu_o <= 16'h0000; // IDIV
default: alu_o <= 16'h0000;
endcase
end
`AAA:
if (al[3:0]>4'h9 || af) begin
alu_o[3:0] <= al[3:0] + 4'd6;
/trunk/rtl/verilog/rtf8088.v
279,7 → 279,7
`define REPZ 8'hF3
`define HLT 8'hF4
`define CMC 8'hF5
`define IMUL 8'b1111011x
//`define IMUL 8'b1111011x
`define CLC 8'hF8
`define STC 8'hF9
`define CLI 8'hFA
/trunk/rtl/verilog/LODS.v
3,9 → 3,9
// Fetch string data from memory.
//
//
// 2009,2010 Robert Finch
// 2009,2010,2013 Robert Finch
// Stratford
// robfinch<remove>@opencores.org
// robfinch<remove>@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify
27,7 → 27,7
if (w && (si==16'hFFFF) && !df) begin
ir <= `NOP;
int_num <= 8'd13;
state <= INT1;
state <= INT2;
end
else begin
cyc_type <= `CT_RDMEM;
/trunk/rtl/verilog/EXECUTE.v
189,23 → 189,23
sf <= resnw;
zf <= reszw;
end
`IMUL:
begin
state <= IFETCH;
wrregs <= 1'b1;
w <= 1'b1;
rrr <= 3'd0;
res <= alu_o;
if (w) begin
cf <= wp[31:16]!={16{resnw}};
vf <= wp[31:16]!={16{resnw}};
dx <= wp[31:16];
end
else begin
cf <= ah!={8{resnb}};
vf <= ah!={8{resnb}};
end
end
// `IMUL:
// begin
// state <= IFETCH;
// wrregs <= 1'b1;
// w <= 1'b1;
// rrr <= 3'd0;
// res <= alu_o;
// if (w) begin
// cf <= wp[31:16]!={16{resnw}};
// vf <= wp[31:16]!={16{resnw}};
// dx <= wp[31:16];
// end
// else begin
// cf <= ah!={8{resnb}};
// vf <= ah!={8{resnb}};
// end
// end
 
 
//-----------------------------------------------------------------
/trunk/rtl/verilog/WRITE_BACK.v
35,7 → 35,7
4'b1000: ax <= res;
4'b1001: cx <= res;
4'b1010: dx <= res;
4'b1011: bx <= res;
4'b1011: begin bx <= res; $display("BX <- %h", res); end
4'b1100: sp <= res;
4'b1101: bp <= res;
4'b1110: si <= res;
/trunk/rtl/verilog/DECODE.v
267,7 → 267,7
//-----------------------------------------------------------------
`MOV_M2AL,`MOV_M2AX,`MOV_AL2M,`MOV_AX2M,`CALL,`JMP:
begin
`INITIATE_CODE_READ
code_read();
state <= FETCH_DISP16_ACK;
end
 
284,7 → 284,7
if (ir==`LDS || ir==`LES)
w <= 1'b1;
if (fetch_modrm) begin
`INITIATE_CODE_READ
code_read();
state <= EACALC;
end
else
/trunk/rtl/verilog/STOS.v
3,9 → 3,9
// Store string data to memory.
//
//
// 2009-2012 Robert Finch
// 2009-2013 Robert Finch
// Stratford
// robfinch<remove>@opencores.org
// robfinch<remove>@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify
24,11 → 24,20
//=============================================================================
//
STOS:
`include "check_for_ints.v"
if (pe_nmi) begin
rst_nmi <= 1'b1;
int_num <= 8'h02;
ir <= `NOP;
state <= INT2;
end
else if (irq_i & ie) begin
ir <= `NOP;
state <= INTA0;
end
else if (w && (di==16'hFFFF)) begin
ir <= `NOP;
int_num <= 8'd13;
state <= INT1;
state <= INT2;
end
else if (repdone)
state <= IFETCH;
/trunk/rtl/verilog/CONTROL_LOGIC.v
3,8 → 3,8
// - assorted control logic
//
//
// (C) 2009,2010 Robert Finch
// robfinch[remove]@opencores.org
// (C) 2009,2010,2013 Robert Finch
// robfinch[remove]@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify
203,9 → 203,10
wire repz = prefix1==`REPZ || prefix2==`REPZ;
wire repnz = prefix1==`REPNZ || prefix2==`REPNZ;
 
// ZF is tested only for SCAS, CMPS
wire repdone =
((repz | repnz) & cxz) ||
(repz & !zf) ||
(repnz & zf)
(repz && !zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW)) ||
(repnz && zf && (ir==`SCASB||ir==`SCASW||ir==`CMPSB||ir==`CMPSW))
;
 
/trunk/rtl/verilog/IFETCH.v
2,8 → 2,8
// Fetch instruction
//
//
// (C) 2009,2010,2012 Robert Finch, Stratford
// robfinch<remove>@opencores.org
// (C) 2009,2010,2012,2013 Robert Finch, Stratford
// robfinch<remove>@finitron.ca
//
//
// This source file is free software: you can redistribute it and/or modify
36,7 → 36,13
//
IFETCH:
begin
$display("\r\n******************************************************");
$display("time: %d", $time);
$display("CSIP: %h", csip);
$display("AX=%h SI=%h", ax, si);
$display("BX=%h DI=%h", bx, di);
$display("CX=%h BP=%h", cx, bp);
$display("DX=%h SP=%h", dx, sp);
// Reset all instruction processing flags at instruction fetch
cyc_type <= `CT_PASSIVE;
mod <= 2'd0;
88,7 → 94,7
IFETCH_ACK:
if (ack_i) begin
nack_ir();
$display("IR: %h",dat_i);
$display("CSIP: %h IR: %h",csip,dat_i);
if (!hasPrefix)
ir_ip <= ip;
// ir_ip <= dat_i;
/trunk/rtl/verilog/FETCH_IMMEDIATE.v
6,7 → 6,7
//
//
// 2009-2012 Robert Finch
// robfinch[remove]@opencores.org
// robfinch[remove]@finitron.ca
// Stratford
//
// This source file is free software: you can redistribute it and/or modify
34,13 → 34,13
//
FETCH_IMM8:
begin
`INITIATE_CODE_READ
code_read();
state <= FETCH_IMM8_ACK;
end
 
FETCH_IMM8_ACK:
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
lock_o <= bus_locked;
b <= {{8{dat_i[7]}},dat_i};
state <= EXECUTE;
49,23 → 49,23
FETCH_IMM16:
begin
lock_o <= 1'b1;
`INITIATE_CODE_READ
code_read();
state <= FETCH_IMM16_ACK;
end
FETCH_IMM16_ACK:
if (ack_i) begin
`PAUSE_CODE_READ
pause_code_read();
state <= FETCH_IMM16a;
b[ 7:0] <= dat_i;
end
FETCH_IMM16a:
begin
`CONTINUE_CODE_READ
continue_code_read();
state <= FETCH_IMM16a_ACK;
end
FETCH_IMM16a_ACK:
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
lock_o <= bus_locked;
b[15:8] <= dat_i;
$display("Fetched #%h", {dat_i,b[7:0]});
/trunk/rtl/verilog/EACALC.v
35,7 → 35,7
// Terminate an outstanding MODRM fetch cycle
if (cyc_o) begin
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
mod <= dat_i[7:6];
rrr <= dat_i[5:3];
sreg3 <= dat_i[5:3];
139,8 → 139,21
begin
b <= rmo;
end
// The TEST instruction is the only one needing to fetch an immediate value.
8'hF6,8'hF7:
b <= rmo;
// 000 = TEST
// 010 = NOT
// 011 = NEG
// 100 = MUL
// 101 = IMUL
// 110 = DIV
// 111 = IDIV
if (rrr==3'b000) begin // TEST
a <= rmo;
state <= w ? FETCH_IMM16 : FETCH_IMM8;
end
else
b <= rmo;
default:
begin
if (d) begin
165,23 → 178,23
EACALC_DISP16:
begin
lock_o <= 1'b1;
`INITIATE_CODE_READ
code_read();
state <= EACALC_DISP16_ACK;
end
EACALC_DISP16_ACK:
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
disp16[7:0] <= dat_i;
state <= EACALC_DISP16a;
end
EACALC_DISP16a:
begin
`INITIATE_CODE_READ
code_read();
state <= EACALC_DISP16a_ACK;
end
EACALC_DISP16a_ACK:
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
lock_o <= bus_locked;
disp16[15:8] <= dat_i;
state <= EACALC1;
193,12 → 206,12
//
EACALC_DISP8:
begin
`INITIATE_CODE_READ
code_read();
state <= EACALC_DISP8_ACK;
end
EACALC_DISP8_ACK:
if (ack_i) begin
`TERMINATE_CODE_READ
term_code_read();
disp16 <= {{8{dat_i[7]}},dat_i};
state <= EACALC1;
end
222,7 → 235,7
endcase
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
end
8'h01:
234,13 → 247,13
endcase
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
end
8'h03:
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
else
state <= FETCH_DATA;
247,7 → 260,7
default:
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
else
state <= FETCH_DATA;
256,7 → 269,7
`MOV_I16M:
if (ip==16'hFFFF) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
else
state <= FETCH_IMM16;
274,7 → 287,7
$display("EACALC1: state <= STORE_DATA");
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
else begin
res <= rrro;
286,7 → 299,7
$display("EACALC1: state <= FETCH_DATA");
if (w && (offsdisp==16'hFFFF)) begin
int_num <= 8'h0d;
state <= INT;
state <= INT2;
end
else
state <= FETCH_DATA;

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