URL
https://opencores.org/ocsvn/rtfsimpleuart/rtfsimpleuart/trunk
Subversion Repositories rtfsimpleuart
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- This comparison shows the changes necessary to convert path
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- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/rtfsimpleuart/trunk/doc/rtfSimpleUartWishboneDatasheet.txt
0,0 → 1,35
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|WISHBONE Datasheet |
|WISHBONE SoC Architecture Specification, Revision B.3 |
| |
|Description: Specifications: |
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|General Description: simple UART core |
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|Supported Cycles: SLAVE,READ/WRITE |
| SLAVE,BLOCK READ/WRITE |
| SLAVE,RMW |
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|Data port, size: 8 bit |
|Data port, granularity: 8 bit |
|Data port, maximum operand size: 8 bit |
|Data transfer ordering: Undefined |
|Data transfer sequencing: Undefined |
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|Clock frequency constraints: none |
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|Supported signal list and Signal Name WISHBONE equiv. |
|cross reference to equivalent ack_o ACK_O |
|WISHBONE signals adr_i[3:0] ADR_I() |
| clk_i CLK_I |
| rst_i RST_I() |
| dat_i(7:0) DAT_I() |
| dat_o(7:0) DAT_O() |
| cyc_i CYC_I |
| stb_i STB_I |
| we_i WE_I |
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|Special requirements: |
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