OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

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  • This comparison shows the changes necessary to convert path 
    /s1_core
    from Rev 110 to Rev 111
    ↔ Reverse comparison
  •

Rev 110 → Rev 111

/trunk/tools/bin/s1_sim_run
0,0 → 1,27
#!/bin/bash
 
set -e
if ( (test $# != 1) || ((test $1 != "icarus") && (test $1 != "vcs")) ) then
echo "Usage: $0 {icarus|vcs}"
exit 1
fi
test_var S1_ROOT
 
echo -e "Running simulation using $1"
cd $S1_ROOT/run/sim/$1
ln -f -s $S1_ROOT/tests/boot/rom_harness.hex .
ln -f -s $S1_ROOT/tests/ram_harness.hex .
./testbench 2>&1 | tee sim.log
 
#if(test $1 == "icarus") then
#fi
 
#if(test $1 == "vcs") then
#fi
 
echo -e "Simulation with $1 completed!"
echo -e "To see the output:"
echo -e "less $S1_ROOT/run/sim/$1/sim.log"
echo -e "gtkwave $S1_ROOT/run/sim/$1/trace.vcd"
 
 
trunk/tools/bin/s1_sim_run Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/s1_synth =================================================================== --- trunk/tools/bin/s1_synth (revision 110) +++ trunk/tools/bin/s1_synth (revision 111) @@ -1,10 +1,10 @@ #!/bin/bash +set -e if ( (test $# != 1) || ((test $1 != "xst") && (test $1 != "fpga") && (test $1 != "dc")) ) then echo "Usage: $0 {xst|fpga|dc}" - exit 1; + exit 1 fi - test_var S1_ROOT echo -e "Synthesizing the design using $1"
trunk/tools/bin/s1_synth Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/tools/bin/s1_sim_build =================================================================== --- trunk/tools/bin/s1_sim_build (revision 110) +++ trunk/tools/bin/s1_sim_build (revision 111) @@ -1,10 +1,10 @@ #!/bin/bash +set -e if ( (test $# != 1) || ((test $1 != "icarus") && (test $1 != "vcs")) ) then echo "Usage: $0 {icarus|vcs}" - exit 1; + exit 1 fi - test_var S1_ROOT echo -e "Building design and testbench using $1"
trunk/tools/bin/s1_sim_build Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sourceme =================================================================== --- trunk/sourceme (revision 110) +++ trunk/sourceme (revision 111) @@ -1,8 +1,10 @@ +# Bash sourceme file. +# Please set the environment variables in this file, source it and then run 'update_filelist'. # General paths settings -export S1_ROOT=~/s1_core/trunk -export T1_ROOT=/opt/opensparc-t1 -export PATH=.:$S1_ROOT/tools/bin:$PATH +export S1_ROOT=/home/ubuntu/Design/OpenCores/s1_core/trunk +export T1_ROOT=/home/ubuntu/Design/SunMicrosystems/OpenSPARC-T1 +export PATH=$PATH:$S1_ROOT/tools/bin # Filelist names export FILELIST_ICARUS=$S1_ROOT/hdl/filelist.icarus @@ -11,9 +13,4 @@ export FILELIST_DC=$S1_ROOT/hdl/filelist.dc export FILELIST_XST=$S1_ROOT/hdl/filelist.xst -# Alias to quickly "Change Directory to Design"... -alias cdd='cd $S1_ROOT' -# Reminder for enviroment variables -echo "Please set the environment variables in this file and then run 'update_filelist'." -
/trunk/hdl/filelist.dc
1,139 → 1,139
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
analyze -format verilog -define { FPGA_SYN , FPGA_SYN_1THREAD , FPGA_SYN_NO_SPU } /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
 
# The Tcl script under $S1_ROOT/tools/src/build_dc.cmd is attached at the end of the filelist for DC;
# if you modify this file *REMEMBER* to run 'update_filelist' or you'll run the old version!!!
/trunk/hdl/filelist.icarus
1,142 → 1,142
/home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
/home/fabrizio/s1_core/hdl/behav/testbench/mem_harness.v
/home/fabrizio/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/testbench/mem_harness.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/testbench/testbench.v
+incdir+/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top
+define+FPGA_SYN
+define+FPGA_SYN_1THREAD
+define+FPGA_SYN_NO_SPU
/trunk/hdl/filelist.vcs
1,139 → 1,139
-v /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
-v /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
-v /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
/home/fabrizio/s1_core/hdl/behav/testbench/mem_harness.v
/home/fabrizio/s1_core/hdl/behav/testbench/testbench.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
-v /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/testbench/mem_harness.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/testbench/testbench.v
+incdir+/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top
/trunk/hdl/filelist.fpga
1,140 → 1,140
/home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
/home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
/home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
/home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
+incdir+/home/fabrizio/s1_core/hdl/rtl/s1_top
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
+incdir+/home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top
+define+FPGA_SYN
+define+FPGA_SYN_1THREAD
+define+FPGA_SYN_NO_SPU
/trunk/hdl/filelist.xst
1,136 → 1,136
verilog work /home/fabrizio/s1_core/hdl/behav/sparc_libs/m1_lib.v
verilog work /home/fabrizio/s1_core/hdl/behav/sparc_libs/u1_lib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_asi_decode.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_idct.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_scm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_incr64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_shft.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_tcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_misctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_pcx_qmon.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/synchronizer_asr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cpx_spc_buf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_incr46.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_clib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_pib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_prencoder16.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_icd.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_bist.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/cluster_header.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_byp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_ctldp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_frf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_par16.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x80.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_tlb.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/test_stub_scan.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_irf.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/tlu_mmu_ctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_eclccr.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/mul64.v
verilog work /home/fabrizio/s1_core/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/rst_ctrl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/int_ctrl.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/spc2wbm.v
verilog work /home/fabrizio/s1_core/hdl/rtl/s1_top/s1_top.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/u1_lib.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/behav/sparc_libs/m1_lib.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluor32.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc_dec.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_cmp35.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tcl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cluster_header.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_bist.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tlbdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_mbist.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_incr64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_tlb.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_ctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dec.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_zcmp64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ctr5.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_misctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/mul64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_intdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_scm.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_top.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_tdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_incr46.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl1.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluaddsub.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_clib.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_eccctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_32eql.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_asi_decode.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_buf.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_dcd.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_pcx_qmon.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_rndrob.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_cntl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_dcl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_frf.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x80.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/synchronizer_asr.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog_rs1.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swpla.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_shft.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/swrvr_dlib.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclcomp7.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_excpctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_wb.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_mdqctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rndrob.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_divcntl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluadder64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par34.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alulogic.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x32.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qctl2.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_pib.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_tagdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_mmu_dp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_dec64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecc.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctldp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_reg.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_icd.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp2.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_vis.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf16x160.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_ifqctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lfsr5.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par16.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_rf32x152b.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu_16eql.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_par32.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_wseldp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div_yreg.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/test_stub_scan.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_mul_dp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_fcl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_invctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_qdp1.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_rrobin_picker.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_lru4.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_inc3.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl_visctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_sscan.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dc_parity_gen.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcache_lfsr.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_ecl_cnt6.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_byp_eccgen.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_idct.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_swl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cmp_sram_redhdr.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_dp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/cpx_spc_rpt.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_tlu_penc64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml_cwp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_prencoder16.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_rwdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_hyperv.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_r_irf_register.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_div.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclbyplog.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluzcmp64.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_milfsm.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_rml.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrcmpl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/bw_clk_cl_sparc_cmp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_errctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_part_add32.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_eclccr.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/tlu_addern_32.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_rrobin_picker2.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_imd.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ffu_ctl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_ifu_thrfsm.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_aluspr.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_stb_ctldp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/sparc_exu_alu.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/sparc_core/lsu_dcdp.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/rst_ctrl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/int_ctrl.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/spc2wbm.v
verilog work /home/ubuntu/Design/OpenCores/s1_core/trunk/hdl/rtl/s1_top/s1_top.v
/trunk/docs/REQUIREMENTS.txt
9,7 → 9,8
- sed stream editor;
- for simulations: Icarus Verilog (free software)
or Synopsys VCS MX (commercial);
- for synthesis: Icarus Verilog (free software) or
- for synthesis: Xilinx XST (commercial, some versions
are free), Icarus Verilog (free software) or
Synopsys Design Compiler (commercial).
 
As you can easily understand, whatever GNU/Linux or
51,3 → 52,4
GNU/Linux x86 PC; please check on the Download Area of the
Simply RISC website at http://www.srisc.com .
 
 
/trunk/docs/SIMULATION.txt
4,8 → 4,9
To run a simulation using the free software Icarus Verilog
simulator use the following commands:
 
build_icarus
run_icarus
s1_sim_build icarus
compile_test hello
s1_sim_run icarus
 
If you want to use a commercial tool such as Synopsys VCS then
set up your PATH enviroment variable so that you are able to
12,8 → 13,9
find the "vcs" executable, and then type in the following
commands:
 
build_vcs
run_vcs
s1_sim_build vcs
compile_test hello
s1_simrun vcs
 
Within this design the only visible difference between Icarus
and VCS is the speed: the commercial tool could be hundreds of
/trunk/docs/INSTALL.txt
3,7 → 3,7
 
To install the package just extract it:
 
tar zxvf s1.tar.gz
tar zxvf s1_core.tar.gz
 
then edit the top-level "sourceme" file to reflect the locations
of the S1 design (we call "S1 root directory" the one containing
11,8 → 11,7
the first one is mandatory, the second path is needed only if you
want to update the SPARC Core source file bundled with this tarball
with an updated version of the T1 design released by the OpenSPARC
community (to see how to update it, please read UPDATING.txt
).
community (to see how to update it, please read UPDATING.txt).
 
After that just use on your GNU/Linux or Unix box a bash shell
to source this file:
/trunk/docs/SYNTHESIS.txt
5,17 → 5,23
used for simulations, you can still use the free Icarus
Verilog software (that will target an FPGA application)
or a commercial Design Compiler tool from Synopsys (that
will be used for ASIC).
will be used for ASIC). In addition there is also a good
synthesis tool for FPGAs from Xilinx named XST (could be
"Xilinx Synthesis Tool").
 
To synthesize using XST:
 
s1_synth xst
 
With Icarus you will use the "fpga" target, to do so
just run:
 
build_fpga
s1_synth fpga
 
If you want to use Synopsys Design Compiler instead you
have to use:
 
build_dc
s1_synth dc
 
Please note that the commercial tools are NOT supported, and
they will probably not work unless you fix all the required
22,12 → 28,10
parameters properly (we are focusing on free software since
we want to build up a community of developers around the S1).
 
The results for these two kinds of scripts are in the
directories:
The results for these scripts are in the directories:
 
run/synth/xst/
run/synth/fpga/
run/synth/dc/
 
and
 
run/synth/dc/
 
/trunk/docs/README.txt
1,7 → 1,7
Simply RISC S1 Core
===================
 
This is the README file for the S1 Core (codename "Sirocco");
This is the README file for the Simply RISC S1 Core;
all the informations you need are contained in the text files
that you can find in the "docs" subdirectory:
 
21,5 → 21,5
Please note that from OpenCores http://www.opencores.org or the
Simply RISC website at http://www.srisc.com you can always
download a single PDF specification that is just a collection of
the text files included in the CVS tree and listed above.
the text files included in the SVN tree and listed above.
 
/trunk/README.txt
1,24 → 1,5
Simply RISC S1 Core
===================
 
This is the README file for the S1 Core (codename "Sirocco");
all the informations you need are contained in the text files
that you can find in the "docs" subdirectory:
 
- README.txt Summary (this file)
- INSTALL.txt Quick Installation Guide
- REQUIREMENTS.txt System Requirements
- SIMULATION.txt Simulation Environment
- SYNTHESIS.txt Synthesis Environment
- SPEC.txt Functional Specification
- SUPPORT.txt Support and References
- LICENSE.txt License for Design and Documentation
- TODO.txt To Do List
 
Probably now you just have to read the docs/INSTALL.txt file.
 
Please note that from OpenCores http://www.opencores.org or the
Simply RISC website at http://www.srisc.com you can always
download a single PDF specification that is just a collection of
the text files included in the CVS tree and listed above.
 
link docs/README.txt
trunk/README.txt Property changes : Added: svn:special ## -0,0 +1 ## +* \ No newline at end of property

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