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URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

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Rev 113 → Rev 114

/trunk/docs/INSTALL.txt
1,5 → 1,5
Simply RISC S1 Core - Quick Installation Guide
==============================================
S1 Core - Quick Installation Guide
==================================
 
To install the package just extract it:
 
/trunk/docs/LICENSE.txt
1,5 → 1,5
Simply RISC S1 Core - License for Design and Documentation
==========================================================
S1 Core - License for Design and Documentation
==============================================
 
The S1 Core is a free hardware design released under the
GNU General Public License (GPL) version, 2 unless otherwise
/trunk/docs/README.txt
1,9 → 1,9
Simply RISC S1 Core
===================
S1 Core README
==============
 
This is the README file for the Simply RISC S1 Core;
all the informations you need are contained in the text files
that you can find in the "docs" subdirectory:
This is the README file for the S1 Core; all the information
you need are contained in the text files that you can find in
the "docs" subdirectory:
 
- README.txt Summary (this file)
- INSTALL.txt Quick Installation Guide
18,8 → 18,7
 
Probably now you just have to read the docs/INSTALL.txt file.
 
Please note that from OpenCores http://www.opencores.org or the
Simply RISC website at http://www.srisc.com you can always
download a single PDF specification that is just a collection of
the text files included in the SVN tree and listed above.
Please note that from OpenCores http://www.opencores.org you can
always download a single PDF specification that is just a collection
of the text files included in the SVN tree and listed above.
 
/trunk/docs/REQUIREMENTS.txt
1,5 → 1,5
Simply RISC S1 Core - System Requirements
=========================================
S1 Core - System Requirements
=============================
 
You can run simulation and synthesis of the S1 Core
almost on any machine: all you need is a Unix-like
16,8 → 16,7
As you can easily understand, whatever GNU/Linux or
Unix machine should be suitable for your purposes;
we haven't tried on Windows with Cygwin but we suspect
that it could work (please let us know your experience
at support@srisc.com and we'll list it here).
that it could work.
 
Infact since the only tool you need for simulation and
synthesis is Icarus Verilog, and since it is free
49,7 → 48,6
there's an x86 to sparc64 GCC cross-compiler available
on the web so you should be able to compile test programs
for the S1 Core using not only a SPARC machine but whatever
GNU/Linux x86 PC; please check on the Download Area of the
Simply RISC website at http://www.srisc.com .
GNU/Linux x86 PC.
 
 
/trunk/docs/SIMULATION.txt
1,5 → 1,5
Simply RISC S1 Core - Simulation Environment
============================================
S1 Core - Simulation Environment
================================
 
To run a simulation using the free software Icarus Verilog
simulator use the following commands:
/trunk/docs/SPEC.txt
1,5 → 1,5
Simply RISC S1 Core - Functional Specification
==============================================
S1 Core - Functional Specification
==================================
 
Preface
-------
8,7 → 8,7
Wishbone Bridge, a Reset Controller and an Interrupt
Controller.
___________________________________
| Simply RISC S1 Core |
| S1 Core |
| _______ _____ ________ ________ |
|| || || || ||
|| Reset || Int || SPARC ||Wishbone||
35,7 → 35,7
kernel are ready for the T1.
There's also a complete GNU/Linux distribution, Ubuntu,
that comes ready for the SPARC Core of the T1 and could be
used in a seamless way also for Simply RISC S1 based micros.
used in a seamless way also for S1 based micros.
 
S1 Memory Map
-------------
/trunk/docs/SUPPORT.txt
1,7 → 1,7
Simply RISC S1 Core - Support and References
============================================
S1 Core - Support and References
================================
 
The S1 Core has been developed by Simply RISC LLP and
The S1 Core has been developed by Fabrizio Fazzino and
the OpenCores community, and it's been released as
Free Hardware Design under the GPL license version 2.
You have all the freedom granted by this license, but
10,8 → 10,8
1) all the files bundled with this package come
WITHOUT WARRANTY, so USE THEM AT YOUR OWN RISK;
 
2) you do NOT have the right to pretend the support
you need from Simply RISC LLP.
2) you do NOT have the right to demand the support
you need from Fabrizio Fazzino.
 
Anyway we will try to provide all the free support
that we can, and now we try to list how to ask for
50,19 → 50,3
discuss with real experts about your problems with
the Wishbone interconnect protocol.
 
If you still need support or you want to take part
in the development of the S1 Core, then you can
contact us at
 
support@srisc.com
 
and we will try to help you if possible. If you find
something that can be corrected and/or improved in
the design or in the documentation please let us know
and we will fix it in the next release.
 
To see if there is a new release available just check
from time to time on the Simply RISC website:
 
http://www.srisc.com
 
/trunk/docs/SYNTHESIS.txt
1,5 → 1,5
Simply RISC S1 Core - Synthesis Environment
===========================================
S1 Core - Synthesis Environment
===============================
 
The scripts to run synthesis are similar to the ones
used for simulations, you can still use the free Icarus
/trunk/docs/TODO.txt
1,5 → 1,5
Simply RISC S1 Core - To Do List
================================
S1 Core - To Do List
====================
 
This is the list of the higher priority tasks:
- synth problem: Icarus assertion failed
/trunk/docs/UPDATING.txt
1,5 → 1,5
Simply RISC S1 Core - OpenSPARC sources updating
================================================
S1 Core - OpenSPARC sources updating
====================================
 
To update the source files of the SPARC Core to the latest
version provided by Sun Microsystems with their OpenSPARC
/trunk/docs/other/ACCESSES.txt
1,5 → 1,5
Simply RISC S1 Core - Boot Code
===============================
S1 Core - Boot Code
===================
 
This is the disassembled boot code; the original source code can be
found inside the official OpenSPARC T1 tarball, in the file:
/trunk/docs/other/BLOCKS.txt
1,5 → 1,5
Simply RISC S1 Core - Blocks of the SPARC Core
==============================================
S1 Core - Blocks of the SPARC Core
==================================
 
When you are in the OpenSPARC environment and you run
"rsyn sparc" to synthetize just the SPARC Core, you
/trunk/hdl/behav/testbench/mem_harness.v
1,8 → 1,7
/*
* Memory Harness with Wishbone Slave interface
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/behav/testbench/s1_defs.h
1,8 → 1,7
/*
* Simply RISC S1 Definitions
* S1 Definitions
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/behav/testbench/testbench.v
1,8 → 1,7
/*
* Simply RISC S1 Testbench
* S1 Testbench
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
78,7 → 77,7
initial begin
 
// Display start message
$display("INFO: TBENCH: Starting Simply RISC S1 Core simulation...");
$display("INFO: TBENCH: Starting S1 Core simulation...");
 
// Create VCD trace file
$dumpfile("trace.vcd");
90,7 → 89,7
#1000
sys_reset <= 1'b0;
#49000
$display("INFO: TBENCH: Completed Simply RISC S1 Core simulation!");
$display("INFO: TBENCH: Completed S1 Core simulation!");
$finish;
 
end
99,7 → 98,7
* Module instances
*/
 
// Simply RISC S1 Core
// S1 Core
s1_top s1_top_0 (
 
// System inputs
/trunk/hdl/rtl/s1_top/cachedir.v
1,8 → 1,7
/*
* Simply RISC CacheDir
* CacheDir
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/int_ctrl.v
1,8 → 1,7
/*
* Interrupt Controller
* S1 Interrupt Controller
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/os2wb.v
2,7 → 2,7
//////////////////////////////////////////////////////////////////////////////////
// Company: (C) Athree, 2009
// Engineer: Dmitry Rozhdestvenskiy
// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
// Email: dmitryr@a3.spb.ru divx4log@narod.ru
//
// Design Name: Bridge from SPARC Core to Wishbone Master
// Module Name: os2wb
/trunk/hdl/rtl/s1_top/pcx_fifo.v
1,8 → 1,7
/*
* Simply RISC PCX FIFO
* PCX FIFO
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/rst_ctrl.v
1,8 → 1,7
/*
* Reset Controller
* S1 Reset Controller
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/s1_defs.h
1,8 → 1,7
/*
* Simply RISC S1 Definitions
* S1 Definitions
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/s1_top.v
1,8 → 1,7
/*
* Simply RISC S1 Core Top-Level
* S1 Core Top-Level
*
* (C) 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/simple_fifo.v
1,8 → 1,7
/*
* Simply RISC Simple FIFO
* Simple FIFO
*
* (C) Copyleft 2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) Copyleft 2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/hdl/rtl/s1_top/spc2wbm.v
1,8 → 1,7
/*
* Bridge from SPARC Core to Wishbone Master
*
* (C) 2006-2007 Simply RISC LLP
* AUTHOR: Fabrizio Fazzino <fabrizio.fazzino@srisc.com>
* (C) 2006-2007 Fabrizio Fazzino
*
* LICENSE:
* This is a Free Hardware Design; you can redistribute it and/or
/trunk/tests/boot/boot.s
1,5 → 1,5
/*
* Simply RISC S1 Core - Boot code
* S1 Core - Boot code
*
* Cutdown version from the original OpenSPARC T1:
*
/trunk/tools/bin/compile_test
15,7 → 15,6
rm -f *.o *~ *.bin *.dump *.hex # Make clean
if [ $# -ne 1 ]; then
echo "compile_test - Script to compile a test for the S1 Core";
echo "(C) 2006 by Simply RISC";
echo "Usage:";
echo " compile_test <TEST_NAME>";
echo "where parameter is the test name without extension (e.g. 'hello').";
/trunk/tools/bin/tar_env
5,7 → 5,7
# otherwise you will get a huge file.
 
test_env S1_ROOT
TARBALL=$HOME/simplyrisc-s1.tar
TARBALL=$HOME/s1_core.tar
 
rm -f $TARBALL* $S1_ROOT/*.tar*
cd $S1_ROOT/..
/trunk/tools/bin/tracan.sh
6,7 → 6,6
 
if [ $# != 1 ]; then
echo "Tracan - Trace Analyzer"
echo "(C) 2006 by Simply RISC"
echo "Usage:"
echo " tracan <VCDFILE>"
echo ""
/trunk/tools/bin/update_sparccore
3,7 → 3,6
# Check command line parameter
if ( (test $# != 1) || ((test $1 != "-me") && (test $1 != "-se") && (test $1 != "-ee")) ) then
echo "update_sparccore - Script to update SPARC Core sources from a fresh OpenSPARC installation";
echo "(C) 2007 by Simply RISC";
echo "Usage:";
echo " update_sparccore {-me|-se|-ee}";
echo "where parameter refers to the S1 Core version you want to obtain in your environment:";
/trunk/tools/src/TRACAN.txt
1,5 → 1,5
Simply RISC S1 Core - Tracan (Trace Analyzer)
=============================================
S1 Core - Tracan (Trace Analyzer)
=================================
 
This small tool has been written to convert the waveforms of the
original OpenSPARC T1 simulation environment into a format similar
48,5 → 48,3
your name into this file!
- Enjoy!
 
The development team at Simply RISC LLP
 
/trunk/tools/src/bw_r_dcd.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core
// Empty module for cacheless S1 Core
 
module bw_r_dcd (
// Outputs
/trunk/tools/src/bw_r_icd.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core
// Empty module for cacheless S1 Core
 
module bw_r_icd(icd_wsel_fetdata_s1, icd_wsel_topdata_s1, icd_fuse_repair_value,
icd_fuse_repair_en, so, rclk, se, si, reset_l, sehold, fdp_icd_index_bf,
/trunk/tools/src/bw_r_idct.v
1,4 → 1,4
// Empty module for cacheless Simply RISC S1 Core
// Empty module for cacheless S1 Core
 
module bw_r_idct(rdtag_w0_y, rdtag_w1_y, rdtag_w2_y, rdtag_w3_y, so, rclk, se,
si, reset_l, sehold, rst_tri_en, index0_x, index1_x, index_sel_x,
/trunk/tools/src/sourceme
1,6 → 1,6
 
# General paths settings
export S1_ROOT=/usr/design/simplyrisc-s1
export S1_ROOT=/usr/design/s1_core
export T1_ROOT=/usr/design/opensparc-t1/current
export PATH=.:$S1_ROOT/tools/bin:$PATH
 
/trunk/tools/src/tracan.cpp
50,8 → 50,8
case FWD_RQ: strcpy(str_type, "FWD_RQ"); break;
case FWD_RPY: strcpy(str_type, "FWD_RPY"); break;
case RSVD_RQ: strcpy(str_type, "RSVD_RQ"); break;
case ATOM_REQ_A: strcpy(str_type, "ATOM_REQ_A"); break; // Added by Simply RISC
case ATOM_REQ_B: strcpy(str_type, "ATOM_REQ_B"); break; // Added by Simply RISC
case ATOM_REQ_A: strcpy(str_type, "ATOM_REQ_A"); break; // Added for S1 Core
case ATOM_REQ_B: strcpy(str_type, "ATOM_REQ_B"); break; // Added for S1 Core
default: sprintf(str_type, "Unknown_0x%02llX", bitsToInt(buf, PCX_RQ_HI,PCX_RQ_LO));
}
switch(bitsToInt(buf, PCX_SZ_HI,PCX_SZ_LO)) {
/trunk/tools/src/tracan.h
106,7 → 106,7
#define FWD_RQ 0x0D // NF
#define FWD_RPY 0x0E // NF
#define RSVD_RQ 0x1F // NF
// Added by Simply RISC
// Added for S1 Core
#define ATOM_REQ_A 0x0A
#define ATOM_REQ_B 0x0B
 
/trunk/tools/src/waves_s1.gtkw
2,10 → 2,10
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Mon Nov 30 21:49:20 2015
[*]
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/run/sim/icarus/trace.vcd"
[dumpfile] "/home/ubuntu/Work/SVN/s1_core/trunk/run/sim/icarus/trace.vcd"
[dumpfile_mtime] "Mon Nov 30 21:48:09 2015"
[dumpfile_size] 9925089
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/src/waves_s1.gtkw"
[savefile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/src/waves_s1.gtkw"
[timestart] 0
[size] 1855 1151
[pos] -1 -1
/trunk/tools/src/waves_t1.gtkw
2,10 → 2,10
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Sun Nov 22 17:04:48 2015
[*]
[dumpfile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/traces/v9_allinst:model_core1:core1_mini:0/trace.vcd"
[dumpfile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/traces/v9_allinst:model_core1:core1_mini:0/trace.vcd"
[dumpfile_mtime] "Mon May 1 14:33:41 2006"
[dumpfile_size] 20236723
[savefile] "/home/ubuntu/Work/SVN/SimplyRISC/S1_Core/s1_core/trunk/tools/opt/tracan/waves.gtkw"
[savefile] "/home/ubuntu/Work/SVN/s1_core/trunk/tools/opt/tracan/waves.gtkw"
[timestart] 1984200
[size] 1855 1151
[pos] -1 -1

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