URL
https://opencores.org/ocsvn/s6soc/s6soc/trunk
Subversion Repositories s6soc
Compare Revisions
- This comparison shows the changes necessary to convert path
/s6soc/trunk
- from Rev 24 to Rev 23
- ↔ Reverse comparison
Rev 24 → Rev 23
/rtl/cpu/ziptimer.v
67,7 → 67,7
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
o_int); |
parameter BW = 32, VW = (BW-1), RELOADABLE=1; |
parameter BW = 32, VW = (BW-1); |
input i_clk, i_rst, i_ce; |
// Wishbone inputs |
input i_wb_cyc, i_wb_stb, i_wb_we; |
79,49 → 79,34
// Interrupt line |
output reg o_int; |
|
reg r_running; |
reg r_auto_reload, r_running; |
reg [(VW-1):0] r_reload_value; |
|
wire wb_write; |
assign wb_write = ((i_wb_cyc)&&(i_wb_stb)&&(i_wb_we)); |
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wire auto_reload; |
wire [(VW-1):0] reload_value; |
|
initial r_running = 1'b0; |
initial r_auto_reload = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
r_running <= 1'b0; |
else if (wb_write) |
r_running <= (|i_wb_data[(VW-1):0]); |
else if ((o_int)&&(~auto_reload)) |
else if ((o_int)&&(~r_auto_reload)) |
r_running <= 1'b0; |
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generate |
if (RELOADABLE != 0) |
begin |
reg r_auto_reload; |
reg [(VW-1):0] r_reload_value; |
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initial r_auto_reload = 1'b0; |
always @(posedge i_clk) |
if (wb_write) |
r_auto_reload <= (i_wb_data[(BW-1)]); |
|
always @(posedge i_clk) |
if (wb_write) |
r_auto_reload <= (i_wb_data[(BW-1)]); |
// If setting auto-reload mode, and the value to other |
// than zero, set the auto-reload value |
always @(posedge i_clk) |
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0])) |
r_reload_value <= i_wb_data[(VW-1):0]; |
|
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assign auto_reload = r_auto_reload; |
|
// If setting auto-reload mode, and the value to other |
// than zero, set the auto-reload value |
always @(posedge i_clk) |
if ((wb_write)&&(i_wb_data[(BW-1)])&&(|i_wb_data[(VW-1):0])) |
r_reload_value <= i_wb_data[(VW-1):0]; |
assign reload_value = r_reload_value; |
end else begin |
assign auto_reload = 1'b0; |
assign reload_value = 0; |
end endgenerate |
|
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reg [(VW-1):0] r_value; |
initial r_value = 0; |
always @(posedge i_clk) |
129,11 → 114,10
r_value <= i_wb_data[(VW-1):0]; |
else if ((r_running)&&(i_ce)&&(~o_int)) |
r_value <= r_value + {(VW){1'b1}}; // r_value - 1; |
else if ((r_running)&&(auto_reload)&&(o_int)) |
r_value <= reload_value; |
else if ((r_running)&&(r_auto_reload)&&(o_int)) |
r_value <= r_reload_value; |
|
// Set the interrupt on our last tick, as we transition from one to |
// zero. |
// Set the interrupt on our last tick. |
initial o_int = 1'b0; |
always @(posedge i_clk) |
if (i_rst) |
150,9 → 134,9
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generate |
if (VW < BW-1) |
assign o_wb_data = { auto_reload, {(BW-1-VW){1'b0}}, r_value }; |
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value }; |
else |
assign o_wb_data = { auto_reload, r_value }; |
assign o_wb_data = { r_auto_reload, r_value }; |
endgenerate |
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endmodule |