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https://opencores.org/ocsvn/s6soc/s6soc/trunk
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- This comparison shows the changes necessary to convert path
/s6soc/trunk
- from Rev 30 to Rev 29
- ↔ Reverse comparison
Rev 30 → Rev 29
/rtl/cpu/zipcpu.v
471,13 → 471,7
// If we aren't pipelined, then no one will be changing what's in the |
// pipeline (i.e. clear_pipeline), while our only instruction goes |
// through the ... pipeline. |
// |
// However, in hind sight this logic didn't work. What happens when |
// something gets in the pipeline and then (due to interrupt or some |
// such) needs to be voided? Thus we avoid simplification and keep |
// what worked here. |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled) |
&&(~clear_pipeline); |
assign mem_ce = (master_ce)&&(opvalid_mem)&&(~mem_stalled)&&(~clear_pipeline); |
`endif |
`ifdef OPT_PIPELINED_BUS_ACCESS |
assign mem_stalled = (~master_ce)||(alu_busy)||((opvalid_mem)&&( |
627,8 → 621,6
always @(posedge i_clk) |
if (op_ce) |
r_op_pipe <= dcd_pipe; |
else if (mem_ce) // Clear us any time an op_ is clocked in |
r_op_pipe <= 1'b0; |
assign op_pipe = r_op_pipe; |
`else |
assign op_pipe = 1'b0; |
1001,27 → 993,31
&&((opvalid)||(mem_rdbusy) |
||(div_busy)||(fpu_busy)||(alu_busy)) |
&&( |
// Okay, what happens if the result register |
// from instruction 1 becomes the input for |
// instruction two, *and* there's an immediate |
// offset in instruction two? In that case, we |
// need an extra clock between the two |
// instructions to calculate the base plus |
// offset. |
// |
// What if instruction 1 (or before) is in a |
// memory pipeline? We may no longer know what |
// the register was! We will then need to |
// blindly wait. We'll temper this only waiting |
// if we're not piping this new instruction. |
// If we were piping, the pipe logic in the |
// decode circuit has told us that the hazard |
// is clear, so we're okay then. |
// |
// Stall on memory ops writing to my register |
// (i.e. loads), or on any write to my |
// register if I have an immediate offset |
// Actually, this is worse. I can't tell |
// whether or not my register is going to |
// be written to, so |
// Note the exception for writing to the PC: |
// if I write to the PC, the whole next |
// instruction is invalid, not just the |
// operand. That'll get wiped in the |
// next operation anyway, so don't stall |
// here. This keeps a BC X, BNZ Y from |
// stalling between the two branches. |
// BC X, BRA Y is still clear, since BRA Y |
// is an early branch instruction. |
// (This exception is commented out in |
// order to help keep our logic simple, and |
// because multiple conditional branches |
// following each other constitutes a |
// fairly unusualy code structure.) |
// |
((~dcd_zI)&&( |
((opR == dcdB)&&(opR_wr)) |
||((mem_rdbusy)&&(~dcd_pipe)) |
)) |
||(((opvalid_mem)||(mem_rdbusy)) |
&&(op_pipe)))) |
// Stall following any instruction that will |
// set the flags, if we're going to need the |
// flags (CC) register for opB. |
/rtl/cpu/idecode.v
71,7 → 71,7
output reg o_gie; |
output reg [6:0] o_dcdR, o_dcdA, o_dcdB; |
output wire [31:0] o_I; |
output wire o_zI; |
output reg o_zI; |
output reg [3:0] o_cond; |
output reg o_wF; |
output reg [3:0] o_op; |
86,8 → 86,9
wire dcdA_stall, dcdB_stall, dcdF_stall; |
wire o_dcd_early_branch; |
wire [(AW-1):0] o_dcd_branch_pc; |
reg o_dcdI, o_dcdIz; |
`ifdef OPT_PIPELINED |
reg r_lock, r_pipe, r_zI; |
reg r_lock, r_pipe; |
`endif |
|
|
342,9 → 343,7
o_rA <= w_rA; |
o_rB <= w_rB; |
r_I <= w_I; |
`ifdef OPT_PIPELINED |
r_zI <= w_Iz; |
`endif |
o_zI <= w_Iz; |
|
// Turn a NOOP into an ALU operation--subtract in |
// particular, although it doesn't really matter as long |
369,10 → 368,8
|
`ifdef OPT_PIPELINED |
assign o_lock = r_lock; |
assign o_zI = r_zI; |
`else |
assign o_lock = 1'b0; |
assign o_zI = 1'b0; |
`endif |
|
generate |
445,8 → 442,8
// Note that we're not using iword here ... there's a lot of logic |
// taking place, and it's only valid if the new word is not compressed. |
// |
reg r_valid; |
`ifdef OPT_PIPELINED |
reg r_valid; |
reg r_pipe; |
initial r_pipe = 1'b0; |
always @(posedge i_clk) |
461,6 → 458,9
&&((i_instruction[13:0]==r_I[13:0]) |
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1))); |
assign o_pipe = r_pipe; |
`else |
assign o_pipe = 1'b0; |
`endif |
|
always @(posedge i_clk) |
if (i_rst) |
471,9 → 471,6
r_valid <= 1'b1; |
else if (~i_stalled) |
r_valid <= 1'b0; |
`else |
assign o_pipe = 1'b0; |
`endif |
|
|
assign o_I = { {(32-22){r_I[22]}}, r_I[21:0] }; |