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/src/spec.tex
1,4 → 1,41
\documentclass{gqtekspec}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%% Filename: spec.tex
%%
%% Project: CMod S6 System on a Chip, ZipCPU demonstration project
%%
%% Purpose:
%%
%% Creator: Dan Gisselquist, Ph.D.
%% Gisselquist Technology, LLC
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%% Copyright (C) 2015-2016, Gisselquist Technology, LLC
%%
%% This program is free software (firmware): you can redistribute it and/or
%% modify it under the terms of the GNU General Public License as published
%% by the Free Software Foundation, either version 3 of the License, or (at
%% your option) any later version.
%%
%% This program is distributed in the hope that it will be useful, but WITHOUT
%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
%% for more details.
%%
%% You should have received a copy of the GNU General Public License along
%% with this program. (It's in the $(ROOT)/doc directory, run make with no
%% target there if the PDF file isn't present.) If not, see
%% <http://www.gnu.org/licenses/> for a copy.
%%
%% License: GPL, v3, as defined and found on www.gnu.org,
%% http://www.gnu.org/licenses/gpl.html
%%
%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%
%%
\usepackage{import}
\usepackage{bytefield}
\project{CMod S6 SoC}
26,6 → 63,8
with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
\end{license}
\begin{revisionhistory}
0.5 & 2/13/2017 & Gisselquist & Draft updates to support the 8-bit byte ZipCPU
\\\hline
0.3 & 5/23/2016 & Gisselquist & Draft for comment, includes ZipOS and PMod
pin mapping\\\hline
0.2 & 5/14/2016 & Gisselquist & Updated Draft, still not complete \\\hline
156,6 → 195,32
memory.
 
 
\chapter{Getting Started}
\section{Building the Compiler}
%% git clone
%% Setting zip_param_cis to zero
%% Setting ZIP_DIVIDE to zero
%% Setting ZIP_PIPELINED to zero -- Disables the ZIP_ATOMIC instructions
%% Setting ZIP_THUMB to zero -- Disables the CIS instructions
\section{Building the ADEPT Utilities}
% Install the digilent adept utilities
% Expand the tar file
% tar -xvzf digilent.adept.utilities_2.2.1-x86_64.tar.gz
% Install them
% cd digilent.adept.utilities_2.2.1-x86_64.tar.gz
% sudo ./install.sh
% Answer Y to install the binaries into /usr/local/bin, and again
% to place the manual pages into /usr/local/man.
% Install the Digilent ADEPT Runtime
% Answer Y to store the libraries into /usr/local/lib64/digilent/adept
% Answer Y to install system binaries into /usr/sbin
% Answer Y to install data into /usr/share/digilent/adept/data
% Answer Y to install runtime configuration data files into /etc
%
\section{Building and Running the Host Software}
\section{Building the Board Software}
\section{Building the ZipOS}
 
\chapter{Software}
This chapter provides an overview of the software that is available to support
the S6~SoC. This includes not only the RTL, the Makefiles, and the software
303,7 → 368,7
program because, if you can get this program running, you know you have
a lot of things working and working correctly. For example, running
this program means you can run the {\tt zip-gcc} compiler, load
the auxiliar configuration, load the program info flash memory, load
the auxiliary configuration, load the program info flash memory, load
the primary configuration, and read from the UART port. It also means
that you must have the UART port properly configured and wired to your
CMod board.
409,7 → 474,7
 
\item {\tt void post(unsigned event\_mask)}
 
Certain devices, such as the real--time clock and the doorbell
Certain software devices, such as the real--time clock and the doorbell
reader, need the ability of being able to post events to any listener
within the O/S. The POST system call allows them to POST events in
this manner.
637,12 → 702,10
\begin{table}[htbp]
\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline
\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline
\scalebox{0.9}{\tt 0x000100} & \scalebox{0.9}{\tt 0x000107} & R/W & Peripheral I/O Control \\\hline
\scalebox{0.9}{\tt 0x000200} & \scalebox{0.9}{\tt 0x000201} & R/(W) & Debugging scope\\\hline
\scalebox{0.9}{\tt 0x000400} & \scalebox{0.9}{\tt 0x00043f} & R/W & Internal Configuration Access Port\\\hline
\scalebox{0.9}{\tt 0x000800} & \scalebox{0.9}{\tt 0x000803} & R/W & RTC Clock (if present)\\\hline
\scalebox{0.9}{\tt 0x002000} & \scalebox{0.9}{\tt 0x002fff} & R/W & 16kB On-Chip Block RAM \\\hline
\scalebox{0.9}{\tt 0x400000} & \scalebox{0.9}{\tt 0x7fffff} & R & 16~MB SPI Flash memory\\\hline
\scalebox{0.9}{\tt 0x0000400} & \scalebox{0.9}{\tt 0x00043f} & R/W & Peripheral I/O Control \\\hline
\scalebox{0.9}{\tt 0x0000800} & \scalebox{0.9}{\tt 0x00080f} & R/(W) & Debugging scope\\\hline
\scalebox{0.9}{\tt 0x0004000} & \scalebox{0.9}{\tt 0x03fff} & R/W & 16kB On-Chip Block RAM \\\hline
\scalebox{0.9}{\tt 0x1000000} & \scalebox{0.9}{\tt 0x7fffff} & R & 16~MB SPI Flash memory\\\hline
\end{tabular}
\caption{Address Regions}\label{tbl:memregions}
\end{center}\end{table}
649,7 → 712,8
In general, the address regions that are made up of RAM or flash act like
memory. The RAM can be read and written, and the flash acts like read only
memory.\footnote{The Flash can be written, but only by an external command
while in the alternate configuration.}
while in the alternate configuration.} Furthermore, {\em only} the RAM offers
the capability of byte-wise writes across the bus.
 
This isn't quite true with the other address regions. Accessing the I/O
region, while it will act like a memory, it may also have side-effects. For
658,23 → 722,26
 
Finally, to keep the address decoder simple, many of these addresses are
multiply mapped. Hence you may find the I/O peripherals mapped throughout the
{\tt 0x0100}--{\tt 0x01ff} address region. Other memory addresses are similarly
{\tt 0x0400}--{\tt 0x07ff} address region. Other memory addresses are similarly
overmapped. This overmapping was a resource minimization feature, to get the
bus to fit within a minimum number of FPGA resources.
bus to fit within a minimum number of FPGA resources. For this reason,
addresses not explicitly defined in this specification are undefined.
Likewise, attempting to write a byte or half-word to anything other than RAM
will have undefined results.
 
\section{Peripheral I/O Control}
Tbl.~\ref{tbl:ioregs}
\begin{table}[htbp]
\begin{center}\begin{reglist}
PIC &\scalebox{0.8}{\tt 0x0100} & 32 & R/W & Interrupt Controller \\\hline
BUSERR &\scalebox{0.8}{\tt 0x0101} & 32 & R & Last Bus Error Address\\\hline
TIMA &\scalebox{0.8}{\tt 0x0102} & 32 & R/W & ZipTimer A\\\hline
TIMB &\scalebox{0.8}{\tt 0x0103} & 32 & R/W & ZipTimer B\\\hline
PWM &\scalebox{0.8}{\tt 0x0104} & 32 & R/W & PWM Audio Controller\\\hline
SPIO &\scalebox{0.8}{\tt 0x0105} & 32 & R/W & Special Purpose I/O, Keypad, LED Controller \\\hline
GPIO &\scalebox{0.8}{\tt 0x0106} & 32 & R/W & GPIO Controller \\\hline
UART &\scalebox{0.8}{\tt 0x0107} & 32 & R/W & UART data\\\hline
VERSION &\scalebox{0.8}{\tt 0x0108} & 32 & R & Build date\\\hline
PIC &\scalebox{0.8}{\tt 0x0400} & 32 & R/W & Interrupt Controller \\\hline
BUSERR &\scalebox{0.8}{\tt 0x0404} & 32 & R & Last Bus Error Address\\\hline
TIMER &\scalebox{0.8}{\tt 0x0408} & 32 & R/W & ZipTimer\\\hline
WDOG &\scalebox{0.8}{\tt 0x040c} & 32 & R/W & Watchdog Timer\\\hline
PWM &\scalebox{0.8}{\tt 0x0410} & 32 & R/W & PWM Audio Controller\\\hline
SPIO &\scalebox{0.8}{\tt 0x0414} & 32 & R/W & Special Purpose I/O, Keypad, LED Controller \\\hline
GPIO &\scalebox{0.8}{\tt 0x0418} & 32 & R/W & GPIO Controller \\\hline
UART &\scalebox{0.8}{\tt 0x041c} & 32 & R/W & UART data\\\hline
VERSION &\scalebox{0.8}{\tt 0x0420} & 32 & R & Build date\\\hline
\end{reglist}
\caption{I/O Peripheral Registers}\label{tbl:ioregs}
\end{center}\end{table}
751,8 → 818,8
writing a `1' to the active bit mask, the interrupt will be acknowledged and
reset, whereas writing a `0' leaves the interrupt untouched. In this fashion,
as individual interrupts are handled, a `1' may be written to this bottom mask
to clear the interrupt. Be aware, however, that any interrupt acknowledgement
may also globally enable or disable interrupts.
to clear the interrupt. Be aware, however, that any write for the purpose of
acknowledging an interrupt will also globally enable or disable interrupts.
 
\subsection{Last Bus Error Address}
The Bus Error peripheral simply records the address of the last bus error,
765,16 → 832,17
restart.
 
\subsection{ZipTimer}
The S6~SoC contains two ZipTimers, available for the CPU to use. These are
countdown timers. Writing any non--zero value to them will cause them to
immediately start counting down from that value towards zero, and to interrupt
the CPU upon the transition to zero. Writing a new value while the timer is
The S6~SoC contains two ZipTimers, one general purpose and one watchdog,
available for the CPU to use. These are both countdown timers. Writing any
non--zero value to them will cause them to immediately start counting down
from that value towards zero, and to interrupt the CPU upon the transition to
zero. Writing a new value while the timer is
running will cause that new value to automatically load into the timer and
start counting from there. Writing a zero to the timer disables the timer, and
causes it to stop.
 
ZipTimer A can be set to auto reload by setting the top bit as well as the
interval. When so set, the timer will automatically
The general purpose ZipTimer can be set to auto reload by setting the top bit
as well as the interval. When so set, the timer will automatically
load it's last set value upon reaching zero and interrupting the CPU. This
effectively turns it into an interrupt timer if desired. To set this feature,
write to the timer the number of clock ticks before an interrupt, but also set
784,15 → 852,15
a cycle at zero, setting it for a 80,000 cycle period requires setting the
timer value to one less than 80,000.}
 
ZipTimer B has been wired for a different purpose. ZipTimer B does not support
auto reload, nor will it interrupt the CPU. Instead, ZipTimer B has been wired
as a watchdog timer. When this timer transitions to zero, the CPU will be
rebooted. One way to use this timer would be in conjunction with the ZipTimer
A, and to write a number to it upon any entry to the interrupt service routine.
If given enough time, this would cause the CPU to reboot if for any reason it
locked up.
The watchdog timer has been wired for a different purpose. It does not support
auto reload, nor will it interrupt the CPU. When this timer transitions to
zero, the CPU will be rebooted. One way to use this timer would be in
conjunction with the general purpose timer, and to write a number to it upon
any entry to the interrupt service routine. If given enough time, this would
cause the CPU to reboot if for any reason it locked up and failed to interrupt
at the general timer interrupt request time.
 
The ZipOS uses ZipTimer~A for task swapping. By setting the timer for
The ZipOS uses the ZipTimer for task swapping. By setting the timer for
1~ms, the ZipOS examines every task for a potential task swap every millisecond.
Of course, if the various tasks are running from Flash at 52~clocks per
instruction, this means that as few as 1,538~instructions may be executed
947,8 → 1015,8
Moving on to the UART \ldots although the UART module itself
within the S6~SoC is highly configurable, as built
the UART can only handle 9600~Baud, 8--data bits, no parity, and one stop bit.
Changing this involves changing the constant {\tt uart\_setup} within
{\tt busmaster.v}. Further, the UART has only a single byte data buffer, so
Changing this involves changing the constant {\tt UART\_SETUP} within
{\tt toplevel.v}. Further, the UART has only a single byte data buffer, so
reading from the port has a real--time requirement associated with it: the
data buffer must be emptied before the next value is read.
Attempts to read from this port will either return an 8--bit data value from
958,8 → 1026,8
and then third immediately clearing the interrupt. (The interrupt cannot
be cleared while data is waiting.) Writing to the UART port is done in a
similar fashion. First, wait until the UART transmit interrupt is asserted
(this will likely be most of the time), second write to the UART port, and
then third clear the interrupt. As with the read interrupt, clearing the
(this will likely be most of the time), second, write to the UART port, and
then third, clear the interrupt. As with the read interrupt, clearing the
transmit interrupt prior to writing to the port will have no effect. Likewise,
clearing the transmit interrupt after the byte has been written will have no
affect either.
971,52 → 1039,6
to configure and use this scope, please see the {\tt WBSCOPE} project on
OpenCores.
 
\section{Internal Configuration Access Port}
The Internal Configuration Access Port (ICAP) provides access to the internal
configuration details of the FPGA. This access was designed so as to provide
the CPU with the capability to command a different FPGA load. In particular,
the code in Fig.~\ref{fig:reload} should reconfigure the FPGA from any given
Quad SPI {\tt address}.\footnote{According to Xilinx's technical support, this
will only work if the JTAG port is not busy--such as when the USB port is
disconnected.}
\begin{figure}\begin{center}\begin{tabbing}
{\tt warmboot(uint32 address) \{} \\
\hbox to 0.25in{}\={\tt uint32\_t *icape6 = (volatile uint32\_t *)0x{\em <ICAPE port address>};}\\
\>{\tt icape6[13] = (address<<2)\&0x0ffff;}\\
\>{\tt icape6[14] = ((address>>14)\&0x0ff)|((0x03)<<8);}\\
\>{\tt icape6[4] = 14;}\\
\>{\em // The CMod~S6 is now reconfiguring itself from the new address.}\\
\>{\em // If all goes well, this routine will never return.}\\
{\tt \}}
\end{tabbing}
\caption{Spartan--6 ICAPE Usage}\label{fig:reload}
\end{center}\end{figure}
 
One subtle problem with this port is that it will not work if the CMod is
plugged in to the USB JTAG port. It will only work if the CMod has been
provided with an independent power supply, leaving the USB JTAG unplugged.
 
For further details, please see either the {\tt WBICAPETWO} project on
OpenCores as well as Xilinx's ``Spartan-6 FPGA Configuration User Guide''.
 
\section{Real--Time Clock}
 
The Real Time Clock will be included if there is enough area to support it.
(There isn't currently \ldots)
The four registers of this port correspond to a clock, a timer, a stopwatch,
and an alarm. If space is tight, the timer and stopwatch, or indeed the entire
clock, may be removed from the design. For further details regarding how to
set and use this clock, please see the {\tt RTCCLOCK} project on OpenCores.
 
There is currently not enough area on the chip to support the Real--Time Clock
together with all of the other peripherals listed here. You can adjust whether
the clock is included or not by adjusting the {\tt `define} lines at the top
of {\tt busmaster.v}. For example, it may be possible to get the RTC back by
disabling the ICAPE2 interface.
 
In place of the RTC capability, the ZipOS offers a software based RTC capability
to simulate the clock register of this port.
 
\section{On-Chip Block RAM}
 
The block RAM is the fastest memory available to the processor. It is also
1035,9 → 1057,9
\begin{table}[htbp]
\begin{center}\begin{tabular}{|p{0.75in}|p{0.75in}|p{0.5in}|p{3.0in}|}\hline
\rowcolor[gray]{0.85} Start & End & & Purpose \\\hline\hline
\scalebox{0.9}{\tt 0x400000} & \scalebox{0.9}{\tt 0x43ffff} & R & Primary configuration space\\\hline
\scalebox{0.9}{\tt 0x440000} & \scalebox{0.9}{\tt 0x47ffff} & R & Alternate configuration space\\\hline
\scalebox{0.9}{\tt 0x480000} & \scalebox{0.9}{\tt 0x7fffff} & R & Zip~CPU program memory\\\hline
\scalebox{0.9}{\tt 0x1000000} & \scalebox{0.9}{\tt 0x10fffff} & R & Primary configuration space\\\hline
\scalebox{0.9}{\tt 0x1100000} & \scalebox{0.9}{\tt 0x11fffff} & R & Alternate configuration space\\\hline
\scalebox{0.9}{\tt 0x1200000} & \scalebox{0.9}{\tt 0x1ffffff} & R & Zip~CPU program memory\\\hline
\end{tabular}
\caption{Flash Address Regions}\label{tbl:flash-addresses}
\end{center}\end{table}

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