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URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

Subversion Repositories s6soc

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  • This comparison shows the changes necessary to convert path 
    /s6soc/trunk/rtl
    from Rev 12 to Rev 13
    ↔ Reverse comparison
  •

Rev 12 → Rev 13

/txuart.v
104,7 → 104,7
`define TXU_IDLE 4'hf
//
//
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, i_cts, o_busy);
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data, o_uart, o_busy);
input i_clk, i_reset;
input [29:0] i_setup;
input i_break;
111,7 → 111,6
input i_wr;
input [7:0] i_data;
output reg o_uart;
input i_cts;
output wire o_busy;
 
wire [27:0] clocks_per_baud, break_condition;
227,7 → 226,6
end
end
 
// assign o_busy = (r_busy)||(~i_cts);
assign o_busy = (r_busy);
endmodule
 
/toplevel.v
115,22 → 115,6
.RST(1'b0));
 
//
// Generate active-high reset.
//
// Actually, we don't. Instead, let this board reset through
// the reconfiguration/power on process and we never use this
// wire.
//
/*
reg r_reset;
initial r_reset = 1'b1;
always @(posedge i_clk_12mhz)
r_reset <= 1'b0;
*/
assign reset_s = 1'b0;
 
 
//
// The UART serial interface
//
// Perhaps this should be part of our simulation model as well.
145,7 → 129,7
 
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
assign tx_break = 1'b0;
rxuart rcvuart(clk_s, reset_s, uart_setup,
rxuart rcvuart(clk_s, 1'b0, uart_setup,
i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
165,7 → 149,7
wire [1:0] qspi_bmod;
wire [15:0] w_gpio;
 
busmaster masterbus(clk_s, reset_s,
busmaster masterbus(clk_s, 1'b0,
// External ... bus control (if enabled)
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts,
// SPI/SD-card flash
/builddate.v
1,7 → 149,7
`define DATESTAMP 32'h20160428
`define DATESTAMP 32'h20160430
/alttop.v
46,7 → 46,7
module alttop(i_clk_8mhz,
o_qspi_cs_n, o_qspi_sck, io_qspi_dat,
i_btn, o_led, o_pwm, o_pwm_shutdown_n, o_pwm_gain,
i_uart, o_uart, i_uart_cts, o_uart_rts,
i_uart, o_uart, o_uart_cts, i_uart_rts,
i_kp_row, o_kp_col,
i_gpio, o_gpio,
io_scl, io_sda,
69,8 → 69,8
input i_uart;
output wire o_uart;
// and it's associated control wires
input i_uart_cts;
output wire o_uart_rts;
output wire o_uart_cts;
input i_uart_rts;
// Our keypad
input [3:0] i_kp_row;
output wire [3:0] o_kp_col;
132,7 → 132,7
i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
o_uart, i_uart_cts, tx_busy);
o_uart, tx_busy);
 
 
//
153,13 → 153,13
wire [7:0] w_depp_data;
 
`ifndef BYPASS_LOGIC
altbusmaster slavedbus(clk_s, reset_s,
altbusmaster slavedbus(clk_s, 1'b0,
// External ... bus control (if enabled)
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
io_depp_data, w_depp_data, o_depp_wait,
// External UART interface
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
rx_stb, rx_data, tx_stb, tx_data, tx_busy, w_uart_cts,
// SPI/SD-card flash
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
// Board lights and switches
171,6 → 171,7
// GPIO lines
{ i_gpio, io_scl, io_sda }, w_gpio
);
assign o_uart_cts = (w_uart_cts)&&(i_uart_rts);
 
//
// Quad SPI support
210,7 → 211,7
 
assign uart_setup = 30'h080002b6;
 
assign o_uart_rts = 1'b1;
assign o_uart_cts = 1'b1;
`endif
//
// I2C support
/busmaster.v
251,7 → 251,8
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = { gpio_int, pwm_int, keypad_int,
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
(~o_tx_stb), rx_rdy,
tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
/altbusmaster.v
52,7 → 52,7
i_depp_data, o_depp_data, o_depp_wait,
// External UART interface
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_rts,
o_uart_cts,
// The SPI Flash lines
o_qspi_cs_n, o_qspi_sck, o_qspi_dat, i_qspi_dat, o_qspi_mod,
// The board I/O
77,7 → 77,7
output reg o_tx_stb;
output reg [7:0] o_tx_data;
input i_tx_busy;
output wire o_uart_rts;
output wire o_uart_cts;
// SPI flash control
output wire o_qspi_cs_n, o_qspi_sck;
output wire [3:0] o_qspi_dat;
254,7 → 254,8
reg rx_rdy;
wire [11:0] int_vector;
assign int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
(~o_tx_stb), rx_rdy,
tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
270,12 → 271,12
 
wire [31:0] timer_a, timer_b;
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
ziptimer #(32,20)
ziptimer #(32,31)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer #(32,20)
ziptimer #(32,31)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
322,11 → 323,13
assign io_stall = 1'b0;
 
wire pwm_ack, pwm_stall;
wbpwmaudio theaudio(i_clk, wb_cyc,
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)), wb_we,
1'b0, wb_data,
pwm_ack, pwm_stall, pwm_data, o_pwm, o_pwm_aux,
pwm_int);
wbpwmaudio #(14'd10000,2,0,14)
theaudio(i_clk, wb_cyc,
((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h4)),
wb_we, 1'b0, wb_data,
pwm_ack, pwm_stall, pwm_data, o_pwm,
o_pwm_aux, //={pwm_shutdown_n,pwm_gain}
pwm_int);
 
//
// Special Purpose I/O: Keypad, button, LED status and control
379,7 → 382,7
else if (i_rx_stb)
rx_rdy <= (rx_rdy | i_rx_stb);
end
assign o_uart_rts = (~rx_rdy);
assign o_uart_cts = (~rx_rdy);
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
//
// uart_ack gets returned as part of io_ack, since that happens when

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