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URL https://opencores.org/ocsvn/s6soc/s6soc/trunk

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    /s6soc/trunk/rtl
    from Rev 7 to Rev 8
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Rev 7 → Rev 8

/wbpwmaudio.v
120,7 → 120,7
initial timer = DEFAULT_RELOAD;
always @(posedge i_clk)
if (timer == 0)
timer <= {{(32-TIMING_BITS){1'b0}}, w_reload_value };
timer <= w_reload_value;
else
timer <= timer - {{(TIMING_BITS-1){1'b0}},1'b1};
 
/rtclight.v
53,8 → 53,8
// A once-per-day strobe on the last clock of the day
o_ppd);
parameter DEFAULT_SPEED = 32'd2814750,
IMPLEMENT_TIMER=1, IMPLEMENT_STOPWATCH=1,
CKBITS = 24; // 100 Mhz
CKBITS = 24, // 100 Mhz
IMPLEMENT_TIMER=1, IMPLEMENT_STOPWATCH=1;
input i_clk;
input i_wb_cyc, i_wb_stb, i_wb_we;
input [2:0] i_wb_addr;
412,9 → 412,17
// meaning that my verilator simulation is running about 300x slower
// than board time.
// initial ckspeed = 32'd786432000;
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data;
generate
if (CKBITS < 32)
begin
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data[(CKBITS-1):0];
end else begin
always @(posedge i_clk)
if ((sp_sel)&&(i_wb_we))
ckspeed <= i_wb_data;
end endgenerate
 
assign o_interrupt = tm_int || al_int;
 
423,6 → 431,14
// connecting this module to a year/month/date date/calendar module.
assign o_ppd = (ck_ppd)&&(ck_pps);
 
wire [31:0] w_ckspeed;
generate
if (CKBITS < 32)
assign w_ckspeed = { {(32-CKBITS){1'b0}}, ckspeed };
else
assign w_ckspeed = ckspeed;
endgenerate
 
always @(posedge i_clk)
case(i_wb_addr[2:0])
3'b000: o_data <= { 10'h0, ck_last_clock };
429,7 → 445,7
3'b001: o_data <= bus_timer_return;
3'b010: o_data <= bus_stopwatch_return;
3'b011: o_data <= { 6'h00, al_tripped, al_enabled, 2'b00, alarm_time };
3'b100: o_data <= ckspeed;
3'b100: o_data <= w_ckspeed;
default: o_data <= 32'h000;
endcase
 
/wbqspiflash.v
52,7 → 52,7
//
///////////////////////////////////////////////////////////////////////////
//
`include "flash_config.v"
`include "flashconfig.v"
//
`define WBQSPI_RESET 0
`define WBQSPI_RESET_QUADMODE 1
/cpu/ziptimer.v
121,7 → 121,7
initial o_int = 1'b0;
always @(posedge i_clk)
if (i_ce)
o_int<=(r_running)&&(r_value == {{(VW-1){1'b0}},1'b1 });
o_int <= (r_running)&&(r_value == { {(VW-1){1'b0}}, 1'b1 });
else
o_int <= 1'b0;
 
132,9 → 132,9
 
generate
if (VW < BW-1)
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
else
assign o_wb_data = { r_auto_reload, r_value };
else
assign o_wb_data = { r_auto_reload, {(BW-1-VW){1'b0}}, r_value };
endgenerate
 
endmodule
/wbdeppsimple.v
0,0 → 1,155
////////////////////////////////////////////////////////////////////////////////
//
// Filename: wbdeppsimple.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is a very simple DEPP to Wishbone driver. It cannot handle
// pipeline reads or writes, it cannot compress anything being
// transmitted, however it can read/write a 32-bit wishbone bus with a
// proper software driver.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module wbdeppsimple(i_clk,
i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
o_wb_cyc, o_wb_stb, o_wb_we, o_wb_addr, o_wb_data,
i_wb_ack, i_wb_stall, i_wb_err, i_wb_data, i_int);
input i_clk;
// DEPP interface
input i_astb_n, i_dstb_n, i_write_n;
input [7:0] i_depp;
output reg [7:0] o_depp;
output wire o_wait;
// Wishbone master interface
output reg o_wb_cyc, o_wb_stb, o_wb_we;
output reg [31:0] o_wb_addr, o_wb_data;
input i_wb_ack, i_wb_stall, i_wb_err;
input [31:0] i_wb_data;
input i_int;
 
// Synchronize the incoming signals
reg x_dstb_n, x_astb_n, x_write_n,
r_dstb_n, r_astb_n, r_write_n,
l_dstb_n, l_astb_n;
reg [7:0] x_depp, r_depp;
initial x_dstb_n = 1'b1;
initial r_dstb_n = 1'b1;
initial l_dstb_n = 1'b1;
initial x_astb_n = 1'b1;
initial r_astb_n = 1'b1;
initial l_astb_n = 1'b1;
always @(posedge i_clk)
begin
{ x_dstb_n, x_astb_n, x_write_n, x_depp }
<= { i_dstb_n, i_astb_n, i_write_n, i_depp };
{ r_dstb_n, r_astb_n, r_write_n, r_depp }
<= { x_dstb_n, x_astb_n, x_write_n, x_depp };
{ l_dstb_n, l_astb_n } <= { r_dstb_n, r_astb_n };
end
 
wire w_wait;
assign w_wait = ~(&{x_dstb_n, x_astb_n,
r_dstb_n, r_astb_n,
l_dstb_n, l_astb_n});
 
reg [7:0] addr;
reg [31:0] r_data;
 
wire astb, dstb, w_write;
assign astb = (~r_astb_n)&&(l_astb_n);
assign dstb = (~r_dstb_n)&&(l_dstb_n);
assign w_write= (~r_write_n);
 
initial o_wb_cyc = 1'b0;
initial o_wb_stb = 1'b0;
initial addr = 8'h00;
always @(posedge i_clk)
begin
if ((w_write)&&(astb))
addr <= r_depp;
 
if ((w_write)&&(dstb)&&(addr[7:3]==5'h00))
begin
case(addr[2:0])
//
3'b000: o_wb_addr[31:24] <= r_depp;
3'b001: o_wb_addr[23:16] <= r_depp;
3'b010: o_wb_addr[15: 8] <= r_depp;
3'b011: o_wb_addr[ 7: 0] <= r_depp;
//
3'b100: o_wb_data[31:24] <= r_depp;
3'b101: o_wb_data[23:16] <= r_depp;
3'b110: o_wb_data[15: 8] <= r_depp;
3'b111: o_wb_data[ 7: 0] <= r_depp;
//
endcase
end
if ((o_wb_cyc)&&(i_wb_ack)&&(~o_wb_we))
r_data <= i_wb_data;
 
// Direct BUS control
if ((w_write)&&(dstb)&&(|addr[7:3]))
begin
o_wb_cyc <= r_depp[0];
o_wb_stb <= r_depp[0];
o_wb_we <= r_depp[1];
end else begin
o_wb_stb <= 1'b0;
if ((o_wb_cyc)&&(i_wb_ack))
o_wb_cyc <= 1'b0;
end
end
 
assign o_wait = (w_wait);
 
reg r_int, r_err;
initial r_int = 1'b0;
initial r_err = 1'b0;
always @(posedge i_clk)
begin
if (addr[4])
o_depp <= { 5'h0, o_wb_cyc, r_int, r_err };
else case(addr[2:0])
3'b000: o_depp <= o_wb_addr[31:24];
3'b001: o_depp <= o_wb_addr[23:16];
3'b010: o_depp <= o_wb_addr[15: 8];
3'b011: o_depp <= o_wb_addr[ 7: 0];
3'b100: o_depp <= r_data[31:24];
3'b101: o_depp <= r_data[23:16];
3'b110: o_depp <= r_data[15: 8];
3'b111: o_depp <= r_data[ 7: 0];
endcase
 
r_int <= (i_int) ||((r_int)&&((~dstb)||(w_write)||(~addr[4])));
r_err <= (i_wb_err)||((r_err)&&((~dstb)||(w_write)||(~addr[4])));
end
 
endmodule
/builddate.v
1,0 → 1,155
`define DATESTAMP 32'h20160422
`define DATESTAMP 32'h20160423
/alttop.v
49,7 → 49,10
i_uart, o_uart, i_uart_cts, o_uart_rts,
i_kp_row, o_kp_col,
i_gpio, o_gpio,
io_scl, io_sda);
io_scl, io_sda,
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n, io_depp_data,
o_depp_wait
);
input i_clk_8mhz;
//
// Quad SPI Flash
76,6 → 79,10
output wire [15:2] o_gpio;
// and our I2C port
inout io_scl, io_sda;
// Finally, the DEPP interface ... if so enabled
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
inout [7:0] io_depp_data;
output wire o_depp_wait;
 
//
// Clock management
107,22 → 114,6
.RST(1'b0));
 
//
// Generate active-high reset.
//
// Actually, we don't. Instead, let this board reset through
// the reconfiguration/power on process and we never use this
// wire.
//
/*
reg r_reset;
initial r_reset = 1'b1;
always @(posedge i_clk_12mhz)
r_reset <= 1'b0;
*/
assign reset_s = 1'b0;
 
 
//
// The UART serial interface
//
// Perhaps this should be part of our simulation model as well.
137,7 → 128,7
 
wire rx_break, rx_parity_err, rx_frame_err, rx_ck_uart, tx_break;
assign tx_break = 1'b0;
rxuart rcvuart(clk_s, reset_s, uart_setup,
rxuart rcvuart(clk_s, 1'b0, uart_setup,
i_uart, rx_stb, rx_data,
rx_break, rx_parity_err, rx_frame_err, rx_ck_uart);
txuart tcvuart(clk_s, reset_s, uart_setup, tx_break, tx_stb, tx_data,
159,9 → 150,15
wire [3:0] qspi_dat;
wire [1:0] qspi_bmod;
wire [15:0] w_gpio;
wire [7:0] w_depp_data;
 
`ifndef BYPASS_LOGIC
altbusmaster slavedbus(clk_s, reset_s,
// External ... bus control (if enabled)
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
io_depp_data, w_depp_data, o_depp_wait,
// External UART interface
rx_stb, rx_data, tx_stb, tx_data, tx_busy, o_uart_rts,
// SPI/SD-card flash
o_qspi_cs_n, o_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
187,6 → 184,34
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
 
`else
reg [26:0] r_counter;
always @(posedge clk_s)
r_counter <= r_counter+1;
assign o_led[0] = r_counter[26];
assign o_led[1] = r_counter[25];
assign o_led[2] = r_counter[24];
assign o_led[3] = r_counter[23];
// assign o_led[0] = 1'b1;
// assign o_led[1] = 1'b0;
// assign o_led[2] = 1'b1;
// assign o_led[3] = 1'b0;
 
assign w_gpio = 16'h3;
assign o_pwm = 1'b0;
assign o_pwm_shutdown_n = 1'b0;
assign o_pwm_gain = 1'b0;
 
assign o_depp_wait = (~i_depp_astb_n);
assign w_depp_data = 8'h00;
assign io_qspi_dat = 4'bzzzz;
assign o_qspi_cs_n = 1'b1;
assign o_qspi_sck = 1'b1;
 
assign uart_setup = 30'h080002b6;
 
assign o_uart_rts = 1'b1;
`endif
//
// I2C support
//
201,4 → 226,9
assign io_scl = (w_gpio[1]) ? 1'bz : 1'b0;
assign o_gpio[15:2] = w_gpio[15:2];
 
//
// DEPP return data support
//
assign io_depp_data = (~i_depp_write_n)? 8'bzzzz_zzzz : w_depp_data;
 
endmodule
/busmaster.v
59,11 → 59,10
o_uart_setup,
// GPIO lines
i_gpio, o_gpio);
parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
input i_clk, i_rst;
// The bus commander, via an external JTAG port
input i_rx_stb;
input [7:0] i_rx_data;
output reg o_tx_stb;
260,7 → 259,7
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
initial bus_err_addr = `DATESTAMP;
initial bus_err_addr = 0; // `DATESTAMP;
always @(posedge i_clk)
if (wb_err)
bus_err_addr <= wb_addr;
290,7 → 289,7
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5,23,0,0) // 80 MHz clock
#(23'h35afe5,23,0,0) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
/altbusmaster.v
43,9 → 43,13
`define FANCY_ICAP_ACCESS
`endif
`define FLASH_ACCESS
`define CFG_SCOPE
`define INCLUDE_RTC // 2017 slice LUTs w/o, 2108 with (!!!)
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC // About 90 LUTs
module altbusmaster(i_clk, i_rst,
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
i_depp_data, o_depp_data, o_depp_wait,
// External UART interface
i_rx_stb, i_rx_data, o_tx_stb, o_tx_data, i_tx_busy,
o_uart_rts,
// The SPI Flash lines
58,15 → 62,19
o_uart_setup,
// GPIO lines
i_gpio, o_gpio);
parameter ZIP_ADDRESS_WIDTH=23, ZA=ZIP_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
BUS_ADDRESS_WIDTH=23, BAW=23; // 24bits->2,258,23b->2181
parameter BUS_ADDRESS_WIDTH=23,
BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
input i_clk, i_rst;
// The bus commander, via an external JTAG port
// The bus commander, via an external DEPP port
input i_depp_astb_n, i_depp_dstb_n, i_depp_write_n;
input wire [7:0] i_depp_data;
output wire [7:0] o_depp_data;
output wire o_depp_wait;
// Serial inputs
input i_rx_stb;
input [7:0] i_rx_data;
output wire o_tx_stb;
output wire [7:0] o_tx_data;
output reg o_tx_stb;
output reg [7:0] o_tx_data;
input i_tx_busy;
output wire o_uart_rts;
// SPI flash control
95,7 → 103,7
//
//
wire wb_cyc, wb_stb, wb_we, wb_stall, wb_ack, wb_err;
wire [31:0] wb_data, wb_idata;
wire [31:0] wb_data, wb_idata, w_wbu_addr;
wire [(BAW-1):0] wb_addr;
wire [5:0] io_addr;
assign io_addr = {
109,27 → 117,12
// Wires going to devices
// And then headed back home
wire w_interrupt;
// Oh, and the debug control for the ZIP CPU
wire zip_dbg_ack, zip_dbg_stall;
wire [31:0] zip_dbg_data;
 
 
`ifdef WBUBUS
//
//
// The BUS master (source): The WB to UART conversion bus
//
//
wire zip_cyc, zip_stb, zip_we, zip_cpu_int;
wire [(ZA-1):0] w_zip_addr;
wire [(BAW-1):0] zip_addr;
wire [31:0] zip_data;
// and then coming from devices
wire zip_ack, zip_stall, zip_err;
wire dwb_we, dwb_stb, dwb_cyc, dwb_ack, dwb_stall, dwb_err;
wire [(BAW-1):0] dwb_addr;
wire [31:0] dwb_odata;
 
// wire [31:0] zip_debug;
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
// The wishbone interface
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
138,12 → 131,25
// Provide feedback to the UART
o_tx_stb, o_tx_data, i_tx_busy);
assign o_uart_rts = (~rx_rdy);
`else
//
//
// Another BUS master (source): A conversion from DEPP to busmaster
//
//
wbdeppsimple deppdrive(i_clk,
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
i_depp_data, o_depp_data, o_depp_wait,
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
wb_ack, wb_stall, wb_err, wb_idata,
w_interrupt);
`endif
 
generate
if (ZA < BAW)
assign wb_addr = { {(BAW-ZA){1'b0}}, w_wbu_addr };
if (BAW < 32)
assign wb_addr = w_wbu_addr[(BAW-1):0];
else
assign wb_addr = w_zip_addr;
assign wb_addr = w_wbu_addr;
endgenerate
 
wire io_sel, flash_sel, flctl_sel, scop_sel, cfg_sel, mem_sel,
154,7 → 160,7
assign rtc_stall = 1'b0;
`endif
wire io_stall, flash_stall, scop_stall, cfg_stall, mem_stall;
reg io_ack, uart_ack;
reg io_ack;
 
wire [31:0] flash_data, scop_data, cfg_data, mem_data, pwm_data,
spio_data, gpio_data, uart_data;
162,7 → 168,6
reg [(BAW-1):0] bus_err_addr;
 
assign wb_ack = (wb_cyc)&&((io_ack)||(scop_ack)||(cfg_ack)
||(uart_ack)
`ifdef INCLUDE_RTC
||(rtc_ack)
`endif
186,9 → 191,8
: 32'h00))));
*/
assign wb_idata = (io_ack|scop_ack)?((io_ack )? io_data : scop_data)
: ((cfg_ack|uart_ack) ? ((cfg_ack)?cfg_data: uart_data)
: ((mem_ack|rtc_ack)?((mem_ack)?mem_data:rtc_data)
: flash_data)); // if (flash_ack)
: ((cfg_ack) ? cfg_data : flash_data));//if (flash_ack)
assign wb_err = ((wb_cyc)&&(wb_stb)&&(none_sel || many_sel)) || many_ack;
 
// Addresses ...
195,9 → 199,9
// 0000 xxxx configuration/control registers
// 1 xxxx xxxx xxxx xxxx xxxx Up-sampler taps
assign io_sel =((wb_cyc)&&(io_addr[5:0]==6'h1));
assign flctl_sel= 1'b0; // ((wb_cyc)&&(io_addr[5:1]==5'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:1]==5'h1));
assign cfg_sel =((wb_cyc)&&(io_addr[5:2]==4'h1));
assign scop_sel =((wb_cyc)&&(io_addr[5:0]==6'h2));
assign flctl_sel=((wb_cyc)&&(io_addr[5:0]==6'h3));
assign cfg_sel =((wb_cyc)&&(io_addr[5:1]==5'h2));
// zip_sel is not on the bus at this point
`ifdef INCLUDE_RTC
assign rtc_sel =((wb_cyc)&&(io_addr[5:3]==3'h1));
206,16 → 210,15
assign flash_sel=((wb_cyc)&&(io_addr[5]));
 
assign none_sel =((wb_cyc)&&(wb_stb)&&(io_addr==6'h0));
/*
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
// +{3'h0, scop_sel}
+{3'h0, scop_sel}
+{3'h0, cfg_sel}
+{3'h0, rtc_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
*/
assign many_sel = 1'b0;
// assign many_sel = 1'b0;
 
wire many_ack;
assign many_ack =((wb_cyc)&&(
238,17 → 241,16
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = { gpio_int, pwm_int, keypad_int,
1'b0, rx_rdy, tmrb_int, tmra_int,
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
wire [31:0] pic_data;
icontrol #(11) pic(i_clk, 1'b0,
(wb_cyc)&&(wb_stb)&&(io_sel)
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
initial bus_err_addr = `DATESTAMP;
initial bus_err_addr = 0; // `DATESTAMP;
always @(posedge i_clk)
if (wb_err)
bus_err_addr <= wb_addr;
255,11 → 257,13
 
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer #(32,20)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
ziptimer #(32,20)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
tmrb_int);
276,7 → 280,7
assign rtc_ack = r_rtc_ack;
 
rtclight
#(32'h35afe5) // 80 MHz clock
#(23'h35afe5,23,0,0) // 80 MHz clock
thetime(i_clk, wb_cyc,
((wb_stb)&&(rtc_sel)), wb_we,
{ 1'b0, wb_addr[1:0] }, wb_data, rtc_data,
338,8 → 342,38
// hardware buffer.
//
// We'll add the flag for two stop bits.
assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
// assign o_uart_setup = 30'h080002b6; // 115200 MBaud @ an 80MHz clock
assign o_uart_setup = 30'h0000208d; // 9600 MBaud, 8N1
 
initial o_tx_stb = 1'b0;
initial o_tx_data = 8'h00;
always @(posedge i_clk)
if ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(wb_we))
begin
o_tx_data <= wb_data[7:0];
o_tx_stb <= 1'b1;
end
else if ((o_tx_stb)&&(~i_tx_busy))
o_tx_stb <= 1'b0;
initial rx_rdy = 1'b0;
always @(posedge i_clk)
if (i_rx_stb)
r_rx_data <= i_rx_data;
always @(posedge i_clk)
begin
if((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7)&&(~wb_we))
rx_rdy <= i_rx_stb;
else if (i_rx_stb)
rx_rdy <= (rx_rdy | i_rx_stb);
end
assign o_uart_rts = (~rx_rdy);
assign uart_data = { 23'h0, ~rx_rdy, r_rx_data };
//
// uart_ack gets returned as part of io_ack, since that happens when
// io_sel and wb_stb are defined
//
// always @(posedge i_clk)
// uart_ack<= ((wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h7));
 
 
 
349,7 → 383,7
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflashp #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[21:0], wb_data,
wb_addr[(24-3):0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
flash_interrupt);
377,8 → 411,17
//
// ON-CHIP RAM MEMORY ACCESS
//
`ifdef IMPLEMENT_ONCHIP_RAM
memdev #(12) ram(i_clk, wb_cyc, (wb_stb)&&(mem_sel), wb_we,
wb_addr[11:0], wb_data, mem_ack, mem_stall, mem_data);
`else
assign mem_data = 32'h00;
assign mem_stall = 1'b0;
reg r_mem_ack;
always @(posedge i_clk)
r_mem_ack <= (wb_cyc)&&(wb_stb)&&(mem_sel);
assign mem_ack = r_mem_ack;
`endif
 
//
//
389,15 → 432,22
//
wire [31:0] scop_cfg_data;
wire scop_cfg_ack, scop_cfg_stall, scop_cfg_interrupt;
`ifdef CFG_SCOPE
`ifdef DBG_SCOPE
wire scop_cfg_trigger;
assign scop_cfg_trigger = (wb_cyc)&&(wb_stb)&&(cfg_sel);
wbscope #(5'ha) wbcfgscope(i_clk, 1'b1, scop_cfg_trigger, cfg_scope,
// Wishbone interface
i_clk, wb_cyc, ((wb_stb)&&(scop_sel)&&(wb_addr[2:1]==2'b01)),
i_clk, wb_cyc, (wb_stb)&&(scop_sel),
wb_we, wb_addr[0], wb_data,
scop_cfg_ack, scop_cfg_stall, scop_cfg_data,
scop_cfg_interrupt);
`else
reg r_scop_cfg_ack;
always @(posedge i_clk)
r_scop_cfg_ack <= (wb_cyc)&&(wb_stb)&&(scop_sel);
assign scop_cfg_ack = r_scop_cfg_ack;
assign scop_cfg_data = 32'h000;
assign scop_cfg_stall= 1'b0;
`endif
 
assign scop_interrupt = scop_cfg_interrupt;
407,4 → 457,3
 
endmodule
 
// 0x8684 interrupts ...???
/Makefile
0,0 → 1,89
################################################################################
#
# Filename: rtl/Makefile
#
# Project: CMod S6 System on a Chip, ZipCPU demonstration project
#
# Purpose: This makefile builds a verilator simulation of the zipsystem.
# It does not make the system within Vivado or Quartus.
#
# Creator: Dan Gisselquist, Ph.D.
# Gisselquist Technology, LLC
#
################################################################################
#
# Copyright (C) 2015-2016, Gisselquist Technology, LLC
#
# This program is free software (firmware): you can redistribute it and/or
# modify it under the terms of the GNU General Public License as published
# by the Free Software Foundation, either version 3 of the License, or (at
# your option) any later version.
#
# This program is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program. (It's in the $(ROOT)/doc directory, run make with no
# target there if the PDF file isn't present.) If not, see
# <http://www.gnu.org/licenses/> for a copy.
#
# License: GPL, v3, as defined and found on www.gnu.org,
# http://www.gnu.org/licenses/gpl.html
#
#
################################################################################
#
#
.PHONY: all
all: busmaster altbusmaster
 
CPUD := cpu
RAWZIP := zipbones.v zipcpu.v cpudefs.v \
prefetch.v idecode.v cpuops.v memops.v \
wbdblpriarb.v
ZIPSRC := $(addprefix $(CPUD)/,$(RAWZIP))
BUSSRC := builddate.v llqspi.v wbicape6.v wbicapesimple.v wbscope.v \
memdev.v rtclight.v spio.v wbgpio.v wbpwmaudio.v
MAINSRC := busmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) $(ZIPSRC)
# toplevel.v rxuart.v txuart.v
ALTSRC := altbusmaster.v builddate.v flash_config.v wbqspiflash.v \
$(BUSSRC) wbdeppsimple.v
# alttop.v rxuart.v txuart.v
# rtcdate.v wbubus.v
 
VOBJ := obj_dir
 
$(VOBJ)/Vbusmaster.cpp: $(MAINSRC)
verilator -cc -y $(CPUD) busmaster.v
$(VOBJ)/Vbusmaster.h: $(VOBJ)/Vbusmaster.cpp
 
$(VOBJ)/Valtbusmaster.cpp: $(ALTSRC)
verilator -cc -y $(CPUD) altbusmaster.v
$(VOBJ)/Valtbusmaster.h: $(VOBJ)/Valtbusmaster.cpp
 
$(VOBJ)/Vbusmaster__ALL.a: $(VOBJ)/Vbusmaster.cpp $(VOBJ)/Vbusmaster.h
cd $(VOBJ); make --no-print-directory -f Vbusmaster.mk
 
$(VOBJ)/Valtbusmaster__ALL.a: $(VOBJ)/Valtbusmaster.cpp $(VOBJ)/Valtbusmaster.h
cd $(VOBJ); make --no-print-directory -f Valtbusmaster.mk
 
cpudefs.h: cpudefs.v
@echo "Building cpudefs.h"
@echo "// " > $@
@echo "// Do not edit this file, it is automatically generated!" >> $@
@echo "// To generate this file, \"make cpudefs.h\" in the rtl directory." >> $@
@echo "// " >> $@
@grep "^\`" $^ | sed -e '{ s/^`/#/ }' >> $@
 
.PHONY: busmaster
busmaster: $(VOBJ)/Vbusmaster__ALL.a
 
.PHONY: altbusmaster
altbusmaster: $(VOBJ)/Valtbusmaster__ALL.a
 
.PHONY: clean
clean:
rm -rf $(VOBJ) cpudefs.h
/spio.v
6,6 → 6,8
//
// Purpose:
//
// With the USB cord on top, the board facing you, LED[0] is on the left.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//

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