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Rev 8 → Rev 11

/deppbyte.v
0,0 → 1,135
////////////////////////////////////////////////////////////////////////////////
//
// Filename: deppbyte.v
//
// Project: CMod S6 System on a Chip, ZipCPU demonstration project
//
// Purpose: This is a very simple DEPP to synchronous byte transfer. It
// is used in place of a serial port.
//
// This approach uses address zero *only*.
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2015-2016, Gisselquist Technology, LLC
//
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory, run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
//
// License: GPL, v3, as defined and found on www.gnu.org,
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
//
module deppbyte(i_clk,
i_astb_n, i_dstb_n, i_write_n,i_depp, o_depp, o_wait,
o_rx_stb, o_rx_data,
i_tx_stb, i_tx_data, o_tx_busy);
input i_clk;
// DEPP interface
input i_astb_n, i_dstb_n, i_write_n;
input [7:0] i_depp;
output reg [7:0] o_depp;
output wire o_wait;
// Byte-wise interface to the rest of the world
output reg o_rx_stb;
output reg [7:0] o_rx_data;
input i_tx_stb;
input [7:0] i_tx_data;
output reg o_tx_busy;
 
// Synchronize the incoming signals
reg x_dstb_n, x_astb_n, x_write_n,
r_dstb_n, r_astb_n, r_write_n,
l_dstb_n, l_astb_n, l_write_n;
reg [7:0] x_depp, r_depp;
initial x_dstb_n = 1'b1;
initial r_dstb_n = 1'b1;
initial l_dstb_n = 1'b1;
initial x_astb_n = 1'b1;
initial r_astb_n = 1'b1;
initial l_astb_n = 1'b1;
always @(posedge i_clk)
begin
{ x_dstb_n, x_astb_n, x_write_n, x_depp }
<= { i_dstb_n, i_astb_n, i_write_n, i_depp };
{ r_dstb_n, r_astb_n, r_write_n, r_depp }
<= { x_dstb_n, x_astb_n, x_write_n, x_depp };
{ l_dstb_n, l_astb_n, l_write_n } <= { r_dstb_n, r_astb_n, r_write_n };
end
 
reg [7:0] addr;
wire astb, dstb, w_write;
assign astb = (~r_astb_n)&&(l_astb_n);
assign dstb = (~r_dstb_n)&&(l_dstb_n);
assign w_write= (~r_write_n);
 
 
initial addr = 8'h00;
initial o_rx_stb = 1'b0;
always @(posedge i_clk)
begin
if ((w_write)&&(astb))
addr <= r_depp;
 
if ((w_write)&&(dstb)&&(addr==0))
begin
o_rx_stb <= 1'b1;
o_rx_data <= r_depp;
end else
o_rx_stb <= 1'b0;
end
 
// Much as I hate to use signals that have not been synchronized with a
// two clock transfer, this line needs to be brought low within 10ms
// (less than one clock) of when the strobe lines are brought low, and
// raised high again within 10 ms of when the strobe lines are raised
// again.
assign o_wait = ((~i_dstb_n)||(~i_astb_n));
 
// For one clock, following any read from address zero, we allow the
// port to write one new byte into our interface. This works because
// the interface will guarantee that the strobe signals are inactive
// (high) for at least 40ns before attempting a new transaction.
//
// Just about nothing else works. 'cause we can't allow changes
// in the middle of a transaction, and we won't know if the clock
// involved is in the middle of a transaction until after the time
// has passed. Therefore, we're going to be busy most of the time
// and just allow a byte to pass through on the one (and only) clock
// following a transaction.
always @(posedge i_clk)
o_tx_busy <= ((~l_dstb_n)&&(r_dstb_n)&&(l_write_n)&&(addr == 0))
? 1'b0 : 1'b1;
 
// If we don't have a byte to write, stuff it with all ones. The high
// bit will then indicate that there's nothing available to the
// interface when it next reads.
//
// Okay, new philosophy. Stuff the high bit with ones, allow the other
// bits to contain status level information --- should any one wish to
// send such.
initial o_depp = 8'hff;
always @(posedge i_clk)
if (~o_tx_busy)
o_depp <= {((i_tx_stb)? i_tx_data[7] : 1'b1),
i_tx_data[6:0] };
 
endmodule
/wbqspiflash.v
65,10 → 65,10
`define WBQSPI_READ_CMD 8
`define WBQSPI_READ_DATA 9
`define WBQSPI_WAIT_TIL_RDIDLE 10
`define WBQSPI_READ_ID_CMD 11
`define WBQSPI_READ_ID 12
`define WBQSPI_READ_STATUS 13
`define WBQSPI_READ_CONFIG 14
`define WBQSPI_READ_ID_CMD 11 //
`define WBQSPI_READ_ID 12 //
`define WBQSPI_READ_STATUS 13 //
`define WBQSPI_READ_CONFIG 14 //
`define WBQSPI_WAIT_TIL_IDLE 15
//
//
147,6 → 147,7
end
 
reg [7:0] last_status;
reg [9:0] reset_counter;
reg quad_mode_enabled;
reg spif_cmd, spif_override;
reg [(ADDRESS_WIDTH-3):0] spif_addr;
153,6 → 154,7
reg [31:0] spif_data;
reg [5:0] state;
reg spif_ctrl, spif_req;
reg alt_cmd, alt_ctrl;
wire [(ADDRESS_WIDTH-17):0] spif_sector;
assign spif_sector = spif_addr[(ADDRESS_WIDTH-3):14];
 
165,9 → 167,12
initial spi_len = 2'b00;
initial quad_mode_enabled = 1'b0;
initial o_interrupt = 1'b0;
initial spif_override = 1'b1;
always @(posedge i_clk_100mhz)
begin
spif_override <= 1'b0;
alt_cmd <= (reset_counter[9:8]==2'b10)?reset_counter[3]:1'b1; // Toggle CS_n
alt_ctrl <= (reset_counter[9:8]==2'b10)?reset_counter[0]:1'b1; // Toggle clock too
if (state == `WBQSPI_RESET)
begin
// From a reset, we should
185,7 → 190,8
state <= `WBQSPI_RESET_QUADMODE;
spif_req <= 1'b0;
spif_override <= 1'b1;
last_status <= 8'hfc; //
last_status <= 8'h00; //
reset_counter <= 10'h3fc; //
// This guarantees that we aren't starting in quad
// I/O mode, where the FPGA configuration scripts may
// have left us.
193,21 → 199,28
begin
// Okay, so here's the problem: we don't know whether or not
// the Xilinx loader started us up in Quad Read I/O idle mode.
// So, thus we need to
// So, thus we need to toggle the clock and CS_n, with fewer
// clocks than are necessary to transmit a word.
//
// Not ready to handle the bus yet, so stall any requests
o_wb_ack <= 1'b0;
o_wb_stall <= 1'b1;
 
// Do something ...
if (last_status == 8'h00)
if (reset_counter == 10'h00)
begin
spif_override <= 1'b0;
state <= `WBQSPI_IDLE;
 
// Find out if we can use Quad I/O mode ...
state <= `WBQSPI_READ_CONFIG;
spi_wr <= 1'b1;
spi_len <= 2'b01;
spi_in <= { 8'h35, 24'h00};
 
end else begin
last_status <= last_status - 8'h1;
reset_counter <= reset_counter - 10'h1;
spif_override <= 1'b1;
spif_cmd <= last_status[3]; // Toggle CS_n
spif_ctrl <= last_status[0]; // Toggle clock too
end
end else if (state == `WBQSPI_IDLE)
begin
1184,8 → 1197,8
end
 
// Command and control during the reset sequence
assign o_qspi_cs_n = (spif_override)?spif_cmd :w_qspi_cs_n;
assign o_qspi_sck = (spif_override)?spif_ctrl:w_qspi_sck;
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
assign o_qspi_cs_n = (spif_override)?alt_cmd :w_qspi_cs_n;
assign o_qspi_sck = (spif_override)?alt_ctrl:w_qspi_sck;
assign o_qspi_mod = (spif_override)? 2'b01 :w_qspi_mod;
assign o_qspi_dat = (spif_override)? 4'b00 :w_qspi_dat;
endmodule
/cpu/idecode.v
75,21 → 75,25
output reg [3:0] o_cond;
output reg o_wF;
output reg [3:0] o_op;
output reg o_ALU, o_M, o_DV, o_FP, o_break, o_lock;
output reg o_ALU, o_M, o_DV, o_FP, o_break;
output wire o_lock;
output reg o_wR, o_rA, o_rB;
output wire o_early_branch;
output wire [(AW-1):0] o_branch_pc;
output wire o_ljmp;
output reg o_pipe;
output wire o_pipe;
 
wire dcdA_stall, dcdB_stall, dcdF_stall;
wire o_dcd_early_branch;
wire [(AW-1):0] o_dcd_branch_pc;
reg o_dcdI, o_dcdIz;
`ifdef OPT_PIPELINED
reg r_lock, r_pipe;
`endif
 
 
wire [4:0] w_op;
wire w_ldi, w_mov, w_cmptst, w_ldixx, w_ALU;
wire w_ldi, w_mov, w_cmptst, w_ldilo, w_ALU, w_brev, w_noop;
wire [4:0] w_dcdR, w_dcdB, w_dcdA;
wire w_dcdR_pc, w_dcdR_cc;
wire w_dcdA_pc, w_dcdA_cc;
98,16 → 102,9
wire w_wF, w_dcdM, w_dcdDV, w_dcdFP;
wire w_wR, w_rA, w_rB, w_wR_n;
wire w_ljmp;
wire [31:0] iword;
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
wire [31:0] iword;
`ifdef OPT_VLIW
reg [16:0] r_nxt_half;
assign iword = (o_phase)
119,16 → 116,37
assign iword = { 1'b0, i_instruction[30:0] };
`endif
 
generate
if (EARLY_BRANCHING != 0)
assign w_ljmp = (iword == 32'h7c87c000);
else
assign w_ljmp = 1'b0;
endgenerate
 
 
assign w_op= iword[26:22];
assign w_mov = (w_op == 5'h0f);
assign w_ldi = (w_op[4:1] == 4'hb);
assign w_brev = (w_op == 5'hc);
assign w_cmptst = (w_op[4:1] == 4'h8);
assign w_ldixx = (w_op[4:1] == 4'h4);
assign w_ldilo = (w_op[4:0] == 5'h9);
assign w_ALU = (~w_op[4]);
 
// 4 LUTs
//
// Two parts to the result register: the register set, given for
// moves in i_word[18] but only for the supervisor, and the other
// four bits encoded in the instruction.
//
assign w_dcdR = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[18]:i_gie,
iword[30:27] };
// 2 LUTs
//
// If the result register is either CC or PC, and this would otherwise
// be a floating point instruction with floating point opcode of 0,
// then this is a NOOP.
assign w_noop = (w_op[4:0] == 5'h18)&&(w_dcdR[3:1] == 3'h7);
 
// 4 LUTs
assign w_dcdB = { ((~iword[31])&&(w_mov)&&(~i_gie))?iword[13]:i_gie,
iword[17:14] };
175,7 → 193,7
||(w_op[4:1]== 4'h8);
// 1 LUTs -- do we read a register for operand B? Specifically, do
// we need to stall if the register is not (yet) ready?
assign w_rB = (w_mov)||((iword[18])&&((~w_ldi)&&(~w_ldixx)));
assign w_rB = (w_mov)||((iword[18])&&(~w_ldi));
// 1 LUT: All but STO, NOOP/BREAK/LOCK, and CMP/TST write back to w_dcdR
assign w_wR_n = ((w_dcdM)&&(w_op[0]))
||((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7))
188,7 → 206,7
// and writes to the PC/CC register(s).
assign w_wF = (w_cmptst)
||((w_cond[3])&&((w_dcdFP)||(w_dcdDV)
||((w_ALU)&&(~w_mov)&&(~w_ldixx)
||((w_ALU)&&(~w_mov)&&(~w_ldilo)&&(~w_brev)
&&(iword[30:28] != 3'h7))));
 
// Bottom 13 bits: no LUT's
271,8 → 289,10
 
if ((w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)
&&(
(w_op[2:0] != 3'h2) // LOCK
&&(w_op[2:0] != 3'h1) // BREAK
(w_op[2:0] != 3'h1) // BREAK
`ifdef OPT_PIPELINED
&&(w_op[2:0] != 3'h2) // LOCK
`endif
&&(w_op[2:0] != 3'h0))) // NOOP
o_illegal <= 1'b1;
end
313,7 → 333,7
// o_FP plus these four bits uniquely defines the FP
// instruction, o_DV plus the bottom of these defines
// the divide, etc.
o_op <= (w_ldi)? 4'hf:w_op[3:0];
o_op <= (w_ldi)||(w_noop)? 4'hf:w_op[3:0];
 
// Default values
o_dcdR <= { w_dcdR_cc, w_dcdR_pc, w_dcdR};
325,13 → 345,20
r_I <= w_I;
o_zI <= w_Iz;
 
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst); // 1 LUT
// Turn a NOOP into an ALU operation--subtract in
// particular, although it doesn't really matter as long
// as it doesn't take longer than one clock. Note
// also that this depends upon not setting any registers
// or flags, which should already be true.
o_ALU <= (w_ALU)||(w_ldi)||(w_cmptst)||(w_noop); // 2 LUT
o_M <= w_dcdM;
o_DV <= w_dcdDV;
o_FP <= w_dcdFP;
 
o_break <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b001);
o_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
`ifdef OPT_PIPELINED
r_lock <= (w_op[4:3]==2'b11)&&(w_dcdR[3:1]==3'h7)&&(w_op[2:0]==3'b010);
`endif
`ifdef OPT_VLIW
r_nxt_half <= { iword[31], iword[13:5],
((iword[21])? iword[20:19] : 2'h0),
339,6 → 366,12
`endif
end
 
`ifdef OPT_PIPELINED
assign o_lock = r_lock;
`else
assign o_lock = 1'b0;
`endif
 
generate
if (EARLY_BRANCHING!=0)
begin
410,16 → 443,25
// taking place, and it's only valid if the new word is not compressed.
//
reg r_valid;
`ifdef OPT_PIPELINED
reg r_pipe;
initial r_pipe = 1'b0;
always @(posedge i_clk)
if (i_ce)
o_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
r_pipe <= (r_valid)&&(i_pf_valid)&&(~i_instruction[31])
&&(w_dcdM)&&(o_M)&&(o_op[0] ==i_instruction[22])
&&(i_instruction[17:14] == o_dcdB[3:0])
&&(i_instruction[17:14] != o_dcdA[3:0])
&&(i_gie == o_gie)
&&((i_instruction[21:19]==o_cond[2:0])
||(o_cond[2:0] == 3'h0))
&&((i_instruction[13:0]==r_I[13:0])
||({1'b0, i_instruction[13:0]}==(r_I[13:0]+14'h1)));
assign o_pipe = r_pipe;
`else
assign o_pipe = 1'b0;
`endif
 
always @(posedge i_clk)
if (i_rst)
r_valid <= 1'b0;
/cpu/zipcpu.v
869,10 → 869,8
always @(posedge i_clk)
if (i_rst)
r_op_lock <= 1'b0;
else if ((op_ce)&&(dcd_lock))
r_op_lock <= 1'b1;
else if ((op_ce)||(clear_pipeline))
r_op_lock <= 1'b0;
else if (op_ce)
r_op_lock <= (dcd_lock)&&(~clear_pipeline);
assign op_lock = r_op_lock;
 
end else begin
1180,16 → 1178,16
generate
if (IMPLEMENT_LOCK != 0)
begin
reg r_bus_lock;
initial r_bus_lock = 1'b0;
reg [1:0] r_bus_lock;
initial r_bus_lock = 2'b00;
always @(posedge i_clk)
if (i_rst)
r_bus_lock <= 1'b0;
r_bus_lock <= 2'b00;
else if ((op_ce)&&(op_lock))
r_bus_lock <= 1'b1;
else if (~opvalid_mem)
r_bus_lock <= 1'b0;
assign bus_lock = r_bus_lock;
r_bus_lock <= 2'b11;
else if ((|r_bus_lock)&&((~opvalid_mem)||(~op_ce)))
r_bus_lock <= r_bus_lock + 2'b11;
assign bus_lock = |r_bus_lock;
end else begin
assign bus_lock = 1'b0;
end endgenerate
1640,7 → 1638,7
else if ((new_pc)||((~dcd_stalled)&&(pf_valid)))
pf_pc <= pf_pc + {{(AW-1){1'b0}},1'b1};
`else
else if ((alu_pc_valid)&&(~clear_pipeline))
else if (((alu_pc_valid)&&(~clear_pipeline))||(mem_pc_valid))
pf_pc <= alu_pc;
`endif
 
/builddate.v
1,7 → 1638,7
`define DATESTAMP 32'h20160423
`define DATESTAMP 32'h20160428
/busmaster.v
60,7 → 60,7
// GPIO lines
i_gpio, o_gpio);
parameter BUS_ADDRESS_WIDTH=23, ZIP_ADDRESS_WIDTH=BUS_ADDRESS_WIDTH,
CMOD_ZIPCPU_RESET_ADDRESS=23'h400100,
CMOD_ZIPCPU_RESET_ADDRESS=23'h480000,
ZA=ZIP_ADDRESS_WIDTH, BAW=BUS_ADDRESS_WIDTH; // 24bits->2,258,23b->2181
input i_clk, i_rst;
input i_rx_stb;
222,8 → 222,9
assign many_sel =((wb_cyc)&&(wb_stb)&&(
{3'h0, io_sel}
+{3'h0, flctl_sel}
// +{3'h0, scop_sel}
+{3'h0, scop_sel}
+{3'h0, cfg_sel}
+{3'h0, rtc_sel}
+{3'h0, mem_sel}
+{3'h0, flash_sel} > 1));
*/
264,14 → 265,14
if (wb_err)
bus_err_addr <= wb_addr;
 
wire [31:0] timer_a, timer_b;
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer #(32,20)
ziptimer #(32,31)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
wb_we, wb_data, zta_ack, zta_stall, timer_a,
tmra_int);
ziptimer #(32,20)
ziptimer #(32,31)
zipt_b(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h3),
wb_we, wb_data, ztb_ack, ztb_stall, timer_b,
389,9 → 390,8
//
// FLASH MEMORY CONFIGURATION ACCESS
//
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflash #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[(24-3):0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,
/altbusmaster.v
38,7 → 38,7
//
`include "builddate.v"
//
`define IMPLEMENT_ONCHIP_RAM
// `define IMPLEMENT_ONCHIP_RAM
`ifndef VERILATOR
`define FANCY_ICAP_ACCESS
`endif
45,6 → 45,7
`define FLASH_ACCESS
`define DBG_SCOPE // About 204 LUTs, at 2^6 addresses
`define INCLUDE_RTC // About 90 LUTs
`define WBUBUS
module altbusmaster(i_clk, i_rst,
// DEPP I/O Control
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
123,14 → 124,26
// The BUS master (source): The WB to UART conversion bus
//
//
wbubus busbdriver(i_clk, i_rx_stb, i_rx_data,
wire dep_rx_stb, dep_tx_stb, dep_tx_busy;
wire [7:0] dep_rx_data, dep_tx_data;
deppbyte deppdrive(i_clk,
i_depp_astb_n, i_depp_dstb_n, i_depp_write_n,
i_depp_data, o_depp_data, o_depp_wait,
dep_rx_stb, dep_rx_data,
dep_tx_stb, dep_tx_data, dep_tx_busy);
 
wbubus busbdriver(i_clk,
// i_rx_stb, i_rx_data, // UART control
dep_rx_stb, dep_rx_data, // DEPP control
// The wishbone interface
wb_cyc, wb_stb, wb_we, w_wbu_addr, wb_data,
wb_ack, wb_stall, wb_err, wb_idata,
w_interrupt,
// Provide feedback to the UART
o_tx_stb, o_tx_data, i_tx_busy);
assign o_uart_rts = (~rx_rdy);
// Provide feedback to the DEPP interface
dep_tx_stb, dep_tx_data, dep_tx_busy);
// // Provide feedback to the UART
// o_tx_stb, o_tx_data, i_tx_busy
// assign o_uart_rts = (~rx_rdy);
`else
//
//
239,14 → 252,14
//
//
reg rx_rdy;
wire [10:0] int_vector;
assign int_vector = { gpio_int, pwm_int, keypad_int,
wire [11:0] int_vector;
assign int_vector = { flash_interrupt, gpio_int, pwm_int, keypad_int,
~i_tx_busy, rx_rdy, tmrb_int, tmra_int,
rtc_interrupt, scop_interrupt,
wb_err, button_int };
 
wire [31:0] pic_data;
icontrol #(11) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
icontrol #(12) pic(i_clk, 1'b0, (wb_stb)&&(io_sel)
&&(wb_addr[3:0]==4'h0)&&(wb_we),
wb_data, pic_data, int_vector, w_interrupt);
 
255,8 → 268,8
if (wb_err)
bus_err_addr <= wb_addr;
 
wire [31:0] timer_a, timer_b;
wire zta_ack, zta_stall, ztb_ack, ztb_stall;
wire [31:0] timer_a, timer_b;
ziptimer #(32,20)
zipt_a(i_clk, 1'b0, 1'b1, wb_cyc,
(wb_stb)&&(io_sel)&&(wb_addr[3:0]==4'h2),
380,9 → 393,8
//
// FLASH MEMORY CONFIGURATION ACCESS
//
wire flash_cs_n, flash_sck, flash_mosi;
wbqspiflashp #(24) flashmem(i_clk,
wb_cyc,(wb_stb&&flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_cyc,(wb_stb)&&(flash_sel),(wb_stb)&&(flctl_sel),wb_we,
wb_addr[(24-3):0], wb_data,
flash_ack, flash_stall, flash_data,
o_qspi_sck, o_qspi_cs_n, o_qspi_mod, o_qspi_dat, i_qspi_dat,

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