URL
https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk
Subversion Repositories sata_controller_core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sata_controller_core/trunk
- from Rev 12 to Rev 13
- ↔ Reverse comparison
Rev 12 → Rev 13
/sata2_fifo_v1_00_a/hdl/vhdl/sata_link_layer.vhd
275,6 → 275,7
signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1); |
signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1); |
signal rx_fifo_data_count : std_logic_vector(0 to 9); |
signal rx_fifo_reset : std_logic; |
|
----------------------------------------------------------------------------- |
-- Pre-Scramble Write FIFO from Command Layer |
1187,11 → 1188,12
--------------------------------------------------------------------------- |
rx_fifo_din <= rx_datain; |
rx_fifo_re <= descrambler_din_re_r; |
rx_fifo_reset <= sw_reset or descrambler_reset; |
|
RX_FIFO : rx_tx_fifo |
port map ( |
clk => sata_user_clk, |
rst => sw_reset, |
rst => rx_fifo_reset, |
rd_en => rx_fifo_re, |
din => rx_fifo_din, |
wr_en => rx_fifo_we_next, |
/sata2_bus_v1_00_a/base_system/pcores/sata_core_v1_00_a/hdl/vhdl/sata_link_layer.vhd
275,6 → 275,7
signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1); |
signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1); |
signal rx_fifo_data_count : std_logic_vector(0 to 9); |
signal rx_fifo_reset : std_logic; |
|
----------------------------------------------------------------------------- |
-- Pre-Scramble Write FIFO from Command Layer |
1187,11 → 1188,12
--------------------------------------------------------------------------- |
rx_fifo_din <= rx_datain; |
rx_fifo_re <= descrambler_din_re_r; |
rx_fifo_reset <= sw_reset or descrambler_reset; |
|
RX_FIFO : rx_tx_fifo |
port map ( |
clk => sata_user_clk, |
rst => sw_reset, |
rst => rx_fifo_reset, |
rd_en => rx_fifo_re, |
din => rx_fifo_din, |
wr_en => rx_fifo_we_next, |