OpenCores
URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sata_controller_core
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/netlist/rx_tx_fifo.xco
0,0 → 1,84
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Apr 6 17:04:40 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=true
CSET almost_full_flag=false
CSET component_name=rx_tx_fifo
CSET data_count=true
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=509
CSET full_threshold_negate_value=508
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=32
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
# END Parameters
GENERATE
# CRC: e7d8a21d
/trunk/netlist/read_write_fifo.xco
0,0 → 1,84
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Apr 6 17:05:34 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=true
CSET almost_full_flag=false
CSET component_name=read_write_fifo
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=0
CSET full_threshold_assert_value=510
CSET full_threshold_negate_value=509
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=512
CSET output_data_width=32
CSET output_depth=512
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
# END Parameters
GENERATE
# CRC: 93678f6a
/trunk/netlist/user_fifo.xco
0,0 → 1,84
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Apr 6 17:06:28 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=user_fifo
CSET data_count=false
CSET data_count_width=11
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_negate_value=5
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=256
CSET full_threshold_negate_value=255
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
CSET input_depth=1024
CSET output_data_width=32
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=11
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=11
# END Parameters
GENERATE
# CRC: b44c501c
/trunk/netlist/coregen.cgp
0,0 → 1,19
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6vlx240t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
 
/trunk/netlist/.lso
0,0 → 1,19
fifo_generator_v6_2
/trunk/netlist/Makefile
0,0 → 1,28
# This Makefile will generate the NGC files based on only the XCO files
# DO NOT Delete the XCO files!
 
FILES=rx_tx_fifo.xco read_write_fifo.xco user_fifo.xco \
 
.SUFFIXES: .xco .ngc
 
.xco.ngc:
coregen -p coregen.cgp -b $<
 
ALL: $(FILES:.xco=.ngc)
 
 
clean:
rm -rf *~ *.txt *.ncf *.ise *.vho *.tcl *.log *.pdf *.xrpt
rm -rf tmp xlnx_auto_0_xdb
rm -rf *.gise *.xise *.asy *.cgc _xmsgs
 
clean_ngc:
rm -rf *.ngc
 
clean_cdc:
rm -rf *.cdc
 
clean_vhd:
rm -rf *.vhd
 
real_clean: clean clean_ngc clean_cdc clean_vhd
/trunk/doc/README
0,0 → 1,42
The SATA2 core implements the Command, Transport and Link Layers of
the SATA2 protocol and provides a Physical Layer Wrapper for
the transceivers.
 
The Design source files can be found under 'hdl/vhdl' and
'hdl/verilog' directories
 
/hdl/vhdl:
sata_core.vhd
_________|__________
| |
command_layer.vhd sata_link_layer.vhd
_________________________|________
| | | |
sata_phy.v scrambler.vhd crc.vhd mux_161.vhd
 
 
hdl/verilog:
sata_phy.v
_________|________________________________
| | |
oob_control.v sata_gtx_dual.v mgt_usrclk_source_mmcm.v
____|_____ |
| | sata_gtx.v
mux_41.v mux_21.v
The synthesis Makefile is under 'syn' and the coregen netlist
Makefile for FIFOs is under 'netlist'
 
Notes:
* To use with Xilinx Virtex6 ML605 board -
Supply a 150 MHz reference clock for the GTX transceivers. This can be
done by dividing the 200 MHz reference clock on the ML605 board or by
configuring the programmable clock sources on the FMC XM104 connectivity
card.
* After providing a reset, check for the LINKUP signal before using the
core. The OOB controller asserts LINKUP after completing the link
initialization and synchronization process.
 
/trunk/hdl/verilog/mux_21.v
0,0 → 1,46
//--------------------------------------------------------------------------------
// Entity mux_21
// Version: 1.0
// Author: Ashwin Mendon
// Description: 2 bit 2:1 Multiplexer
//--------------------------------------------------------------------------------
 
// Copyright (C) 2012
// Ashwin A. Mendon
//
// This file is part of SATA2 core.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
module mux_21
(
input wire [1:0] a,
input wire [1:0] b,
input wire sel,
output reg [1:0] o
);
 
always @ (a or b or sel)
begin
case (sel)
1'b0:
o = a;
1'b1:
o = b;
endcase
end
 
endmodule
 
/trunk/hdl/verilog/mux_41.v
0,0 → 1,52
//--------------------------------------------------------------------------------
// Entity mux_21
// Version: 1.0
// Author: Ashwin Mendon
// Description: 32 bit 4:1 Multiplexer
//--------------------------------------------------------------------------------
 
// Copyright (C) 2012
// Ashwin A. Mendon
//
// This file is part of SATA2 core.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
module mux_41
(
input wire [31:0] a,
input wire [31:0] b,
input wire [31:0] c,
input wire [31:0] d,
input wire [1:0] sel,
output reg [31:0] o
);
 
always @ (a or b or c or d or sel)
begin
case (sel)
2'b00:
o = a;
2'b01:
o = b;
2'b10:
o = c;
2'b11:
o = d;
endcase
end
 
endmodule
 
/trunk/hdl/verilog/sata_gtx_dual.v
0,0 → 1,417
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.8
// \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
// / / Filename : sata_gtx_dual.v
// /___/ /\
// \ \ / \
// \___\/\___\
//
//
// Module SATA_GTX_DUAL (a GTX Wrapper)
// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
//
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
 
 
`timescale 1ns / 1ps
 
 
//***************************** Entity Declaration ****************************
 
(* CORE_GENERATION_INFO = "SATA_PHY,v6_gtxwizard_v1_8,{protocol_file=sata2}" *)
module SATA_GTX_DUAL #
(
// Simulation attributes
parameter WRAPPER_SIM_GTXRESET_SPEEDUP = 0 // Set to 1 to speed up sim reset
)
(
//_________________________________________________________________________
//_________________________________________________________________________
//GTX0 (X0Y4)
 
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] GTX0_LOOPBACK_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [3:0] GTX0_RXCHARISK_OUT,
output [3:0] GTX0_RXDISPERR_OUT,
output [3:0] GTX0_RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [2:0] GTX0_RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
output GTX0_RXBYTEISALIGNED_OUT,
output GTX0_RXBYTEREALIGN_OUT,
input GTX0_RXENMCOMMAALIGN_IN,
input GTX0_RXENPCOMMAALIGN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
output [31:0] GTX0_RXDATA_OUT,
output GTX0_RXRECCLK_OUT,
input GTX0_RXRESET_IN,
input GTX0_RXUSRCLK_IN,
input GTX0_RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
output GTX0_RXELECIDLE_OUT,
input [2:0] GTX0_RXEQMIX_IN,
input GTX0_RXN_IN,
input GTX0_RXP_IN,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input GTX0_RXBUFRESET_IN,
output [2:0] GTX0_RXSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
input GTX0_GTXRXRESET_IN,
input GTX0_MGTREFCLKRX_IN,
input GTX0_PLLRXRESET_IN,
output GTX0_RXPLLLKDET_OUT,
output GTX0_RXRESETDONE_OUT,
//------------------- Receive Ports - RX Ports for SATA --------------------
output GTX0_COMINITDET_OUT,
output GTX0_COMWAKEDET_OUT,
// -------------- Speed Neg Module ports ------------------------
input [6:0] DADDR, //DRP address
input DEN, //DRP enable
input [15:0] DI, //DRP data in
output[15:0] DO, //DRP data out
output DRDY, //DRP ready
input DWE, //DRP write enable
input DCLK,
 
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [3:0] GTX0_TXCHARISK_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] GTX0_TXDATA_IN,
output GTX0_TXOUTCLK_OUT,
input GTX0_TXRESET_IN,
input GTX0_TXUSRCLK_IN,
input GTX0_TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
input [3:0] GTX0_TXDIFFCTRL_IN,
output GTX0_TXN_OUT,
output GTX0_TXP_OUT,
input [4:0] GTX0_TXPOSTEMPHASIS_IN,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
input [3:0] GTX0_TXPREEMPHASIS_IN,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
input GTX0_GTXTXRESET_IN,
output GTX0_TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input GTX0_TXELECIDLE_IN,
//------------------- Transmit Ports - TX Ports for SATA -------------------
output GTX0_COMFINISH_OUT,
input GTX0_TXCOMINIT_IN,
input GTX0_TXCOMWAKE_IN,
 
 
//_________________________________________________________________________
//_________________________________________________________________________
//GTX1 (X0Y5)
 
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] GTX1_LOOPBACK_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [3:0] GTX1_RXDISPERR_OUT,
output [3:0] GTX1_RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [2:0] GTX1_RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
output GTX1_RXBYTEISALIGNED_OUT,
output GTX1_RXBYTEREALIGN_OUT,
input GTX1_RXENMCOMMAALIGN_IN,
input GTX1_RXENPCOMMAALIGN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
output [31:0] GTX1_RXDATA_OUT,
output GTX1_RXRECCLK_OUT,
input GTX1_RXRESET_IN,
input GTX1_RXUSRCLK_IN,
input GTX1_RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
output GTX1_RXELECIDLE_OUT,
input [2:0] GTX1_RXEQMIX_IN,
input GTX1_RXN_IN,
input GTX1_RXP_IN,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input GTX1_RXBUFRESET_IN,
output [2:0] GTX1_RXSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
input GTX1_GTXRXRESET_IN,
input GTX1_MGTREFCLKRX_IN,
input GTX1_PLLRXRESET_IN,
output GTX1_RXPLLLKDET_OUT,
output GTX1_RXRESETDONE_OUT,
//------------------- Receive Ports - RX Ports for SATA --------------------
output GTX1_COMINITDET_OUT,
output GTX1_COMWAKEDET_OUT,
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [3:0] GTX1_TXCHARISK_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] GTX1_TXDATA_IN,
output GTX1_TXOUTCLK_OUT,
input GTX1_TXRESET_IN,
input GTX1_TXUSRCLK_IN,
input GTX1_TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
input [3:0] GTX1_TXDIFFCTRL_IN,
output GTX1_TXN_OUT,
output GTX1_TXP_OUT,
input [4:0] GTX1_TXPOSTEMPHASIS_IN,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
input [3:0] GTX1_TXPREEMPHASIS_IN,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
input GTX1_GTXTXRESET_IN,
output GTX1_TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input GTX1_TXELECIDLE_IN,
//------------------- Transmit Ports - TX Ports for SATA -------------------
output GTX1_COMFINISH_OUT,
input GTX1_TXCOMINIT_IN,
input GTX1_TXCOMWAKE_IN
 
 
);
 
//***************************** Wire Declarations *****************************
 
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
//********************************* Main Body of Code**************************
 
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
 
 
//------------------------- GTX Instances -------------------------------
 
 
 
//_________________________________________________________________________
//_________________________________________________________________________
//GTX0 (X0Y4)
 
SATA_GTX #
(
// Simulation attributes
.GTX_SIM_GTXRESET_SPEEDUP (WRAPPER_SIM_GTXRESET_SPEEDUP),
// Share RX PLL parameter
.GTX_TX_CLK_SOURCE ("RXPLL"),
// Save power parameter
.GTX_POWER_SAVE (10'b0000110100)
)
gtx0_sata_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK_IN (GTX0_LOOPBACK_IN),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISK_OUT (GTX0_RXCHARISK_OUT),
.RXDISPERR_OUT (GTX0_RXDISPERR_OUT),
.RXNOTINTABLE_OUT (GTX0_RXNOTINTABLE_OUT),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT_OUT (GTX0_RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED_OUT (GTX0_RXBYTEISALIGNED_OUT),
.RXBYTEREALIGN_OUT (GTX0_RXBYTEREALIGN_OUT),
.RXENMCOMMAALIGN_IN (GTX0_RXENMCOMMAALIGN_IN),
.RXENPCOMMAALIGN_IN (GTX0_RXENPCOMMAALIGN_IN),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA_OUT (GTX0_RXDATA_OUT),
.RXRECCLK_OUT (GTX0_RXRECCLK_OUT),
.RXRESET_IN (GTX0_RXRESET_IN),
.RXUSRCLK_IN (GTX0_RXUSRCLK_IN),
.RXUSRCLK2_IN (GTX0_RXUSRCLK2_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.RXELECIDLE_OUT (GTX0_RXELECIDLE_OUT),
.RXEQMIX_IN (GTX0_RXEQMIX_IN),
.RXN_IN (GTX0_RXN_IN),
.RXP_IN (GTX0_RXP_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET_IN (GTX0_RXBUFRESET_IN),
.RXSTATUS_OUT (GTX0_RXSTATUS_OUT),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GTXRXRESET_IN (GTX0_GTXRXRESET_IN),
.MGTREFCLKRX_IN ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),
.PLLRXRESET_IN (GTX0_PLLRXRESET_IN),
.RXPLLLKDET_OUT (GTX0_RXPLLLKDET_OUT),
.RXRESETDONE_OUT (GTX0_RXRESETDONE_OUT),
//------------------- Receive Ports - RX Ports for SATA --------------------
.COMINITDET_OUT (GTX0_COMINITDET_OUT),
.COMWAKEDET_OUT (GTX0_COMWAKEDET_OUT),
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
.DADDR (DADDR),
.DCLK (DCLK),
.DEN (DEN),
.DI (DI),
.DRDY (DRDY),
.DO (DO),
.DWE (DWE),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXCHARISK_IN (GTX0_TXCHARISK_IN),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA_IN (GTX0_TXDATA_IN),
.TXOUTCLK_OUT (GTX0_TXOUTCLK_OUT),
.TXRESET_IN (GTX0_TXRESET_IN),
.TXUSRCLK_IN (GTX0_TXUSRCLK_IN),
.TXUSRCLK2_IN (GTX0_TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.TXDIFFCTRL_IN (GTX0_TXDIFFCTRL_IN),
.TXN_OUT (GTX0_TXN_OUT),
.TXP_OUT (GTX0_TXP_OUT),
.TXPOSTEMPHASIS_IN (GTX0_TXPOSTEMPHASIS_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXPREEMPHASIS_IN (GTX0_TXPREEMPHASIS_IN),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GTXTXRESET_IN (GTX0_GTXTXRESET_IN),
.MGTREFCLKTX_IN ({tied_to_ground_i , GTX0_MGTREFCLKRX_IN}),
.PLLTXRESET_IN (tied_to_ground_i),
.TXPLLLKDET_OUT (),
.TXRESETDONE_OUT (GTX0_TXRESETDONE_OUT),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXELECIDLE_IN (GTX0_TXELECIDLE_IN),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.COMFINISH_OUT (GTX0_COMFINISH_OUT),
.TXCOMINIT_IN (GTX0_TXCOMINIT_IN),
.TXCOMWAKE_IN (GTX0_TXCOMWAKE_IN)
 
);
 
 
 
//_________________________________________________________________________
//_________________________________________________________________________
//GTX1 (X0Y5)
 
SATA_GTX #
(
// Simulation attributes
.GTX_SIM_GTXRESET_SPEEDUP (WRAPPER_SIM_GTXRESET_SPEEDUP),
// Share RX PLL parameter
.GTX_TX_CLK_SOURCE ("RXPLL"),
// Save power parameter
.GTX_POWER_SAVE (10'b0000110100)
)
gtx1_sata_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK_IN (GTX1_LOOPBACK_IN),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXDISPERR_OUT (GTX1_RXDISPERR_OUT),
.RXNOTINTABLE_OUT (GTX1_RXNOTINTABLE_OUT),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT_OUT (GTX1_RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED_OUT (GTX1_RXBYTEISALIGNED_OUT),
.RXBYTEREALIGN_OUT (GTX1_RXBYTEREALIGN_OUT),
.RXENMCOMMAALIGN_IN (GTX1_RXENMCOMMAALIGN_IN),
.RXENPCOMMAALIGN_IN (GTX1_RXENPCOMMAALIGN_IN),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA_OUT (GTX1_RXDATA_OUT),
.RXRECCLK_OUT (GTX1_RXRECCLK_OUT),
.RXRESET_IN (GTX1_RXRESET_IN),
.RXUSRCLK_IN (GTX1_RXUSRCLK_IN),
.RXUSRCLK2_IN (GTX1_RXUSRCLK2_IN),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.RXELECIDLE_OUT (GTX1_RXELECIDLE_OUT),
.RXEQMIX_IN (GTX1_RXEQMIX_IN),
.RXN_IN (GTX1_RXN_IN),
.RXP_IN (GTX1_RXP_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET_IN (GTX1_RXBUFRESET_IN),
.RXSTATUS_OUT (GTX1_RXSTATUS_OUT),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GTXRXRESET_IN (GTX1_GTXRXRESET_IN),
.MGTREFCLKRX_IN ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),
.PLLRXRESET_IN (GTX1_PLLRXRESET_IN),
.RXPLLLKDET_OUT (GTX1_RXPLLLKDET_OUT),
.RXRESETDONE_OUT (GTX1_RXRESETDONE_OUT),
//------------------- Receive Ports - RX Ports for SATA --------------------
.COMINITDET_OUT (GTX1_COMINITDET_OUT),
.COMWAKEDET_OUT (GTX1_COMWAKEDET_OUT),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXCHARISK_IN (GTX1_TXCHARISK_IN),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA_IN (GTX1_TXDATA_IN),
.TXOUTCLK_OUT (GTX1_TXOUTCLK_OUT),
.TXRESET_IN (GTX1_TXRESET_IN),
.TXUSRCLK_IN (GTX1_TXUSRCLK_IN),
.TXUSRCLK2_IN (GTX1_TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.TXDIFFCTRL_IN (GTX1_TXDIFFCTRL_IN),
.TXN_OUT (GTX1_TXN_OUT),
.TXP_OUT (GTX1_TXP_OUT),
.TXPOSTEMPHASIS_IN (GTX1_TXPOSTEMPHASIS_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXPREEMPHASIS_IN (GTX1_TXPREEMPHASIS_IN),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GTXTXRESET_IN (GTX1_GTXTXRESET_IN),
.MGTREFCLKTX_IN ({tied_to_ground_i , GTX1_MGTREFCLKRX_IN}),
.PLLTXRESET_IN (tied_to_ground_i),
.TXPLLLKDET_OUT (),
.TXRESETDONE_OUT (GTX1_TXRESETDONE_OUT),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXELECIDLE_IN (GTX1_TXELECIDLE_IN),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.COMFINISH_OUT (GTX1_COMFINISH_OUT),
.TXCOMINIT_IN (GTX1_TXCOMINIT_IN),
.TXCOMWAKE_IN (GTX1_TXCOMWAKE_IN)
 
);
 
 
 
endmodule
 
/trunk/hdl/verilog/oob_control.v
0,0 → 1,632
//*****************************************************************************/
// Module : OOB_control
// Version: 1.0
// Author: Ashwin Mendon
// Description: This module handles the Out-Of-Band (OOB) sinaling requirements
// for link initialization and synchronization
// It has been modified from XAPP870 to support Xilinx Virtex 6 GTX
// transceivers
//*****************************************************************************/
 
// Copyright (C) 2012
// Ashwin A. Mendon
//
// This file is part of SATA2 core.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
module OOB_control (
 
clk, // Clock
reset, // reset
oob_control_ila_control,
/**** GTX ****/
link_reset,
rxreset, // GTX PCS reset
rx_locked, // GTX PLL is locked
gen2, // Generation 2 speed
txcominit, // TX OOB issue RESET/INIT
txcomwake, // TX OOB issue WAKE
cominitdet, // RX OOB detect INIT
comwakedet, // RX OOB detect WAKE
rxelecidle, // RX electrical idle
txelecidle_out,// TX electircal idel
rxbyteisaligned,// RX byte alignment completed
 
tx_dataout, // Outgoing TX data to GTX
tx_charisk_out,// TX byted is K character
rx_datain, // Data from GTX
rx_charisk_in, // K character from GTX
/**** GTX ****/
 
/**** LINK LAYER ****/
// INPUT
tx_datain, // Incoming TX data from SATA Link Layer
tx_charisk_in, // K character indicator
// OUTPUT
rx_dataout, // Data to SATA Link Layer
rx_charisk_out,
 
linkup, // SATA link is established
linkup_led_out, // LINKUP LED output
align_en_out,
CurrentState_out // Current state for Chipscope
/**** LINK LAYER ****/
 
);
 
parameter CHIPSCOPE = "FALSE";
input clk;
input reset;
input [35:0] oob_control_ila_control;
input link_reset;
input rx_locked;
input gen2;
// Added for GTX
input cominitdet;
input comwakedet;
// Added for GTX
input rxelecidle;
input rxbyteisaligned;
input [31:0] tx_datain;
input tx_charisk_in;
input [3:0] rx_charisk_in;
input [31:0] rx_datain; //changed for GTX
output rxreset;
// Added for GTX
output txcominit;
output txcomwake;
// Added for GTX
output txelecidle_out;
output [31:0] tx_dataout; //changed for GTX
output tx_charisk_out;
output [31:0] rx_dataout;
output [3:0] rx_charisk_out;
output linkup;
output linkup_led_out;
output align_en_out;
output [7:0] CurrentState_out;
parameter [3:0]
host_comreset = 8'h00,
wait_dev_cominit = 8'h01,
host_comwake = 8'h02,
wait_dev_comwake = 8'h03,
wait_after_comwake = 8'h04,
wait_after_comwake1 = 8'h05,
host_d10_2 = 8'h06,
host_send_align = 8'h07,
link_ready = 8'h08,
link_idle = 8'h09;
 
// Primitves
parameter ALIGN = 4'b00;
parameter SYNC = 4'b01;
parameter DIAL = 4'b10;
//parameter R_RDY = 4'b11;
parameter LINK_LAYER = 4'b11;
 
reg [7:0] CurrentState, NextState;
reg [7:0] count160;
reg [17:0] count;
reg [4:0] count160_round;
reg [3:0] align_char_cnt_reg;
reg align_char_cnt_rst, align_char_cnt_inc;
reg count_en;
reg tx_charisk_r, tx_charisk, tx_charisk_next;
reg txelecidle, txelecidle_next;
reg count160_done, count160_go;
reg [1:0] align_byte_count ; // Counter for ALIGN Byte Count
reg linkup_r, linkup_r_next;
reg rxreset;
reg [31:0] tx_datain_r;
wire [31:0] tx_dataout_i;
reg [31:0] rx_dataout_i;
wire [31:0] tx_align, tx_sync, tx_dial, tx_r_rdy;
reg [3:0] rx_charisk_r;
reg txcominit_r, txcomwake_r;
wire [1:0] align_count_mux_out;
reg [8:0] align_count;
reg [1:0] prim_type, prim_type_next;
wire align_det, sync_det, cont_det, sof_det, eof_det, x_rdy_det, r_err_det, r_ok_det;
wire comreset_done, dev_cominit_done, host_comwake_done, dev_comwake_done;
reg align_en, align_en_r;
reg rxelecidle_r;
reg [31:0] rx_datain_r;
reg [3:0] rx_charisk_in_r;
reg rxbyteisaligned_r;
reg comwakedet_r, cominitdet_r;
 
// OOB FSM Logic Process
always @ ( CurrentState or count or rxelecidle_r or rx_locked or rx_datain_r or
cominitdet_r or comwakedet_r or
align_det or sync_det or cont_det or
tx_charisk_in )
begin : Comb_FSM
count_en = 1'b0;
NextState = host_comreset;
linkup_r_next = linkup_r;
txcominit_r =1'b0;
txcomwake_r = 1'b0;
rxreset = 1'b0;
txelecidle_next = txelecidle;
prim_type_next = prim_type;
tx_charisk_next = tx_charisk;
rx_dataout_i = 32'b0;
rx_charisk_r = 4'b0;
 
case (CurrentState)
host_comreset :
begin
txelecidle_next = 1'b1;
prim_type_next = ALIGN;
if (rx_locked)
begin
if ((~gen2 && count == 18'h00051) || (gen2 && count == 18'h000A2))
begin
txcominit_r =1'b0;
NextState = wait_dev_cominit;
end
else //Issue COMRESET
begin
txcominit_r =1'b1;
count_en = 1'b1;
NextState = host_comreset;
end
end
else
begin
txcominit_r =1'b0;
NextState = host_comreset;
end
end
 
wait_dev_cominit : //1
begin
if (cominitdet_r == 1'b1) //device cominit detected
begin
NextState = host_comwake;
end
else
begin
`ifdef SIM
if(count == 18'h001ff)
`else
if(count == 18'h203AD) //restart comreset after no cominit for at least 880us
`endif
begin
count_en = 1'b0;
NextState = host_comreset;
end
else
begin
count_en = 1'b1;
NextState = wait_dev_cominit;
end
end
end
 
host_comwake : //2
begin
if ((~gen2 && count == 18'h0004E) || (gen2 && count == 18'h0009B))
begin
txcomwake_r =1'b0;
NextState = wait_dev_comwake;
end
else
begin
txcomwake_r =1'b1;
count_en = 1'b1;
NextState = host_comwake;
end
 
end
 
wait_dev_comwake : //3
begin
if (comwakedet_r == 1'b1) //device comwake detected
begin
NextState = wait_after_comwake;
end
else
begin
if(count == 18'h203AD) //restart comreset after no cominit for 880us
begin
count_en = 1'b0;
NextState = host_comreset;
end
else
begin
count_en = 1'b1;
NextState = wait_dev_comwake;
end
end
end
 
 
wait_after_comwake : // 4
begin
if (count == 6'h3F)
begin
NextState = wait_after_comwake1;
end
else
begin
count_en = 1'b1;
NextState = wait_after_comwake;
end
end
 
 
wait_after_comwake1 : //5
begin
if (rxelecidle_r == 1'b0)
begin
rxreset = 1'b1;
NextState = host_d10_2;
end
else
NextState = wait_after_comwake1;
end
 
host_d10_2 : //6
begin
txelecidle_next = 1'b0;
 
// D10.2-D10.2 "dial tone"
rx_dataout_i = rx_datain_r;
prim_type_next = DIAL;
tx_charisk_next = 1'b0;
 
if (align_det)
begin
NextState = host_send_align;
end
else
begin
if(count == 18'h203AD) // restart comreset after 880us
begin
count_en = 1'b0;
NextState = host_comreset;
end
else
begin
count_en = 1'b1;
NextState = host_d10_2;
end
end
end
host_send_align : //7
begin
rx_dataout_i = rx_datain_r;
// Send Align primitives. Align is
// K28.5, D10.2, D10.2, D27.3
prim_type_next = ALIGN;
tx_charisk_next = 1'b1;
if (sync_det) // SYNC detected
begin
linkup_r_next = 1'b1;
NextState = link_ready;
end
else
NextState = host_send_align;
end
link_ready : // 8
begin
if (rxelecidle_r == 1'b1)
begin
NextState = link_ready;
linkup_r_next = 1'b0;
end
else
begin
NextState = link_ready;
linkup_r_next = 1'b1;
rx_charisk_r = rx_charisk_in_r;
rx_dataout_i = rx_datain_r;
// Send LINK_LAYER DATA
prim_type_next = LINK_LAYER;
if (align_en)
tx_charisk_next = 1'b1;
else
tx_charisk_next = tx_charisk_in;
end
end
default : NextState = host_comreset;
endcase
end
 
 
// OOB FSM Synchronous Process
 
always@(posedge clk or posedge reset)
begin : Seq_FSM
if (reset)
begin
CurrentState = host_comreset;
prim_type = ALIGN;
tx_charisk = 1'b0;
txelecidle = 1'b1;
linkup_r = 1'b0;
align_en_r = 1'b0;
rxelecidle_r = 1'b0;
rx_datain_r = 32'b0;
rx_charisk_in_r = 4'b0;
rxbyteisaligned_r = 1'b0;
cominitdet_r = 1'b0;
comwakedet_r = 1'b0;
end
else
begin
CurrentState = NextState;
prim_type = prim_type_next;
tx_charisk = tx_charisk_next;
txelecidle = txelecidle_next;
linkup_r = linkup_r_next;
align_en_r = align_en;
rxelecidle_r = rxelecidle;
rx_datain_r = rx_datain;
rx_charisk_in_r = rx_charisk_in;
rxbyteisaligned_r = rxbyteisaligned;
cominitdet_r = cominitdet;
comwakedet_r = comwakedet;
end
end
 
 
always@(posedge clk)
begin : Tx_Charisk
begin
tx_charisk_r = tx_charisk;
end
end
 
always@(posedge clk or posedge reset)
begin : comreset_OOB_count
if (reset)
begin
count160 = 8'b0;
count160_round = 5'b0;
end
else if (count160_go)
begin
if (count160 == 8'h10 )
begin
count160 = 8'b0;
count160_round = count160_round + 1;
end
else
count160 = count160 + 1;
end
else
begin
count160 = 8'b0;
count160_round = 5'b0;
end
end
 
always@(posedge clk or posedge reset)
begin : freecount
if (reset)
begin
count = 18'b0;
end
else if (count_en)
begin
count = count + 1;
end
else
begin
count = 18'b0;
 
end
end
 
 
assign comreset_done = (CurrentState == host_comreset && count160_round == 5'h15) ? 1'b1 : 1'b0;
assign host_comwake_done = (CurrentState == host_comwake && count160_round == 5'h0b) ? 1'b1 : 1'b0;
 
assign txcominit = txcominit_r;
assign txcomwake = txcomwake_r;
assign txelecidle_out = txelecidle;
//Primitive detection
// Changed for 32-bit GTX
assign align_det = (rx_datain_r == 32'h7B4A4ABC) && (rxbyteisaligned_r == 1'b1); //prevent invalid align at wrong speed
assign sync_det = (rx_datain_r == 32'hB5B5957C);
assign cont_det = (rx_datain_r == 32'h9999AA7C);
assign sof_det = (rx_datain_r == 32'h3737B57C);
assign eof_det = (rx_datain_r == 32'hD5D5B57C);
assign x_rdy_det = (rx_datain_r == 32'h5757B57C);
assign r_err_det = (rx_datain_r == 32'h5656B57C);
assign r_ok_det = (rx_datain_r == 32'h3535B57C);
 
assign linkup = linkup_r;
assign linkup_led_out = ((CurrentState == link_ready) && (rxelecidle_r == 1'b0)) ? 1'b1 : 1'b0;
assign CurrentState_out = CurrentState;
assign rx_charisk_out = rx_charisk_r;
assign tx_charisk_out = tx_charisk;
assign rx_dataout = rx_dataout_i;
 
// SATA Primitives
 
// ALIGN
assign tx_align = 32'h7B4A4ABC;
 
// SYNC
assign tx_sync = 32'hB5B5957C;
 
// Dial Tone
assign tx_dial = 32'h4A4A4A4A;
 
// R_RDY
assign tx_r_rdy = 32'h4A4A957C;
 
// Mux to switch between ALIGN and other primitives/data
mux_21 i_align_count
(
.a (prim_type),
.b (ALIGN),
.sel (align_en_r),
.o (align_count_mux_out)
);
// Output to Link Layer to Pause writing data frame
assign align_en_out = align_en;
 
//ALIGN Primitives transmitted every 256 DWORDS for speed alignment
always@(posedge clk or posedge reset)
begin : align_cnt
if (reset)
begin
align_count = 9'b0;
align_byte_count = 2'b0;
end
else if (align_count < 9'h0FF) //255
begin
if (align_count == 9'h001) //de-assert after 2 ALIGN primitives
begin
align_en = 1'b0;
end
align_count = align_count + 1;
align_byte_count = align_byte_count + 1;
end
else
begin
align_byte_count = 2'b0;
align_count = 9'b0;
align_en = 1'b1;
end
end
 
 
//OUTPUT MUX
mux_41 i_tx_out
(
.a (tx_align),
.b (tx_sync),
.c (tx_dial),
//.d (tx_r_rdy),
.d (tx_datain),
.sel (align_count_mux_out),
.o (tx_dataout_i)
);
 
assign tx_dataout = tx_dataout_i;
 
 
// OOB ILA
wire [15:0] trig0;
wire [15:0] trig1;
wire [15:0] trig2;
wire [15:0] trig3;
wire [31:0] trig4;
wire [3:0] trig5;
wire [31:0] trig6;
wire [31:0] trig7;
wire [35:0] control;
 
if (CHIPSCOPE == "TRUE") begin
oob_control_ila i_oob_control_ila
(
.control(oob_control_ila_control),
.clk(clk),
.trig0(trig0),
.trig1(trig1),
.trig2(trig2),
.trig3(trig3),
.trig4(trig4),
.trig5(trig5),
.trig6(trig6),
.trig7(trig7)
);
end
 
assign trig0[0] = txcomwake_r;
assign trig0[1] = tx_charisk;
assign trig0[2] = rxbyteisaligned_r;
assign trig0[3] = count_en;
assign trig0[4] = tx_charisk_in;
assign trig0[5] = txelecidle;
assign trig0[6] = rx_locked;
assign trig0[7] = gen2;
assign trig0[11:8] = rx_charisk_in_r;
assign trig0[15:12] = 4'b0;
assign trig1[15:12] = prim_type;
assign trig1[11:10] = 2'b0;
assign trig1[9] = align_en_r;
assign trig1[8] = rxelecidle_r;
assign trig1[7:0] = CurrentState_out;
assign trig2[15:7] = align_count;
assign trig2[6:5] = align_byte_count;
assign trig2[4] = cominitdet_r;
assign trig2[3] = comwakedet_r;
assign trig2[2] = align_det;
assign trig2[1] = sync_det;
assign trig2[0] = cont_det;
assign trig3[0] = sof_det;
assign trig3[1] = eof_det;
assign trig3[2] = x_rdy_det;
assign trig3[3] = r_err_det;
assign trig3[4] = r_ok_det;
assign trig3[15:5] = 11'b0;
assign trig4 = rx_datain_r;
assign trig5[0] = txcominit_r;
assign trig5[1] = linkup_r;
assign trig5[2] = align_en;
assign trig5[3] = 1'b0;
assign trig6 = tx_datain;
assign trig7 = tx_dataout_i;
 
endmodule
 
module oob_control_ila
(
control,
clk,
trig0,
trig1,
trig2,
trig3,
trig4,
trig5,
trig6,
trig7
);
input [35:0] control;
input clk;
input [15:0] trig0;
input [15:0] trig1;
input [15:0] trig2;
input [15:0] trig3;
input [31:0] trig4;
input [3:0] trig5;
input [31:0] trig6;
input [31:0] trig7;
endmodule
/trunk/hdl/verilog/mgt_usrclk_source_mmcm.v
0,0 → 1,196
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.8
// \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
// / / Filename : mgt_usrclk_source_mmcm.v
// /___/ /\ Timestamp :
// \ \ / \
// \___\/\___\
//
//
// Module MGT_USRCLK_SOURCE (for use with GTX Transceivers)
// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
//
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
 
 
`timescale 1ns / 1ps
 
//***********************************Entity Declaration*******************************
module MGT_USRCLK_SOURCE_MMCM #
(
parameter MULT = 2,
parameter DIVIDE = 2,
parameter CLK_PERIOD = 6.4,
parameter OUT0_DIVIDE = 2,
parameter OUT1_DIVIDE = 2,
parameter OUT2_DIVIDE = 2,
parameter OUT3_DIVIDE = 2
)
(
output CLK0_OUT,
output CLK1_OUT,
output CLK2_OUT,
output CLK3_OUT,
input CLK_IN,
output MMCM_LOCKED_OUT,
input MMCM_RESET_IN
);
 
 
`define DLY #1
 
//*********************************Wire Declarations**********************************
 
wire [15:0] tied_to_ground_vec_i;
wire tied_to_ground_i;
wire clkout0_i;
wire clkout1_i;
wire clkout2_i;
wire clkout3_i;
wire clkfbout_i;
 
//*********************************** Beginning of Code *******************************
 
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 16'h0000;
 
// Instantiate a MMCM module to divide the reference clock. Uses internal feedback
// for improved jitter performance, and to avoid consuming an additional BUFG
MMCM_ADV #
(
.COMPENSATION ("ZHOLD"),
.CLKFBOUT_MULT_F (MULT),
.DIVCLK_DIVIDE (DIVIDE),
.CLKFBOUT_PHASE (0),
.CLKIN1_PERIOD (CLK_PERIOD),
.CLKIN2_PERIOD (10), //Not used
.CLKOUT0_DIVIDE_F (OUT0_DIVIDE),
.CLKOUT0_PHASE (0),
.CLKOUT1_DIVIDE (OUT1_DIVIDE),
.CLKOUT1_PHASE (0),
 
.CLKOUT2_DIVIDE (OUT2_DIVIDE),
.CLKOUT2_PHASE (0),
.CLKOUT3_DIVIDE (OUT3_DIVIDE),
.CLKOUT3_PHASE (0),
.CLOCK_HOLD ("TRUE")
)
mmcm_adv_i
(
.CLKIN1 (CLK_IN),
.CLKIN2 (1'b0),
.CLKINSEL (1'b1),
.CLKFBIN (clkfbout_i),
.CLKOUT0 (clkout0_i),
.CLKOUT0B (),
.CLKOUT1 (clkout1_i),
.CLKOUT1B (),
.CLKOUT2 (clkout2_i),
.CLKOUT2B (),
.CLKOUT3 (clkout3_i),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
.CLKFBOUT (clkfbout_i),
.CLKFBOUTB (),
.CLKFBSTOPPED (),
.CLKINSTOPPED (),
.DO (),
.DRDY (),
.DADDR (7'd0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'd0),
.DWE (1'b0),
.LOCKED (MMCM_LOCKED_OUT),
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
.PWRDWN (1'b0),
.RST (MMCM_RESET_IN)
);
BUFG clkout0_bufg_i
(
.O (CLK0_OUT),
.I (clkout0_i)
);
 
 
BUFG clkout1_bufg_i
(
.O (CLK1_OUT),
.I (clkout1_i)
);
 
 
BUFG clkout2_bufg_i
(
.O (CLK2_OUT),
.I (clkout2_i)
);
BUFG clkout3_bufg_i
(
.O (CLK3_OUT),
.I (clkout3_i)
);
 
endmodule
 
/trunk/hdl/verilog/sata_phy.v
0,0 → 1,737
//*****************************************************************************/
// Module : sata_phy
// Version: 1.0
// Author: Ashwin Mendon
// Description: This module provides a wrapper for the SATA GTX wrapper modules
// the Out of Band Signaling controller module and the clock generating
// modules
// It has been modified from XAPP870 to support Xilinx Virtex 6 GTX
// transceivers
//*****************************************************************************/
 
// Copyright (C) 2012
// Ashwin A. Mendon
//
// This file is part of SATA2 core.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
module sata_phy #
(
// Refclk attributes
parameter CLKINDC_B = "TRUE",
// Channel bonding attributes
parameter CHAN_BOND_MODE_0 = "OFF", // "MASTER", "SLAVE", or "OFF"
parameter CHAN_BOND_LEVEL_0 = 0, // 0 to 7. See UG for details
parameter CHAN_BOND_MODE_1 = "OFF", // "MASTER", "SLAVE", or "OFF"
parameter CHAN_BOND_LEVEL_1 = 0 // 0 to 7. See UG for details
)
 
(
sata_phy_ila_control,
oob_control_ila_control,
REFCLK_PAD_P_IN, // MGTCLKA, clocks GTP_X0Y0-2
REFCLK_PAD_N_IN, // MGTCLKA
GTXRESET_IN, // GTX initialization
PLLLKDET_OUT_N, // TX PLL LOCK
 
TXP0_OUT,
TXN0_OUT,
RXP0_IN,
RXN0_IN,
DCMLOCKED_OUT,
GEN2_led,
sata_user_clk,
LINKUP,
LINKUP_led,
align_en_out,
tx_datain,
tx_charisk_in,
rx_dataout,
rx_charisk_out,
CurrentState_out,
rxelecidle_out,
CLKIN_150
);
parameter CHIPSCOPE = "FALSE";
input [35:0] sata_phy_ila_control;
input [35:0] oob_control_ila_control;
input REFCLK_PAD_P_IN; // GTP reference clock input
input REFCLK_PAD_N_IN; // GTP reference clock input
input GTXRESET_IN; // Main GTP reset
input RXP0_IN; // Receiver input
input RXN0_IN; // Receiver input
// Input from Link Layer
input [31:0] tx_datain;
input tx_charisk_in;
output DCMLOCKED_OUT; // DCM locked
output PLLLKDET_OUT_N; // PLL Lock Detect
output TXP0_OUT;
output TXN0_OUT;
output LINKUP;
output LINKUP_led;
output GEN2_led;
output align_en_out;
output sata_user_clk;
// Outputs to Link Layer
output [31:0] rx_dataout;
output [3:0] rx_charisk_out;
output [7:0] CurrentState_out;
output rxelecidle_out;
input CLKIN_150;
 
wire [3:0] rxcharisk;
// OOB generate and detect
wire txcominit, txcomwake;
wire cominitdet, comwakedet;
// OOB generate and detect
wire sync_det_out, align_det_out;
wire tx_charisk_out;
wire txelecidle, rxelecidle0, rxelecidle1, rxenelecidleresetb;
wire resetdone0, resetdone1;
wire [31:0] txdata, rxdata; // TX/RX data
wire [31:0] rxdataout; // RX USER data
wire [4:0] state_out;
wire PLLLKDET_OUT;
wire linkup, linkup_led_out;
wire align_en_out;
wire clk0, clk2x, dcm_clk0, dcm_clkdv, dcm_clk2x; // DCM output clocks
wire mmcm_locked;
wire GEN2; //this is the selection for GEN2 when set to 1
wire system_reset;
wire speed_neg_rst;
wire [6:0] daddr; //DRP Address
wire den; //DRP enable
wire [15:0] di; //DRP data in
wire [15:0] do; //DRP data out
wire drdy; //DRP ready
wire dwe; //DRP write enable
wire rxreset; //GTP Rxreset
wire RXBYTEREALIGN0, RXBYTEISALIGNED0;
wire RXRECCLK0;
wire mmcm_reset;
wire rst_debounce;
wire push_button_rst;
wire mmcm_clk_in;
wire gtx_refclk;
wire gtx_refclk_bufg;
wire gtx_reset;
wire rst_0;
reg rst_1;
reg rst_2;
reg rst_3;
 
// Clock counters to check clock toggle
reg [15:0] gtx_refclk_count;
reg [15:0] gtx_refclk_bufg_count;
reg [15:0] gtx_txoutclk_count;
reg [15:0] gtx_txusrclk_count;
reg [15:0] gtx_txusrclk2_count;
reg [15:0] CLKIN_200_count;
reg [15:0] CLKIN_150_count;
 
//------------------------ MGT Wrapper Wires ------------------------------
//________________________________________________________________________
//________________________________________________________________________
//GTX0 (X0Y4)
 
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gtx0_loopback_i;
//--------------------- Receive Ports - 8b10b Decoder ----------------------
wire [3:0] gtx0_rxdisperr_i;
wire [3:0] gtx0_rxnotintable_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [2:0] gtx0_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gtx0_rxbyteisaligned_i;
wire gtx0_rxbyterealign_i;
wire gtx0_rxenmcommaalign_i;
wire gtx0_rxenpcommaalign_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire [31:0] gtx0_rxdata_i;
wire gtx0_rxrecclk_i;
wire gtx0_rxreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gtx0_rxelecidle_i;
wire [2:0] gtx0_rxeqmix_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gtx0_rxbufreset_i;
wire [2:0] gtx0_rxstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gtx0_gtxrxreset_i;
wire gtx0_pllrxreset_i;
wire gtx0_rxplllkdet_i;
wire gtx0_rxresetdone_i;
//------------------- Receive Ports - RX Ports for SATA --------------------
wire gtx0_cominitdet_i;
wire gtx0_comwakedet_i;
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
wire [3:0] gtx0_txcharisk_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire [31:0] gtx0_txdata_i;
wire gtx0_txoutclk_i;
wire gtx0_txreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire [3:0] gtx0_txdiffctrl_i;
wire [4:0] gtx0_txpostemphasis_i;
//------------- Transmit Ports - TX Driver and OOB signalling --------------
wire [3:0] gtx0_txpreemphasis_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gtx0_gtxtxreset_i;
wire gtx0_txresetdone_i;
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
wire gtx0_txelecidle_i;
//------------------- Transmit Ports - TX Ports for SATA -------------------
wire comfinish;
wire gtx0_txcominit_i;
wire gtx0_txcomwake_i;
 
 
//________________________________________________________________________
//________________________________________________________________________
//GTX1 (X0Y5)
 
//---------------------- Loopback and Powerdown Ports ----------------------
wire [2:0] gtx1_loopback_i;
//--------------------- Receive Ports - 8b10b Decoder ----------------------
wire [3:0] gtx1_rxdisperr_i;
wire [3:0] gtx1_rxnotintable_i;
//----------------- Receive Ports - Clock Correction Ports -----------------
wire [2:0] gtx1_rxclkcorcnt_i;
//------------- Receive Ports - Comma Detection and Alignment --------------
wire gtx1_rxbyteisaligned_i;
wire gtx1_rxbyterealign_i;
wire gtx1_rxenmcommaalign_i;
wire gtx1_rxenpcommaalign_i;
//----------------- Receive Ports - RX Data Path interface -----------------
wire [31:0] gtx1_rxdata_i;
wire gtx1_rxrecclk_i;
wire gtx1_rxreset_i;
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
wire gtx1_rxelecidle_i;
wire [2:0] gtx1_rxeqmix_i;
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
wire gtx1_rxbufreset_i;
wire [2:0] gtx1_rxstatus_i;
//---------------------- Receive Ports - RX PLL Ports ----------------------
wire gtx1_gtxrxreset_i;
wire gtx1_pllrxreset_i;
wire gtx1_rxplllkdet_i;
wire gtx1_rxresetdone_i;
//------------------- Receive Ports - RX Ports for SATA --------------------
wire gtx1_cominitdet_i;
wire gtx1_comwakedet_i;
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
wire [3:0] gtx1_txcharisk_i;
//---------------- Transmit Ports - TX Data Path interface -----------------
wire [31:0] gtx1_txdata_i;
wire gtx1_txoutclk_i;
wire gtx1_txreset_i;
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
wire [3:0] gtx1_txdiffctrl_i;
wire [4:0] gtx1_txpostemphasis_i;
//------------- Transmit Ports - TX Driver and OOB signalling --------------
wire [3:0] gtx1_txpreemphasis_i;
//--------------------- Transmit Ports - TX PLL Ports ----------------------
wire gtx1_gtxtxreset_i;
wire gtx1_txresetdone_i;
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
wire gtx1_txelecidle_i;
//------------------- Transmit Ports - TX Ports for SATA -------------------
wire gtx1_comfinish_i;
wire gtx1_txcominit_i;
wire gtx1_txcomwake_i;
 
 
 
 
//----------------------------- Global Signals -----------------------------
wire gtx0_tx_system_reset_c;
wire gtx0_rx_system_reset_c;
wire gtx1_tx_system_reset_c;
wire gtx1_rx_system_reset_c;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [7:0] tied_to_vcc_vec_i;
wire drp_clk_in_i;
 
//--------------------------- User Clocks ---------------------------------
wire gtx0_txusrclk_i;
wire gtx0_txusrclk2_i;
wire txoutclk_mmcm0_locked_i;
wire txoutclk_mmcm0_reset_i;
wire gtx0_txoutclk_to_mmcm_i;
 
 
//--------------------------- Reference Clocks ----------------------------
wire q1_clk1_refclk_i;
wire q1_clk1_refclk_i_bufg;
//--------------------------- Reference Clocks ----------------------------
 
 
assign system_reset = rst_debounce;
//assign gtx_reset = rst_debounce|| speed_neg_rst;
assign gtx_reset = rst_debounce;
//assign mmcm_reset = ~PLLLKDET_OUT || speed_neg_rst;
assign mmcm_reset = ~PLLLKDET_OUT;
assign GEN2_led = GEN2;
assign LINKUP = linkup;
assign LINKUP_led = linkup_led_out;
assign align_en_out = align_en_out;
assign DCMLOCKED_OUT = mmcm_locked; // LED active high
 
assign PLLLKDET_OUT_N = PLLLKDET_OUT;
assign rxelecidlereset0 = (rxelecidle0 && resetdone0);
assign rxenelecidleresetb = !rxelecidlereset0;
 
assign rx_dataout = rxdataout;
 
 
always @(posedge gtx_refclk_bufg)
begin : GTX_REF_CLK_CNT
begin
gtx_refclk_count = gtx_refclk_count + 1;
end
end
 
always @(posedge mmcm_clk_in)
begin : GTX_TXOUTCLK_CNT
begin
gtx_txoutclk_count = gtx_txoutclk_count + 1;
end
end
 
 
always @(posedge gtx0_txusrclk_i)
begin : GTX_TXUSRCLK_CNT
begin
gtx_txusrclk_count = gtx_txusrclk_count + 1;
end
end
 
always @(posedge gtx0_txusrclk2_i)
begin : GTX_TXUSRCLK2_CNT
begin
gtx_txusrclk2_count = gtx_txusrclk2_count + 1;
end
end
 
 
always @(posedge CLKIN_150)
begin : CLKIN_150_CNT
begin
CLKIN_150_count = CLKIN_150_count + 1;
end
end
 
assign rst_0 = GTXRESET_IN;
always @(posedge CLKIN_150)
begin
rst_1 <= rst_0;
rst_2 <= rst_1;
rst_3 <= rst_2;
end
 
assign rst_debounce = (rst_1 & rst_2 & rst_3);
 
//assign rst_debounce = GTXRESET_IN;
 
 
// SATA PHY output clock assignments
assign sata_user_clk = gtx0_txusrclk2_i;
 
 
OOB_control OOB_control_i
(
.oob_control_ila_control (oob_control_ila_control),
//-------- GTX Ports --------/
.clk (gtx0_txusrclk2_i),
.reset (gtx_reset),
.link_reset (1'b0),
.rxreset (rxreset),
.rx_locked (PLLLKDET_OUT),
// OOB generation and detection signals from GTX
.txcominit (txcominit),
.txcomwake (txcomwake),
.cominitdet (cominitdet),
.comwakedet (comwakedet),
 
.rxelecidle (rxelecidle0),
.txelecidle_out (txelecidle),
.rxbyteisaligned (RXBYTEISALIGNED0),
.tx_dataout (txdata), // outgoing GTP data
.tx_charisk_out (tx_charisk_out), // GTP charisk out
.rx_datain (rxdata), // incoming GTP data
.rx_charisk_in (rxcharisk), // GTP charisk in
.gen2 (1'b1), // for SATA Generation 2
//----- USER DATA PORTS---------//
.tx_datain (tx_datain), // User datain port
.tx_charisk_in (tx_charisk_in), // User charisk in port
.rx_dataout (rxdataout), // User dataout port
.rx_charisk_out (rx_charisk_out), // User charisk out port
.linkup (linkup),
.linkup_led_out (linkup_led_out),
.align_en_out (align_en_out),
.CurrentState_out (CurrentState_out)
);
 
assign rxelecidle_out = rxelecidle0;
 
 
// Static signal Assigments
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 8'hff;
 
//---------------------Dedicated GTX Reference Clock Inputs ---------------
// The dedicated reference clock inputs you selected in the GUI are implemented using
// IBUFDS_GTXE1 instances.
//
// In the UCF file for this example design, you will see that each of
// these IBUFDS_GTXE1 instances has been LOCed to a particular set of pins. By LOCing to these
// locations, we tell the tools to use the dedicated input buffers to the GTX reference
// clock network, rather than general purpose IOs. To select other pins, consult the
// Implementation chapter of UG___, or rerun the wizard.
//
// This network is the highest performace (lowest jitter) option for providing clocks
// to the GTX transceivers.
IBUFDS_GTXE1 gtx_refclk_ibufds_i
(
.O (gtx_refclk),
.ODIV2 (),
.CEB (tied_to_ground_i),
.I (REFCLK_PAD_P_IN),
.IB (REFCLK_PAD_N_IN)
);
 
BUFG gtx_refclk_bufg_i
(
.I (gtx_refclk),
.O (gtx_refclk_bufg)
);
 
 
//--------------------------------- User Clocks ---------------------------
// The clock resources in this section were added based on userclk source selections on
// the Latency, Buffering, and Clocking page of the GUI. A few notes about user clocks:
// * The userclk and userclk2 for each GTX datapath (TX and RX) must be phase aligned to
// avoid data errors in the fabric interface whenever the datapath is wider than 10 bits
// * To minimize clock resources, you can share clocks between GTXs. GTXs using the same frequency
// or multiples of the same frequency can be accomadated using MMCMs. Use caution when
// using RXRECCLK as a clock source, however - these clocks can typically only be shared if all
// the channels using the clock are receiving data from TX channels that share a reference clock
// source with each other.
 
// assign txoutclk_mmcm0_reset_i = !gtx0_rxplllkdet_i;
 
 
 
BUFG txoutclk_bufg_i
(
.I (gtx0_txoutclk_i),
.O (mmcm_clk_in)
);
 
 
MGT_USRCLK_SOURCE_MMCM #
(
.MULT (8.0),
.DIVIDE (2),
.CLK_PERIOD (6.666),
.OUT0_DIVIDE (4.0),
.OUT1_DIVIDE (2.0),
.OUT2_DIVIDE (1),
.OUT3_DIVIDE (1)
)
txoutclk_mmcm0_i
(
.CLK0_OUT (gtx0_txusrclk2_i),
.CLK1_OUT (gtx0_txusrclk_i),
.CLK2_OUT (),
.CLK3_OUT (),
.CLK_IN (mmcm_clk_in),
.MMCM_LOCKED_OUT (mmcm_locked),
.MMCM_RESET_IN (mmcm_reset)
);
 
 
//instantiate GTX tile(two transceivers)
 
SATA_GTX_DUAL #
(
.WRAPPER_SIM_GTXRESET_SPEEDUP (0),
)
sata_gtx_dual_i
(
//_____________________________________________________________________
//_____________________________________________________________________
//GTX0 (X0Y4)
//---------------------- Loopback and Powerdown Ports ----------------------
.GTX0_LOOPBACK_IN (gtx0_loopback_i),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.GTX0_RXCHARISK_OUT (rxcharisk),
.GTX0_RXDISPERR_OUT (gtx0_rxdisperr_i),
.GTX0_RXNOTINTABLE_OUT (gtx0_rxnotintable_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GTX0_RXCLKCORCNT_OUT (gtx0_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GTX0_RXBYTEISALIGNED_OUT (RXBYTEISALIGNED0),
.GTX0_RXBYTEREALIGN_OUT (gtx0_rxbyterealign_i),
.GTX0_RXENMCOMMAALIGN_IN (gtx0_rxenmcommaalign_i),
.GTX0_RXENPCOMMAALIGN_IN (gtx0_rxenpcommaalign_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GTX0_RXDATA_OUT (rxdata),
.GTX0_RXRECCLK_OUT (gtx0_rxrecclk_i),
.GTX0_RXRESET_IN (rxreset),
.GTX0_RXUSRCLK_IN (gtx0_txusrclk_i),
.GTX0_RXUSRCLK2_IN (gtx0_txusrclk2_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GTX0_RXELECIDLE_OUT (rxelecidle0),
.GTX0_RXEQMIX_IN (gtx0_rxeqmix_i),
.GTX0_RXN_IN (RXN0_IN),
.GTX0_RXP_IN (RXP0_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GTX0_RXBUFRESET_IN (gtx_reset),
.GTX0_RXSTATUS_OUT (gtx0_rxstatus_i),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GTX0_GTXRXRESET_IN (gtx_reset),
.GTX0_MGTREFCLKRX_IN (CLKIN_150),
.GTX0_PLLRXRESET_IN (),
.GTX0_RXPLLLKDET_OUT (PLLLKDET_OUT),
.GTX0_RXRESETDONE_OUT (gtx0_rxresetdone_i),
//------------------- Receive Ports - RX Ports for SATA --------------------
.GTX0_COMINITDET_OUT (cominitdet),
.GTX0_COMWAKEDET_OUT (comwakedet),
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
// Speed Negotiation Control module is disabled here and the design is fixed for
// SATA GEN2 disks
.DADDR (7'b0),
.DCLK (mmcm_clk_in),
.DEN (1'b0),
.DI (16'b0),
.DRDY (),
.DO (),
.DWE (1'b0),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.GTX0_TXCHARISK_IN ({1'b0,1'b0,1'b0,tx_charisk_out}),
//.GTX0_TXCHARISK_IN ({1'b0,tx_charisk_out,1'b0,tx_charisk_out}),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GTX0_TXDATA_IN (txdata),
.GTX0_TXOUTCLK_OUT (gtx0_txoutclk_i),
.GTX0_TXRESET_IN (),
.GTX0_TXUSRCLK_IN (gtx0_txusrclk_i),
.GTX0_TXUSRCLK2_IN (gtx0_txusrclk2_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GTX0_TXDIFFCTRL_IN (gtx0_txdiffctrl_i),
.GTX0_TXN_OUT (TXN0_OUT),
.GTX0_TXP_OUT (TXP0_OUT),
.GTX0_TXPOSTEMPHASIS_IN (gtx0_txpostemphasis_i),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.GTX0_TXPREEMPHASIS_IN (gtx0_txpreemphasis_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GTX0_GTXTXRESET_IN (gtx_reset),
.GTX0_TXRESETDONE_OUT (gtx0_txresetdone_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.GTX0_TXELECIDLE_IN (txelecidle),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.GTX0_COMFINISH_OUT (comfinish),
.GTX0_TXCOMINIT_IN (txcominit),
.GTX0_TXCOMWAKE_IN (txcomwake),
 
//_____________________________________________________________________
//_____________________________________________________________________
//GTX1 (X0Y5)
//---------------------- Loopback and Powerdown Ports ----------------------
.GTX1_LOOPBACK_IN (gtx1_loopback_i),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.GTX1_RXDISPERR_OUT (gtx1_rxdisperr_i),
.GTX1_RXNOTINTABLE_OUT (gtx1_rxnotintable_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.GTX1_RXCLKCORCNT_OUT (gtx1_rxclkcorcnt_i),
//------------- Receive Ports - Comma Detection and Alignment --------------
.GTX1_RXBYTEISALIGNED_OUT (),
.GTX1_RXBYTEREALIGN_OUT (gtx1_rxbyterealign_i),
.GTX1_RXENMCOMMAALIGN_IN (gtx1_rxenmcommaalign_i),
.GTX1_RXENPCOMMAALIGN_IN (gtx1_rxenpcommaalign_i),
//----------------- Receive Ports - RX Data Path interface -----------------
.GTX1_RXDATA_OUT (),
.GTX1_RXRECCLK_OUT (gtx1_rxrecclk_i),
.GTX1_RXRESET_IN (rxreset),
.GTX1_RXUSRCLK_IN (gtx0_txusrclk_i),
.GTX1_RXUSRCLK2_IN (gtx0_txusrclk2_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GTX1_RXELECIDLE_OUT (rxelecidle1),
.GTX1_RXEQMIX_IN (gtx1_rxeqmix_i),
.GTX1_RXN_IN (),
.GTX1_RXP_IN (),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.GTX1_RXBUFRESET_IN (gtx_reset),
.GTX1_RXSTATUS_OUT (),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GTX1_GTXRXRESET_IN (gtx_reset),
.GTX1_MGTREFCLKRX_IN (CLKIN_150),
.GTX1_PLLRXRESET_IN (),
.GTX1_RXPLLLKDET_OUT (gtx1_rxplllkdet_i),
.GTX1_RXRESETDONE_OUT (gtx1_rxresetdone_i),
//------------------- Receive Ports - RX Ports for SATA --------------------
.GTX1_COMINITDET_OUT (gtx1_cominitdet_i),
.GTX1_COMWAKEDET_OUT (gtx1_comwakedet_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.GTX1_TXCHARISK_IN ({1'b0,1'b0,1'b0,tx_charisk_out}),
//.GTX1_TXCHARISK_IN ({1'b0,tx_charisk_out,1'b0,tx_charisk_out}),
//---------------- Transmit Ports - TX Data Path interface -----------------
.GTX1_TXDATA_IN (txdata),
.GTX1_TXOUTCLK_OUT (gtx1_txoutclk_i),
.GTX1_TXRESET_IN (),
.GTX1_TXUSRCLK_IN (gtx0_txusrclk_i),
.GTX1_TXUSRCLK2_IN (gtx0_txusrclk2_i),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.GTX1_TXDIFFCTRL_IN (gtx1_txdiffctrl_i),
.GTX1_TXN_OUT (),
.GTX1_TXP_OUT (),
.GTX1_TXPOSTEMPHASIS_IN (gtx1_txpostemphasis_i),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.GTX1_TXPREEMPHASIS_IN (gtx1_txpreemphasis_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GTX1_GTXTXRESET_IN (gtx_reset),
.GTX1_TXRESETDONE_OUT (gtx1_txresetdone_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.GTX1_TXELECIDLE_IN (txelecidle),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.GTX1_COMFINISH_OUT (gtx1_comfinish_i),
.GTX1_TXCOMINIT_IN (gtx1_txcominit_i),
.GTX1_TXCOMWAKE_IN (gtx1_txcomwake_i)
 
);
 
// SATA PHY ILA
wire [7:0] trig0;
wire [15:0] trig1;
wire [1:0] trig2;
wire [15:0] trig3;
wire [15:0] trig4;
wire [15:0] trig5;
wire [15:0] trig6;
wire [15:0] trig7;
wire [15:0] trig8;
wire [15:0] trig9;
wire [15:0] trig10;
wire [35:0] control;
 
if (CHIPSCOPE == "TRUE") begin
sata_phy_ila i_sata_phy_ila
(
.control(sata_phy_ila_control),
.clk(gtx0_txusrclk2_i),
.trig0(trig0),
.trig1(trig1),
.trig2(trig2),
.trig3(trig3),
.trig4(trig4),
.trig5(trig5),
.trig6(trig6),
.trig7(trig7),
.trig8(trig8),
.trig9(trig9),
.trig10(trig10)
);
end
 
assign trig0 = CurrentState_out;
assign trig1[0] = gtx0_rxstatus_i;
assign trig1[1] = gtx0_txusrclk_i;
assign trig1[2] = gtx0_txusrclk2_i;
assign trig1[3] = gtx_reset;
assign trig1[4] = comfinish;
assign trig1[5] = PLLLKDET_OUT;
assign trig1[6] = mmcm_reset;
assign trig1[7] = mmcm_locked;
assign trig1[8] = rxelecidle0;
assign trig1[9] = RXBYTEISALIGNED0;
assign trig1[10] = gtx0_rxresetdone_i;
assign trig1[11] = txelecidle;
assign trig1[12] = txcominit;
assign trig1[13] = txcomwake;
assign trig1[14] = cominitdet;
assign trig1[15] = comwakedet;
assign trig2 = 2'b0;
assign trig3[0] = gtx0_txresetdone_i;
assign trig3[1] = speed_neg_rst;
assign trig3[2] = GTXRESET_IN;
assign trig3[3] = rst_1;
assign trig3[6:4] = rxcharisk;
assign trig3[15:7] = 9'b0;
assign trig4 = gtx_refclk_count;
assign trig5 = gtx_txoutclk_count;
assign trig6 = gtx_txusrclk_count;
assign trig7 = gtx_txusrclk2_count;
assign trig8 = 16'b0;
assign trig9 = CLKIN_200_count;
assign trig10 = CLKIN_150_count;
 
endmodule
 
 
module sata_phy_ila
(
control,
clk,
trig0,
trig1,
trig2,
trig3,
trig4,
trig5,
trig6,
trig7,
trig8,
trig9,
trig10
);
input [35:0] control;
input clk;
input [7:0] trig0;
input [15:0] trig1;
input [1:0] trig2;
input [15:0] trig3;
input [15:0] trig4;
input [15:0] trig5;
input [15:0] trig6;
input [15:0] trig7;
input [15:0] trig8;
input [15:0] trig9;
input [15:0] trig10;
endmodule
/trunk/hdl/verilog/sata_gtx.v
0,0 → 1,638
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version : 1.8
// \ \ Application : Virtex-6 FPGA GTX Transceiver Wizard
// / / Filename : sata_gtx.v
// /___/ /\ Timestamp :
// \ \ / \
// \___\/\___\
//
//
// Module SATA_GTX (a GTX Wrapper)
// Generated by Xilinx Virtex-6 FPGA GTX Transceiver Wizard
//
//
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
 
 
`timescale 1ns / 1ps
 
 
//***************************** Entity Declaration ****************************
 
module SATA_GTX #
(
// Simulation attributes
parameter GTX_SIM_GTXRESET_SPEEDUP = 0, // Set to 1 to speed up sim reset
// Share RX PLL parameter
parameter GTX_TX_CLK_SOURCE = "TXPLL",
// Save power parameter
parameter GTX_POWER_SAVE = 10'b0000000000
)
(
//---------------------- Loopback and Powerdown Ports ----------------------
input [2:0] LOOPBACK_IN,
//--------------------- Receive Ports - 8b10b Decoder ----------------------
output [3:0] RXCHARISK_OUT,
output [3:0] RXDISPERR_OUT,
output [3:0] RXNOTINTABLE_OUT,
//----------------- Receive Ports - Clock Correction Ports -----------------
output [2:0] RXCLKCORCNT_OUT,
//------------- Receive Ports - Comma Detection and Alignment --------------
output RXBYTEISALIGNED_OUT,
output RXBYTEREALIGN_OUT,
input RXENMCOMMAALIGN_IN,
input RXENPCOMMAALIGN_IN,
//----------------- Receive Ports - RX Data Path interface -----------------
output [31:0] RXDATA_OUT,
output RXRECCLK_OUT,
input RXRESET_IN,
input RXUSRCLK_IN,
input RXUSRCLK2_IN,
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
output RXELECIDLE_OUT,
input [2:0] RXEQMIX_IN,
input RXN_IN,
input RXP_IN,
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
input RXBUFRESET_IN,
output [2:0] RXSTATUS_OUT,
//---------------------- Receive Ports - RX PLL Ports ----------------------
input GTXRXRESET_IN,
input [1:0] MGTREFCLKRX_IN,
input PLLRXRESET_IN,
output RXPLLLKDET_OUT,
output RXRESETDONE_OUT,
//------------------- Receive Ports - RX Ports for SATA --------------------
output COMINITDET_OUT,
output COMWAKEDET_OUT,
// -------------- Speed Neg Module ports ------------------------
input [6:0] DADDR, //DRP address
input DEN, //DRP enable
input [15:0] DI, //DRP data in
output[15:0] DO, //DRP data out
output DRDY, //DRP ready
input DWE, //DRP write enable
input DCLK,
 
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
input [3:0] TXCHARISK_IN,
//---------------- Transmit Ports - TX Data Path interface -----------------
input [31:0] TXDATA_IN,
output TXOUTCLK_OUT,
input TXRESET_IN,
input TXUSRCLK_IN,
input TXUSRCLK2_IN,
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
input [3:0] TXDIFFCTRL_IN,
output TXN_OUT,
output TXP_OUT,
input [4:0] TXPOSTEMPHASIS_IN,
//------------- Transmit Ports - TX Driver and OOB signalling --------------
input [3:0] TXPREEMPHASIS_IN,
//--------------------- Transmit Ports - TX PLL Ports ----------------------
input GTXTXRESET_IN,
input [1:0] MGTREFCLKTX_IN,
input PLLTXRESET_IN,
output TXPLLLKDET_OUT,
output TXRESETDONE_OUT,
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
input TXELECIDLE_IN,
//------------------- Transmit Ports - TX Ports for SATA -------------------
output COMFINISH_OUT,
input TXCOMINIT_IN,
input TXCOMWAKE_IN
 
 
);
 
 
//***************************** Wire Declarations *****************************
 
// ground and vcc signals
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
 
 
//RX Datapath signals
wire [31:0] rxdata_i;
 
 
//TX Datapath signals
wire [31:0] txdata_i;
//
//********************************* Main Body of Code**************************
//------------------------- Static signal Assigments ---------------------
 
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
//------------------- GTX Datapath byte mapping -----------------
// The GTX provides little endian data (first byte received on RXDATA[7:0])
assign RXDATA_OUT = rxdata_i;
 
// The GTX transmits little endian data (TXDATA[7:0] transmitted first)
assign txdata_i = TXDATA_IN;
 
 
 
 
 
//------------------------- GTX Instantiations --------------------------
GTXE1 #
(
//_______________________ Simulation-Only Attributes __________________
//.SIM_RECEIVER_DETECT_PASS ("TRUE"),
//.SIM_TX_ELEC_IDLE_LEVEL ("X"),
//.SIM_GTXRESET_SPEEDUP (GTX_SIM_GTXRESET_SPEEDUP),
//.SIM_VERSION ("2.0"),
//.SIM_TXREFCLK_SOURCE (3'b000),
//.SIM_RXREFCLK_SOURCE (3'b000),
 
//--------------------------TX PLL----------------------------
.TX_CLK_SOURCE (GTX_TX_CLK_SOURCE),
.TX_OVERSAMPLE_MODE ("FALSE"),
.TXPLL_COM_CFG (24'h21680a),
.TXPLL_CP_CFG (8'h0D),
.TXPLL_DIVSEL_FB (2),
.TXPLL_DIVSEL_OUT (1),
.TXPLL_DIVSEL_REF (1),
.TXPLL_DIVSEL45_FB (5),
.TXPLL_LKDET_CFG (3'b111),
.TX_CLK25_DIVIDER (6),
.TXPLL_SATA (2'b01),
.TX_TDCC_CFG (2'b11),
.PMA_CAS_CLK_EN ("FALSE"),
.POWER_SAVE (GTX_POWER_SAVE),
 
//-----------------------TX Interface-------------------------
.GEN_TXUSRCLK ("FALSE"),
.TX_DATA_WIDTH (40),
.TX_USRCLK_CFG (6'h00),
//.TXOUTCLK_CTRL ("TXOUTCLKPMA_DIV2"),
.TXOUTCLK_CTRL ("TXPLLREFCLK_DIV2"),
.TXOUTCLK_DLY (10'b0000000000),
 
//------------TX Buffering and Phase Alignment----------------
.TX_PMADATA_OPT (1'b0),
.PMA_TX_CFG (20'h80082),
.TX_BUFFER_USE ("TRUE"),
.TX_BYTECLK_CFG (6'h00),
.TX_EN_RATE_RESET_BUF ("TRUE"),
.TX_XCLK_SEL ("TXOUT"),
.TX_DLYALIGN_CTRINC (4'b0100),
.TX_DLYALIGN_LPFINC (4'b0110),
.TX_DLYALIGN_MONSEL (3'b000),
.TX_DLYALIGN_OVRDSETTING (8'b10000000),
 
//-----------------------TX Gearbox---------------------------
.GEARBOX_ENDEC (3'b000),
.TXGEARBOX_USE ("FALSE"),
 
//--------------TX Driver and OOB Signalling------------------
.TX_DRIVE_MODE ("DIRECT"),
.TX_IDLE_ASSERT_DELAY (3'b100),
.TX_IDLE_DEASSERT_DELAY (3'b010),
.TXDRIVE_LOOPBACK_HIZ ("FALSE"),
.TXDRIVE_LOOPBACK_PD ("FALSE"),
 
//------------TX Pipe Control for PCI Express/SATA------------
.COM_BURST_VAL (4'b0101),
 
//----------------TX Attributes for PCI Express---------------
.TX_DEEMPH_0 (5'b11010),
.TX_DEEMPH_1 (5'b10000),
.TX_MARGIN_FULL_0 (7'b1001110),
.TX_MARGIN_FULL_1 (7'b1001001),
.TX_MARGIN_FULL_2 (7'b1000101),
.TX_MARGIN_FULL_3 (7'b1000010),
.TX_MARGIN_FULL_4 (7'b1000000),
.TX_MARGIN_LOW_0 (7'b1000110),
.TX_MARGIN_LOW_1 (7'b1000100),
.TX_MARGIN_LOW_2 (7'b1000010),
.TX_MARGIN_LOW_3 (7'b1000000),
.TX_MARGIN_LOW_4 (7'b1000000),
 
//--------------------------RX PLL----------------------------
.RX_OVERSAMPLE_MODE ("FALSE"),
.RXPLL_COM_CFG (24'h21680a),
.RXPLL_CP_CFG (8'h0D),
.RXPLL_DIVSEL_FB (2),
.RXPLL_DIVSEL_OUT (1),
.RXPLL_DIVSEL_REF (1),
.RXPLL_DIVSEL45_FB (5),
.RXPLL_LKDET_CFG (3'b111),
.RX_CLK25_DIVIDER (6),
 
//-----------------------RX Interface-------------------------
.GEN_RXUSRCLK ("FALSE"),
.RX_DATA_WIDTH (40),
.RXRECCLK_CTRL ("RXRECCLKPMA_DIV2"),
.RXRECCLK_DLY (10'b0000000000),
.RXUSRCLK_DLY (16'h0000),
 
//--------RX Driver,OOB signalling,Coupling and Eq.,CDR-------
.AC_CAP_DIS ("FALSE"),
.CDR_PH_ADJ_TIME (5'b10100),
.OOBDETECT_THRESHOLD (3'b111),
//.PMA_CDR_SCAN (27'h640404C),
.PMA_CDR_SCAN (27'h6C08040),
//.PMA_RX_CFG (25'h05ce049),
.PMA_RX_CFG (25'h0DCE111),
.RCV_TERM_GND ("FALSE"),
.RCV_TERM_VTTRX ("TRUE"),
.RX_EN_IDLE_HOLD_CDR ("FALSE"),
.RX_EN_IDLE_RESET_FR ("TRUE"),
.RX_EN_IDLE_RESET_PH ("TRUE"),
.TX_DETECT_RX_CFG (14'h1832),
.TERMINATION_CTRL (5'b00000),
.TERMINATION_OVRD ("FALSE"),
.CM_TRIM (2'b01),
.PMA_RXSYNC_CFG (7'h00),
.PMA_CFG (76'h0040000040000000003),
.BGTEST_CFG (2'b00),
.BIAS_CFG (17'h00000),
 
//------------RX Decision Feedback Equalizer(DFE)-------------
.DFE_CAL_TIME (5'b01100),
.DFE_CFG (8'b00011011),
.RX_EN_IDLE_HOLD_DFE ("TRUE"),
.RX_EYE_OFFSET (8'h4C),
.RX_EYE_SCANMODE (2'b00),
 
//-----------------------PRBS Detection-----------------------
.RXPRBSERR_LOOPBACK (1'b0),
 
//----------------Comma Detection and Alignment---------------
.ALIGN_COMMA_WORD (2),
.COMMA_10B_ENABLE (10'b1111111111),
.COMMA_DOUBLE ("FALSE"),
.DEC_MCOMMA_DETECT ("TRUE"), //changed
.DEC_PCOMMA_DETECT ("TRUE"), //changed
.DEC_VALID_COMMA_ONLY ("FALSE"),
//.MCOMMA_10B_VALUE (10'b0110000011),
.MCOMMA_10B_VALUE (10'b1010000011),
.MCOMMA_DETECT ("TRUE"),
.PCOMMA_10B_VALUE (10'b0101111100),
.PCOMMA_DETECT ("TRUE"),
.RX_DECODE_SEQ_MATCH ("TRUE"),
.RX_SLIDE_AUTO_WAIT (5),
//.RX_SLIDE_MODE ("OFF"),
.RX_SLIDE_MODE ("PCS"),
.SHOW_REALIGN_COMMA ("FALSE"),
 
//---------------RX Loss-of-sync State Machine----------------
.RX_LOS_INVALID_INCR (8),
.RX_LOS_THRESHOLD (128),
.RX_LOSS_OF_SYNC_FSM ("FALSE"),
 
//-----------------------RX Gearbox---------------------------
.RXGEARBOX_USE ("FALSE"),
 
//-----------RX Elastic Buffer and Phase alignment------------
.RX_BUFFER_USE ("TRUE"),
.RX_EN_IDLE_RESET_BUF ("TRUE"),
.RX_EN_MODE_RESET_BUF ("TRUE"),
.RX_EN_RATE_RESET_BUF ("TRUE"),
.RX_EN_REALIGN_RESET_BUF ("FALSE"),
.RX_EN_REALIGN_RESET_BUF2 ("FALSE"),
.RX_FIFO_ADDR_MODE ("FULL"),
.RX_IDLE_HI_CNT (4'b1000),
.RX_IDLE_LO_CNT (4'b0000),
.RX_XCLK_SEL ("RXREC"),
.RX_DLYALIGN_CTRINC (4'b1110),
.RX_DLYALIGN_EDGESET (5'b00010),
.RX_DLYALIGN_LPFINC (4'b1110),
.RX_DLYALIGN_MONSEL (3'b000),
.RX_DLYALIGN_OVRDSETTING (8'b10000000),
 
//----------------------Clock Correction----------------------
.CLK_COR_ADJ_LEN (4),
.CLK_COR_DET_LEN (4),
.CLK_COR_INSERT_IDLE_FLAG ("FALSE"),
.CLK_COR_KEEP_IDLE ("FALSE"),
//.CLK_COR_MAX_LAT (20),
.CLK_COR_MAX_LAT (18),
//.CLK_COR_MIN_LAT (14),
.CLK_COR_MIN_LAT (16),
.CLK_COR_PRECEDENCE ("TRUE"),
.CLK_COR_REPEAT_WAIT (0),
.CLK_COR_SEQ_1_1 (10'b0110111100),
.CLK_COR_SEQ_1_2 (10'b0001001010),
.CLK_COR_SEQ_1_3 (10'b0001001010),
.CLK_COR_SEQ_1_4 (10'b0001111011),
.CLK_COR_SEQ_1_ENABLE (4'b1111),
.CLK_COR_SEQ_2_1 (10'b0100000000),
.CLK_COR_SEQ_2_2 (10'b0100000000),
.CLK_COR_SEQ_2_3 (10'b0100000000),
.CLK_COR_SEQ_2_4 (10'b0100000000),
//.CLK_COR_SEQ_2_ENABLE (4'b1111),
.CLK_COR_SEQ_2_ENABLE (4'b0000),
.CLK_COR_SEQ_2_USE ("FALSE"),
.CLK_CORRECT_USE ("TRUE"),
 
//----------------------Channel Bonding----------------------
.CHAN_BOND_1_MAX_SKEW (1),
.CHAN_BOND_2_MAX_SKEW (1),
.CHAN_BOND_KEEP_ALIGN ("FALSE"),
.CHAN_BOND_SEQ_1_1 (10'b0000000000),
.CHAN_BOND_SEQ_1_2 (10'b0000000000),
.CHAN_BOND_SEQ_1_3 (10'b0000000000),
.CHAN_BOND_SEQ_1_4 (10'b0000000000),
.CHAN_BOND_SEQ_1_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_1 (10'b0000000000),
.CHAN_BOND_SEQ_2_2 (10'b0000000000),
.CHAN_BOND_SEQ_2_3 (10'b0000000000),
.CHAN_BOND_SEQ_2_4 (10'b0000000000),
.CHAN_BOND_SEQ_2_CFG (5'b00000),
.CHAN_BOND_SEQ_2_ENABLE (4'b1111),
.CHAN_BOND_SEQ_2_USE ("FALSE"),
.CHAN_BOND_SEQ_LEN (1),
.PCI_EXPRESS_MODE ("FALSE"),
 
//-----------RX Attributes for PCI Express/SATA/SAS----------
.SAS_MAX_COMSAS (52),
.SAS_MIN_COMSAS (40),
.SATA_BURST_VAL (3'b100),
.SATA_IDLE_VAL (3'b100),
.SATA_MAX_BURST (7),
.SATA_MAX_INIT (22),
.SATA_MAX_WAKE (7),
.SATA_MIN_BURST (4),
.SATA_MIN_INIT (12),
.SATA_MIN_WAKE (4),
.TRANS_TIME_FROM_P2 (12'h03c),
.TRANS_TIME_NON_P2 (8'h19),
.TRANS_TIME_RATE (8'hff),
.TRANS_TIME_TO_P2 (10'h064)
 
)
gtxe1_i
(
//---------------------- Loopback and Powerdown Ports ----------------------
.LOOPBACK (LOOPBACK_IN),
.RXPOWERDOWN (2'b00),
.TXPOWERDOWN (2'b00),
//------------ Receive Ports - 64b66b and 64b67b Gearbox Ports -------------
.RXDATAVALID (),
.RXGEARBOXSLIP (tied_to_ground_i),
.RXHEADER (),
.RXHEADERVALID (),
.RXSTARTOFSEQ (),
//--------------------- Receive Ports - 8b10b Decoder ----------------------
.RXCHARISCOMMA (),
.RXCHARISK (RXCHARISK_OUT),
.RXDEC8B10BUSE (tied_to_vcc_i),
.RXDISPERR (RXDISPERR_OUT),
.RXNOTINTABLE (RXNOTINTABLE_OUT),
.RXRUNDISP (),
.USRCODEERR (tied_to_ground_i),
//----------------- Receive Ports - Channel Bonding Ports ------------------
.RXCHANBONDSEQ (),
.RXCHBONDI (tied_to_ground_vec_i[3:0]),
.RXCHBONDLEVEL (tied_to_ground_vec_i[2:0]),
.RXCHBONDMASTER (tied_to_ground_i),
.RXCHBONDO (),
.RXCHBONDSLAVE (tied_to_ground_i),
.RXENCHANSYNC (tied_to_ground_i),
//----------------- Receive Ports - Clock Correction Ports -----------------
.RXCLKCORCNT (RXCLKCORCNT_OUT),
//------------- Receive Ports - Comma Detection and Alignment --------------
.RXBYTEISALIGNED (RXBYTEISALIGNED_OUT),
.RXBYTEREALIGN (RXBYTEREALIGN_OUT),
.RXCOMMADET (),
.RXCOMMADETUSE (tied_to_vcc_i),
.RXENMCOMMAALIGN (RXENMCOMMAALIGN_IN),
.RXENPCOMMAALIGN (RXENPCOMMAALIGN_IN),
.RXSLIDE (tied_to_ground_i),
//--------------------- Receive Ports - PRBS Detection ---------------------
.PRBSCNTRESET (tied_to_ground_i),
.RXENPRBSTST (tied_to_ground_vec_i[2:0]),
.RXPRBSERR (),
//----------------- Receive Ports - RX Data Path interface -----------------
.RXDATA (rxdata_i),
.RXRECCLK (RXRECCLK_OUT),
.RXRECCLKPCS (),
.RXRESET (RXRESET_IN),
.RXUSRCLK (RXUSRCLK_IN),
.RXUSRCLK2 (RXUSRCLK2_IN),
//---------- Receive Ports - RX Decision Feedback Equalizer(DFE) -----------
.DFECLKDLYADJ (tied_to_ground_vec_i[5:0]),
.DFECLKDLYADJMON (),
.DFEDLYOVRD (tied_to_vcc_i),
.DFEEYEDACMON (),
.DFESENSCAL (),
.DFETAP1 (tied_to_ground_vec_i[4:0]),
.DFETAP1MONITOR (),
.DFETAP2 (tied_to_ground_vec_i[4:0]),
.DFETAP2MONITOR (),
.DFETAP3 (tied_to_ground_vec_i[3:0]),
.DFETAP3MONITOR (),
.DFETAP4 (tied_to_ground_vec_i[3:0]),
.DFETAP4MONITOR (),
.DFETAPOVRD (tied_to_vcc_i),
//----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
.GATERXELECIDLE (tied_to_ground_i),
.IGNORESIGDET (tied_to_ground_i),
.RXCDRRESET (RXBUFRESET_IN),
.RXELECIDLE (RXELECIDLE_OUT),
.RXEQMIX ({tied_to_ground_vec_i[6:0],RXEQMIX_IN}),
.RXN (RXN_IN),
.RXP (RXP_IN),
//------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
.RXBUFRESET (RXBUFRESET_IN),
.RXBUFSTATUS (),
.RXCHANISALIGNED (),
.RXCHANREALIGN (),
.RXDLYALIGNDISABLE (tied_to_ground_i),
.RXDLYALIGNMONENB (tied_to_ground_i),
.RXDLYALIGNMONITOR (),
.RXDLYALIGNOVERRIDE (tied_to_vcc_i),
.RXDLYALIGNRESET (tied_to_ground_i),
.RXDLYALIGNSWPPRECURB (tied_to_vcc_i),
.RXDLYALIGNUPDSW (tied_to_ground_i),
.RXENPMAPHASEALIGN (tied_to_ground_i),
.RXPMASETPHASE (tied_to_ground_i),
.RXSTATUS (RXSTATUS_OUT),
//------------- Receive Ports - RX Loss-of-sync State Machine --------------
.RXLOSSOFSYNC (),
//-------------------- Receive Ports - RX Oversampling ---------------------
.RXENSAMPLEALIGN (tied_to_ground_i),
.RXOVERSAMPLEERR (),
//---------------------- Receive Ports - RX PLL Ports ----------------------
.GREFCLKRX (tied_to_ground_i),
.GTXRXRESET (GTXRXRESET_IN),
.MGTREFCLKRX (MGTREFCLKRX_IN),
.NORTHREFCLKRX (tied_to_ground_vec_i[1:0]),
.PERFCLKRX (tied_to_ground_i),
.PLLRXRESET (PLLRXRESET_IN),
.RXPLLLKDET (RXPLLLKDET_OUT),
.RXPLLLKDETEN (tied_to_vcc_i),
.RXPLLPOWERDOWN (tied_to_ground_i),
.RXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
.RXRATE (tied_to_ground_vec_i[1:0]),
.RXRATEDONE (),
.RXRESETDONE (RXRESETDONE_OUT),
.SOUTHREFCLKRX (tied_to_ground_vec_i[1:0]),
//------------ Receive Ports - RX Pipe Control for PCI Express -------------
.PHYSTATUS (),
.RXVALID (),
//--------------- Receive Ports - RX Polarity Control Ports ----------------
.RXPOLARITY (tied_to_ground_i),
//------------------- Receive Ports - RX Ports for SATA --------------------
.COMINITDET (COMINITDET_OUT),
.COMSASDET (),
.COMWAKEDET (COMWAKEDET_OUT),
//----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
.DADDR (DADDR),
.DCLK (DCLK),
.DEN (DEN),
.DI (DI),
.DRDY (DRDY),
.DRPDO (DO),
.DWE (DWE),
//------------ Transmit Ports - 64b66b and 64b67b Gearbox Ports ------------
.TXGEARBOXREADY (),
.TXHEADER (tied_to_ground_vec_i[2:0]),
.TXSEQUENCE (tied_to_ground_vec_i[6:0]),
.TXSTARTSEQ (tied_to_ground_i),
//-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
.TXBYPASS8B10B (tied_to_ground_vec_i[3:0]),
.TXCHARDISPMODE (tied_to_ground_vec_i[3:0]),
.TXCHARDISPVAL (tied_to_ground_vec_i[3:0]),
.TXCHARISK (TXCHARISK_IN),
.TXENC8B10BUSE (tied_to_vcc_i),
.TXKERR (),
.TXRUNDISP (),
//----------------------- Transmit Ports - GTX Ports -----------------------
.GTXTEST (13'b1000000000000),
.MGTREFCLKFAB (),
.TSTCLK0 (tied_to_ground_i),
.TSTCLK1 (tied_to_ground_i),
.TSTIN (20'b11111111111111111111),
.TSTOUT (),
//---------------- Transmit Ports - TX Data Path interface -----------------
.TXDATA (txdata_i),
.TXOUTCLK (TXOUTCLK_OUT),
.TXOUTCLKPCS (),
.TXRESET (TXRESET_IN),
.TXUSRCLK (TXUSRCLK_IN),
.TXUSRCLK2 (TXUSRCLK2_IN),
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.TXBUFDIFFCTRL (3'b100),
//.TXDIFFCTRL TXDIFFCTRL_IN,
.TXDIFFCTRL (4'b1000),
.TXINHIBIT (tied_to_ground_i),
.TXN (TXN_OUT),
.TXP (TXP_OUT),
.TXPOSTEMPHASIS (TXPOSTEMPHASIS_IN),
//------------- Transmit Ports - TX Driver and OOB signalling --------------
.TXPREEMPHASIS (TXPREEMPHASIS_IN),
//--------- Transmit Ports - TX Elastic Buffer and Phase Alignment ---------
.TXBUFSTATUS (),
//------ Transmit Ports - TX Elastic Buffer and Phase Alignment Ports ------
.TXDLYALIGNDISABLE (tied_to_vcc_i),
.TXDLYALIGNMONENB (tied_to_ground_i),
.TXDLYALIGNMONITOR (),
.TXDLYALIGNOVERRIDE (tied_to_ground_i),
.TXDLYALIGNRESET (tied_to_ground_i),
.TXDLYALIGNUPDSW (tied_to_vcc_i),
.TXENPMAPHASEALIGN (tied_to_ground_i),
.TXPMASETPHASE (tied_to_ground_i),
//--------------------- Transmit Ports - TX PLL Ports ----------------------
.GREFCLKTX (tied_to_ground_i),
.GTXTXRESET (GTXTXRESET_IN),
.MGTREFCLKTX (MGTREFCLKTX_IN),
.NORTHREFCLKTX (tied_to_ground_vec_i[1:0]),
.PERFCLKTX (tied_to_ground_i),
.PLLTXRESET (PLLTXRESET_IN),
.SOUTHREFCLKTX (tied_to_ground_vec_i[1:0]),
.TXPLLLKDET (TXPLLLKDET_OUT),
.TXPLLLKDETEN (tied_to_vcc_i),
.TXPLLPOWERDOWN (tied_to_ground_i),
.TXPLLREFSELDY (tied_to_ground_vec_i[2:0]),
.TXRATE (tied_to_ground_vec_i[1:0]),
.TXRATEDONE (),
.TXRESETDONE (TXRESETDONE_OUT),
//------------------- Transmit Ports - TX PRBS Generator -------------------
.TXENPRBSTST (tied_to_ground_vec_i[2:0]),
.TXPRBSFORCEERR (tied_to_ground_i),
//------------------ Transmit Ports - TX Polarity Control ------------------
.TXPOLARITY (tied_to_ground_i),
//--------------- Transmit Ports - TX Ports for PCI Express ----------------
.TXDEEMPH (tied_to_ground_i),
.TXDETECTRX (tied_to_ground_i),
.TXELECIDLE (TXELECIDLE_IN),
.TXMARGIN (tied_to_ground_vec_i[2:0]),
.TXPDOWNASYNCH (tied_to_ground_i),
.TXSWING (tied_to_ground_i),
//------------------- Transmit Ports - TX Ports for SATA -------------------
.COMFINISH (COMFINISH_OUT),
.TXCOMINIT (TXCOMINIT_IN),
.TXCOMSAS (tied_to_ground_i),
.TXCOMWAKE (TXCOMWAKE_IN)
 
);
endmodule
 
/trunk/hdl/vhdl/sata_core.vhd
0,0 → 1,289
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
----------------------------------------------------------------------------------------
-- ENTITY: sata_core
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: The SATA core implements the Command, Transport and Link Layers of
-- the SATA protocol and provides a Physical Layer Wrapper for the GTX
-- transceivers. The Physical Layer Wrapper also includes an Out of Band
-- Signaling (OOB) controller state machine which deals with initialization
-- and synchronization of the SATA link. It can interface with SATA 2
-- Winchester style Hard Disks as well as Flash-based Solid State Drives
-- The core provides a simple interface to issue READ/WRITE sector commands.
-- The DATA interface is 32-bit FIFO like.
-- A 150 MHz input reference clock is needed for the GTX transceivers.
-- The output data is delivered 4 bytes @ 75 MHz (user output clock)
-- for a theoretical peak bandwidth of 300 MB/s (SATA 2).
--
--
-- PORTS:
-- Command, Control and Status --
-- ready_for_cmd : When asserted, SATA core is ready to execute new command.
-- This signal goes low after new_cmd is asserted.
-- It also serves as the command done signal
-- new_cmd : Asserted for one clock cycle to start a request
-- cmd_type : "01" for READ request and "10" for WRITE request
-- sector_count : Number of sectors requested by user
-- sector_addr : Starting address of request
-- Data and User Clock --
 
-- sata_din : Data from user to Write to Disk
-- sata_din_we : Write Enable to SATA Core when FULL is low
-- sata_core_full : SATA Core Full- de-assert WE
-- sata_dout : Data output from SATA Core
-- sata_dout_re : Read Enable from SATA asserted when EMPTY is low
-- sata_core_empty : SATA Core Empty- de-assert RE
-- SATA_USER_DATA_CLK_IN : SATA Core Write Clock
-- SATA_USER_DATA_CLK_OUT : SATA Core Read Clock
-- sata_timer : SATA core timer output to check performance
--PHY Signals--
-- CLKIN_150 : 150 Mhz input reference clock for the GTX transceivers
-- reset : Resets GTX and SATA core; can be tied to a software reset
 
-- LINKUP : Indicates Link Initialization done (OOB) and SATA link is up
--GTX transmit/receive pins: Connected to the FMC_HPC pins on a ML605 board
-- TXP0_OUT, TXN0_OUT, RXP0_IN, RXN0_IN
-----------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity sata_core is
generic(
CHIPSCOPE : boolean := false;
DATA_WIDTH : natural := 32
);
port(
-- ChipScope ILA / Trigger Signals
sata_rx_frame_ila_control : in std_logic_vector(35 downto 0);
sata_tx_frame_ila_control : in std_logic_vector(35 downto 0);
sata_phy_ila_control : in std_logic_vector(35 downto 0);
oob_control_ila_control : in std_logic_vector(35 downto 0);
cmd_layer_ila_control : in std_logic_vector(35 downto 0);
scrambler_ila_control : in std_logic_vector(35 downto 0);
descrambler_ila_control : in std_logic_vector(35 downto 0);
---------------------------------------
-- SATA Interface -----
-- Command, Control and Status --
ready_for_cmd : out std_logic;
new_cmd : in std_logic;
cmd_type : in std_logic_vector(1 downto 0);
sector_count : in std_logic_vector(31 downto 0);
sector_addr : in std_logic_vector(31 downto 0);
-- Data and User Clock --
sata_din : in std_logic_vector(31 downto 0);
sata_din_we : in std_logic;
sata_core_full : out std_logic;
sata_dout : out std_logic_vector(31 downto 0);
sata_dout_re : in std_logic;
sata_core_empty : out std_logic;
SATA_USER_DATA_CLK_IN : in std_logic;
SATA_USER_DATA_CLK_OUT : out std_logic;
 
-- Timer --
sata_timer : out std_logic_vector(31 downto 0);
 
-- PHY Signals
-- Clock and Reset Signals
CLKIN_150 : in std_logic;
reset : in std_logic;
 
LINKUP : out std_logic;
TXP0_OUT : out std_logic;
TXN0_OUT : out std_logic;
RXP0_IN : in std_logic;
RXN0_IN : in std_logic;
PLLLKDET_OUT_N : out std_logic;
DCMLOCKED_OUT : out std_logic
);
end sata_core;
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture BEHAV of sata_core is
 
-- Sata Phy
signal sata_user_clk : std_logic;
--signal GTXRESET : std_logic;
signal LINKUP_i : std_logic;
-- Sata Phy
 
signal REFCLK_PAD_P_IN_i : std_logic;
signal REFCLK_PAD_N_IN_i : std_logic;
-- COMMAND LAYER / LINK LAYER SIGNALS
signal ll_ready_for_cmd_i : std_logic;
signal sata_ready_for_cmd_i : std_logic;
signal ll_cmd_start : std_logic;
signal ll_cmd_type : std_logic_vector(1 downto 0);
signal ll_dout : std_logic_vector(31 downto 0);
signal ll_dout_we : std_logic;
signal ll_din : std_logic_vector(31 downto 0);
signal ll_din_re : std_logic;
signal sector_count_int : integer;
 
-- User FIFO signals
signal user_din_re : std_logic;
signal user_fifo_dout : std_logic_vector(31 downto 0);
signal user_fifo_full : std_logic;
signal user_fifo_prog_full : std_logic;
signal user_fifo_empty : std_logic;
 
signal write_fifo_full_i : std_logic;
signal read_fifo_empty : std_logic;
 
-- USER FIFO DECLARATION
component user_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
prog_full: OUT std_logic;
empty: OUT std_logic);
end component;
 
-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin
 
--- User Logic Fifo for writing data ---
USER_FIFO_i : user_fifo
port map (
rst => reset,
clk => sata_user_clk,
din => sata_din,
wr_en => sata_din_we,
dout => user_fifo_dout,
rd_en => user_din_re,
full => user_fifo_full,
prog_full => user_fifo_prog_full,
empty => user_fifo_empty);
 
-- SATA Core Output Signals
ready_for_cmd <= sata_ready_for_cmd_i;
sata_core_full <= write_fifo_full_i;
sata_core_empty <= read_fifo_empty;
SATA_USER_DATA_CLK_OUT <= sata_user_clk;
LINKUP <= LINKUP_i;
-----------------------------------------------------------------------------
-- Command Layer Instance
-----------------------------------------------------------------------------
 
COMMAND_LAYER_i : entity work.command_layer
generic map
(
CHIPSCOPE => CHIPSCOPE
)
port map
(
-- ChipScope Signal
cmd_layer_ila_control => cmd_layer_ila_control,
-- Clock and Reset Signals
sw_reset => reset,
clk => sata_user_clk,
new_cmd => new_cmd,
cmd_done => sata_ready_for_cmd_i,
cmd_type => cmd_type,
sector_count => sector_count,
sector_addr => sector_addr,
user_din => user_fifo_dout,
user_din_re_out => user_din_re,
user_dout => sata_dout,
user_dout_re => sata_dout_re,
write_fifo_full => write_fifo_full_i,
user_fifo_empty => user_fifo_empty,
user_fifo_full => user_fifo_prog_full,
sector_timer_out => sata_timer,
 
-- Signals from/to Link Layer
ll_ready_for_cmd => ll_ready_for_cmd_i,
ll_cmd_start => ll_cmd_start,
ll_cmd_type => ll_cmd_type,
ll_dout => ll_dout,
ll_dout_we => ll_dout_we,
ll_din => ll_din,
ll_din_re => ll_din_re
);
 
------------------------------------------
-- Sata Link Layer Module Instance
------------------------------------------
sector_count_int <= conv_integer(sector_count);
 
SATA_LINK_LAYER_i: entity work.sata_link_layer
generic map(
CHIPSCOPE => CHIPSCOPE,
DATA_WIDTH => DATA_WIDTH
)
port map(
-- Clock and Reset Signals
CLKIN_150 => CLKIN_150,
sw_reset => reset,
-- ChipScope ILA / Trigger Signals
sata_rx_frame_ila_control => sata_rx_frame_ila_control ,
sata_tx_frame_ila_control => sata_tx_frame_ila_control ,
oob_control_ila_control => oob_control_ila_control,
sata_phy_ila_control => sata_phy_ila_control,
scrambler_ila_control => scrambler_ila_control,
descrambler_ila_control => descrambler_ila_control,
---------------------------------------
-- Ports from/to User Logic
read_fifo_empty => read_fifo_empty,
write_fifo_full => write_fifo_full_i,
GTX_RESET_IN => reset,
sector_count => sector_count_int,
sata_user_clk_out => sata_user_clk,
-- Ports from/to Command Layer
ready_for_cmd_out => ll_ready_for_cmd_i,
new_cmd_in => ll_cmd_start,
cmd_type => ll_cmd_type,
sata_din => ll_dout,
sata_din_we => ll_dout_we,
sata_dout => ll_din,
sata_dout_re => ll_din_re,
---------------------------------------
-- Ports to SATA PHY
REFCLK_PAD_P_IN => REFCLK_PAD_P_IN_i,
REFCLK_PAD_N_IN => REFCLK_PAD_N_IN_i,
TXP0_OUT => TXP0_OUT,
TXN0_OUT => TXN0_OUT,
RXP0_IN => RXP0_IN,
RXN0_IN => RXN0_IN,
PLLLKDET_OUT_N => PLLLKDET_OUT_N,
DCMLOCKED_OUT => DCMLOCKED_OUT,
LINKUP_led => LINKUP_i
);
 
end BEHAV;
/trunk/hdl/vhdl/mux_161.vhd
0,0 → 1,100
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
 
--------------------------------------------------------------------------------
-- Entity mux_161
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: 32 bit 16:1 Multiplexer
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
 
entity mux_161 is
generic(
DATA_WIDTH: natural := 32
);
 
port(
a : in std_logic_vector(DATA_WIDTH-1 downto 0);
b : in std_logic_vector(DATA_WIDTH-1 downto 0);
c : in std_logic_vector(DATA_WIDTH-1 downto 0);
d : in std_logic_vector(DATA_WIDTH-1 downto 0);
e : in std_logic_vector(DATA_WIDTH-1 downto 0);
f : in std_logic_vector(DATA_WIDTH-1 downto 0);
g : in std_logic_vector(DATA_WIDTH-1 downto 0);
h : in std_logic_vector(DATA_WIDTH-1 downto 0);
i : in std_logic_vector(DATA_WIDTH-1 downto 0);
j : in std_logic_vector(DATA_WIDTH-1 downto 0);
k : in std_logic_vector(DATA_WIDTH-1 downto 0);
l : in std_logic_vector(DATA_WIDTH-1 downto 0);
m : in std_logic_vector(DATA_WIDTH-1 downto 0);
n : in std_logic_vector(DATA_WIDTH-1 downto 0);
o : in std_logic_vector(DATA_WIDTH-1 downto 0);
p : in std_logic_vector(DATA_WIDTH-1 downto 0);
sel : in std_logic_vector(3 downto 0);
output : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end mux_161;
 
architecture mux_behav of mux_161 is
begin
process(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,sel)
begin
case (sel) is
when "0000" =>
output <= a;
when "0001" =>
output <= b;
when "0010" =>
output <= c;
when "0011" =>
output <= d;
when "0100" =>
output <= e;
when "0101" =>
output <= f;
when "0110" =>
output <= g;
when "0111" =>
output <= h;
when "1000" =>
output <= i;
when "1001" =>
output <= j;
when "1010" =>
output <= k;
when "1011" =>
output <= l;
when "1100" =>
output <= m;
when "1101" =>
output <= n;
when "1110" =>
output <= o;
when others =>
output <= p;
end case;
end process;
end mux_behav;
 
/trunk/hdl/vhdl/sata_link_layer.vhd
0,0 → 1,1560
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
----------------------------------------------------------------------------------------
-- ENTITY: sata_link_layer
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: This sub-module implements the Transport and Link Layers of the SATA Protocol
-- It is the heart of the SATA Core where the major functions of sending/receiving
-- sequences of Frame Information Structures (FIS), packing them into
-- Frames and sending/receiving Frames are accomplished.
-- The Master FSM deals with the Transport Layer functions of sending receiving FISs
-- using the TX and RX FSMs.
-- The TX and RX FSMs use the crc, scrambler and primitive muxes to construct and
-- deconstruct Frames. They also implement a Frame transmission/reception protocol.
-- PORTS:
-----------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity sata_link_layer is
generic(
CHIPSCOPE : boolean := false;
DATA_WIDTH : natural := 32
);
port(
-- Clock and Reset Signals
--clk : in std_logic;
sw_reset : in std_logic;
-- ChipScope ILA / Trigger Signals
sata_rx_frame_ila_control : in std_logic_vector(35 downto 0);
sata_tx_frame_ila_control : in std_logic_vector(35 downto 0);
--master_fsm_ila_control : in std_logic_vector(35 downto 0);
oob_control_ila_control : in std_logic_vector(35 downto 0);
sata_phy_ila_control : in std_logic_vector(35 downto 0);
scrambler_ila_control : in std_logic_vector (35 downto 0);
descrambler_ila_control : in std_logic_vector (35 downto 0);
---------------------------------------
-- Signals from/to User Logic
sata_user_clk_out : out std_logic;
GTX_RESET_IN : in std_logic;
ready_for_cmd_out : out std_logic;
new_cmd_in : in std_logic;
cmd_type : in std_logic_vector(1 downto 0);
sector_count : in integer;
sata_din : in std_logic_vector(DATA_WIDTH-1 downto 0);
sata_din_we : in std_logic;
sata_dout : out std_logic_vector(DATA_WIDTH-1 downto 0);
sata_dout_re : in std_logic;
read_fifo_empty : out std_logic;
write_fifo_full : out std_logic;
---------------------------------------
-- Ports from/to SATA PHY
REFCLK_PAD_P_IN : in std_logic; -- MGTCLKA, clocks GTP_X0Y0-2
REFCLK_PAD_N_IN : in std_logic; -- MGTCLKA
TXP0_OUT : out std_logic;
TXN0_OUT : out std_logic;
RXP0_IN : in std_logic;
RXN0_IN : in std_logic;
PLLLKDET_OUT_N : out std_logic;
DCMLOCKED_OUT : out std_logic;
LINKUP_led : out std_logic;
--GEN2_led : out std_logic;
CLKIN_150 : in std_logic
);
end sata_link_layer;
 
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture BEHAV of sata_link_layer is
 
-------------------------------------------------------------------------------
-- LINK LAYER
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
--Commands
constant IDEN_DEV : std_logic_vector(1 downto 0) := "00";
constant READ_DMA : std_logic_vector(1 downto 0) := "01";
constant WRITE_DMA : std_logic_vector(1 downto 0) := "10";
constant SET_FEATURES : std_logic_vector(1 downto 0) := "11";
--Primitves
constant SYNC : std_logic_vector(3 downto 0) := "0000";
constant R_RDY : std_logic_vector(3 downto 0) := "0001";
constant R_IP : std_logic_vector(3 downto 0) := "0010";
constant R_OK : std_logic_vector(3 downto 0) := "0011";
constant R_ERR : std_logic_vector(3 downto 0) := "0100";
constant X_RDY : std_logic_vector(3 downto 0) := "0101";
constant WTRM : std_logic_vector(3 downto 0) := "0110";
constant HOLD : std_logic_vector(3 downto 0) := "0111";
constant HOLD_ACK : std_logic_vector(3 downto 0) := "1000";
constant CONT : std_logic_vector(3 downto 0) := "1001";
 
constant SOF : std_logic_vector(3 downto 0) := "1010";
constant EOF : std_logic_vector(3 downto 0) := "1011";
constant FIS : std_logic_vector(3 downto 0) := "1100";
constant PRIM_SCRM : std_logic_vector(3 downto 0) := "1101";
 
constant COMMAND_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(5, 16); -- (6DWORDS: 5 + 1CRC)
--constant DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(259, 16); -- 260 WORDS (130DWORDS: 1FIS_TYPE + 128DATA + 1CRC)
constant REG_FIS_NDWORDS : std_logic_vector(15 downto 0) := conv_std_logic_vector(6, 16); -- (6DWORDS: 5 + 1CRC)
constant DATA_FIS_NDWORDS : integer := 130;
constant SECTOR_NDWORDS : integer := 128; -- 256 WORDS / 512 Byte Sector
constant NDWORDS_PER_DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(2048, 16);--128*16
constant NDWORDS_PER_DATA_FIS_32 : std_logic_vector(31 downto 0) := conv_std_logic_vector(2048, 32);--128*16
constant SYNC_COUNT_VALUE : std_logic_vector(7 downto 0) := conv_std_logic_vector(30, 8); -- 50 WORDS
-----------------------------------------------------------------------------
-- Finite State Machine Declaration (curr and next states)
-----------------------------------------------------------------------------
type MASTER_FSM_TYPE is (idle, capture_dev_sign, wait_for_cmd, H2D_REG_FIS, D2H_DMA_ACT_FIS,
H2D_DATA_FIS, D2H_REG_FIS, D2H_DATA_FIS, D2H_PIO_SETUP, dead
);
signal master_fsm_curr, master_fsm_next : MASTER_FSM_TYPE := idle;
signal master_fsm_value : std_logic_vector (0 to 3);
 
 
type RX_FRAME_FSM_TYPE is (idle, send_R_RDY, send_R_IP, send_HOLD_ACK, send_R_OK,
send_SYNC, wait_for_X_RDY, dead
);
signal rx_frame_curr, rx_frame_next : RX_FRAME_FSM_TYPE := idle;
signal rx_frame_value : std_logic_vector (0 to 3);
 
 
type TX_FRAME_FSM_TYPE is (idle, send_X_RDY, send_SOF, send_FIS, send_EOF, send_WTRM,
send_SYNC, send_HOLD_ACK, send_HOLD, dead
);
signal tx_frame_curr, tx_frame_next : TX_FRAME_FSM_TYPE := idle;
signal tx_frame_value : std_logic_vector (0 to 3);
-----------------------------------------------------------------------------
-- Finite State Machine Declaration (curr and next states)
-----------------------------------------------------------------------------
 
signal new_cmd : std_logic;
 
signal FIS_word_count, FIS_word_count_next : std_logic_vector(0 to 15); --Counter for FIS WORD Count (WRITE)
signal FIS_count_value, FIS_count_value_next : std_logic_vector(0 to 15); --Counter LIMIT for FIS WORD Count (WRITE)
signal rx_sector_count : std_logic_vector(0 to 15); --Counter for number of received sectors
signal tx_sector_count, tx_sector_count_next : std_logic_vector(0 to 15); --Counter for number of transmitted sectors
signal dword_count : std_logic_vector(0 to 7); --Counter for DWORDS in each received sector
signal DATA_FIS_dword_count : std_logic_vector(0 to 15); --Counter for DWORDS in each received DATA FIS
signal dword_count_init_value : std_logic_vector(0 to 31);
signal dword_count_value : std_logic_vector(0 to 15);
signal start_rx, start_tx, rx_done, tx_done : std_logic;
signal start_rx_next, start_tx_next, rx_done_next, tx_done_next : std_logic;
signal prim_type_rx, prim_type_tx, prim_type : std_logic_vector (0 to 3);
signal prim_type_rx_next, prim_type_tx_next : std_logic_vector (0 to 3);
signal rx_tx_state_sel, rx_tx_state_sel_next : std_logic;
signal sync_count_rx, sync_count_rx_next : std_logic_vector (0 to 7);
signal sync_count_tx, sync_count_tx_next : std_logic_vector (0 to 7);
signal ready_for_cmd_next : std_logic;
signal ready_for_cmd : std_logic;
signal frame_err, frame_err_next : std_logic;
signal tx_err, tx_err_next : std_logic;
 
signal tx_r_rdy, tx_r_ip, tx_r_ok, tx_r_err : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_x_rdy, tx_wtrm, tx_sof, tx_eof, tx_sync : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_hold, tx_hold_ack, tx_cont : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_dataout : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_charisk_out : std_logic;
signal tx_charisk_RX_FRAME, tx_charisk_TX_FRAME: std_logic;
signal output_mux_sel : std_logic_vector(0 to 3);
signal align_en_out : std_logic;
 
-- Primitive Detectors
signal SYNC_det : std_logic;
signal R_RDY_det : std_logic;
signal R_IP_det : std_logic;
signal R_OK_det : std_logic;
signal R_ERR_det : std_logic;
signal SOF_det : std_logic;
signal EOF_det : std_logic;
signal X_RDY_det : std_logic;
signal WTRM_det : std_logic;
signal CONT_det : std_logic;
signal HOLD_det : std_logic;
signal HOLD_det_r : std_logic;
signal HOLD_det_r2 : std_logic;
signal HOLD_det_r3 : std_logic;
signal HOLD_det_r4 : std_logic;
signal HOLD_start_det : std_logic;
signal HOLD_stop_det : std_logic;
signal HOLD_stop_after_ALIGN_det : std_logic;
signal CORNER_CASE_HOLD : std_logic;
signal HOLD_ACK_det : std_logic;
signal ALIGN_det : std_logic;
signal ALIGN_det_r : std_logic;
signal ALIGN_det_r2 : std_logic;
signal TWO_HOLD_det : std_logic;
signal TWO_HOLD_det_r : std_logic;
 
-----------------------------------------------------------------------------
-- Internal Signals
-----------------------------------------------------------------------------
signal sata_user_clk : std_logic;
signal rx_datain : std_logic_vector(0 to DATA_WIDTH-1);
signal rxelecidle : std_logic;
signal rx_charisk_in : std_logic_vector(3 downto 0);
-- Debugging OOB
signal OOB_state : std_logic_vector (0 to 7);
 
signal LINKUP : std_logic;
signal GEN2_led_i : std_logic;
 
-- Scrambler/DeScrambler
signal scrambler_din : std_logic_vector(0 to DATA_WIDTH-1);
signal scrambler_dout : std_logic_vector(0 to DATA_WIDTH-1);
signal scrambler_en, scrambler_en_r : std_logic;
signal scrambler_din_re, scrambler_din_re_r : std_logic;
signal scrambler_dout_we : std_logic;
signal scrambler_reset : std_logic;
signal scrambler_reset_after_FIS : std_logic;
signal descrambler_din : std_logic_vector(0 to DATA_WIDTH-1);
signal descrambler_dout : std_logic_vector(0 to DATA_WIDTH-1);
signal descrambler_en : std_logic;
signal descrambler_din_re, descrambler_din_re_r : std_logic;
signal descrambler_dout_we : std_logic;
signal descrambler_reset : std_logic;
signal scrambler_count : std_logic_vector(0 to 15);
signal scrambler_count_init_value : std_logic_vector(0 to 31);
signal scrambler_count_value : std_logic_vector(0 to 15);
signal scrambler_count_en_reg_fis : std_logic;
signal scrambler_count_en_data_fis : std_logic;
-- CRC
signal crc_reset : std_logic;
signal crc_din : std_logic_vector(0 to DATA_WIDTH-1);
signal crc_dout : std_logic_vector(0 to DATA_WIDTH-1);
signal crc_dout_r : std_logic_vector(0 to DATA_WIDTH-1);
signal crc_en : std_logic;
-----------------------------------------------------------------------------
-- Post-DeScramble Read FIFO to Command Layer
-----------------------------------------------------------------------------
signal read_fifo_re : std_logic;
signal read_fifo_we : std_logic;
signal read_fifo_empty_i : std_logic;
signal read_fifo_almost_empty : std_logic;
signal read_fifo_full : std_logic;
signal read_fifo_prog_full : std_logic;
signal read_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
signal read_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
 
-----------------------------------------------------------------------------
-- Pre-DeScramble RX FIFO from PHY Layer
-----------------------------------------------------------------------------
signal rx_fifo_we : std_logic;
signal rx_fifo_we_next : std_logic;
signal rx_fifo_re : std_logic;
signal rx_fifo_empty : std_logic;
signal rx_fifo_almost_empty : std_logic;
signal rx_fifo_full : std_logic;
signal rx_fifo_prog_full : std_logic;
signal rx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
signal rx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
signal rx_fifo_data_count : std_logic_vector(0 to 9);
 
-----------------------------------------------------------------------------
-- Pre-Scramble Write FIFO from Command Layer
-----------------------------------------------------------------------------
signal write_fifo_we : std_logic;
signal write_fifo_re : std_logic;
signal write_fifo_empty : std_logic;
signal write_fifo_almost_empty : std_logic;
signal write_fifo_full_i : std_logic;
signal write_fifo_prog_full : std_logic;
signal write_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
signal write_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
 
-----------------------------------------------------------------------------
-- Post-Scramble TX FIFO to PHY Layer
-----------------------------------------------------------------------------
signal tx_fifo_re : std_logic;
signal tx_fifo_re_next : std_logic;
signal tx_fifo_we : std_logic;
signal tx_fifo_empty : std_logic;
signal tx_fifo_almost_empty : std_logic;
signal tx_fifo_full : std_logic;
signal tx_fifo_prog_full : std_logic;
signal tx_fifo_din : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_fifo_dout : std_logic_vector(0 to DATA_WIDTH-1);
signal tx_fifo_data_count : std_logic_vector(0 to 9);
 
-----------------------------------------------------------------------------
-- Replay FIFO Signals
-----------------------------------------------------------------------------
signal replay_buffer_clear : std_logic;
signal replay_buffer_clear_next: std_logic;
 
-----------------------------------------------------------------------------
-- FIFO Declarations
-----------------------------------------------------------------------------
component read_write_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
rd_en: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
almost_empty: OUT std_logic;
empty: OUT std_logic;
full: OUT std_logic;
prog_full: OUT std_logic
);
end component;
 
component rx_tx_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
rd_en: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
almost_empty: OUT std_logic;
empty: OUT std_logic;
full: OUT std_logic;
prog_full: OUT std_logic;
data_count: OUT std_logic_vector(9 downto 0)
);
end component;
 
-----------------------------------------------------------------------------
-- SATA PHY Declaration
-----------------------------------------------------------------------------
component sata_phy
port (
oob_control_ila_control: in std_logic_vector(35 downto 0);
sata_phy_ila_control : in std_logic_vector(35 downto 0);
REFCLK_PAD_P_IN : in std_logic; -- MGTCLKA, clocks GTP_X0Y0-2
REFCLK_PAD_N_IN : in std_logic; -- MGTCLKA
GTXRESET_IN : in std_logic; -- GTP initialization
PLLLKDET_OUT_N : out std_logic;
TXP0_OUT : out std_logic;
TXN0_OUT : out std_logic;
RXP0_IN : in std_logic;
RXN0_IN : in std_logic;
DCMLOCKED_OUT : out std_logic;
LINKUP : out std_logic;
LINKUP_led : out std_logic;
sata_user_clk : out std_logic;
GEN2_led : out std_logic;
align_en_out : out std_logic;
tx_datain : in std_logic_vector(DATA_WIDTH-1 downto 0);
tx_charisk_in : in std_logic;
rx_dataout : out std_logic_vector(DATA_WIDTH-1 downto 0);
rx_charisk_out : out std_logic_vector(3 downto 0);
CurrentState_out : out std_logic_vector(7 downto 0);
rxelecidle_out : out std_logic;
CLKIN_150 : in std_logic
);
end component;
 
component sata_rx_frame_ila
port (
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(3 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(7 downto 0);
trig3 : in std_logic_vector(3 downto 0);
trig4 : in std_logic_vector(3 downto 0);
trig5 : in std_logic_vector(7 downto 0);
trig6 : in std_logic_vector(31 downto 0);
trig7 : in std_logic_vector(31 downto 0);
trig8 : in std_logic_vector(31 downto 0);
trig9 : in std_logic_vector(31 downto 0);
trig10 : in std_logic_vector(31 downto 0);
trig11 : in std_logic_vector(7 downto 0);
trig12 : in std_logic_vector(15 downto 0);
trig13 : in std_logic_vector(15 downto 0);
trig14 : in std_logic_vector(15 downto 0);
trig15 : in std_logic_vector(31 downto 0)
);
end component;
 
 
component sata_tx_frame_ila
port (
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(3 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(3 downto 0);
trig5 : in std_logic_vector(31 downto 0);
trig6 : in std_logic_vector(31 downto 0);
trig7 : in std_logic_vector(31 downto 0);
trig8 : in std_logic_vector(15 downto 0);
trig9 : in std_logic_vector(15 downto 0);
trig10 : in std_logic_vector(31 downto 0);
trig11 : in std_logic_vector(31 downto 0);
trig12 : in std_logic_vector(31 downto 0);
trig13 : in std_logic_vector(15 downto 0);
trig14 : in std_logic_vector(15 downto 0);
trig15 : in std_logic_vector(9 downto 0)
);
end component;
 
-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin
 
-------------------------------------------------------------------------------
-- LINK LAYER
-------------------------------------------------------------------------------
 
-----------------------------------------------------------------------------
-- PROCESS: MASTER_FSM_VALUE_PROC
-- PURPOSE: ChipScope State Indicator Signal
-----------------------------------------------------------------------------
MASTER_FSM_VALUE_PROC : process (master_fsm_curr) is
begin
case (master_fsm_curr) is
when idle => master_fsm_value <= x"0";
when capture_dev_sign => master_fsm_value <= x"1";
when wait_for_cmd => master_fsm_value <= x"2";
when H2D_REG_FIS => master_fsm_value <= x"3";
when D2H_DMA_ACT_FIS => master_fsm_value <= x"4";
when H2D_DATA_FIS => master_fsm_value <= x"5";
when D2H_DATA_FIS => master_fsm_value <= x"6";
when D2H_REG_FIS => master_fsm_value <= x"7";
when D2H_PIO_SETUP => master_fsm_value <= x"8";
when dead => master_fsm_value <= x"9";
when others => master_fsm_value <= x"A";
end case;
end process MASTER_FSM_VALUE_PROC;
-----------------------------------------------------------------------------
-- PROCESS: MASTER_FSM_STATE_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
MASTER_FSM_STATE_PROC : process (sata_user_clk)
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1') then
--Initializing internal signals
master_fsm_curr <= idle;
FIS_count_value <= (others => '0');
start_rx <= '0';
start_tx <= '0';
new_cmd <= '0';
ready_for_cmd <= '0';
else
-- Register all Current Signals to their _next Signals
master_fsm_curr <= master_fsm_next;
FIS_count_value <= FIS_count_value_next;
start_rx <= start_rx_next;
start_tx <= start_tx_next;
ready_for_cmd <= ready_for_cmd_next;
if (new_cmd_in = '1') then
new_cmd <= '1';
else
new_cmd <= '0';
end if;
end if;
end if;
end process MASTER_FSM_STATE_PROC;
 
-----------------------------------------------------------------------------
-- PROCESS: MASTER_FSM_LOGIC_PROC
-- PURPOSE: Implements a Sequence of FIS transfers for sending READ/WRITE sector
-- command. (Transport Layer)
-----------------------------------------------------------------------------
MASTER_FSM_LOGIC_PROC : process (master_fsm_curr, rx_done, tx_done, tx_err,
LINKUP, new_cmd, tx_sector_count
) is
begin
-- Register _next to current signals
master_fsm_next <= master_fsm_curr;
FIS_count_value_next <= (others => '0');
start_rx_next <= start_rx;
start_tx_next <= start_tx;
---------------------------------------------------------------------------
-- Finite State Machine
---------------------------------------------------------------------------
case (master_fsm_curr) is
-- x0
when idle =>
if (LINKUP = '1') then
start_rx_next <= '1';
master_fsm_next <= capture_dev_sign;
end if;
-- x1
when capture_dev_sign =>
start_rx_next <= '0';
if (rx_done = '1') then
master_fsm_next <= wait_for_cmd;
end if;
 
-- x2
when wait_for_cmd =>
if (new_cmd = '1') then
start_tx_next <= '1';
master_fsm_next <= H2D_REG_FIS;
end if;
 
-- x3
when H2D_REG_FIS =>
FIS_count_value_next <= COMMAND_FIS;
start_tx_next <= '0';
if (tx_done = '1') then
start_rx_next <= '1';
case (cmd_type) is
when IDEN_DEV =>
master_fsm_next <= D2H_PIO_SETUP;
when READ_DMA =>
master_fsm_next <= D2H_DATA_FIS;
when WRITE_DMA =>
master_fsm_next <= D2H_DMA_ACT_FIS;
when others =>
master_fsm_next <= D2H_REG_FIS;
end case;
end if;
if(tx_err = '1') then
start_tx_next <= '1';
master_fsm_next <= H2D_REG_FIS;
end if;
 
-- x4
when D2H_DMA_ACT_FIS =>
start_rx_next <= '0';
if (rx_done = '1') then
start_tx_next <= '1';
master_fsm_next <= H2D_DATA_FIS;
end if;
 
-- x5
when H2D_DATA_FIS =>
--FIS_count_value_next <= conv_std_logic_vector(((SECTOR_NDWORDS * sector_count) + 1), 16);
FIS_count_value_next <= (NDWORDS_PER_DATA_FIS + 1);
start_tx_next <= '0';
if ((tx_done = '1') or (tx_err = '1')) then
start_rx_next <= '1';
if (tx_sector_count >= conv_std_logic_vector(sector_count, 16)) then
master_fsm_next <= D2H_REG_FIS;
else
master_fsm_next <= D2H_DMA_ACT_FIS;
end if;
end if;
 
-- x6
when D2H_DATA_FIS =>
start_rx_next <= '0';
if (rx_done = '1') then
if (cmd_type = READ_DMA) then
start_rx_next <= '1';
master_fsm_next <= D2H_REG_FIS;
else
master_fsm_next <= wait_for_cmd;
end if;
end if;
 
-- x7
when D2H_REG_FIS =>
start_rx_next <= '0';
if (rx_done = '1') then
master_fsm_next <= wait_for_cmd;
end if;
 
-- x8
when D2H_PIO_SETUP =>
start_rx_next <= '0';
if (rx_done = '1') then
start_rx_next <= '1';
master_fsm_next <= D2H_DATA_FIS;
end if;
 
-- x9
when dead =>
master_fsm_next <= dead;
-- xA
when others =>
master_fsm_next <= dead;
 
end case;
end process MASTER_FSM_LOGIC_PROC;
 
ready_for_cmd_next <= '1' when (master_fsm_curr = wait_for_cmd) else '0';
ready_for_cmd_out <= ready_for_cmd;
 
-----------------------------------------------------------------------------
-- PROCESS: RX_FRAME_VALUE_PROC
-- PURPOSE: ChipScope State Indicator Signal
-----------------------------------------------------------------------------
RX_FRAME_VALUE_PROC : process (rx_frame_curr) is
begin
case (rx_frame_curr) is
when idle => rx_frame_value <= x"0";
when send_R_RDY => rx_frame_value <= x"1";
when send_R_IP => rx_frame_value <= x"2";
when send_HOLD_ACK => rx_frame_value <= x"3";
when send_R_OK => rx_frame_value <= x"4";
when send_SYNC => rx_frame_value <= x"5";
when wait_for_X_RDY => rx_frame_value <= x"6";
when dead => rx_frame_value <= x"7";
when others => rx_frame_value <= x"8";
end case;
end process RX_FRAME_VALUE_PROC;
-----------------------------------------------------------------------------
-- PROCESS: RX_FRAME_STATE_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
RX_FRAME_STATE_PROC : process (sata_user_clk)
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1') then
--Initializing internal signals
rx_frame_curr <= idle;
sync_count_rx <= (others => '0');
rx_done <= '0';
rx_fifo_we <= '0';
prim_type_rx <= (others => '0');
ALIGN_det_r <= '0';
ALIGN_det_r2 <= '0';
HOLD_det_r <= '0';
HOLD_det_r2 <= '0';
HOLD_det_r3 <= '0';
HOLD_det_r4 <= '0';
TWO_HOLD_det_r <= '0';
else
-- Register all Current Signals to their _next Signals
rx_frame_curr <= rx_frame_next;
sync_count_rx <= sync_count_rx_next;
rx_done <= rx_done_next;
rx_fifo_we <= rx_fifo_we_next;
prim_type_rx <= prim_type_rx_next;
ALIGN_det_r <= ALIGN_det;
ALIGN_det_r2 <= ALIGN_det_r;
HOLD_det_r <= HOLD_det;
HOLD_det_r2 <= HOLD_det_r;
HOLD_det_r3 <= HOLD_det_r2;
HOLD_det_r4 <= HOLD_det_r3;
TWO_HOLD_det_r <= TWO_HOLD_det;
end if;
end if;
end process RX_FRAME_STATE_PROC;
 
-----------------------------------------------------------------------------
-- PROCESS: RX_FRAME_LOGIC_PROC
-- PURPOSE: Receive FRAME from disk and unpack the FIS
-----------------------------------------------------------------------------
RX_FRAME_LOGIC_PROC : process (rx_frame_curr, sync_count_rx, ALIGN_det, HOLD_det,
HOLD_stop_after_ALIGN_det,
SOF_det, EOF_det, HOLD_start_det, HOLD_stop_det, SYNC_det,
start_rx, LINKUP, rx_datain, rx_sector_count, sector_count
) is
begin
-- Register _next to current signals
rx_frame_next <= rx_frame_curr;
sync_count_rx_next <= sync_count_rx;
rx_done_next <= rx_done;
prim_type_rx_next <= prim_type_rx;
rx_fifo_we_next <= '0';
---------------------------------------------------------------------------
-- Finite State Machine
---------------------------------------------------------------------------
case (rx_frame_curr) is
-- x0
when idle =>
rx_done_next <= '0';
prim_type_rx_next <= SYNC;
if (start_rx = '1') then
--if (master_fsm_curr = capture_dev_sign) then
rx_frame_next <= send_R_RDY;
--else
-- rx_frame_next <= wait_for_X_RDY;
--end if;
end if;
 
-- x6
--Wait for X_RDY before sending R_RDY
when wait_for_X_RDY =>
prim_type_rx_next <= SYNC;
if (X_RDY_det = '1') then
rx_frame_next <= send_R_RDY;
end if;
-- x1
when send_R_RDY =>
--Send R_RDY to get device signature
prim_type_rx_next <= R_RDY;
if (SOF_det = '1') then
rx_frame_next <= send_R_IP;
end if;
 
-- x2
when send_R_IP =>
--Send R_IP to indicate Reception in Progress
prim_type_rx_next <= R_IP;
rx_fifo_we_next <= '1';
 
if (ALIGN_det = '1' or HOLD_det = '1') then
rx_fifo_we_next <= '0';
end if;
 
if (EOF_det = '1') then
rx_fifo_we_next <= '0';
rx_frame_next <= send_R_OK;
end if;
 
-- Check for 2 HOLD primitives followed by CONT which indicates FIS pause
if (HOLD_start_det = '1') then
rx_fifo_we_next <= '0';
rx_frame_next <= send_HOLD_ACK;
end if;
 
-- x3
when send_HOLD_ACK =>
-- Send HOLD ACK to Acknowledge FIS pause
prim_type_rx_next <= HOLD_ACK;
if (HOLD_stop_after_ALIGN_det = '1') then
rx_fifo_we_next <= '1';
rx_frame_next <= send_R_IP;
end if;
if (HOLD_stop_det = '1') then
rx_frame_next <= send_R_IP;
end if;
 
-- x4
when send_R_OK =>
-- Send R_OK to indicate good frame
prim_type_rx_next <= R_OK;
if (SYNC_det = '1') then
if (master_fsm_curr = D2H_DATA_FIS) then
if (rx_sector_count < conv_std_logic_vector(sector_count,16)) then
rx_frame_next <= send_R_RDY;
else
rx_done_next <= '1';
rx_frame_next <= idle;
end if;
else
rx_frame_next <= send_SYNC;
end if;
end if;
 
-- x5
when send_SYNC =>
-- Send SYNC to indicate host idle
prim_type_rx_next <= SYNC;
if (sync_count_rx = SYNC_COUNT_VALUE) then
rx_done_next <= '1';
sync_count_rx_next <= (others => '0');
rx_frame_next <= idle;
else
sync_count_rx_next <= sync_count_rx + 1;
end if;
 
-- x6
when dead =>
rx_frame_next <= dead;
 
-- x7
when others =>
rx_frame_next <= dead;
 
end case;
end process RX_FRAME_LOGIC_PROC;
 
-- Counter for number of received sectors (used when number of RX sectors exceeds max 16 in one data FIS)
RX_SECTOR_CNT: process(sata_user_clk) is
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1' or new_cmd = '1') then
dword_count <= (others => '0');
rx_sector_count <= (others => '0');
elsif ((dword_count < (SECTOR_NDWORDS-1)) and (master_fsm_curr = D2H_DATA_FIS) and (rx_fifo_we_next = '1')) then
dword_count <= dword_count + 1;
elsif (dword_count = (SECTOR_NDWORDS-1)) then
dword_count <= (others => '0');
rx_sector_count <= rx_sector_count + 1;
elsif (EOF_det = '1') then
dword_count <= (others => '0');
else
dword_count <= dword_count;
rx_sector_count <= rx_sector_count;
end if;
end if;
end process RX_SECTOR_CNT;
 
 
-- DATA FIS DWORD Counter for stripping off DATA FIS header and CRC
DATA_FIS_DWORD_CNT: process(sata_user_clk) is
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1') then
DATA_FIS_dword_count <= (others => '0');
dword_count_init_value <= (others => '0');
elsif ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count < dword_count_value)) then
if (descrambler_dout_we = '1') then
DATA_FIS_dword_count <= DATA_FIS_dword_count + 1;
else
DATA_FIS_dword_count <= DATA_FIS_dword_count;
end if;
elsif ((DATA_FIS_dword_count = dword_count_value) and (master_fsm_curr = D2H_DATA_FIS)) then
if(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
dword_count_init_value <= (dword_count_init_value - NDWORDS_PER_DATA_FIS_32);
end if;
DATA_FIS_dword_count <= (others => '0');
else
DATA_FIS_dword_count <= (others => '0');
end if;
 
if(new_cmd = '1') then
dword_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
dword_count_value <= (others => '0');
elsif(dword_count_init_value < NDWORDS_PER_DATA_FIS_32) then
dword_count_value <= dword_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
elsif(dword_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
dword_count_value <= NDWORDS_PER_DATA_FIS + 1;
end if;
end if;
end process DATA_FIS_DWORD_CNT;
 
-----------------------------------------------------------------------------
-- PROCESS: TX_FRAME_VALUE_PROC
-- PURPOSE: ChipScope State Indicator Signal
-----------------------------------------------------------------------------
TX_FRAME_VALUE_PROC : process (tx_frame_curr) is
begin
case (tx_frame_curr) is
when idle => tx_frame_value <= x"0";
when send_X_RDY => tx_frame_value <= x"1";
when send_SOF => tx_frame_value <= x"2";
when send_FIS => tx_frame_value <= x"3";
when send_EOF => tx_frame_value <= x"4";
when send_WTRM => tx_frame_value <= x"5";
when send_SYNC => tx_frame_value <= x"6";
when send_HOLD_ACK => tx_frame_value <= x"7";
when send_HOLD => tx_frame_value <= x"8";
when dead => tx_frame_value <= x"9";
when others => tx_frame_value <= x"A";
end case;
end process TX_FRAME_VALUE_PROC;
-----------------------------------------------------------------------------
-- PROCESS: TX_FRAME_STATE_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
TX_FRAME_STATE_PROC : process (sata_user_clk)
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1') then
--Initializing internal signals
tx_frame_curr <= idle;
sync_count_tx <= (others => '0');
rx_tx_state_sel <= '0';
tx_done <= '0';
tx_fifo_re <= '0';
frame_err <= '0';
tx_err <= '0';
replay_buffer_clear <= '0';
prim_type_tx <= (others => '0');
FIS_word_count <= (others => '0');
tx_sector_count <= (others => '0');
elsif(new_cmd = '1') then
tx_sector_count <= (others => '0');
else
-- Register all Current Signals to their _next Signals
tx_frame_curr <= tx_frame_next;
sync_count_tx <= sync_count_tx_next;
rx_tx_state_sel <= rx_tx_state_sel_next;
tx_done <= tx_done_next;
tx_fifo_re <= tx_fifo_re_next;
frame_err <= frame_err_next;
tx_err <= tx_err_next;
replay_buffer_clear <= replay_buffer_clear_next;
prim_type_tx <= prim_type_tx_next;
FIS_word_count <= FIS_word_count_next;
tx_sector_count <= tx_sector_count_next;
end if;
end if;
end process TX_FRAME_STATE_PROC;
 
-----------------------------------------------------------------------------
-- PROCESS: TX_FRAME_LOGIC_PROC
-- PURPOSE: Next State and Output Logic
-----------------------------------------------------------------------------
TX_FRAME_LOGIC_PROC : process (tx_frame_curr, FIS_word_count, sector_count,
tx_sector_count,
R_RDY_det, R_OK_det, sync_count_tx, start_tx,
LINKUP, frame_err
) is
begin
-- Register _next to current signals
tx_frame_next <= tx_frame_curr;
sync_count_tx_next <= sync_count_tx;
rx_tx_state_sel_next <= rx_tx_state_sel;
tx_fifo_re_next <= tx_fifo_re;
tx_done_next <= tx_done;
frame_err_next <= frame_err;
tx_err_next <= tx_err;
replay_buffer_clear_next <= replay_buffer_clear;
prim_type_tx_next <= prim_type_tx;
FIS_word_count_next <= FIS_word_count;
tx_sector_count_next <= tx_sector_count;
---------------------------------------------------------------------------
-- Finite State Machine
---------------------------------------------------------------------------
case (tx_frame_curr) is
-- x0
when idle =>
tx_done_next <= '0';
tx_err_next <= '0';
replay_buffer_clear_next <= '0';
prim_type_tx_next <= SYNC;
FIS_word_count_next <= (others => '0');
 
if (start_tx = '1') then
rx_tx_state_sel_next <= '1';
tx_frame_next <= send_X_RDY;
end if;
-- x1
when send_X_RDY =>
-- Send X_RDY to indicate host ready to transmit
prim_type_tx_next <= X_RDY;
if (R_RDY_det = '1') then
tx_frame_next <= send_SOF;
end if;
 
-- x2
when send_SOF =>
--Send SOF to indicate start of new FRAME
prim_type_tx_next <= SOF;
if (align_en_out = '0') then
tx_frame_next <= send_FIS;
end if;
 
-- x3
when send_FIS =>
--Send FIS data
prim_type_tx_next <= FIS;
-- ALIGN primitives after 256 DWORDS
if (align_en_out = '1' or tx_fifo_almost_empty = '1') then
FIS_word_count_next <= FIS_word_count;
tx_fifo_re_next <= '0';
else
FIS_word_count_next <= FIS_word_count + '1';
tx_fifo_re_next <= '1';
end if;
-- Receive buffer empty condition
if (HOLD_start_det = '1') then
tx_frame_next <= send_HOLD_ACK;
end if;
-- Transmit buffer empty condition
if (tx_fifo_almost_empty = '1') then
if (align_en_out = '0') then
prim_type_tx_next <= HOLD;
tx_frame_next <= send_HOLD;
end if;
end if;
-- Transmitted sector count
if(((conv_integer(FIS_word_count) mod SECTOR_NDWORDS)=0) and (conv_integer(FIS_word_count)>0) and (align_en_out='0') and (tx_fifo_almost_empty='0')) then
tx_sector_count_next <= tx_sector_count + 1;
else
tx_sector_count_next <= tx_sector_count;
end if;
if ((tx_sector_count >= conv_std_logic_vector(sector_count, 16)) or (FIS_word_count >= FIS_count_value)) then
if (align_en_out = '0') then
FIS_word_count_next <= (others => '0');
tx_fifo_re_next <= '1';
prim_type_tx_next <= FIS;
tx_frame_next <= send_EOF;
end if;
end if;
 
-- x7
when send_HOLD_ACK =>
-- Send HOLD ACK to Acknowledge FIS pause
prim_type_tx_next <= HOLD_ACK;
tx_fifo_re_next <= '0';
--if (HOLD_stop_det = '1') then
if (R_IP_det = '1') then
tx_frame_next <= send_FIS;
end if;
 
-- x8
when send_HOLD =>
-- Send HOLD to indicate transmit buffer empty
prim_type_tx_next <= HOLD;
tx_fifo_re_next <= '0';
if (tx_fifo_empty = '0') then
tx_frame_next <= send_FIS;
end if;
 
-- x4
when send_EOF =>
--Send EOF to indicate end of FRAME
tx_fifo_re_next <= '0';
prim_type_tx_next <= EOF;
if (align_en_out = '0') then
tx_frame_next <= send_WTRM;
end if;
 
-- x5
when send_WTRM =>
-- Send WTRM to indicate Waiting for Frame Termination
prim_type_tx_next <= WTRM;
if (R_OK_det = '1' or R_ERR_det = '1' or SYNC_det = '1') then
if (R_ERR_det = '1' or SYNC_det = '1') then
if (master_fsm_curr = H2D_REG_FIS) then
frame_err_next <= '1';
else
frame_err_next <= '0';
end if;
end if;
if (R_OK_det = '1') then
replay_buffer_clear_next <= '1';
frame_err_next <= '0';
end if;
tx_frame_next <= send_SYNC;
end if;
 
-- x6
when send_SYNC =>
-- Send SYNC to indicate host idle
prim_type_tx_next <= SYNC;
if (sync_count_tx = SYNC_COUNT_VALUE) then
sync_count_tx_next <= (others => '0');
if (frame_err = '1') then
tx_err_next <= '1';
else
tx_done_next <= '1';
end if;
rx_tx_state_sel_next <= '0';
tx_frame_next <= idle;
else
sync_count_tx_next <= sync_count_tx + 1;
end if;
 
-- x8
when dead =>
tx_frame_next <= dead;
 
-- x9
when others =>
tx_frame_next <= dead;
 
end case;
end process TX_FRAME_LOGIC_PROC;
 
-- ASYNCHRONOUS MUXES
tx_charisk_RX_FRAME <= '1';
tx_charisk_TX_FRAME <= '0' when (((tx_frame_curr = send_FIS) and (tx_fifo_almost_empty = '0')) or ((tx_frame_curr=send_FIS) and
(tx_fifo_almost_empty = '1') and (master_fsm_curr = H2D_REG_FIS))) else '1';
--tx_charisk_TX_FRAME <= '0' when ((tx_frame_curr = send_FIS) and (tx_fifo_almost_empty = '0')) else '1';
--tx_charisk_out <= '0' when ((tx_frame_curr = send_FIS) or (prim_type_tx = PRIM_SCRM)) else tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
tx_charisk_out <= tx_charisk_RX_FRAME when (rx_tx_state_sel = '0') else tx_charisk_TX_FRAME;
prim_type <= prim_type_rx when (rx_tx_state_sel = '0') else prim_type_tx;
-- ASYNCHRONOUS MUXES
 
-- Primitive detection
ALIGN_det <= '1' when (rx_datain = x"7B4A4ABC") else '0';
SYNC_det <= '1' when (rx_datain = x"B5B5957C") else '0';
R_RDY_det <= '1' when (rx_datain = x"4A4A957C") else '0';
R_IP_det <= '1' when (rx_datain = x"5555B57C") else '0';
R_OK_det <= '1' when (rx_datain = x"3535B57C") else '0';
R_ERR_det <= '1' when (rx_datain = x"5656B57C") else '0';
SOF_det <= '1' when (rx_datain = x"3737B57C") else '0';
EOF_det <= '1' when (rx_datain = x"D5D5B57C") else '0';
X_RDY_det <= '1' when (rx_datain = x"5757B57C") else '0';
WTRM_det <= '1' when (rx_datain = x"5858B57C") else '0';
CONT_det <= '1' when (rx_datain = x"9999AA7C") else '0';
HOLD_det <= '1' when (rx_datain = x"D5D5AA7C") else '0';
HOLD_start_det <= '1' when (((TWO_HOLD_det_r = '1') and (CONT_det = '1')) or (CORNER_CASE_HOLD = '1')) else '0';
TWO_HOLD_det <= '1' when ((rx_datain = x"D5D5AA7C") and (HOLD_det_r = '1')) else '0';
HOLD_stop_det <= '1' when ((rx_datain = x"D5D5AA7C") and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) else '0';
HOLD_stop_after_ALIGN_det <= '1' when ((HOLD_det_r = '1') and (ALIGN_det_r2 = '1') and (ALIGN_det_r = '0') and (TWO_HOLD_det = '0')) or ((TWO_HOLD_det_r = '1') and (CONT_det = '0')) else '0';
-- Corner Case
-- ALIGN primitives are received between two HOLD primitives or between 2 HOLD and a CONT primitive
CORNER_CASE_HOLD <= '1' when ((CONT_det = '1') and (HOLD_det_r4 = '1')) else '0';
 
 
-- SATA Primitives
-- SYNC
tx_sync <= x"B5B5957C";
 
-- R_RDY
tx_r_rdy <= x"4A4A957C";
 
-- R_OK
tx_r_ok <= x"3535B57C";
 
-- R_ERR
tx_r_err <= x"5656B57C";
 
-- R_IP
tx_r_ip <= x"5555B57C";
 
-- X_RDY
tx_x_rdy <= x"5757B57C";
 
-- CONT
tx_cont <= x"9999AA7C";
 
-- WTRM
tx_wtrm <= x"5858B57C";
 
-- SOF
tx_sof <= x"3737B57C";
 
-- EOF
tx_eof <= x"D5D5B57C";
 
-- HOLD
tx_hold <= x"D5D5AA7C";
 
-- HOLD_ACK
tx_hold_ack <= x"9595AA7C";
 
-- Output Mux
OUTPUT_MUX_i: entity work.mux_161
generic map
(
DATA_WIDTH => 32
)
port map
(
a => tx_sync,
b => tx_r_rdy,
c => tx_r_ip,
d => tx_r_ok,
e => tx_r_err,
f => tx_x_rdy,
g => tx_wtrm,
h => tx_hold,
i => tx_hold_ack,
j => tx_cont,
k => tx_sof,
l => tx_eof,
m => tx_fifo_dout,
--n => tx_prim_scrm,
n => (others => '0'),
o => (others => '0'),
p => (others => '0'),
sel=> output_mux_sel,
output=> tx_dataout
);
 
output_mux_sel <= prim_type;
 
-------------------------------------------------------------------------------
-- LINK LAYER
-------------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Pre-DeScramble RX FIFO from PHY Layer
---------------------------------------------------------------------------
rx_fifo_din <= rx_datain;
rx_fifo_re <= descrambler_din_re_r;
RX_FIFO : rx_tx_fifo
port map (
clk => sata_user_clk,
rst => sw_reset,
rd_en => rx_fifo_re,
din => rx_fifo_din,
wr_en => rx_fifo_we_next,
dout => rx_fifo_dout,
almost_empty => rx_fifo_almost_empty,
empty => rx_fifo_empty,
full => rx_fifo_full,
prog_full => rx_fifo_prog_full,
data_count => rx_fifo_data_count
);
 
---------------------------------------------------------------------------
-- DESCRAMBLER
---------------------------------------------------------------------------
--descrambler_din(0 to 15) <= rx_fifo_dout(16 to 31);
--descrambler_din(16 to 31) <= rx_fifo_dout(0 to 15);
descrambler_din <= rx_fifo_dout;
descrambler_en <= not(rx_fifo_almost_empty);
descrambler_reset <= '1' when ((start_rx='1') or ((rx_frame_curr = send_R_OK) and (SYNC_det = '1'))) else '0';
 
DESCRAMBLER_i: entity work.scrambler
generic map(
CHIPSCOPE => FALSE
)
port map(
-- Clock and Reset Signals
clk => sata_user_clk,
reset => descrambler_reset,
-- ChipScope ILA / Trigger Signals
scrambler_ila_control => descrambler_ila_control,
---------------------------------------
-- Signals from/to Sata Link Layer FIFOs
prim_scrambler => '0',
scrambler_en => descrambler_en,
din_re => descrambler_din_re,
data_in => descrambler_din,
data_out => descrambler_dout,
dout_we => descrambler_dout_we
);
 
---------------------------------------------------------------------------
-- Post-DeScramble Read FIFO to Command Layer
---------------------------------------------------------------------------
read_fifo_din <= descrambler_dout;
read_fifo_we <= descrambler_dout_we when ((master_fsm_curr = D2H_DATA_FIS) and (DATA_FIS_dword_count > 0) and (DATA_FIS_dword_count < dword_count_value)) else '0';
READ_FIFO_i : read_write_fifo
port map (
clk => sata_user_clk,
rst => sw_reset,
rd_en => read_fifo_re,
din => read_fifo_din,
wr_en => read_fifo_we,
dout => read_fifo_dout,
almost_empty => read_fifo_almost_empty,
empty => read_fifo_empty_i,
full => read_fifo_full,
prog_full => read_fifo_prog_full
);
-- Data Output to Command Layer
sata_dout <= read_fifo_dout;
-- Input from Command Layer
read_fifo_re <= sata_dout_re;
 
read_fifo_empty <= read_fifo_empty_i;
---------------------------------------------------------------------------
-- Pre-Scramble Write FIFO from Command Layer
---------------------------------------------------------------------------
write_fifo_we <= sata_din_we;
write_fifo_din <= sata_din;
write_fifo_full <= write_fifo_prog_full;
--write_fifo_re <= scrambler_din_re_r when (scrambler_en = '1') else '0';
write_fifo_re <= scrambler_din_re_r when ((scrambler_en='1') and (scrambler_count_en_reg_fis='1')) or ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (write_fifo_empty = '0')) else '0';
 
WRITE_FIFO_i : read_write_fifo
port map (
clk => sata_user_clk,
rst => sw_reset,
din => write_fifo_din,
wr_en => write_fifo_we,
dout => write_fifo_dout,
rd_en => write_fifo_re,
almost_empty => write_fifo_almost_empty,
empty => write_fifo_empty,
full => write_fifo_full_i,
prog_full => write_fifo_prog_full
);
 
---------------------------------------------------------------------------
-- CRC
---------------------------------------------------------------------------
crc_reset <= scrambler_reset;
crc_en <= scrambler_dout_we;
crc_din <= write_fifo_dout;
 
CRC_i : entity work.crc
generic map (
CHIPSCOPE => FALSE
)
port map (
clk => sata_user_clk,
reset => crc_reset,
--crc_ila_control => crc_ila_control,
crc_en => crc_en,
data_in => crc_din,
data_out => crc_dout
);
 
---------------------------------------------------------------------------
-- SCRAMBLER
---------------------------------------------------------------------------
REGISTER_PROCESS : process(sata_user_clk) is
begin
if sata_user_clk'event and sata_user_clk = '1' then
if sw_reset = '1' then
scrambler_din_re_r <= '0';
descrambler_din_re_r <= '0';
crc_dout_r <= (others => '0');
else
scrambler_din_re_r <= scrambler_din_re;
descrambler_din_re_r <= descrambler_din_re;
crc_dout_r <= crc_dout;
end if;
end if;
end process REGISTER_PROCESS;
 
 
scrambler_count_en_reg_fis <= '1' when (master_fsm_curr = H2D_REG_FIS) else '0';
scrambler_count_en_data_fis <= '1' when ((master_fsm_curr = H2D_DATA_FIS) or ((master_fsm_curr = D2H_DMA_ACT_FIS) and (tx_sector_count > 0))) else '0';
 
-- To disable scrambler after the REG FIS
SCRAMBLER_CNT: process(sata_user_clk) is
begin
if ((sata_user_clk'event) and (sata_user_clk = '1')) then
if (sw_reset = '1') then
scrambler_count <= (others => '0');
scrambler_count_init_value <= (others => '0');
scrambler_count_value <= (others => '0');
scrambler_reset_after_FIS <= '0';
elsif ((scrambler_count < (REG_FIS_NDWORDS)) and (scrambler_count_en_reg_fis = '1')) then
scrambler_count <= scrambler_count + 1;
elsif ((scrambler_count < scrambler_count_value) and (scrambler_count_en_data_fis = '1') and (tx_fifo_we = '1') and (write_fifo_empty = '0')) then
scrambler_count <= scrambler_count + 1;
if (scrambler_count = NDWORDS_PER_DATA_FIS) then
scrambler_reset_after_FIS <= '1';
end if;
elsif (( scrambler_count = (NDWORDS_PER_DATA_FIS+1)) and (scrambler_count_en_data_fis = '1')) then
scrambler_count_init_value <= (scrambler_count_init_value - NDWORDS_PER_DATA_FIS_32);
scrambler_count <= (others => '0');
scrambler_reset_after_FIS <= '0';
else
scrambler_count <= scrambler_count;
end if;
 
if (scrambler_reset = '1') then
scrambler_count <= (others => '0');
scrambler_reset_after_FIS <= '0';
end if;
 
if(new_cmd = '1') then
scrambler_count_init_value <= conv_std_logic_vector((SECTOR_NDWORDS * sector_count), 32);
scrambler_count_value <= (others => '0');
elsif(scrambler_count_init_value < NDWORDS_PER_DATA_FIS_32) then
scrambler_count_value <= scrambler_count_init_value(16 to 31) + conv_std_logic_vector(1,16);
elsif(scrambler_count_init_value >= NDWORDS_PER_DATA_FIS_32) then
scrambler_count_value <= NDWORDS_PER_DATA_FIS + 1;
end if;
end if;
end process SCRAMBLER_CNT;
 
 
scrambler_reset <= (sw_reset or new_cmd or scrambler_reset_after_FIS or (tx_done and scrambler_count_en_reg_fis)) ;
scrambler_din <= crc_dout_r when ((scrambler_count = REG_FIS_NDWORDS) and (scrambler_count_en_reg_fis = '1')) or ((scrambler_count = scrambler_count_value) and (scrambler_count_en_data_fis = '1')) else write_fifo_dout;
scrambler_en <= not(write_fifo_empty) when (((scrambler_count_en_reg_fis = '1') and (scrambler_count < REG_FIS_NDWORDS))
--or ((scrambler_count_en_data_fis = '1') and (scrambler_count = NDWORDS_PER_DATA_FIS) and (tx_fifo_prog_full = '1'))
or ((scrambler_count_en_data_fis = '1') and (scrambler_count = (scrambler_count_value - '1'))))
else not(write_fifo_almost_empty) when ((scrambler_count_en_data_fis = '1') and (scrambler_count < scrambler_count_value) and (tx_fifo_prog_full = '0'))
else '0';
-- Corner Case: tx_fifo_almost_full goes high when (scrambler_count = NDWORDS_PER_DATA_FIS)
SCRAMBLER_i: entity work.scrambler
generic map(
CHIPSCOPE => FALSE
)
port map(
-- Clock and Reset Signals
clk => sata_user_clk,
reset => scrambler_reset,
-- ChipScope ILA / Trigger Signals
scrambler_ila_control => scrambler_ila_control,
---------------------------------------
-- Signals from/to Sata Link Layer FIFOs
prim_scrambler => '0',
scrambler_en => scrambler_en,
din_re => scrambler_din_re,
data_in => scrambler_din,
data_out => scrambler_dout,
dout_we => scrambler_dout_we
);
 
---------------------------------------------------------------------------
-- Post-Scramble TX FIFO to PHY Layer
---------------------------------------------------------------------------
-- Input Signals from User Logic
tx_fifo_din <= scrambler_dout;
tx_fifo_we <= scrambler_dout_we;
TX_FIFO: rx_tx_fifo
port map (
clk => sata_user_clk,
rst => sw_reset,
rd_en => tx_fifo_re,
din => tx_fifo_din,
wr_en => tx_fifo_we,
dout => tx_fifo_dout,
almost_empty => tx_fifo_almost_empty,
empty => tx_fifo_empty,
full => tx_fifo_full,
prog_full => tx_fifo_prog_full,
data_count => tx_fifo_data_count
);
 
---------------------------------------------------------------------------
-- Sata Phy Instantiation
---------------------------------------------------------------------------
SATA_PHY_i : sata_phy
port map (
oob_control_ila_control=> oob_control_ila_control,
sata_phy_ila_control => sata_phy_ila_control,
REFCLK_PAD_P_IN => REFCLK_PAD_P_IN ,
REFCLK_PAD_N_IN => REFCLK_PAD_N_IN ,
GTXRESET_IN => GTX_RESET_IN ,
PLLLKDET_OUT_N => PLLLKDET_OUT_N ,
TXP0_OUT => TXP0_OUT,
TXN0_OUT => TXN0_OUT,
RXP0_IN => RXP0_IN ,
RXN0_IN => RXN0_IN ,
DCMLOCKED_OUT => DCMLOCKED_OUT,
LINKUP => LINKUP ,
LINKUP_led => LINKUP_led ,
sata_user_clk => sata_user_clk ,
GEN2_led => GEN2_led_i ,
align_en_out => align_en_out,
tx_datain => tx_dataout,
tx_charisk_in => tx_charisk_out,
rx_dataout => rx_datain,
rx_charisk_out => rx_charisk_in,
CurrentState_out => OOB_state,
rxelecidle_out => rxelecidle,
CLKIN_150 => CLKIN_150
);
sata_user_clk_out <= sata_user_clk;
-----------------------------------------------------------------------------
-- ILA Instantiations
-----------------------------------------------------------------------------
chipscope_gen_ila : if (CHIPSCOPE) generate
SATA_RX_FRAME_ILA_i : sata_rx_frame_ila
port map (
control => sata_rx_frame_ila_control,
clk => sata_user_clk,
trig0 => rx_frame_value,
trig1 => tx_dataout,
trig2 => sync_count_rx,
trig3 => master_fsm_value,
trig4 => rx_charisk_in,
trig5 => OOB_state,
trig6 => rx_datain,
trig7 => rx_fifo_dout,
trig8 => read_fifo_din,
trig9 => read_fifo_dout,
trig10(0) => SOF_det,
trig10(1) => EOF_det,
trig10(2) => X_RDY_det,
trig10(3) => WTRM_det,
trig10(4) => HOLD_start_det,
trig10(5) => HOLD_stop_det,
trig10(6) => SYNC_det,
trig10(7) => CONT_det,
trig10(8) => ALIGN_det,
trig10(9) => new_cmd,
trig10(10) => start_rx,
trig10(11) => rx_done,
trig10(12) => descrambler_dout_we,
trig10(13) => tx_charisk_out,
trig10(14) => sw_reset,
trig10(15) => LINKUP,
trig10(16) => rx_fifo_we_next,
trig10(17) => rx_fifo_re,
trig10(18) => rx_fifo_empty,
trig10(19) => descrambler_reset,
trig10(20) => descrambler_en,
trig10(21) => read_fifo_we,
trig10(22) => read_fifo_re,
trig10(23) => rx_fifo_almost_empty,
trig10(24) => HOLD_det_r,
trig10(25) => ALIGN_det_r,
trig10(26) => TWO_HOLD_det,
trig10(27) => read_fifo_empty_i,
trig10(28) => TWO_HOLD_det_r,
trig10(29) => HOLD_det,
trig10(30) => HOLD_stop_after_ALIGN_det,
trig10(31) => ALIGN_det_r2,
trig11 => dword_count,
trig12 => rx_sector_count,
trig13 => DATA_FIS_dword_count,
trig14 => dword_count_value,
trig15 => dword_count_init_value
);
 
 
SATA_TX_FRAME_ILA_i : sata_tx_frame_ila
port map (
control => sata_tx_frame_ila_control,
clk => sata_user_clk,
trig0 => tx_frame_value,
trig1 => tx_dataout,
trig2 => rx_datain,
trig3 => tx_fifo_dout,
trig4 => master_fsm_value,
trig5 => tx_fifo_din,
trig6 => write_fifo_din,
trig7 => write_fifo_dout,
trig8 => FIS_word_count,
trig9 => scrambler_count,
trig10(0) => tx_fifo_we,
trig10(1) => tx_fifo_re,
trig10(2) => tx_fifo_full,
trig10(3) => align_en_out,
trig10(4) => SYNC_det,
trig10(5) => R_RDY_det,
trig10(6) => R_IP_det,
trig10(7) => R_OK_det,
trig10(8) => R_ERR_det,
trig10(9) => start_tx,
trig10(10) => tx_done,
trig10(11) => tx_fifo_almost_empty,
trig10(12) => tx_charisk_out,
trig10(13) => tx_fifo_empty,
trig10(14) => scrambler_din_re,
trig10(15) => ALIGN_det,
trig10(16) => HOLD_start_det,
trig10(17) => HOLD_stop_det,
trig10(18) => CONT_det,
trig10(19) => write_fifo_prog_full,
trig10(20) => tx_err,
trig10(21) => write_fifo_almost_empty,
trig10(22) => new_cmd,
trig10(23) => scrambler_reset_after_FIS,
trig10(24) => write_fifo_we,
trig10(25) => write_fifo_re,
trig10(26) => write_fifo_empty,
trig10(27) => scrambler_en,
trig10(28) => tx_fifo_prog_full,
trig10(29) => scrambler_count_en_data_fis,
trig10(30) => scrambler_reset,
trig10(31) => crc_en,
trig11 => scrambler_din,
trig12 => crc_dout,
trig13 => tx_sector_count,
trig14 => scrambler_count_value,
trig15 => tx_fifo_data_count
);
 
--trig14 => scrambler_count_init_value,
end generate chipscope_gen_ila;
 
end BEHAV;
/trunk/hdl/vhdl/crc.vhd
0,0 → 1,187
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
----------------------------------------------------------------------------------------
-- ENTITY: crc
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: This sub-module implements the CRC Circuit for the SATA Protocol
-- The code takes 32-bit data word inputs and calculates the CRC for the stream
-- The generator polynomial used is
-- 32 26 23 22 16 12 11 10 8 7 5 4 2
-- G(x) = x + x + x + x + x + x + x + x + x + x + x + x + x + x + 1
-- The CRC value is initialized to 0x52325032 as defined in the Serial ATA
-- specification
-- PORTS:
-----------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity crc is
generic(
CHIPSCOPE : boolean := false
);
port(
-- Clock and Reset Signals
clk : in std_logic;
reset : in std_logic;
-- ChipScope ILA / Trigger Signals
--crc_ila_control : in std_logic_vector(35 downto 0);
---------------------------------------
-- Signals from/to Sata Link Layer
crc_en : in std_logic;
data_in : in std_logic_vector(0 to 31);
data_out : out std_logic_vector(0 to 31)
);
end crc;
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture BEHAV of crc is
 
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant CRC_INIT : std_logic_vector(0 to 31) := x"52325032";
signal crc : std_logic_vector (31 downto 0);
signal crc_next : std_logic_vector (31 downto 0);
signal crc_new : std_logic_vector (31 downto 0);
signal data_out_ila : std_logic_vector (31 downto 0);
 
 
-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin
 
-----------------------------------------------------------------------------
-- PROCESS: CRC_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
CRC_PROC : process (clk)
begin
if ((clk'event) and (clk = '1')) then
if (reset = '1') then
--Initializing internal signals
crc <= CRC_INIT;
elsif (crc_en = '1') then
-- Register all Current Signals to their _next Signals
crc <= crc_next;
else
crc <= crc;
end if;
end if;
end process CRC_PROC ;
 
crc_new <= crc xor data_in;
 
crc_next(31) <= crc_new(31) xor crc_new(30) xor crc_new(29) xor crc_new(28) xor crc_new(27) xor crc_new(25) xor crc_new(24) xor
crc_new(23) xor crc_new(15) xor crc_new(11) xor crc_new(9) xor crc_new(8) xor crc_new(5);
crc_next(30) <= crc_new(30) xor crc_new(29) xor crc_new(28) xor crc_new(27) xor crc_new(26) xor crc_new(24) xor crc_new(23) xor
crc_new(22) xor crc_new(14) xor crc_new(10) xor crc_new(8) xor crc_new(7) xor crc_new(4);
crc_next(29) <= crc_new(31) xor crc_new(29) xor crc_new(28) xor crc_new(27) xor crc_new(26) xor crc_new(25) xor crc_new(23) xor
crc_new(22) xor crc_new(21) xor crc_new(13) xor crc_new(9) xor crc_new(7) xor crc_new(6) xor crc_new(3);
crc_next(28) <= crc_new(30) xor crc_new(28) xor crc_new(27) xor crc_new(26) xor crc_new(25) xor crc_new(24) xor crc_new(22) xor
crc_new(21) xor crc_new(20) xor crc_new(12) xor crc_new(8) xor crc_new(6) xor crc_new(5) xor crc_new(2);
crc_next(27) <= crc_new(29) xor crc_new(27) xor crc_new(26) xor crc_new(25) xor crc_new(24) xor crc_new(23) xor crc_new(21) xor
crc_new(20) xor crc_new(19) xor crc_new(11) xor crc_new(7) xor crc_new(5) xor crc_new(4) xor crc_new(1);
crc_next(26) <= crc_new(31) xor crc_new(28) xor crc_new(26) xor crc_new(25) xor crc_new(24) xor crc_new(23) xor crc_new(22) xor
crc_new(20) xor crc_new(19) xor crc_new(18) xor crc_new(10) xor crc_new(6) xor crc_new(4) xor crc_new(3) xor
crc_new(0);
crc_next(25) <= crc_new(31) xor crc_new(29) xor crc_new(28) xor crc_new(22) xor crc_new(21) xor crc_new(19) xor crc_new(18) xor
crc_new(17) xor crc_new(15) xor crc_new(11) xor crc_new(8) xor crc_new(3) xor crc_new(2);
crc_next(24) <= crc_new(30) xor crc_new(28) xor crc_new(27) xor crc_new(21) xor crc_new(20) xor crc_new(18) xor crc_new(17) xor
crc_new(16) xor crc_new(14) xor crc_new(10) xor crc_new(7) xor crc_new(2) xor crc_new(1);
crc_next(23) <= crc_new(31) xor crc_new(29) xor crc_new(27) xor crc_new(26) xor crc_new(20) xor crc_new(19) xor crc_new(17) xor
crc_new(16) xor crc_new(15) xor crc_new(13) xor crc_new(9) xor crc_new(6) xor crc_new(1) xor crc_new(0);
crc_next(22) <= crc_new(31) xor crc_new(29) xor crc_new(27) xor crc_new(26) xor crc_new(24) xor crc_new(23) xor crc_new(19) xor
crc_new(18) xor crc_new(16) xor crc_new(14) xor crc_new(12) xor crc_new(11) xor crc_new(9) xor crc_new(0);
crc_next(21) <= crc_new(31) xor crc_new(29) xor crc_new(27) xor crc_new(26) xor crc_new(24) xor crc_new(22) xor crc_new(18) xor
crc_new(17) xor crc_new(13) xor crc_new(10) xor crc_new(9) xor crc_new(5);
crc_next(20) <= crc_new(30) xor crc_new(28) xor crc_new(26) xor crc_new(25) xor crc_new(23) xor crc_new(21) xor crc_new(17) xor
crc_new(16) xor crc_new(12) xor crc_new(9) xor crc_new(8) xor crc_new(4);
crc_next(19) <= crc_new(29) xor crc_new(27) xor crc_new(25) xor crc_new(24) xor crc_new(22) xor crc_new(20) xor crc_new(16) xor
crc_new(15) xor crc_new(11) xor crc_new(8) xor crc_new(7) xor crc_new(3);
crc_next(18) <= crc_new(31) xor crc_new(28) xor crc_new(26) xor crc_new(24) xor crc_new(23) xor crc_new(21) xor crc_new(19) xor
crc_new(15) xor crc_new(14) xor crc_new(10) xor crc_new(7) xor crc_new(6) xor crc_new(2);
crc_next(17) <= crc_new(31) xor crc_new(30) xor crc_new(27) xor crc_new(25) xor crc_new(23) xor crc_new(22) xor crc_new(20) xor
crc_new(18) xor crc_new(14) xor crc_new(13) xor crc_new(9) xor crc_new(6) xor crc_new(5) xor crc_new(1);
crc_next(16) <= crc_new(30) xor crc_new(29) xor crc_new(26) xor crc_new(24) xor crc_new(22) xor crc_new(21) xor crc_new(19) xor
crc_new(17) xor crc_new(13) xor crc_new(12) xor crc_new(8) xor crc_new(5) xor crc_new(4) xor crc_new(0);
crc_next(15) <= crc_new(30) xor crc_new(27) xor crc_new(24) xor crc_new(21) xor crc_new(20) xor crc_new(18) xor crc_new(16) xor
crc_new(15) xor crc_new(12) xor crc_new(9) xor crc_new(8) xor crc_new(7) xor crc_new(5) xor crc_new(4) xor
crc_new(3);
crc_next(14) <= crc_new(29) xor crc_new(26) xor crc_new(23) xor crc_new(20) xor crc_new(19) xor crc_new(17) xor crc_new(15) xor
crc_new(14) xor crc_new(11) xor crc_new(8) xor crc_new(7) xor crc_new(6) xor crc_new(4) xor crc_new(3) xor
crc_new(2);
crc_next(13) <= crc_new(31) xor crc_new(28) xor crc_new(25) xor crc_new(22) xor crc_new(19) xor crc_new(18) xor crc_new(16) xor
crc_new(14) xor crc_new(13) xor crc_new(10) xor crc_new(7) xor crc_new(6) xor crc_new(5) xor crc_new(3) xor
crc_new(2) xor crc_new(1);
crc_next(12) <= crc_new(31) xor crc_new(30) xor crc_new(27) xor crc_new(24) xor crc_new(21) xor crc_new(18) xor crc_new(17) xor
crc_new(15) xor crc_new(13) xor crc_new(12) xor crc_new(9) xor crc_new(6) xor crc_new(5) xor crc_new(4) xor
crc_new(2) xor crc_new(1) xor crc_new(0);
crc_next(11) <= crc_new(31) xor crc_new(28) xor crc_new(27) xor crc_new(26) xor crc_new(25) xor crc_new(24) xor crc_new(20) xor
crc_new(17) xor crc_new(16) xor crc_new(15) xor crc_new(14) xor crc_new(12) xor crc_new(9) xor crc_new(4) xor
crc_new(3) xor crc_new(1) xor crc_new(0);
crc_next(10) <= crc_new(31) xor crc_new(29) xor crc_new(28) xor crc_new(26) xor crc_new(19) xor crc_new(16) xor crc_new(14) xor
crc_new(13) xor crc_new(9) xor crc_new(5) xor crc_new(3) xor crc_new(2) xor crc_new(0);
crc_next(9) <= crc_new(29) xor crc_new(24) xor crc_new(23) xor crc_new(18) xor crc_new(13) xor crc_new(12) xor crc_new(11) xor
crc_new(9) xor crc_new(5) xor crc_new(4) xor crc_new(2) xor crc_new(1);
crc_next(8) <= crc_new(31) xor crc_new(28) xor crc_new(23) xor crc_new(22) xor crc_new(17) xor crc_new(12) xor crc_new(11) xor
crc_new(10) xor crc_new(8) xor crc_new(4) xor crc_new(3) xor crc_new(1) xor crc_new(0);
crc_next(7) <= crc_new(29) xor crc_new(28) xor crc_new(25) xor crc_new(24) xor crc_new(23) xor crc_new(22) xor crc_new(21) xor
crc_new(16) xor crc_new(15) xor crc_new(10) xor crc_new(8) xor crc_new(7) xor crc_new(5) xor crc_new(3) xor
crc_new(2) xor crc_new(0);
crc_next(6) <= crc_new(30) xor crc_new(29) xor crc_new(25) xor crc_new(22) xor crc_new(21) xor crc_new(20) xor crc_new(14) xor
crc_new(11) xor crc_new(8) xor crc_new(7) xor crc_new(6) xor crc_new(5) xor crc_new(4) xor crc_new(2) xor
crc_new(1);
crc_next(5) <= crc_new(29) xor crc_new(28) xor crc_new(24) xor crc_new(21) xor crc_new(20) xor crc_new(19) xor crc_new(13) xor
crc_new(10) xor crc_new(7) xor crc_new(6) xor crc_new(5) xor crc_new(4) xor crc_new(3) xor crc_new(1) xor
crc_new(0);
crc_next(4) <= crc_new(31) xor crc_new(30) xor crc_new(29) xor crc_new(25) xor crc_new(24) xor crc_new(20) xor crc_new(19) xor
crc_new(18) xor crc_new(15) xor crc_new(12) xor crc_new(11) xor crc_new(8) xor crc_new(6) xor crc_new(4) xor
crc_new(3) xor crc_new(2) xor crc_new(0);
crc_next(3) <= crc_new(31) xor crc_new(27) xor crc_new(25) xor crc_new(19) xor crc_new(18) xor crc_new(17) xor crc_new(15) xor
crc_new(14) xor crc_new(10) xor crc_new(9) xor crc_new(8) xor crc_new(7) xor crc_new(3) xor crc_new(2) xor
crc_new(1);
crc_next(2) <= crc_new(31) xor crc_new(30) xor crc_new(26) xor crc_new(24) xor crc_new(18) xor crc_new(17) xor crc_new(16) xor
crc_new(14) xor crc_new(13) xor crc_new(9) xor crc_new(8) xor crc_new(7) xor crc_new(6) xor crc_new(2) xor
crc_new(1) xor crc_new(0);
crc_next(1) <= crc_new(28) xor crc_new(27) xor crc_new(24) xor crc_new(17) xor crc_new(16) xor crc_new(13) xor crc_new(12) xor
crc_new(11) xor crc_new(9) xor crc_new(7) xor crc_new(6) xor crc_new(1) xor crc_new(0);
crc_next(0) <= crc_new(31) xor crc_new(30) xor crc_new(29) xor crc_new(28) xor crc_new(26) xor crc_new(25) xor crc_new(24) xor
crc_new(16) xor crc_new(12) xor crc_new(10) xor crc_new(9) xor crc_new(6) xor crc_new(0);
 
 
data_out_ila <= crc_next;
--data_out_ila <= crc;
 
-----------------------------------------------------------------------------
-- ILA Instantiation
-----------------------------------------------------------------------------
data_out <= data_out_ila;
 
end BEHAV;
 
 
/trunk/hdl/vhdl/scrambler.vhd
0,0 → 1,191
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
----------------------------------------------------------------------------------------
-- ENTITY: scrambler
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: This sub-module implements the Scrambler Circuit for the SATA Protocol
-- The code provides a parallel implementation of the following
-- generator polynomial
-- 16 15 13 4
-- G(x) = x + x + x + x + 1
-- The output of this scrambler is then XORed with the input data DWORD
-- The scrambler is initialized to a value of 0xF0F6.
-- The first DWORD output of the implementation is equal to 0xC2D2768D
-- PORTS:
-----------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity scrambler is
generic(
CHIPSCOPE : boolean := false
);
port(
-- Clock and Reset Signals
clk : in std_logic;
reset : in std_logic;
-- ChipScope ILA / Trigger Signals
scrambler_ila_control : in std_logic_vector(35 downto 0);
---------------------------------------
-- Signals from/to Sata Link Layer
scrambler_en : in std_logic;
prim_scrambler : in std_logic;
din_re : out std_logic;
data_in : in std_logic_vector(0 to 31);
data_out : out std_logic_vector(0 to 31);
dout_we : out std_logic
);
end scrambler;
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture BEHAV of scrambler is
 
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant SCRAMBLER_INIT : std_logic_vector(0 to 15) := x"F0F6";
signal context : std_logic_vector (15 downto 0);
signal context_next : std_logic_vector (31 downto 0);
signal context_reg : std_logic_vector (31 downto 0);
signal data_out_ila : std_logic_vector (31 downto 0);
signal dout_we_reg : std_logic;
signal dout_we_ila : std_logic;
signal din_re_ila : std_logic;
 
-----------------------------------------------------------------------------
-- ILA Declaration
-----------------------------------------------------------------------------
component scrambler_ila
port (
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(31 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(15 downto 0);
trig5 : in std_logic_vector(3 downto 0)
);
end component;
 
-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin
 
-----------------------------------------------------------------------------
-- PROCESS: SCRAMBLER_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
SCRAMBLER_PROC : process (clk)
begin
if ((clk'event) and (clk = '1')) then
if (reset = '1') then
--Initializing internal signals
context <= SCRAMBLER_INIT;
context_reg <= (others => '0');
dout_we_reg <= '0';
elsif (scrambler_en = '1') then
-- Register all Current Signals to their _next Signals
context <= context_next(31 downto 16);
context_reg <= context_next;
dout_we_reg <= '1';
else
context <= context;
context_reg <= context_reg;
dout_we_reg <= '0';
end if;
end if;
end process SCRAMBLER_PROC ;
 
context_next(31) <= context(12) xor context(10) xor context(7) xor context(3) xor context(1) xor context(0);
context_next(30) <= context(15) xor context(14) xor context(12) xor context(11) xor context(9) xor context(6) xor context(3) xor context(2) xor context(0);
context_next(29) <= context(15) xor context(13) xor context(12) xor context(11) xor context(10) xor context(8) xor context(5) xor context(3) xor context(2) xor context(1);
context_next(28) <= context(14) xor context(12) xor context(11) xor context(10) xor context(9) xor context(7) xor context(4) xor context(2) xor context(1) xor context(0);
context_next(27) <= context(15) xor context(14) xor context(13) xor context(12) xor context(11) xor context(10) xor context(9) xor context(8) xor context(6) xor context(1) xor context(0);
context_next(26) <= context(15) xor context(13) xor context(11) xor context(10) xor context(9) xor context(8) xor context(7) xor context(5) xor context(3) xor context(0);
context_next(25) <= context(15) xor context(10) xor context(9) xor context(8) xor context(7) xor context(6) xor context(4) xor context(3) xor context(2);
context_next(24) <= context(14) xor context(9) xor context(8) xor context(7) xor context(6) xor context(5) xor context(3) xor context(2) xor context(1);
context_next(23) <= context(13) xor context(8) xor context(7) xor context(6) xor context(5) xor context(4) xor context(2) xor context(1) xor context(0);
context_next(22) <= context(15) xor context(14) xor context(7) xor context(6) xor context(5) xor context(4) xor context(1) xor context(0);
context_next(21) <= context(15) xor context(13) xor context(12) xor context(6) xor context(5) xor context(4) xor context(0);
context_next(20) <= context(15) xor context(11) xor context(5) xor context(4);
context_next(19) <= context(14) xor context(10) xor context(4) xor context(3);
context_next(18) <= context(13) xor context(9) xor context(3) xor context(2);
context_next(17) <= context(12) xor context(8) xor context(2) xor context(1);
context_next(16) <= context(11) xor context(7) xor context(1) xor context(0);
context_next(15) <= context(15) xor context(14) xor context(12) xor context(10) xor context(6) xor context(3) xor context(0);
context_next(14) <= context(15) xor context(13) xor context(12) xor context(11) xor context(9) xor context(5) xor context(3) xor context(2);
context_next(13) <= context(14) xor context(12) xor context(11) xor context(10) xor context(8) xor context(4) xor context(2) xor context(1);
context_next(12) <= context(13) xor context(11) xor context(10) xor context(9) xor context(7) xor context(3) xor context(1) xor context(0);
context_next(11) <= context(15) xor context(14) xor context(10) xor context(9) xor context(8) xor context(6) xor context(3) xor context(2) xor context(0);
context_next(10) <= context(15) xor context(13) xor context(12) xor context(9) xor context(8) xor context(7) xor context(5) xor context(3) xor context(2) xor context(1);
context_next(9) <= context(14) xor context(12) xor context(11) xor context(8) xor context(7) xor context(6) xor context(4) xor context(2) xor context(1) xor context(0);
context_next(8) <= context(15) xor context(14) xor context(13) xor context(12) xor context(11) xor context(10) xor context(7) xor context(6) xor context(5) xor context(1) xor context(0);
context_next(7) <= context(15) xor context(13) xor context(11) xor context(10) xor context(9) xor context(6) xor context(5) xor context(4) xor context(3) xor context(0);
context_next(6) <= context(15) xor context(10) xor context(9) xor context(8) xor context(5) xor context(4) xor context(2);
context_next(5) <= context(14) xor context(9) xor context(8) xor context(7) xor context(4) xor context(3) xor context(1);
context_next(4) <= context(13) xor context(8) xor context(7) xor context(6) xor context(3) xor context(2) xor context(0);
context_next(3) <= context(15) xor context(14) xor context(7) xor context(6) xor context(5) xor context(3) xor context(2) xor context(1);
context_next(2) <= context(14) xor context(13) xor context(6) xor context(5) xor context(4) xor context(2) xor context(1) xor context(0);
context_next(1) <= context(15) xor context(14) xor context(13) xor context(5) xor context(4) xor context(1) xor context(0);
context_next(0) <= context(15) xor context(13) xor context(4) xor context(0);
 
data_out_ila <= (context_reg xor data_in) when prim_scrambler = '0' else (context_reg);
 
--dout_we_ila <= dout_we_reg when scrambler_en = '1' else '0';
dout_we_ila <= dout_we_reg;
 
din_re_ila <= '1' when scrambler_en = '1' else '0';
-----------------------------------------------------------------------------
-- ILA Instantiation
-----------------------------------------------------------------------------
data_out <= data_out_ila;
dout_we <= dout_we_ila;
din_re <= din_re_ila;
 
chipscope_gen_ila : if (CHIPSCOPE) generate
SCRAMBLER_ILA_i : scrambler_ila
port map (
control => scrambler_ila_control,
clk => clk,
trig0 => data_in,
trig1 => data_out_ila,
trig2 => context_reg,
trig3 => context_next,
trig4 => context,
trig5(0) => scrambler_en,
trig5(1) => din_re_ila,
trig5(2) => dout_we_ila,
trig5(3) => reset
);
end generate chipscope_gen_ila;
end BEHAV;
 
 
/trunk/hdl/vhdl/command_layer.vhd
0,0 → 1,499
-- Copyright (C) 2012
-- Ashwin A. Mendon
--
-- This file is part of SATA2 core.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
----------------------------------------------------------------------------------------
-- ENTITY: command_layer
-- Version: 1.0
-- Author: Ashwin Mendon
-- Description: This sub-module implements the Command Layer of the SATA Protocol
-- The User Command parameters such as: cmd_type, sector_address, sector_count
-- are encoded into a command FIS according to the ATA format and passed to
-- the Transport Layer.
--
-- PORTS:
-----------------------------------------------------------------------------------------
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
 
entity command_layer is
generic(
CHIPSCOPE : boolean := false
);
port(
-- Clock and Reset Signals
clk : in std_logic;
sw_reset : in std_logic;
-- ChipScope ILA / Trigger Signals
cmd_layer_ila_control : in std_logic_vector(35 downto 0);
---------------------------------------
-- Signals from/to User Logic
new_cmd : in std_logic;
cmd_done : out std_logic;
cmd_type : in std_logic_vector(1 downto 0);
sector_count : in std_logic_vector(31 downto 0);
sector_addr : in std_logic_vector(31 downto 0);
user_din : in std_logic_vector(31 downto 0);
user_din_re_out : out std_logic;
user_dout : out std_logic_vector(31 downto 0);
user_dout_re : in std_logic;
user_fifo_empty : in std_logic;
user_fifo_full : in std_logic;
sector_timer_out : out std_logic_vector(31 downto 0);
-- Signals from/to Link Layer
write_fifo_full : in std_logic;
ll_ready_for_cmd : in std_logic;
ll_cmd_start : out std_logic;
ll_cmd_type : out std_logic_vector(1 downto 0);
ll_dout : out std_logic_vector(31 downto 0);
ll_dout_we : out std_logic;
ll_din : in std_logic_vector(31 downto 0);
ll_din_re : out std_logic
);
end command_layer;
 
-------------------------------------------------------------------------------
-- ARCHITECTURE
-------------------------------------------------------------------------------
architecture BEHAV of command_layer is
 
-------------------------------------------------------------------------------
-- COMMAND LAYER
-------------------------------------------------------------------------------
constant READ_DMA : std_logic_vector(7 downto 0) := x"25";
constant WRITE_DMA : std_logic_vector(7 downto 0) := x"35";
constant REG_FIS_VALUE : std_logic_vector(7 downto 0) := x"27";
constant DATA_FIS_VALUE : std_logic_vector(7 downto 0) := x"46";
constant DEVICE_REG : std_logic_vector(7 downto 0) := x"E0";
constant FEATURES : std_logic_vector(7 downto 0) := x"00";
constant READ_DMA_CMD : std_logic_vector(1 downto 0) := "01";
constant WRITE_DMA_CMD : std_logic_vector(1 downto 0) := "10";
constant DATA_FIS_HEADER : std_logic_vector(31 downto 0) := x"00000046";
constant NDWORDS_PER_DATA_FIS : std_logic_vector(15 downto 0) := conv_std_logic_vector(2048, 16);--128*16
constant SECTOR_NDWORDS : integer := 128; -- 128 DWORDS / 512 Byte Sector
 
component cmd_layer_ila
port (
control : in std_logic_vector(35 downto 0);
clk : in std_logic;
trig0 : in std_logic_vector(3 downto 0);
trig1 : in std_logic_vector(31 downto 0);
trig2 : in std_logic_vector(31 downto 0);
trig3 : in std_logic_vector(31 downto 0);
trig4 : in std_logic_vector(31 downto 0);
trig5 : in std_logic_vector(1 downto 0);
trig6 : in std_logic_vector(1 downto 0);
trig7 : in std_logic_vector(31 downto 0);
trig8 : in std_logic_vector(31 downto 0);
trig9 : in std_logic_vector(23 downto 0);
trig10 : in std_logic_vector(15 downto 0);
trig11 : in std_logic_vector(11 downto 0);
trig12 : in std_logic_vector(15 downto 0);
trig13 : in std_logic_vector(31 downto 0)
);
end component;
 
 
-----------------------------------------------------------------------------
-- Finite State Machine Declaration (curr and next states)
-----------------------------------------------------------------------------
type COMMAND_FSM_TYPE is (wait_for_cmd, build_REG_FIS, send_REG_FIS_DW1,
send_REG_FIS_DW2, send_REG_FIS_DW3, send_REG_FIS_DW4, send_REG_FIS_DW5,
send_DATA_FIS_HEADER, send_write_data, send_cmd_start, wait_for_cmd_start,
wait_for_cmd_done, dead
);
signal command_fsm_curr, command_fsm_next : COMMAND_FSM_TYPE := wait_for_cmd;
signal command_fsm_value : std_logic_vector (0 to 3);
signal ll_cmd_start_next : std_logic;
signal ll_cmd_start_out : std_logic;
signal cmd_done_next : std_logic;
signal cmd_done_out : std_logic;
signal read_fifo_empty : std_logic;
signal ll_dout_next : std_logic_vector(0 to 31);
signal ll_dout_we_next : std_logic;
signal ll_dout_out : std_logic_vector(0 to 31);
signal ll_dout_we_out : std_logic;
signal ll_cmd_type_next : std_logic_vector(0 to 1);
signal ll_cmd_type_out : std_logic_vector(0 to 1);
signal dword_count : std_logic_vector(0 to 15);
signal dword_count_next : std_logic_vector(0 to 15);
signal write_data_count : std_logic_vector(0 to 31);
signal write_data_count_next : std_logic_vector(0 to 31);
signal user_din_re : std_logic;
signal sector_count_int : integer;
 
--- ILA signals ----
signal user_dout_ila : std_logic_vector(0 to 31);
signal ll_din_re_ila : std_logic;
 
--- Timer ----
signal sector_timer : std_logic_vector(31 downto 0);
--signal sata_timer : std_logic_vector(31 downto 0);
 
type reg_fis_type is
record
FIS_type : std_logic_vector(7 downto 0);
pad_8 : std_logic_vector(7 downto 0);
command : std_logic_vector(7 downto 0);
features : std_logic_vector(7 downto 0);
LBA : std_logic_vector(23 downto 0);
device : std_logic_vector(7 downto 0);
LBA_exp : std_logic_vector(23 downto 0);
features_exp : std_logic_vector(7 downto 0);
sector_count : std_logic_vector(15 downto 0);
pad_16 : std_logic_vector(15 downto 0);
pad_32 : std_logic_vector(31 downto 0);
end record;
 
signal reg_fis : reg_fis_type;
signal reg_fis_next : reg_fis_type;
 
-------------------------------------------------------------------------------
-- BEGIN
-------------------------------------------------------------------------------
begin
 
-------------------------------------------------------------------------------
-- LINK LAYER
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- PROCESS: COMMAND_FSM_VALUE_PROC
-- PURPOSE: ChipScope State Indicator Signal
-----------------------------------------------------------------------------
COMMAND_FSM_VALUE_PROC : process (command_fsm_curr) is
begin
case (command_fsm_curr) is
when wait_for_cmd => command_fsm_value <= x"0";
when build_REG_FIS => command_fsm_value <= x"1";
when send_REG_FIS_DW1 => command_fsm_value <= x"2";
when send_REG_FIS_DW2 => command_fsm_value <= x"3";
when send_REG_FIS_DW3 => command_fsm_value <= x"4";
when send_REG_FIS_DW4 => command_fsm_value <= x"5";
when send_REG_FIS_DW5 => command_fsm_value <= x"6";
when send_DATA_FIS_HEADER => command_fsm_value <= x"7";
when send_write_data => command_fsm_value <= x"8";
when send_cmd_start => command_fsm_value <= x"9";
when wait_for_cmd_start => command_fsm_value <= x"A";
when wait_for_cmd_done => command_fsm_value <= x"B";
when dead => command_fsm_value <= x"C";
when others => command_fsm_value <= x"D";
end case;
end process COMMAND_FSM_VALUE_PROC;
-----------------------------------------------------------------------------
-- PROCESS: COMMAND_FSM_STATE_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
COMMAND_FSM_STATE_PROC: process (clk)
begin
if ((clk'event) and (clk = '1')) then
if (sw_reset = '1') then
--Initializing internal signals
command_fsm_curr <= wait_for_cmd;
cmd_done_out <= '0';
ll_cmd_start_out <= '0';
ll_dout_we_out <= '0';
ll_dout_out <= (others => '0');
ll_cmd_type_out <= (others => '0');
write_data_count <= (others => '0');
dword_count <= (others => '0');
reg_fis.FIS_type <= (others => '0');
reg_fis.pad_8 <= (others => '0');
reg_fis.command <= (others => '0');
reg_fis.features <= (others => '0');
reg_fis.LBA <= (others => '0');
reg_fis.device <= (others => '0');
reg_fis.LBA_exp <= (others => '0');
reg_fis.features_exp <= (others => '0');
reg_fis.sector_count <= (others => '0');
reg_fis.pad_16 <= (others => '0');
reg_fis.pad_32 <= (others => '0');
else
-- Register all Current Signals to their _next Signals
command_fsm_curr <= command_fsm_next;
cmd_done_out <= cmd_done_next;
ll_cmd_start_out <= ll_cmd_start_next;
ll_dout_we_out <= ll_dout_we_next;
ll_dout_out <= ll_dout_next;
ll_cmd_type_out <= ll_cmd_type_next;
dword_count <= dword_count_next;
write_data_count <= write_data_count_next;
reg_fis.FIS_type <= reg_fis_next.FIS_type ;
reg_fis.pad_8 <= reg_fis_next.pad_8;
reg_fis.command <= reg_fis_next.command;
reg_fis.features <= reg_fis_next.features;
reg_fis.LBA <= reg_fis_next.LBA;
reg_fis.device <= reg_fis_next.device;
reg_fis.LBA_exp <= reg_fis_next.LBA_exp;
reg_fis.features_exp <= reg_fis_next.features_exp;
reg_fis.sector_count <= reg_fis_next.sector_count;
reg_fis.pad_16 <= reg_fis_next.pad_16;
reg_fis.pad_32 <= reg_fis_next.pad_32;
end if;
end if;
end process COMMAND_FSM_STATE_PROC;
 
-----------------------------------------------------------------------------
-- PROCESS: COMMAND_FSM_LOGIC_PROC
-- PURPOSE: Registering Signals and Next State
-----------------------------------------------------------------------------
COMMAND_FSM_LOGIC_PROC : process (command_fsm_curr, new_cmd, cmd_type,
ll_cmd_start_out, ll_dout_we_out,
ll_dout_out, dword_count, write_data_count
) is
begin
-- Register _next to current signals
command_fsm_next <= command_fsm_curr;
cmd_done_next <= cmd_done_out;
ll_cmd_start_next <= ll_cmd_start_out;
ll_dout_we_next <= ll_dout_we_out;
ll_dout_next <= ll_dout_out;
ll_cmd_type_next <= cmd_type;
user_din_re <= '0';
dword_count_next <= dword_count;
write_data_count_next <= write_data_count;
reg_fis_next.FIS_type <= reg_fis.FIS_type ;
reg_fis_next.pad_8 <= reg_fis.pad_8;
reg_fis_next.command <= reg_fis.command;
reg_fis_next.features <= reg_fis.features;
reg_fis_next.LBA <= reg_fis.LBA;
reg_fis_next.device <= reg_fis.device;
reg_fis_next.LBA_exp <= reg_fis.LBA_exp;
reg_fis_next.features_exp <= reg_fis.features_exp;
reg_fis_next.sector_count <= reg_fis.sector_count;
reg_fis_next.pad_16 <= reg_fis.pad_16;
reg_fis_next.pad_32 <= reg_fis.pad_32;
 
---------------------------------------------------------------------------
-- Finite State Machine
---------------------------------------------------------------------------
case (command_fsm_curr) is
-- x0
when wait_for_cmd =>
cmd_done_next <= '1';
ll_cmd_start_next <= '0';
ll_dout_we_next <= '0';
ll_dout_next <= (others => '0');
if (new_cmd = '1') then
cmd_done_next <= '0';
command_fsm_next <= build_REG_FIS;
end if;
 
-- x1
when build_REG_FIS =>
reg_fis_next.FIS_type <= REG_FIS_VALUE;
reg_fis_next.pad_8 <= x"80";
if (cmd_type = READ_DMA_CMD) then
reg_fis_next.command <= READ_DMA;
else
reg_fis_next.command <= WRITE_DMA;
end if;
reg_fis_next.features <= FEATURES;
reg_fis_next.LBA <= sector_addr(23 downto 0);
reg_fis_next.device <= DEVICE_REG;
reg_fis_next.LBA_exp <= (others => '0');
reg_fis_next.features_exp <= FEATURES;
reg_fis_next.sector_count <= sector_count(15 downto 0);
reg_fis_next.pad_16 <= (others => '0');
reg_fis_next.pad_32 <= (others => '0');
command_fsm_next <= send_REG_FIS_DW1;
 
-- x2
when send_REG_FIS_DW1 =>
ll_dout_next <= reg_fis.FEATURES & reg_fis.command & reg_fis.pad_8 & reg_fis.FIS_type;
ll_dout_we_next <= '1';
command_fsm_next <= send_REG_FIS_DW2;
-- x3
when send_REG_FIS_DW2 =>
ll_dout_next <= reg_fis.device & reg_fis.LBA;
ll_dout_we_next <= '1';
command_fsm_next <= send_REG_FIS_DW3;
-- x4
when send_REG_FIS_DW3 =>
ll_dout_next <= reg_fis.features_exp & reg_fis.LBA_exp;
ll_dout_we_next <= '1';
command_fsm_next <= send_REG_FIS_DW4;
-- x5
when send_REG_FIS_DW4 =>
ll_dout_next <= reg_fis.pad_16 & reg_fis.sector_count ;
ll_dout_we_next <= '1';
command_fsm_next <= send_REG_FIS_DW5;
-- x6
when send_REG_FIS_DW5 =>
ll_dout_next <= reg_fis.pad_32;
ll_dout_we_next <= '1';
command_fsm_next <= send_cmd_start;
 
-- x7
when send_DATA_FIS_HEADER =>
if (user_fifo_full = '1') then
ll_dout_next <= DATA_FIS_HEADER;
ll_dout_we_next <= '1';
command_fsm_next <= send_write_data;
end if;
 
-- x8
when send_write_data =>
if(dword_count >= NDWORDS_PER_DATA_FIS) then
user_din_re <= '0';
ll_dout_we_next <= '0';
ll_dout_next <= (others => '0');
dword_count_next <= (others => '0');
command_fsm_next <= send_DATA_FIS_HEADER;
elsif (write_fifo_full = '1' or user_fifo_empty = '1') then
user_din_re <= '0';
ll_dout_we_next <= '0';
ll_dout_next <= (others => '0');
else
write_data_count_next <= write_data_count + 1;
dword_count_next <= dword_count + 1;
user_din_re <= '1';
ll_dout_next <= user_din;
ll_dout_we_next <= '1';
end if;
 
if (write_data_count = (SECTOR_NDWORDS*sector_count_int)) then
write_data_count_next <= (others => '0');
dword_count_next <= (others => '0');
user_din_re <= '0';
ll_dout_we_next <= '0';
ll_dout_next <= (others => '0');
command_fsm_next <= wait_for_cmd_done;
end if;
-- x9
when send_cmd_start =>
ll_dout_we_next <= '0';
ll_dout_next <= (others => '0');
if (ll_ready_for_cmd = '1') then
ll_cmd_start_next <= '1';
command_fsm_next <= wait_for_cmd_start;
end if;
 
-- xA
when wait_for_cmd_start =>
ll_cmd_start_next <= '0';
if (ll_ready_for_cmd = '0') then
if (cmd_type = READ_DMA_CMD) then
command_fsm_next <= wait_for_cmd_done;
else
command_fsm_next <= send_DATA_FIS_HEADER;
end if;
end if;
 
-- xB
when wait_for_cmd_done =>
if (ll_ready_for_cmd = '1') then
cmd_done_next <= '1';
command_fsm_next <= wait_for_cmd;
end if;
-- xC
when dead =>
command_fsm_next <= dead;
 
-- xD
when others =>
command_fsm_next <= dead;
 
end case;
end process COMMAND_FSM_LOGIC_PROC;
 
cmd_done <= cmd_done_out;
ll_cmd_start <= ll_cmd_start_out;
ll_cmd_type <= ll_cmd_type_out;
 
user_din_re_out <= user_din_re;
user_dout_ila <= ll_din;
user_dout <= user_dout_ila;
ll_dout <= ll_dout_out;
ll_dout_we <= ll_dout_we_out;
ll_din_re_ila <= user_dout_re;
ll_din_re <= ll_din_re_ila;
 
sector_count_int <= conv_integer(sector_count);
 
-----------------------------------------------------------------------------
-- PROCESS: TIMER PROCESS
-- PURPOSE: Count time to read a sector
-----------------------------------------------------------------------------
TIMER_PROC: process (clk)
begin
if ((clk'event) and (clk = '1')) then
if (sw_reset = '1') then
sector_timer <= (others => '0');
-- sata_timer <= (others => '0');
--elsif ((command_fsm_curr = wait_for_cmd_done) and (ready_for_cmd = '1')) then
--sata_timer <= sata_timer + sector_timer;
elsif (command_fsm_curr = wait_for_cmd) then
if (new_cmd = '1') then
sector_timer <= (others => '0');
else
sector_timer <= sector_timer;
end if;
else
sector_timer <= sector_timer + '1';
end if;
end if;
end process TIMER_PROC;
sector_timer_out <= sector_timer;
 
 
chipscope_gen_ila : if (CHIPSCOPE) generate
CMD_LAYER_ILA_i : cmd_layer_ila
port map (
control => cmd_layer_ila_control,
clk => clk,
trig0 => command_fsm_value,
trig1 => user_din,
trig2 => user_dout_ila,
trig3 => ll_din,
trig4 => ll_dout_out,
trig5 => cmd_type,
trig6 => ll_cmd_type_out,
trig7 => sector_timer,
trig8 => sector_addr,
trig9 => reg_fis.LBA,
trig10 => reg_fis.sector_count,
trig11(0) => new_cmd,
trig11(1) => user_din_re,
trig11(2) => user_dout_re,
trig11(3) => ll_ready_for_cmd,
trig11(4) => ll_cmd_start_out,
trig11(5) => ll_dout_we_out,
trig11(6) => ll_din_re_ila,
trig11(7) => cmd_done_out,
trig11(8) => '0',
trig11(9) => write_fifo_full,
trig11(10) => user_fifo_empty,
trig11(11) => user_fifo_full,
trig12 => dword_count,
trig13 => write_data_count
);
end generate chipscope_gen_ila;
end BEHAV;
/trunk/syn/sata_core.scr
0,0 → 1,12
run
-opt_mode speed
-netlist_hierarchy as_optimized
-opt_level 1
-p xc6vlx240tff1156-1
-ifn sata_core.prj
-ifmt mixed
-ram_style BLOCK
-ofn sata_core.ngc
-iobuf YES
-sd {../netlist}
-top sata_core
/trunk/syn/sata_core.prj
0,0 → 1,13
verilog work "../hdl/verilog/sata_gtx.v"
verilog work "../hdl/verilog/sata_gtx_dual.v"
verilog work "../hdl/verilog/mgt_usrclk_source_mmcm.v"
verilog work "../hdl/verilog/mux_21.v"
verilog work "../hdl/verilog/mux_41.v"
verilog work "../hdl/verilog/oob_control.v"
verilog work "../hdl/verilog/sata_phy.v"
vhdl work ../hdl/vhdl/mux_161.vhd
vhdl work ../hdl/vhdl/crc.vhd
vhdl work ../hdl/vhdl/scrambler.vhd
vhdl work ../hdl/vhdl/sata_link_layer.vhd
vhdl work ../hdl/vhdl/command_layer.vhd
vhdl work ../hdl/vhdl/sata_core.vhd
/trunk/syn/.lso
0,0 → 1,13
work
trunk/syn/.lso Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/syn/Makefile =================================================================== --- trunk/syn/Makefile (nonexistent) +++ trunk/syn/Makefile (revision 2) @@ -0,0 +1,45 @@ +PROJECT=sata_core +COMPONENT=sata_core +DEVICE=xc6vlx240tff1156-1 +XST_PRJ=$(PROJECT).scr +XST_SRP=$(PROJECT).srp + +SYNTHESIS=$(COMPONENT).ngc +NGDBUILD=$(COMPONENT).ngd +MAP=$(COMPONENT)_map.ncd +PAR=$(COMPONENT).ncd +BITS=$(COMPONENT).bit + +#netlist: $(NETLIST) +synthesis: $(SYNTHESIS) +ngdbuild: $(NGDBUILD) +map: $(MAP) +par: $(PAR) +bits: $(BITS) + +#$(NETLIST): +# make ../netlist/ + +$(SYNTHESIS): + xst -ifn $(XST_PRJ) -ofn $(XST_SRP) + +$(NGDBUILD): + ngdbuild -p $(DEVICE) -sd ../netlist -uc ../ucf/$(COMPONENT).ucf $(COMPONENT).ngc + +$(MAP): + map -o sata_core_map.ncd -pr b -ol high -timing -xe n -global_opt on $(COMPONENT).ngd $(COMPONENT).pcf + +$(PAR): + par -w -ol high sata_core_map.ncd $(COMPONENT).ncd $(COMPONENT).pcf + +$(BITS): + bitgen -w -f ../etc/bitgen.ut $(COMPONENT) + +clean: + rm -rf $(COMPONENT).lso $(COMPONENT).ngc $(COMPONENT).ngc_xst.xrpt $(PROJECT).ngr $(XST_SRP) _xmsgs *.xrpt *.lst *.ngo *.bld *.log *.xpi xlnx_auto_0.ise xlnx_auto_0_xdb xst *~ + rm -rf $(COMPONENT).ngd + rm -rf $(COMPONENT)_map.ncd $(COMPONENT)_map.map $(COMPONENT)_map.mrp $(COMPONENT)_map.ngm $(COMPONENT)_map.psr + rm -rf $(COMPONENT)_pad.csv $(COMPONENT)_pad.txt + rm -rf $(COMPONENT).ncd $(COMPONENT).pad $(COMPONENT).par $(COMPONENT).pcf $(COMPONENT).ptwx $(COMPONENT).unroutes $(COMPONENT).drc $(COMPONENT).bgn + rm -rf $(COMPONENT).bit + rm -rf *.xml *.html *.xwbt Index: trunk/etc/bitgen.ut =================================================================== --- trunk/etc/bitgen.ut (nonexistent) +++ trunk/etc/bitgen.ut (revision 2) @@ -0,0 +1,14 @@ +-g TdoPin:PULLNONE +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +-g Persist:No + Index: trunk/COPYING3 =================================================================== --- trunk/COPYING3 (nonexistent) +++ trunk/COPYING3 (revision 2) @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. If such problems arise substantially in other domains, we +stand ready to extend this provision to those domains in future versions +of the GPL, as needed to protect the freedom of users. + + Finally, every program is threatened constantly by software patents. +States should not allow patents to restrict development and use of +software on general-purpose computers, but in those that do, we wish to +avoid the special danger that patents applied to a free program could +make it effectively proprietary. To prevent this, the GPL assures that +patents cannot be used to render the program non-free. + + The precise terms and conditions for copying, distribution and +modification follow. + + TERMS AND CONDITIONS + + 0. Definitions. + + "This License" refers to version 3 of the GNU General Public License. + + "Copyright" also means copyright-like laws that apply to other kinds of +works, such as semiconductor masks. + + "The Program" refers to any copyrightable work licensed under this +License. Each licensee is addressed as "you". "Licensees" and +"recipients" may be individuals or organizations. + + To "modify" a work means to copy from or adapt all or part of the work +in a fashion requiring copyright permission, other than the making of an +exact copy. The resulting work is called a "modified version" of the +earlier work or a work "based on" the earlier work. + + A "covered work" means either the unmodified Program or a work based +on the Program. + + To "propagate" a work means to do anything with it that, without +permission, would make you directly or secondarily liable for +infringement under applicable copyright law, except executing it on a +computer or modifying a private copy. Propagation includes copying, +distribution (with or without modification), making available to the +public, and in some countries other activities as well. + + To "convey" a work means any kind of propagation that enables other +parties to make or receive copies. Mere interaction with a user through +a computer network, with no transfer of a copy, is not conveying. + + An interactive user interface displays "Appropriate Legal Notices" +to the extent that it includes a convenient and prominently visible +feature that (1) displays an appropriate copyright notice, and (2) +tells the user that there is no warranty for the work (except to the +extent that warranties are provided), that licensees may convey the +work under this License, and how to view a copy of this License. If +the interface presents a list of user commands or options, such as a +menu, a prominent item in the list meets this criterion. + + 1. Source Code. + + The "source code" for a work means the preferred form of the work +for making modifications to it. "Object code" means any non-source +form of a work. + + A "Standard Interface" means an interface that either is an official +standard defined by a recognized standards body, or, in the case of +interfaces specified for a particular programming language, one that +is widely used among developers working in that language. + + The "System Libraries" of an executable work include anything, other +than the work as a whole, that (a) is included in the normal form of +packaging a Major Component, but which is not part of that Major +Component, and (b) serves only to enable use of the work with that +Major Component, or to implement a Standard Interface for which an +implementation is available to the public in source code form. A +"Major Component", in this context, means a major essential component +(kernel, window system, and so on) of the specific operating system +(if any) on which the executable work runs, or a compiler used to +produce the work, or an object code interpreter used to run it. + + The "Corresponding Source" for a work in object code form means all +the source code needed to generate, install, and (for an executable +work) run the object code and to modify the work, including scripts to +control those activities. However, it does not include the work's +System Libraries, or general-purpose tools or generally available free +programs which are used unmodified in performing those activities but +which are not part of the work. For example, Corresponding Source +includes interface definition files associated with source files for +the work, and the source code for shared libraries and dynamically +linked subprograms that the work is specifically designed to require, +such as by intimate data communication or control flow between those +subprograms and other parts of the work. + + The Corresponding Source need not include anything that users +can regenerate automatically from other parts of the Corresponding +Source. + + The Corresponding Source for a work in source code form is that +same work. + + 2. Basic Permissions. + + All rights granted under this License are granted for the term of +copyright on the Program, and are irrevocable provided the stated +conditions are met. This License explicitly affirms your unlimited +permission to run the unmodified Program. The output from running a +covered work is covered by this License only if the output, given its +content, constitutes a covered work. This License acknowledges your +rights of fair use or other equivalent, as provided by copyright law. + + You may make, run and propagate covered works that you do not +convey, without conditions so long as your license otherwise remains +in force. You may convey covered works to others for the sole purpose +of having them make modifications exclusively for you, or provide you +with facilities for running those works, provided that you comply with +the terms of this License in conveying all material for which you do +not control copyright. Those thus making or running the covered works +for you must do so exclusively on your behalf, under your direction +and control, on terms that prohibit them from making any copies of +your copyrighted material outside their relationship with you. + + Conveying under any other circumstances is permitted solely under +the conditions stated below. Sublicensing is not allowed; section 10 +makes it unnecessary. + + 3. Protecting Users' Legal Rights From Anti-Circumvention Law. + + No covered work shall be deemed part of an effective technological +measure under any applicable law fulfilling obligations under article +11 of the WIPO copyright treaty adopted on 20 December 1996, or +similar laws prohibiting or restricting circumvention of such +measures. + + When you convey a covered work, you waive any legal power to forbid +circumvention of technological measures to the extent such circumvention +is effected by exercising rights under this License with respect to +the covered work, and you disclaim any intention to limit operation or +modification of the work as a means of enforcing, against the work's +users, your or third parties' legal rights to forbid circumvention of +technological measures. + + 4. Conveying Verbatim Copies. + + You may convey verbatim copies of the Program's source code as you +receive it, in any medium, provided that you conspicuously and +appropriately publish on each copy an appropriate copyright notice; +keep intact all notices stating that this License and any +non-permissive terms added in accord with section 7 apply to the code; +keep intact all notices of the absence of any warranty; and give all +recipients a copy of this License along with the Program. + + You may charge any price or no price for each copy that you convey, +and you may offer support or warranty protection for a fee. + + 5. Conveying Modified Source Versions. + + You may convey a work based on the Program, or the modifications to +produce it from the Program, in the form of source code under the +terms of section 4, provided that you also meet all of these conditions: + + a) The work must carry prominent notices stating that you modified + it, and giving a relevant date. + + b) The work must carry prominent notices stating that it is + released under this License and any conditions added under section + 7. This requirement modifies the requirement in section 4 to + "keep intact all notices". + + c) You must license the entire work, as a whole, under this + License to anyone who comes into possession of a copy. This + License will therefore apply, along with any applicable section 7 + additional terms, to the whole of the work, and all its parts, + regardless of how they are packaged. This License gives no + permission to license the work in any other way, but it does not + invalidate such permission if you have separately received it. + + d) If the work has interactive user interfaces, each must display + Appropriate Legal Notices; however, if the Program has interactive + interfaces that do not display Appropriate Legal Notices, your + work need not make them do so. + + A compilation of a covered work with other separate and independent +works, which are not by their nature extensions of the covered work, +and which are not combined with it such as to form a larger program, +in or on a volume of a storage or distribution medium, is called an +"aggregate" if the compilation and its resulting copyright are not +used to limit the access or legal rights of the compilation's users +beyond what the individual works permit. Inclusion of a covered work +in an aggregate does not cause this License to apply to the other +parts of the aggregate. + + 6. Conveying Non-Source Forms. + + You may convey a covered work in object code form under the terms +of sections 4 and 5, provided that you also convey the +machine-readable Corresponding Source under the terms of this License, +in one of these ways: + + a) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by the + Corresponding Source fixed on a durable physical medium + customarily used for software interchange. + + b) Convey the object code in, or embodied in, a physical product + (including a physical distribution medium), accompanied by a + written offer, valid for at least three years and valid for as + long as you offer spare parts or customer support for that product + model, to give anyone who possesses the object code either (1) a + copy of the Corresponding Source for all the software in the + product that is covered by this License, on a durable physical + medium customarily used for software interchange, for a price no + more than your reasonable cost of physically performing this + conveying of source, or (2) access to copy the + Corresponding Source from a network server at no charge. + + c) Convey individual copies of the object code with a copy of the + written offer to provide the Corresponding Source. This + alternative is allowed only occasionally and noncommercially, and + only if you received the object code with such an offer, in accord + with subsection 6b. + + d) Convey the object code by offering access from a designated + place (gratis or for a charge), and offer equivalent access to the + Corresponding Source in the same way through the same place at no + further charge. You need not require recipients to copy the + Corresponding Source along with the object code. If the place to + copy the object code is a network server, the Corresponding Source + may be on a different server (operated by you or a third party) + that supports equivalent copying facilities, provided you maintain + clear directions next to the object code saying where to find the + Corresponding Source. Regardless of what server hosts the + Corresponding Source, you remain obligated to ensure that it is + available for as long as needed to satisfy these requirements. + + e) Convey the object code using peer-to-peer transmission, provided + you inform other peers where the object code and Corresponding + Source of the work are being offered to the general public at no + charge under subsection 6d. + + A separable portion of the object code, whose source code is excluded +from the Corresponding Source as a System Library, need not be +included in conveying the object code work. + + A "User Product" is either (1) a "consumer product", which means any +tangible personal property which is normally used for personal, family, +or household purposes, or (2) anything designed or sold for incorporation +into a dwelling. In determining whether a product is a consumer product, +doubtful cases shall be resolved in favor of coverage. For a particular +product received by a particular user, "normally used" refers to a +typical or common use of that class of product, regardless of the status +of the particular user or of the way in which the particular user +actually uses, or expects or is expected to use, the product. A product +is a consumer product regardless of whether the product has substantial +commercial, industrial or non-consumer uses, unless such uses represent +the only significant mode of use of the product. + + "Installation Information" for a User Product means any methods, +procedures, authorization keys, or other information required to install +and execute modified versions of a covered work in that User Product from +a modified version of its Corresponding Source. The information must +suffice to ensure that the continued functioning of the modified object +code is in no case prevented or interfered with solely because +modification has been made. + + If you convey an object code work under this section in, or with, or +specifically for use in, a User Product, and the conveying occurs as +part of a transaction in which the right of possession and use of the +User Product is transferred to the recipient in perpetuity or for a +fixed term (regardless of how the transaction is characterized), the +Corresponding Source conveyed under this section must be accompanied +by the Installation Information. But this requirement does not apply +if neither you nor any third party retains the ability to install +modified object code on the User Product (for example, the work has +been installed in ROM). + + The requirement to provide Installation Information does not include a +requirement to continue to provide support service, warranty, or updates +for a work that has been modified or installed by the recipient, or for +the User Product in which it has been modified or installed. Access to a +network may be denied when the modification itself materially and +adversely affects the operation of the network or violates the rules and +protocols for communication across the network. + + Corresponding Source conveyed, and Installation Information provided, +in accord with this section must be in a format that is publicly +documented (and with an implementation available to the public in +source code form), and must require no special password or key for +unpacking, reading or copying. + + 7. Additional Terms. + + "Additional permissions" are terms that supplement the terms of this +License by making exceptions from one or more of its conditions. +Additional permissions that are applicable to the entire Program shall +be treated as though they were included in this License, to the extent +that they are valid under applicable law. If additional permissions +apply only to part of the Program, that part may be used separately +under those permissions, but the entire Program remains governed by +this License without regard to the additional permissions. + + When you convey a copy of a covered work, you may at your option +remove any additional permissions from that copy, or from any part of +it. (Additional permissions may be written to require their own +removal in certain cases when you modify the work.) You may place +additional permissions on material, added by you to a covered work, +for which you have or can give appropriate copyright permission. + + Notwithstanding any other provision of this License, for material you +add to a covered work, you may (if authorized by the copyright holders of +that material) supplement the terms of this License with terms: + + a) Disclaiming warranty or limiting liability differently from the + terms of sections 15 and 16 of this License; or + + b) Requiring preservation of specified reasonable legal notices or + author attributions in that material or in the Appropriate Legal + Notices displayed by works containing it; or + + c) Prohibiting misrepresentation of the origin of that material, or + requiring that modified versions of such material be marked in + reasonable ways as different from the original version; or + + d) Limiting the use for publicity purposes of names of licensors or + authors of the material; or + + e) Declining to grant rights under trademark law for use of some + trade names, trademarks, or service marks; or + + f) Requiring indemnification of licensors and authors of that + material by anyone who conveys the material (or modified versions of + it) with contractual assumptions of liability to the recipient, for + any liability that these contractual assumptions directly impose on + those licensors and authors. + + All other non-permissive additional terms are considered "further +restrictions" within the meaning of section 10. If the Program as you +received it, or any part of it, contains a notice stating that it is +governed by this License along with a term that is a further +restriction, you may remove that term. If a license document contains +a further restriction but permits relicensing or conveying under this +License, you may add to a covered work material governed by the terms +of that license document, provided that the further restriction does +not survive such relicensing or conveying. + + If you add terms to a covered work in accord with this section, you +must place, in the relevant source files, a statement of the +additional terms that apply to those files, or a notice indicating +where to find the applicable terms. + + Additional terms, permissive or non-permissive, may be stated in the +form of a separately written license, or stated as exceptions; +the above requirements apply either way. + + 8. Termination. + + You may not propagate or modify a covered work except as expressly +provided under this License. Any attempt otherwise to propagate or +modify it is void, and will automatically terminate your rights under +this License (including any patent licenses granted under the third +paragraph of section 11). + + However, if you cease all violation of this License, then your +license from a particular copyright holder is reinstated (a) +provisionally, unless and until the copyright holder explicitly and +finally terminates your license, and (b) permanently, if the copyright +holder fails to notify you of the violation by some reasonable means +prior to 60 days after the cessation. + + Moreover, your license from a particular copyright holder is +reinstated permanently if the copyright holder notifies you of the +violation by some reasonable means, this is the first time you have +received notice of violation of this License (for any work) from that +copyright holder, and you cure the violation prior to 30 days after +your receipt of the notice. + + Termination of your rights under this section does not terminate the +licenses of parties who have received copies or rights from you under +this License. If your rights have been terminated and not permanently +reinstated, you do not qualify to receive new licenses for the same +material under section 10. + + 9. Acceptance Not Required for Having Copies. + + You are not required to accept this License in order to receive or +run a copy of the Program. Ancillary propagation of a covered work +occurring solely as a consequence of using peer-to-peer transmission +to receive a copy likewise does not require acceptance. However, +nothing other than this License grants you permission to propagate or +modify any covered work. These actions infringe copyright if you do +not accept this License. Therefore, by modifying or propagating a +covered work, you indicate your acceptance of this License to do so. + + 10. Automatic Licensing of Downstream Recipients. + + Each time you convey a covered work, the recipient automatically +receives a license from the original licensors, to run, modify and +propagate that work, subject to this License. You are not responsible +for enforcing compliance by third parties with this License. + + An "entity transaction" is a transaction transferring control of an +organization, or substantially all assets of one, or subdividing an +organization, or merging organizations. If propagation of a covered +work results from an entity transaction, each party to that +transaction who receives a copy of the work also receives whatever +licenses to the work the party's predecessor in interest had or could +give under the previous paragraph, plus a right to possession of the +Corresponding Source of the work from the predecessor in interest, if +the predecessor has it or can get it with reasonable efforts. + + You may not impose any further restrictions on the exercise of the +rights granted or affirmed under this License. For example, you may +not impose a license fee, royalty, or other charge for exercise of +rights granted under this License, and you may not initiate litigation +(including a cross-claim or counterclaim in a lawsuit) alleging that +any patent claim is infringed by making, using, selling, offering for +sale, or importing the Program or any portion of it. + + 11. Patents. + + A "contributor" is a copyright holder who authorizes use under this +License of the Program or a work on which the Program is based. The +work thus licensed is called the contributor's "contributor version". + + A contributor's "essential patent claims" are all patent claims +owned or controlled by the contributor, whether already acquired or +hereafter acquired, that would be infringed by some manner, permitted +by this License, of making, using, or selling its contributor version, +but do not include claims that would be infringed only as a +consequence of further modification of the contributor version. For +purposes of this definition, "control" includes the right to grant +patent sublicenses in a manner consistent with the requirements of +this License. + + Each contributor grants you a non-exclusive, worldwide, royalty-free +patent license under the contributor's essential patent claims, to +make, use, sell, offer for sale, import and otherwise run, modify and +propagate the contents of its contributor version. + + In the following three paragraphs, a "patent license" is any express +agreement or commitment, however denominated, not to enforce a patent +(such as an express permission to practice a patent or covenant not to +sue for patent infringement). To "grant" such a patent license to a +party means to make such an agreement or commitment not to enforce a +patent against the party. + + If you convey a covered work, knowingly relying on a patent license, +and the Corresponding Source of the work is not available for anyone +to copy, free of charge and under the terms of this License, through a +publicly available network server or other readily accessible means, +then you must either (1) cause the Corresponding Source to be so +available, or (2) arrange to deprive yourself of the benefit of the +patent license for this particular work, or (3) arrange, in a manner +consistent with the requirements of this License, to extend the patent +license to downstream recipients. "Knowingly relying" means you have +actual knowledge that, but for the patent license, your conveying the +covered work in a country, or your recipient's use of the covered work +in a country, would infringe one or more identifiable patents in that +country that you have reason to believe are valid. + + If, pursuant to or in connection with a single transaction or +arrangement, you convey, or propagate by procuring conveyance of, a +covered work, and grant a patent license to some of the parties +receiving the covered work authorizing them to use, propagate, modify +or convey a specific copy of the covered work, then the patent license +you grant is automatically extended to all recipients of the covered +work and works based on it. + + A patent license is "discriminatory" if it does not include within +the scope of its coverage, prohibits the exercise of, or is +conditioned on the non-exercise of one or more of the rights that are +specifically granted under this License. You may not convey a covered +work if you are a party to an arrangement with a third party that is +in the business of distributing software, under which you make payment +to the third party based on the extent of your activity of conveying +the work, and under which the third party grants, to any of the +parties who would receive the covered work from you, a discriminatory +patent license (a) in connection with copies of the covered work +conveyed by you (or copies made from those copies), or (b) primarily +for and in connection with specific products or compilations that +contain the covered work, unless you entered into that arrangement, +or that patent license was granted, prior to 28 March 2007. + + Nothing in this License shall be construed as excluding or limiting +any implied license or other defenses to infringement that may +otherwise be available to you under applicable patent law. + + 12. No Surrender of Others' Freedom. + + If conditions are imposed on you (whether by court order, agreement or +otherwise) that contradict the conditions of this License, they do not +excuse you from the conditions of this License. If you cannot convey a +covered work so as to satisfy simultaneously your obligations under this +License and any other pertinent obligations, then as a consequence you may +not convey it at all. For example, if you agree to terms that obligate you +to collect a royalty for further conveying from those to whom you convey +the Program, the only way you could satisfy both those terms and this +License would be to refrain entirely from conveying the Program. + + 13. Use with the GNU Affero General Public License. + + Notwithstanding any other provision of this License, you have +permission to link or combine any covered work with a work licensed +under version 3 of the GNU Affero General Public License into a single +combined work, and to convey the resulting work. The terms of this +License will continue to apply to the part which is the covered work, +but the special requirements of the GNU Affero General Public License, +section 13, concerning interaction through a network will apply to the +combination as such. + + 14. Revised Versions of this License. + + The Free Software Foundation may publish revised and/or new versions of +the GNU General Public License from time to time. Such new versions will +be similar in spirit to the present version, but may differ in detail to +address new problems or concerns. + + Each version is given a distinguishing version number. If the +Program specifies that a certain numbered version of the GNU General +Public License "or any later version" applies to it, you have the +option of following the terms and conditions either of that numbered +version or of any later version published by the Free Software +Foundation. If the Program does not specify a version number of the +GNU General Public License, you may choose any version ever published +by the Free Software Foundation. + + If the Program specifies that a proxy can decide which future +versions of the GNU General Public License can be used, that proxy's +public statement of acceptance of a version permanently authorizes you +to choose that version for the Program. + + Later license versions may give you additional or different +permissions. However, no additional obligations are imposed on any +author or copyright holder as a result of your choosing to follow a +later version. + + 15. Disclaimer of Warranty. + + THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY +APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT +HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY +OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, +THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM +IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF +ALL NECESSARY SERVICING, REPAIR OR CORRECTION. + + 16. Limitation of Liability. + + IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING +WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS +THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY +GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE +USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF +DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD +PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), +EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF +SUCH DAMAGES. + + 17. Interpretation of Sections 15 and 16. + + If the disclaimer of warranty and limitation of liability provided +above cannot be given local legal effect according to their terms, +reviewing courts shall apply local law that most closely approximates +an absolute waiver of all civil liability in connection with the +Program, unless a warranty or assumption of liability accompanies a +copy of the Program in return for a fee. + + END OF TERMS AND CONDITIONS + + How to Apply These Terms to Your New Programs + + If you develop a new program, and you want it to be of the greatest +possible use to the public, the best way to achieve this is to make it +free software which everyone can redistribute and change under these terms. + + To do so, attach the following notices to the program. It is safest +to attach them to the start of each source file to most effectively +state the exclusion of warranty; and each file should have at least +the "copyright" line and a pointer to where the full notice is found. + + + Copyright (C) + + This program is free software: you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation, either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. Index: trunk/ucf/sata_core.ucf =================================================================== --- trunk/ucf/sata_core.ucf (nonexistent) +++ trunk/ucf/sata_core.ucf (revision 2) @@ -0,0 +1,35 @@ + +# SATA Port J11 #J64 FMC pins +Net TXN0_OUT LOC = AF2; #A27 +Net TXP0_OUT LOC = AF1; #A26 +Net RXN0_IN LOC = AF6; #A7 +Net RXP0_IN LOC = AF5; #A6 + +#Net FMC_HPC_DP2_C2M_N LOC = AF2; #A27 +#Net FMC_HPC_DP2_C2M_P LOC = AF1; #A26 +#Net FMC_HPC_DP2_M2C_N LOC = AF6; #A7 +#Net FMC_HPC_DP2_M2C_P LOC = AF5; #A6 + + +# GTX Clock Module constraints +#NET REFCLK_PAD_N_IN LOC=AK5; #FMC_HPC_CLK2_M2C_MGT_C_N +#NET REFCLK_PAD_P_IN LOC=AK6; #FMC_HPC_CLK2_M2C_MGT_C_P + +#### Module LEDs_8Bit constraints +NET PLLLKDET_OUT_N LOC= "AC22" |IOSTANDARD=LVCMOS25; #LED 0 +NET DCMLOCKED_OUT LOC= "AC24" |IOSTANDARD=LVCMOS25; #LED 1 +NET LINKUP LOC= "AE22" |IOSTANDARD=LVCMOS25; #LED 2 + +################################## Clock Constraints ########################## + + # Change this to the 150 Mhz GTX reference clock +Net CLKIN_150 TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz; +Net CLKIN_150 LOC = J9 ; +#Net CLKIN_150 LOC = J9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE; +#Net CLKIN_N LOC = H9 | IOSTANDARD=LVDS_25 | DIFF_TERM = TRUE; + +Net reset TIG; +Net reset LOC = H10 | IOSTANDARD=SSTL15 | PULLUP | TIG; + +

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.