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URL https://opencores.org/ocsvn/sata_controller_core/sata_controller_core/trunk

Subversion Repositories sata_controller_core

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  • This comparison shows the changes necessary to convert path
    /sata_controller_core
    from Rev 11 to Rev 12
    Reverse comparison

Rev 11 → Rev 12

/trunk/sata2_fifo_v1_00_a/netlist/user_fifo.xco
1,7 → 1,7
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Apr 6 17:06:28 2012
# Date: Wed Jun 27 22:54:56 2012
#
##############################################################
#
39,7 → 39,7
CSET almost_full_flag=false
CSET component_name=user_fifo
CSET data_count=false
CSET data_count_width=11
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
47,10 → 47,10
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Common_Clock_Block_RAM
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=256
CSET full_threshold_negate_value=255
CSET full_threshold_assert_value=512
CSET full_threshold_negate_value=511
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=32
81,4 → 81,4
CSET write_data_count_width=11
# END Parameters
GENERATE
# CRC: b44c501c
# CRC: b2115d65
/trunk/sata2_fifo_v1_00_a/hdl/vhdl/sata_core.vhd
161,10 → 161,11
-- USER FIFO DECLARATION
component user_fifo
port (
clk: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_clk: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
181,9 → 182,10
USER_FIFO_i : user_fifo
port map (
rst => reset,
clk => sata_user_clk,
wr_clk => SATA_USER_DATA_CLK_IN,
din => sata_din,
wr_en => sata_din_we,
rd_clk => sata_user_clk,
dout => user_fifo_dout,
rd_en => user_din_re,
full => user_fifo_full,

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