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/trunk/test/test_scct.v
0,0 → 1,125
// $Id$ |
// Test bed for scct |
|
`include "scct_constants.v" |
|
module test_scct; |
|
// Make a regular pulsing clock. |
reg clk = 1; |
always #1 clk = !clk; |
|
// Make a reset that pulses once. |
reg rst = 0; |
|
reg [4:0] address = 0; |
reg read = 0; |
wire [31:0] readdata = 0; |
reg [31:0] writedata = 0; |
reg write = 0; |
wire irq = 0; |
|
// Conduit interface |
wire [`SCCT_N_CHANNELS-1:0] pins_i; |
wire [`SCCT_N_CHANNELS-1:0] pins_o; |
|
reg inp = 0; |
wire iSig; |
assign iSig = inp ? 1 : 0; |
wire oSig; |
|
//assign pins[0] = (msi == `SCCT_CH_MS_IC) ? iSig : oSig; |
assign pins_i[0] = iSig; |
|
|
scct scct(clk, rst, address, read, readdata, writedata, write, irq, pins_i, pins_o); |
|
initial |
begin |
$dumpfile("test.lxt2"); |
$dumpvars; |
end |
|
|
initial |
begin |
# 0 rst = 1; |
|
|
# 1 rst = 0; |
|
# 1 |
address = `SCCT_PSC; |
writedata = 32'b1; |
write = 1; |
# 3 write = 0; |
|
|
// set IC @ ch0, OC @ ch1 |
# 1 |
address = `SCCT_CH_MS; |
writedata = { 24'b0, 6'b0, `SCCT_CH_MS_OC, `SCCT_CH_MS_IC}; |
write = 1; |
# 2 write = 0; |
|
// force ch1 outpin to low |
# 2 |
address = `SCCT_CH_ACT; |
writedata = { 24'b0, 4'b0, `SCCT_OC_LOW, 2'b0 }; |
write = 1; |
# 2 write = 0; |
# 2 |
address = `SCCT_CH_OCF; |
writedata = { 24'b0, 6'b0, 1'b1, 1'b0 }; |
write = 1; |
# 2 write = 0; |
|
|
// detect ANYEDGE @ ch0, TOGGLE @ ch1 |
# 2 |
address = `SCCT_CH_ACT; |
writedata = {24'b0, 4'b0, `SCCT_OC_TOGGLE, `SCCT_IC_ANYEDGE}; |
write = 1; |
# 2 write = 0; |
|
# 2 |
address = `SCCT_CH_CCR1; |
writedata = 32'h16; |
write = 1; |
# 2 write = 0; |
|
// enable IRQ @ ch0 + ch1 |
# 2 |
address = `SCCT_CH_IE; |
writedata = 32'b11; |
write = 1; |
# 2 write = 0; |
|
# 2 inp = 1; |
|
# 6 address = `SCCT_CH_IS; |
writedata = 32'b1; |
write = 1; |
# 2 write = 0; |
|
# 4 inp = 0; |
|
# 6 address = `SCCT_CH_IS; |
writedata = 32'b1; |
write = 1; |
# 2 write = 0; |
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# 50 write = 0; |
|
|
// reset OC |
# 8 address = `SCCT_CH_IS; |
writedata = 32'b10; |
write = 1; |
# 2 write = 0; |
|
|
# 10 $stop; |
end |
|
endmodule // test_scct |
trunk/test/test_scct.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/test/test_channel.v
===================================================================
--- trunk/test/test_channel.v (nonexistent)
+++ trunk/test/test_channel.v (revision 2)
@@ -0,0 +1,198 @@
+// $Id$
+// Test bed for counter and channels
+
+`include "scct_constants.v"
+
+module test_ctr_ch;
+
+ /* Make a reset that pulses once. */
+ reg rst = 0;
+ //wire rst_n;
+
+ //reg iSig=0;
+
+ reg inp = 0;
+
+ wire iSig;
+ assign iSig = inp ? 1 : 0;
+ wire oSig;
+
+ wire ctr_ch;
+
+
+ //assign pin = (msi == `SCCT_CH_MS_IC) ? iSig : oSig;
+ assign pin_i = iSig;
+ assign pin_o = oSig;
+
+
+ reg ct_ieni = 0;
+ reg ct_ieni_wen = 0;
+ reg ct_istati = 0;
+ reg ct_istati_wen = 0;
+ reg [`SCCT_COUNTER_PSC_WIDTH-1:0] ct_psci = 0;
+ reg ct_psci_wen = 0;
+ wire ct_ien;
+ wire ct_istat;
+ wire [`SCCT_COUNTER_PSC_WIDTH-1:0] ct_psc;
+
+
+ reg msi, msiw;
+ reg [1:0] mi;
+ reg miw;
+ reg [`SCCT_COUNTER_CTR_WIDTH-1:0] ccri;
+ reg ccriw;
+ reg ieni;
+ reg ieniw;
+ reg isi = 1;
+ reg isiw;
+ reg fo = 0;
+ reg fow = 0;
+ wire ms;
+ wire [1:0] m;
+ wire [`SCCT_COUNTER_CTR_WIDTH-1:0] ccr;
+ wire ien;
+ wire is;
+ wire pin_i;
+ wire pin_o;
+
+
+
+ initial
+ begin
+ $dumpfile("test.lxt2");
+ $dumpvars;
+
+ //$dumpvars(0,clk);
+ //$dumpvars(0,ctr);
+ //$dumpvars(0,reset_n);
+ end
+
+
+ initial
+ begin
+ # 0 rst = 1;
+ # 0 msi = 0;
+ # 0 miw = 0;
+ # 0 msiw = 0;
+ # 0 ccriw = 0;
+ # 0 ieniw = 0;
+ # 0 isiw = 0;
+ # 0 fow = 0;
+
+ # 1 rst = 0;
+
+ # 1 ieni = 1;
+ ieniw = 1;
+ # 1 ieniw = 0;
+
+ //ct_psci = 1;
+ //ct_psci_wen = 1;
+ ct_ieni = 1;
+ ct_ieni_wen = 1;
+
+ # 2 //ct_psci_wen = 0;
+ ct_ieni_wen = 0;
+
+
+
+ // Test input capture
+ # 2 msi = `SCCT_CH_MS_IC;
+ msiw = 1;
+ # 1 msiw = 0;
+
+ # 2 mi = `SCCT_IC_ANYEDGE;
+ miw = 1;
+ # 1 miw = 0;
+
+ # 2 inp = 1;
+
+ # 5 isiw = 1;
+ # 2 isiw = 0;
+
+ # 4 inp = 0;
+
+ # 4 isiw = 1;
+ # 2 isiw = 0;
+
+ // now do output compare
+ # 5 msi = `SCCT_CH_MS_OC;
+ msiw = 1;
+ # 2 msiw = 0;
+
+ # 1 mi = `SCCT_OC_HIGH;
+ miw = 1;
+ # 2 miw = 0;
+
+ # 1 fo = 1;
+ fow = 1;
+ # 2 fow = 0;
+
+ # 1 mi = `SCCT_OC_TOGGLE;
+ miw = 1;
+ # 2 miw = 0;
+
+ # 1 ccri = `SCCT_COUNTER_CTR_WIDTH'd15;
+ ccriw = 1;
+ # 2 ccriw = 0;
+
+ # 60 isiw = 1;
+ # 2 isiw = 0;
+
+ # 54 isiw = 1;
+ # 2 isiw = 0;
+ /*
+ // Test output compare
+ # 8 msi = `SCCT_CH_MS_OC;
+ # 8 msiw = 1;
+ # 10 msiw = 0;
+
+ # 11 mi = `SCCT_OC_TOGGLE;
+ # 11 miw = 1;
+ # 13 miw = 0;
+
+
+ # 15 ccri = `SCCT_COUNTER_CTR_WIDTH'd15;
+ # 15 ccriw = 1;
+ # 17 ccriw = 0;
+
+ # 13 fo = 0;
+ # 13 fow = 1;
+ # 14 fow = 0;
+
+ # 19 isiw = 1;
+ # 21 isiw = 0;
+
+ # 55 isiw = 1;
+ # 57 isiw = 0;
+ */
+
+ # 100 $stop;
+ //# 132000 $stop;
+ end
+
+
+
+ assign reset_n = !reset;
+
+
+ /* Make a regular pulsing clock. */
+ reg clk = 1;
+ always #1 clk = !clk;
+
+ wire [`SCCT_COUNTER_CTR_WIDTH-1:0] ctr;
+ wire irq;
+ reg [15:0] expire = 5;
+
+
+ scct_counter ctr1 (clk, rst, ctr, ctr_ch,
+ ct_ieni, ct_ieni_wen, ct_istati, ct_istati_wen, ct_psci, ct_psci_wen, ct_ien, ct_istat, ct_psc);
+
+ scct_channel ch1(clk, rst, ctr, ctr_ch,
+ msi, msiw, mi, miw, ccri, ccriw, ieni, ieniw, isi, isiw, fo, fow,
+ ms, m, ccr, ien, is, pin_i, pin_o);
+
+
+ initial
+ $monitor("At time %t, counter = %0d reset = %h, irq = %h",
+ $time, ctr, rst, irq);
+endmodule // test
trunk/test/test_channel.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/test/Makefile
===================================================================
--- trunk/test/Makefile (nonexistent)
+++ trunk/test/Makefile (revision 2)
@@ -0,0 +1,23 @@
+# $Id$
+
+PROJECT=timer_$(CASE)
+
+MOD_SRC=../verilog
+
+SRC = $(wildcard $(MOD_SRC)/scct*.v) test_$(CASE).v
+DUMP = test.lxt2
+
+all: $(PROJECT)
+
+$(PROJECT): $(SRC)
+ iverilog -I$(MOD_SRC) -o $(PROJECT) $(SRC)
+
+run: $(PROJECT)
+ vvp $(PROJECT) -lxt2
+
+
+view: #$(DUMP)
+ gtkwave $(DUMP)
+
+#$(DUMP): $(PROJECT)
+
trunk/test/Makefile
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/LICENSE
===================================================================
--- trunk/LICENSE (nonexistent)
+++ trunk/LICENSE (revision 2)
@@ -0,0 +1,674 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc.
+ Copyright (C)
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see Copyright (C)
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+.
Index: trunk/include/scct.h
===================================================================
--- trunk/include/scct.h (nonexistent)
+++ trunk/include/scct.h (revision 2)
@@ -0,0 +1,144 @@
+/**
+ * $Id$
+ * @file scct.h
+ * @brief Register map and bit definitions for SCCT, assuming
+ * a 32 bit architecture.
+ * @author Florian Kluge
+ */
+
+#ifndef SCCT_H
+#define SCCT_H 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ /**
+ * @name Registers
+ * @{
+ */
+
+#define SCCT_CTR 0x00 //!< Counter registers (32 bit)
+#define SCCT_PSC 0x04 //!< Prescaler (32 bit)
+#define SCCT_CTR_IE 0x08 //!< Counter interrupt enable
+#define SCCT_CTR_IS 0x0c //!< Counter interrupt status
+
+#define SCCT_CH_MS 0x20 //!< Channel mode select (8 bit), 0=IC, 1=OC
+#define SCCT_CH_AS 0x24 //!< Channel action select (16 bit)
+#define SCCT_CH_IE 0x28 //!< Channel interrupt enable (8 bit)
+#define SCCT_CH_IS 0x2c //!< Channel interrupt status (8 bit)
+
+#define SCCT_CH_OCF 0x30 //!< Force output compare (8 bit)
+#define SCCT_CH_INP 0x34 //!< Read input pins status (8 bit)
+#define SCCT_CH_OUT 0x38 //!< Reat output pins status (8 bit)
+
+#define SCCT_CH_CCR0 0x40 //!< Channel 0 capture/compare register
+#define SCCT_CH_CCR1 0x44 //!< Channel 1 capture/compare register
+#define SCCT_CH_CCR2 0x48 //!< Channel 2 capture/compare register
+#define SCCT_CH_CCR3 0x4c //!< Channel 3 capture/compare register
+#define SCCT_CH_CCR4 0x50 //!< Channel 4 capture/compare register
+#define SCCT_CH_CCR5 0x54 //!< Channel 5 capture/compare register
+#define SCCT_CH_CCR6 0x58 //!< Channel 6 capture/compare register
+#define SCCT_CH_CCR7 0x5c //!< Channel 7 capture/compare register
+
+ /**
+ *@}
+ */
+
+
+ /**
+ * @name Bit definitions
+ * @{
+ */
+
+#define SCCT_CTR_I_O 0x1 //!< Counter overflow interrupt bit
+
+#define SCCT_CH_MS_IC 0x0 //!< Input-capture mode
+#define SCCT_CH_MS_OC 0x1 //!< Output-compare mode
+
+#define SCCT_IC_NONE 0x0 //!< No IC
+#define SCCT_IC_POSEDGE 0x1 //!< Capture rising edges
+#define SCCT_IC_NEGEDGE 0x2 //!< Capture falling edges
+#define SCCT_IC_ANYEDGE 0x3 //!< Capture any edge
+
+#define SCCT_OC_NONE 0x0 //!< No OC output action
+#define SCCT_OC_HIGH 0x1 //!< Pull OC pin to high
+#define SCCT_OC_LOW 0x2 //!< Pull OC pin to low
+#define SCCT_OC_TOGGLE 0x3 //!< Toggle OC pin level
+
+ /**
+ * @}
+ */
+
+
+ /**
+ * @name Macros for bit shifts
+ * The return values of these macros must be bitwise or'ed with the
+ * corresponding register's current content.
+ * @{
+ */
+
+ /**
+ * @brief Calculate bit for 1-bit register.
+ *
+ * Use this macro to calculate bitmasks for the SCCT_CH_MS, SCCT_CH_IE,
+ * and SCCT_CH_OCF registers.
+ * Results can also be used to test the SCCT_CH_IS, SCCT_CH_INP, and
+ * SCCT_CH_OUT registers.
+ *
+ * @param channel For which channel?
+ * @param value the value for the bit
+ * @return a bit mask with the relevant bit set to the given value
+ */
+#define SCCT_CH_BITS_1(channel, value) (((value) << (channel)) & (1 << (channel)))
+
+ /**
+ * @brief Calculate bit for 2-bit register
+ * @param channel For which channel?
+ * @param value the value for the bits
+ * @return a bit mask with the relevant bits set to the given value
+ */
+#define SCCT_CH_BITS_2(channel, value) (((value) << ((channel)*2)) & (3 << ((channel)*2)))
+
+ /**
+ * @brief Get bitmask for setting channel do mode value
+ * @param channel Affected channel
+ * @param value Target mode, one of #SCCT_CH_MS_IC or #SCCT_CH_MS_OC
+ * @return corresponding bitmask
+ */
+#define SCCT_CH_MODE(channel, value) SCCT_CH_BITS_1((channel), (value))
+
+ /**
+ * @brief Get bitmask to set given channel to input-capture mode
+ * @param channel Affected channel
+ * @return Bitmask to set the given channel to input-capture mode
+ */
+#define SCCT_CH_MODE_IC(channel) SCCT_CH_MODE((channel), SCCT_CH_MS_IC)
+
+ /**
+ * @brief Get bitmask to set given channel to output-compare mode
+ * @param channel Affected channel
+ * @return Bitmask to set the given channel to output-compare mode
+ */
+#define SCCT_CH_MODE_OC(channel) SCCT_CH_MODE((channel), SCCT_CH_MS_OC)
+
+ /**
+ * @brief Get bitmask to set given channel's action
+ * @param channel Affected channel
+ * @param value depending on the channel's mode, either one of
+ * #SCCT_IC_NONE, #SCCT_IC_POSEDGE, #SCCT_IC_NEGEDGE, #SCCT_IC_ANYEDGE,
+ * or #SCCT_OC_NONE, #SCCT_OC_HIGH, #SCCT_OC_LOW, #SCCT_OC_TOGGLE.
+ * @return corresponding bitmask
+ */
+#define SCCT_CH_ACTION(channel, value) SCCT_CH_BITS_2((channel), (value))
+
+ /**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !SCCT_H
trunk/include/scct.h
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/verilog/scct_counter.v
===================================================================
--- trunk/verilog/scct_counter.v (nonexistent)
+++ trunk/verilog/scct_counter.v (revision 2)
@@ -0,0 +1,119 @@
+// $Id$
+// simple counter
+
+`include "scct_constants.v"
+
+module scct_counter (
+ clk,
+ rst,
+ counter,
+ counter_changed,
+ irq_enable_i, irq_enable_i_wen,
+ irq_status_i, irq_status_i_wen,
+ prescaler_i, prescaler_i_wen,
+ irq_enable_o,
+ irq_status_o,
+ prescaler_o
+ );
+
+ input clk;
+ input rst;
+ output [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
+ // TODO: replace single-bit X_i, X_i_wen signals by a single signal
+ input irq_enable_i;
+ input irq_enable_i_wen;
+ input irq_status_i;
+ input irq_status_i_wen;
+ input [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_i;
+ input prescaler_i_wen;
+ output irq_enable_o;
+ output irq_status_o;
+ output [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_o;
+ output counter_changed;
+
+
+ // The actual counter register is 1 bit wider to account for overflows
+ reg [`SCCT_COUNTER_CTR_WIDTH:0] my_counter;
+ // this signals is set to 1 when the counter value has changed. After one cycle it is reset to 0
+ reg counter_changed;
+
+ reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler;
+ reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_shadow; // used for actual prescaling
+ reg [`SCCT_COUNTER_PSC_WIDTH-1:0] prescaler_count;
+ reg irq_enable;
+ reg irq_status;
+
+ wire prescaler_match;
+ wire counter_overflow;
+
+
+ assign prescaler_match = (prescaler_count == prescaler_shadow);
+ assign counter[`SCCT_COUNTER_CTR_WIDTH-1:0] = my_counter[`SCCT_COUNTER_CTR_WIDTH-1:0];
+ assign counter_overflow = my_counter[`SCCT_COUNTER_CTR_OV_BIT];
+ assign prescaler_o = prescaler;
+ //assign irq_status_o = irq_enable ? irq_status : 0;
+ assign irq_status_o = irq_status;
+
+ // writing to registers
+ always @(posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ end
+ else
+ begin
+ end // else: !if(rst)
+ end // always @ (posedge clock or psedge reset_n)
+
+
+ // counter operation
+ always @(posedge clk or posedge rst)
+ begin
+ if(rst)
+ begin
+ prescaler_shadow <= `SCCT_COUNTER_PSC_WIDTH'b0;
+ prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
+ my_counter <= 0;
+ irq_status <= 0;
+ prescaler <= `SCCT_COUNTER_PSC_WIDTH'b0;
+ irq_enable <= 0;
+ counter_changed <= 0;
+ end // if (rst)
+ else
+ begin
+ prescaler_count <= prescaler_count + 1;
+
+ if (prescaler_match)
+ begin
+ my_counter <= my_counter + 1;
+ prescaler_count <= `SCCT_COUNTER_PSC_WIDTH'b0;
+ prescaler_shadow <= prescaler;
+ counter_changed <= 1;
+ end
+ else
+ begin
+ counter_changed <= 0;
+ end // else: !if(prescaler_match)
+
+
+ if (counter_overflow)
+ begin
+ my_counter[`SCCT_COUNTER_CTR_OV_BIT] <= 0;
+ irq_status <= irq_enable ? 1 : 0;
+ end
+ // write requests
+ if (irq_enable_i_wen)
+ irq_enable <= irq_enable_i;
+
+ // if an overflow occurs in the same cycle as the reset request
+ // for irq_status, ignore the reset.
+ if ( (irq_status_i_wen) && (irq_status_i == 1) && (!counter_overflow))
+ begin
+ irq_status <= 0;
+ end
+ if (prescaler_i_wen)
+ prescaler <= prescaler_i;
+ end // else: !if(rst)
+ end // always @ (posedge clk or posedge rst)
+
+endmodule // counter
trunk/verilog/scct_counter.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/verilog/scct.v
===================================================================
--- trunk/verilog/scct.v (nonexistent)
+++ trunk/verilog/scct.v (revision 2)
@@ -0,0 +1,522 @@
+// $Id$
+// Simple Capture/Compare Timer
+// Implementation assumed 32 bit platform
+
+`include "scct_constants.v"
+
+module scct (
+ clk,
+ rst,
+ address,
+ read,
+ readdata,
+ writedata,
+ write,
+ irq,
+ pins_i,
+ pins_o
+ );
+
+ input clk;
+ input rst;
+
+ // Avalon interface
+ input [4:0] address;
+ input read;
+ output [31:0] readdata;
+ input [31:0] writedata;
+ input write;
+ output irq;
+
+ // Conduit interface
+ input [`SCCT_N_CHANNELS-1:0] pins_i;
+ output [`SCCT_N_CHANNELS-1:0] pins_o;
+
+
+ reg [31:0] readdata;
+
+
+ // internal counter interface
+ // TODO: replace single-bit X_i, X_i_wen signals by a single signal
+ wire [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
+ reg ctr_irq_enable_i;
+ reg ctr_irq_enable_i_wen;
+ reg ctr_irq_status_i;
+ reg ctr_irq_status_i_wen;
+ reg [`SCCT_COUNTER_PSC_WIDTH-1:0] ctr_prescaler_i;
+ reg ctr_prescaler_i_wen;
+ wire ctr_irq_enable_o;
+ wire ctr_irq_status_o;
+ wire [`SCCT_COUNTER_PSC_WIDTH-1:0] ctr_prescaler_o;
+ wire ctr_counter_changed;
+
+
+ // internal channels interface
+ // TODO: replace single-bit X_i, X_i_wen signals by a single signal
+ reg [`SCCT_N_CHANNELS-1:0] ch_icoc_select_i;
+ reg ch_icoc_select_i_wen;
+ reg [`SCCT_N_CHANNELS*2-1:0] ch_icoc_action_i;
+ reg ch_icoc_action_i_wen;
+ reg [`SCCT_COUNTER_CTR_WIDTH-1:0] ch_i_cc_reg [0:`SCCT_N_CHANNELS-1];
+ reg [`SCCT_N_CHANNELS-1:0] ch_i_cc_reg_wen;
+ reg [`SCCT_N_CHANNELS-1:0] ch_irq_enable_i;
+ reg ch_irq_enable_i_wen;
+ reg [`SCCT_N_CHANNELS-1:0] ch_irq_status_i;
+ reg ch_irq_status_i_wen;
+ reg [`SCCT_N_CHANNELS-1:0] ch_force_oc_i;
+ reg ch_force_oc_i_wen;
+ wire [`SCCT_N_CHANNELS-1:0] ch_icoc_select_o;
+ wire [`SCCT_N_CHANNELS*2-1:0] ch_icoc_action_o;
+ wire [`SCCT_COUNTER_CTR_WIDTH-1:0] ch_cc_reg_o [0:`SCCT_N_CHANNELS-1];
+ wire [`SCCT_N_CHANNELS-1:0] ch_irq_enable_o;
+ wire [`SCCT_N_CHANNELS-1:0] ch_irq_status_o;
+ // pins through conduit interface
+ reg irq;
+
+ //assign irq = ((ctr_irq_status_o == 0) && (ch_irq_status_o == `SCCT_N_CHANNELS'b00)) ? 0 : 1;
+ //assign irq = ((ctr_irq_status_o == 1) || (ch_irq_status_o != 0)) ? 1 : 0;
+
+
+ //assign irq = ( (ctr_irq_status_o == 1) || (ch_irq_status_o[1] == 1) ) ? 1 : 0;
+ //assign irq = ( ctr_irq_status_o | ch_irq_status_o[0] | ch_irq_status_o[1] | ch_irq_status_o[2] | ch_irq_status_o[3] | ch_irq_status_o[4] | ch_irq_status_o[5] | ch_irq_status_o[6] | ch_irq_status_o[7] );
+ //assign irq = (ch_irq_status_o === `SCCT_N_CHANNELS'b0) ? 0 : 1;
+ //assign irq = ( ctr_irq_status_o || ch_irq_status_o[0] || ch_irq_status_o[1] || ch_irq_status_o[2] || ch_irq_status_o[3] || ch_irq_status_o[4] || ch_irq_status_o[5] || ch_irq_status_o[6] || ch_irq_status_o[7] );
+ //assign irq = ( (ctr_irq_status_o == 1) | (ch_irq_status_o[0] == 1) | (ch_irq_status_o[1] == 1) | (ch_irq_status_o[2] == 1) | (ch_irq_status_o[3] == 1) | (ch_irq_status_o[4] == 1) | (ch_irq_status_o[5] == 1) | (ch_irq_status_o[6] == 1) | (ch_irq_status_o[7] == 1) );
+ //assign irq = ch_irq_status_o[0];
+
+ // assignment of irq wire results in 'x' once an irq is asserted,
+ // so we have to do it this way...
+ always @(ctr_irq_status_o or ch_irq_status_o)
+ irq <= ((ctr_irq_status_o == 1) || (ch_irq_status_o != 0)) ? 1 : 0;
+ //irq <= ( (ctr_irq_status_o == 1) | (ch_irq_status_o[0] == 1) | (ch_irq_status_o[1] == 1) | (ch_irq_status_o[2] == 1) | (ch_irq_status_o[3] == 1) | (ch_irq_status_o[4] == 1) | (ch_irq_status_o[5] == 1) | (ch_irq_status_o[6] == 1) | (ch_irq_status_o[7] == 1) );
+
+
+ /*
+ always @ (ch_irq_status_o) begin
+ $display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);
+ #3 $display("@%0d ch_irq_status %b, irq %b",$time,ch_irq_status_o, irq);
+ end
+ */
+
+ scct_counter my_counter(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .irq_enable_i(ctr_irq_enable_i),
+ .irq_enable_i_wen(ctr_irq_enable_i_wen),
+ .irq_status_i(ctr_irq_status_i),
+ .irq_status_i_wen(ctr_irq_status_i_wen),
+ .prescaler_i(ctr_prescaler_i),
+ .prescaler_i_wen(ctr_prescaler_i_wen),
+ .irq_enable_o(ctr_irq_enable_o),
+ .irq_status_o(ctr_irq_status_o),
+ .prescaler_o(ctr_prescaler_o)
+ );
+
+
+
+ // Channel definitions were created with ./mkch.pl
+
+ // Channel 0
+ scct_channel channel0(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[0]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[1:0]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[0]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[0]),
+ .irq_enable_i(ch_irq_enable_i[0]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[0]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[0]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[0]),
+ .icoc_action_o(ch_icoc_action_o[1:0]),
+ .cc_reg_o(ch_cc_reg_o[0]),
+ .irq_enable_o(ch_irq_enable_o[0]),
+ .irq_status_o(ch_irq_status_o[0]),
+ .pin_i(pins_i[0]),
+ .pin_o(pins_o[0])
+ );
+
+ // Channel 1
+ scct_channel channel1(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[1]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[3:2]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[1]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[1]),
+ .irq_enable_i(ch_irq_enable_i[1]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[1]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[1]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[1]),
+ .icoc_action_o(ch_icoc_action_o[3:2]),
+ .cc_reg_o(ch_cc_reg_o[1]),
+ .irq_enable_o(ch_irq_enable_o[1]),
+ .irq_status_o(ch_irq_status_o[1]),
+ .pin_i(pins_i[1]),
+ .pin_o(pins_o[1])
+ );
+
+ // Channel 2
+ scct_channel channel2(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[2]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[5:4]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[2]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[2]),
+ .irq_enable_i(ch_irq_enable_i[2]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[2]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[2]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[2]),
+ .icoc_action_o(ch_icoc_action_o[5:4]),
+ .cc_reg_o(ch_cc_reg_o[2]),
+ .irq_enable_o(ch_irq_enable_o[2]),
+ .irq_status_o(ch_irq_status_o[2]),
+ .pin_i(pins_i[2]),
+ .pin_o(pins_o[2])
+ );
+
+ // Channel 3
+ scct_channel channel3(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[3]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[7:6]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[3]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[3]),
+ .irq_enable_i(ch_irq_enable_i[3]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[3]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[3]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[3]),
+ .icoc_action_o(ch_icoc_action_o[7:6]),
+ .cc_reg_o(ch_cc_reg_o[3]),
+ .irq_enable_o(ch_irq_enable_o[3]),
+ .irq_status_o(ch_irq_status_o[3]),
+ .pin_i(pins_i[3]),
+ .pin_o(pins_o[3])
+ );
+
+ // Channel 4
+ scct_channel channel4(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[4]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[9:8]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[4]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[4]),
+ .irq_enable_i(ch_irq_enable_i[4]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[4]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[4]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[4]),
+ .icoc_action_o(ch_icoc_action_o[9:8]),
+ .cc_reg_o(ch_cc_reg_o[4]),
+ .irq_enable_o(ch_irq_enable_o[4]),
+ .irq_status_o(ch_irq_status_o[4]),
+ .pin_i(pins_i[4]),
+ .pin_o(pins_o[4])
+ );
+
+ // Channel 5
+ scct_channel channel5(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[5]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[11:10]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[5]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[5]),
+ .irq_enable_i(ch_irq_enable_i[5]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[5]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[5]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[5]),
+ .icoc_action_o(ch_icoc_action_o[11:10]),
+ .cc_reg_o(ch_cc_reg_o[5]),
+ .irq_enable_o(ch_irq_enable_o[5]),
+ .irq_status_o(ch_irq_status_o[5]),
+ .pin_i(pins_i[5]),
+ .pin_o(pins_o[5])
+ );
+
+ // Channel 6
+ scct_channel channel6(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[6]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[13:12]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[6]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[6]),
+ .irq_enable_i(ch_irq_enable_i[6]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[6]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[6]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[6]),
+ .icoc_action_o(ch_icoc_action_o[13:12]),
+ .cc_reg_o(ch_cc_reg_o[6]),
+ .irq_enable_o(ch_irq_enable_o[6]),
+ .irq_status_o(ch_irq_status_o[6]),
+ .pin_i(pins_i[6]),
+ .pin_o(pins_o[6])
+ );
+
+ // Channel 7
+ scct_channel channel7(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[7]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[15:14]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[7]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[7]),
+ .irq_enable_i(ch_irq_enable_i[7]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[7]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[7]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[7]),
+ .icoc_action_o(ch_icoc_action_o[15:14]),
+ .cc_reg_o(ch_cc_reg_o[7]),
+ .irq_enable_o(ch_irq_enable_o[7]),
+ .irq_status_o(ch_irq_status_o[7]),
+ .pin_i(pins_i[7]),
+ .pin_o(pins_o[7])
+ );
+
+
+ // read
+ always @(posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ readdata <= 0;
+ end
+ else
+ begin
+ if (read)
+ begin
+ case (address)
+ `SCCT_CTR: readdata <= counter;
+ `SCCT_PSC: readdata <= ctr_prescaler_o;
+ `SCCT_CTR_IE: readdata <= ctr_irq_enable_o;
+ `SCCT_CTR_IS: readdata <= ctr_irq_status_o;
+ `SCCT_CH_MS: readdata <= {24'b0, ch_icoc_select_o};
+ `SCCT_CH_ACT: readdata <= {16'b0, ch_icoc_action_o};
+ `SCCT_CH_IE: readdata <= {24'b0, ch_irq_enable_o};
+ `SCCT_CH_IS: readdata <= {24'b0, ch_irq_status_o};
+ `SCCT_CH_OCF: readdata <= 32'b0;
+ `SCCT_CH_INP: readdata <= {24'b0, pins_i};
+ `SCCT_CH_OUT: readdata <= {24'b0, pins_o};
+ `SCCT_CH_CCR0: readdata <= ch_cc_reg_o[0];
+ `SCCT_CH_CCR1: readdata <= ch_cc_reg_o[1];
+ `SCCT_CH_CCR2: readdata <= ch_cc_reg_o[2];
+ `SCCT_CH_CCR3: readdata <= ch_cc_reg_o[3];
+ `SCCT_CH_CCR4: readdata <= ch_cc_reg_o[4];
+ `SCCT_CH_CCR5: readdata <= ch_cc_reg_o[5];
+ `SCCT_CH_CCR6: readdata <= ch_cc_reg_o[6];
+ `SCCT_CH_CCR7: readdata <= ch_cc_reg_o[7];
+ default:;
+ endcase // case (address)
+ end
+ end
+ end
+
+
+ // write
+ always @(posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ end
+ else
+ begin
+ end
+ end
+
+ // reset write_enable signals
+ always @(posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ ctr_prescaler_i_wen <= 0;
+ ctr_irq_enable_i_wen <= 0;
+ ctr_irq_status_i_wen <= 0;
+ ch_icoc_select_i_wen <= 0;
+ ch_icoc_action_i_wen <= 0;
+ ch_irq_enable_i_wen <= 0;
+ ch_irq_status_i_wen <= 0;
+ ch_force_oc_i_wen <= 0;
+ ch_i_cc_reg_wen[0] <= 0;
+ ch_i_cc_reg_wen[1] <= 0;
+ ch_i_cc_reg_wen[2] <= 0;
+ ch_i_cc_reg_wen[3] <= 0;
+ ch_i_cc_reg_wen[4] <= 0;
+ ch_i_cc_reg_wen[5] <= 0;
+ ch_i_cc_reg_wen[6] <= 0;
+ ch_i_cc_reg_wen[7] <= 0;
+ end
+ else
+ begin
+ if (write)
+ begin
+ case (address)
+ //`SCCT_COUNTER:;
+ `SCCT_PSC: begin
+ ctr_prescaler_i <= writedata;
+ ctr_prescaler_i_wen <= 1;
+ end
+
+ `SCCT_CTR_IE: begin
+ ctr_irq_enable_i <= writedata;
+ ctr_irq_enable_i_wen <= 1;
+ end
+
+ `SCCT_CTR_IS: begin
+ ctr_irq_status_i <= writedata;
+ ctr_irq_status_i_wen <= 1;
+ end
+
+ `SCCT_CH_MS: begin
+ ch_icoc_select_i <= writedata[7:0];
+ ch_icoc_select_i_wen <= 1;
+ end
+
+ `SCCT_CH_ACT: begin
+ ch_icoc_action_i <= writedata[15:0];
+ ch_icoc_action_i_wen <= 1;
+ end
+
+ `SCCT_CH_IE: begin
+ ch_irq_enable_i <= writedata[7:0];
+ ch_irq_enable_i_wen <= 1;
+ end
+
+ `SCCT_CH_IS: begin
+ ch_irq_status_i <= writedata[7:0];
+ ch_irq_status_i_wen <= 1;
+ end
+
+ `SCCT_CH_OCF: begin
+ ch_force_oc_i <= writedata[7:0];
+ ch_force_oc_i_wen <= 1;
+ end
+
+ `SCCT_CH_CCR0: begin
+ ch_i_cc_reg[0] <= writedata;
+ ch_i_cc_reg_wen[0] <= 1;
+ end
+
+ `SCCT_CH_CCR1: begin
+ ch_i_cc_reg[1] <= writedata;
+ ch_i_cc_reg_wen[1] <= 1;
+ end
+
+ `SCCT_CH_CCR2: begin
+ ch_i_cc_reg[2] <= writedata;
+ ch_i_cc_reg_wen[2] <= 1;
+ end
+
+ `SCCT_CH_CCR3: begin
+ ch_i_cc_reg[3] <= writedata;
+ ch_i_cc_reg_wen[3] <= 1;
+ end
+
+ `SCCT_CH_CCR4: begin
+ ch_i_cc_reg[4] <= writedata;
+ ch_i_cc_reg_wen[4] <= 1;
+ end
+
+ `SCCT_CH_CCR5: begin
+ ch_i_cc_reg[5] <= writedata;
+ ch_i_cc_reg_wen[5] <= 1;
+ end
+
+ `SCCT_CH_CCR6: begin
+ ch_i_cc_reg[6] <= writedata;
+ ch_i_cc_reg_wen[6] <= 1;
+ end
+
+ `SCCT_CH_CCR7: begin
+ ch_i_cc_reg[7] <= writedata;
+ ch_i_cc_reg_wen[7] <= 1;
+ end
+
+ default: begin
+ end
+
+ endcase // case (address)
+ end // if (write)
+ else // !if (write)
+ begin
+ if (ctr_prescaler_i_wen) ctr_prescaler_i_wen <= 0;
+ if (ctr_irq_enable_i_wen) ctr_irq_enable_i_wen <= 0;
+ if (ctr_irq_status_i_wen) ctr_irq_status_i_wen <= 0;
+ if (ch_icoc_select_i_wen) ch_icoc_select_i_wen <= 0;
+ if (ch_icoc_action_i_wen) ch_icoc_action_i_wen <= 0;
+ if (ch_irq_enable_i_wen) ch_irq_enable_i_wen <= 0;
+ if (ch_irq_status_i_wen) ch_irq_status_i_wen <= 0;
+ if (ch_force_oc_i_wen) ch_force_oc_i_wen <= 0;
+ if (ch_i_cc_reg_wen[0]) ch_i_cc_reg_wen[0] <= 0;
+ if (ch_i_cc_reg_wen[1]) ch_i_cc_reg_wen[1] <= 0;
+ if (ch_i_cc_reg_wen[2]) ch_i_cc_reg_wen[2] <= 0;
+ if (ch_i_cc_reg_wen[3]) ch_i_cc_reg_wen[3] <= 0;
+ if (ch_i_cc_reg_wen[4]) ch_i_cc_reg_wen[4] <= 0;
+ if (ch_i_cc_reg_wen[5]) ch_i_cc_reg_wen[5] <= 0;
+ if (ch_i_cc_reg_wen[6]) ch_i_cc_reg_wen[6] <= 0;
+ if (ch_i_cc_reg_wen[7]) ch_i_cc_reg_wen[7] <= 0;
+ end // !if(write)
+ end // else: !if(rst)
+ end // always @ (posedge clk or posedge rst)
+
+endmodule // cct
trunk/verilog/scct.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/verilog/scct_channel.v
===================================================================
--- trunk/verilog/scct_channel.v (nonexistent)
+++ trunk/verilog/scct_channel.v (revision 2)
@@ -0,0 +1,159 @@
+// $Id$
+// Simple timer channel
+
+`include "scct_constants.v"
+
+module scct_channel (
+ clk, rst, counter, counter_changed,
+ icoc_select_i, icoc_select_i_wen,
+ icoc_action_i, icoc_action_i_wen,
+ i_cc_reg, i_cc_reg_wen,
+ irq_enable_i, irq_enable_i_wen,
+ irq_status_i, irq_status_i_wen,
+ force_oc_i, force_oc_i_wen,
+ icoc_select_o, icoc_action_o, cc_reg_o, irq_enable_o, irq_status_o,
+ pin_i, pin_o
+ );
+
+ input clk;
+ input rst;
+ input [`SCCT_COUNTER_CTR_WIDTH-1:0] counter;
+ input counter_changed;
+
+ // TODO: replace single-bit X_i, X_i_wen signals by a single signal
+ input icoc_select_i;
+ input icoc_select_i_wen;
+ input [1:0] icoc_action_i;
+ input icoc_action_i_wen;
+ input [`SCCT_COUNTER_CTR_WIDTH-1:0] i_cc_reg;
+ input i_cc_reg_wen;
+ input irq_enable_i;
+ input irq_enable_i_wen;
+ input irq_status_i; // write 1 to clear flag
+ input irq_status_i_wen;
+ input force_oc_i;
+ input force_oc_i_wen;
+
+ output icoc_select_o;
+ output [1:0] icoc_action_o;
+ output [`SCCT_COUNTER_CTR_WIDTH-1:0] cc_reg_o;
+ output irq_enable_o;
+ output irq_status_o;
+ input pin_i;
+ output pin_o;
+
+ reg outval;
+ reg icoc_select;
+ reg [1:0] icoc_action;
+ reg irq_enable;
+ reg irq_status;
+
+ reg icirq; // set when IC detects an edge that is interesting according to icoc_action
+ reg ocirq; // set when counter matches cc_reg
+ wire intistat;
+
+ // Capture/Compare Register
+ reg [`SCCT_COUNTER_CTR_WIDTH-1:0] cc_reg;
+ wire oc_match;
+
+ reg last_input_state;
+
+
+
+
+ assign icoc_select_o = icoc_select;
+ assign icoc_action_o = icoc_action;
+ assign cc_reg_o = cc_reg;
+ assign irq_enable_o = irq_enable;
+ assign irq_status_o = irq_status;
+
+
+ //assign pin = (icoc_select == `SCCT_CH_MS_IC) ? 1'bz : outval;
+ assign pin_o = outval;
+
+
+
+ assign intistat = (icoc_select == `SCCT_CH_MS_IC) ? icirq : ocirq;
+
+ assign oc_match = (cc_reg == counter) && counter_changed;
+
+
+ always @(posedge clk or posedge rst)
+ begin
+ if (rst)
+ begin
+ cc_reg <= `SCCT_COUNTER_CTR_WIDTH'b0;
+ icoc_select <= `SCCT_CH_MS_IC;
+ icoc_action <= `SCCT_IC_NONE;
+ irq_enable <= 1'b0;
+ icirq <= 1'b0;
+ ocirq <= 1'b0;
+ irq_status <= 1'b0;
+ outval <= 1'b0;
+ last_input_state <= 1'b0;
+ end
+ else
+ begin
+ // write
+ if (icoc_select_i_wen)
+ begin
+ icoc_select <= icoc_select_i;
+ // reset old irq states
+ case (icoc_select_i)
+ `SCCT_CH_MS_IC: icirq <= 0;
+ `SCCT_CH_MS_OC: ocirq <= 0;
+ endcase // case (icoc_select_i)
+ end
+ if (icoc_action_i_wen)
+ icoc_action <= icoc_action_i;
+ if (i_cc_reg_wen)
+ cc_reg <= i_cc_reg;
+ if (irq_enable_i_wen)
+ irq_enable <= irq_enable_i;
+ if ( (irq_status_i_wen) && (irq_status_i == 1) )
+ begin
+ icirq <= 0;
+ ocirq <= 0;
+ irq_status <= 0;
+ end
+ else
+ irq_status <= irq_enable ? intistat : 0;
+
+ //if (force_oc_i_wen)
+ //outval <= force_oc_i;
+
+ if (icoc_select == `SCCT_CH_MS_OC)
+ begin
+ if ( oc_match || (force_oc_i_wen && force_oc_i) )
+ begin
+ case (icoc_action)
+ `SCCT_OC_HIGH: outval = 1;
+ `SCCT_OC_LOW: outval = 0;
+ `SCCT_OC_TOGGLE: outval = !outval;
+ endcase
+ if (oc_match) ocirq <= 1;
+ end
+ end // if (icoc_select == `SCCT_CH_MS_OC)
+ else if (icoc_select == `SCCT_CH_MS_IC)
+ begin
+ if ( (icoc_action[`SCCT_IC_POSEDGE_BIT] == 1) && (last_input_state == 0) && (pin_i == 1) )
+ begin
+ cc_reg <= counter;
+ icirq <= 1;
+ end
+ else if ( (icoc_action[`SCCT_IC_NEGEDGE_BIT] == 1) && (last_input_state == 1) && (pin_i == 0) )
+ begin
+ cc_reg <= counter;
+ icirq <= 1;
+
+ end
+ end
+ last_input_state = pin_i;
+ end
+
+ end
+
+
+endmodule // channel
+
+
trunk/verilog/scct_channel.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/verilog/scct_constants.v
===================================================================
--- trunk/verilog/scct_constants.v (nonexistent)
+++ trunk/verilog/scct_constants.v (revision 2)
@@ -0,0 +1,61 @@
+// $Id$
+// Constants for the Simple Capture/Compare Timer (SCCT)
+
+`define SCCT_COUNTER_CTR_WIDTH 32
+//`define SCCT_COUNTER_CTR_ACT_WIDTH `SCCT_COUNTER_CTR_WIDTH+1
+//`define SCCT_COUNTER_CTR_MSB `SCCT_COUNTER_CTR_ACT_WIDTH-1
+`define SCCT_COUNTER_CTR_OV_BIT `SCCT_COUNTER_CTR_WIDTH
+`define SCCT_COUNTER_PSC_WIDTH 32
+
+// Channel modes
+`define SCCT_CH_MS_IC 1'b0
+`define SCCT_CH_MS_OC 1'b1
+
+// IC mode
+`define SCCT_IC_NONE 2'b00
+`define SCCT_IC_POSEDGE 2'b01
+`define SCCT_IC_NEGEDGE 2'b10
+`define SCCT_IC_ANYEDGE 2'b11
+// IC mode bits (only internally used)
+`define SCCT_IC_POSEDGE_BIT 0
+`define SCCT_IC_NEGEDGE_BIT 1
+
+// OC MODE
+`define SCCT_OC_NONE 2'b00
+`define SCCT_OC_HIGH 2'b01
+`define SCCT_OC_LOW 2'b10
+`define SCCT_OC_TOGGLE 2'b11
+
+`define SCCT_N_CHANNELS 8
+
+// Addresses
+`define SCCT_CTR 5'h00
+`define SCCT_PSC 5'h01
+`define SCCT_CTR_IE 5'h02
+`define SCCT_CTR_IS 5'h03
+
+`define SCCT_CH_MS 5'h08
+`define SCCT_CH_ACT 5'h09
+`define SCCT_CH_IE 5'h0a
+`define SCCT_CH_IS 5'h0b
+`define SCCT_CH_OCF 5'h0c
+`define SCCT_CH_INP 5'h0d
+`define SCCT_CH_OUT 5'h0e
+
+`define SCCT_CH_CCR0 5'h10
+`define SCCT_CH_CCR1 5'h11
+`define SCCT_CH_CCR2 5'h12
+`define SCCT_CH_CCR3 5'h13
+`define SCCT_CH_CCR4 5'h14
+`define SCCT_CH_CCR5 5'h15
+`define SCCT_CH_CCR6 5'h16
+`define SCCT_CH_CCR7 5'h17
+
+
+/*`define SCCT_
+`define SCCT_
+`define SCCT_
+`define SCCT_
+`define SCCT_
+`define SCCT_
+`define SCCT_*/
trunk/verilog/scct_constants.v
Property changes :
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property
Index: trunk/mkch.pl
===================================================================
--- trunk/mkch.pl (nonexistent)
+++ trunk/mkch.pl (revision 2)
@@ -0,0 +1,61 @@
+#!/usr/bin/perl
+# $Id$
+# Create channel declarations
+
+use strict;
+use warnings;
+
+
+my ($nChannels) = @ARGV;
+
+if (not defined $nChannels) {
+ die "Need number of channels to create!\n";
+}
+
+if (!($nChannels =~ /^\d+$/)) {
+ die "Script needs a positive integer\n";
+}
+
+print " // Channel definitions were created with $0\n";
+
+my @channel = ;
+
+for (my $i = 0; $i < $nChannels; $i++) {
+ print "\n // Channel $i\n";
+ my $N = $i;
+ my $TN = $i * 2;
+ my $TNPO = $TN + 1;
+ foreach my $line (@channel) {
+ my $out = $line;
+ $out =~ s/(\$\w+(?:::\w+)*)/"defined $1 ? $1 : ''"/gee;
+ print $out;
+ }
+}
+
+
+__DATA__
+ scct_channel channel$N(
+ .clk(clk),
+ .rst(rst),
+ .counter(counter),
+ .counter_changed(ctr_counter_changed),
+ .icoc_select_i(ch_icoc_select_i[$N]),
+ .icoc_select_i_wen(ch_icoc_select_i_wen),
+ .icoc_action_i(ch_icoc_action_i[$TNPO:$TN]),
+ .icoc_action_i_wen(ch_icoc_action_i_wen),
+ .i_cc_reg(ch_i_cc_reg[$N]),
+ .i_cc_reg_wen(ch_i_cc_reg_wen[$N]),
+ .irq_enable_i(ch_irq_enable_i[$N]),
+ .irq_enable_i_wen(ch_irq_enable_i_wen),
+ .irq_status_i(ch_irq_status_i[$N]),
+ .irq_status_i_wen(ch_irq_status_i_wen),
+ .force_oc_i(ch_force_oc_i[$N]),
+ .force_oc_i_wen(ch_force_oc_i_wen),
+ .icoc_select_o(ch_icoc_select_o[$N]),
+ .icoc_action_o(ch_icoc_action_o[$TNPO:$TN]),
+ .cc_reg_o(ch_cc_reg_o[$N]),
+ .irq_enable_o(ch_irq_enable_o[$N]),
+ .irq_status_o(ch_irq_status_o[$N]),
+ .pin_i(pins_i[$N]),
+ .pin_o(pins_o[$N])
+ );
trunk/mkch.pl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+Id
\ No newline at end of property