OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

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/sdcard_mass_storage_controller/hooks/pre-revprop-change.tmpl
0,0 → 1,66
#!/bin/sh
 
# PRE-REVPROP-CHANGE HOOK
#
# The pre-revprop-change hook is invoked before a revision property
# is added, modified or deleted. Subversion runs this hook by invoking
# a program (script, executable, binary, etc.) named 'pre-revprop-change'
# (for which this file is a template), with the following ordered
# arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] REVISION (the revision being tweaked)
# [3] USER (the username of the person tweaking the property)
# [4] PROPNAME (the property being set on the revision)
# [5] ACTION (the property is being 'A'dded, 'M'odified, or 'D'eleted)
#
# [STDIN] PROPVAL ** the new property value is passed via STDIN.
#
# If the hook program exits with success, the propchange happens; but
# if it exits with failure (non-zero), the propchange doesn't happen.
# The hook program can use the 'svnlook' utility to examine the
# existing value of the revision property.
#
# WARNING: unlike other hooks, this hook MUST exist for revision
# properties to be changed. If the hook does not exist, Subversion
# will behave as if the hook were present, but failed. The reason
# for this is that revision properties are UNVERSIONED, meaning that
# a successful propchange is destructive; the old value is gone
# forever. We recommend the hook back up the old value somewhere.
#
# On a Unix system, the normal procedure is to have 'pre-revprop-change'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'pre-revprop-change' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'pre-revprop-change.bat' or 'pre-revprop-change.exe',
# but the basic idea is the same.
#
# The hook program typically does not inherit the environment of
# its parent process. For example, a common problem is for the
# PATH environment variable to not be set to its usual value, so
# that subprograms fail to launch unless invoked via absolute path.
# If you're having unexpected problems with a hook program, the
# culprit may be unusual (or missing) environment variables.
#
# Here is an example hook script, for a Unix /bin/sh interpreter.
# For more examples and pre-written hooks, see those in
# the Subversion repository at
# http://svn.collab.net/repos/svn/trunk/tools/hook-scripts/ and
# http://svn.collab.net/repos/svn/trunk/contrib/hook-scripts/
 
 
REPOS="$1"
REV="$2"
USER="$3"
PROPNAME="$4"
ACTION="$5"
 
if [ "$ACTION" = "M" -a "$PROPNAME" = "svn:log" ]; then exit 0; fi
 
echo "Changing revision properties other than svn:log is prohibited" >&2
exit 1
/sdcard_mass_storage_controller/hooks/post-commit.tmpl
0,0 → 1,50
#!/bin/sh
 
# POST-COMMIT HOOK
#
# The post-commit hook is invoked after a commit. Subversion runs
# this hook by invoking a program (script, executable, binary, etc.)
# named 'post-commit' (for which this file is a template) with the
# following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] REV (the number of the revision just committed)
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# Because the commit has already completed and cannot be undone,
# the exit code of the hook program is ignored. The hook program
# can use the 'svnlook' utility to help it examine the
# newly-committed tree.
#
# On a Unix system, the normal procedure is to have 'post-commit'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'post-commit' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'post-commit.bat' or 'post-commit.exe',
# but the basic idea is the same.
#
# The hook program typically does not inherit the environment of
# its parent process. For example, a common problem is for the
# PATH environment variable to not be set to its usual value, so
# that subprograms fail to launch unless invoked via absolute path.
# If you're having unexpected problems with a hook program, the
# culprit may be unusual (or missing) environment variables.
#
# Here is an example hook script, for a Unix /bin/sh interpreter.
# For more examples and pre-written hooks, see those in
# the Subversion repository at
# http://svn.collab.net/repos/svn/trunk/tools/hook-scripts/ and
# http://svn.collab.net/repos/svn/trunk/contrib/hook-scripts/
 
 
REPOS="$1"
REV="$2"
 
mailer.py commit "$REPOS" "$REV" /path/to/mailer.conf
/sdcard_mass_storage_controller/hooks/post-lock.tmpl
0,0 → 1,44
#!/bin/sh
 
# POST-LOCK HOOK
#
# The post-lock hook is run after a path is locked. Subversion runs
# this hook by invoking a program (script, executable, binary, etc.)
# named 'post-lock' (for which this file is a template) with the
# following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] USER (the user who created the lock)
#
# The paths that were just locked are passed to the hook via STDIN (as
# of Subversion 1.2, only one path is passed per invocation, but the
# plan is to pass all locked paths at once, so the hook program
# should be written accordingly).
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# Because the lock has already been created and cannot be undone,
# the exit code of the hook program is ignored. The hook program
# can use the 'svnlook' utility to help it examine the
# newly-created lock.
#
# On a Unix system, the normal procedure is to have 'post-lock'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'post-lock' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'post-lock.bat' or 'post-lock.exe',
# but the basic idea is the same.
#
# Here is an example hook script, for a Unix /bin/sh interpreter:
 
REPOS="$1"
USER="$2"
 
# Send email to interested parties, let them know a lock was created:
mailer.py lock "$REPOS" "$USER" /path/to/mailer.conf
/sdcard_mass_storage_controller/hooks/pre-commit.tmpl
0,0 → 1,81
#!/bin/sh
 
# PRE-COMMIT HOOK
#
# The pre-commit hook is invoked before a Subversion txn is
# committed. Subversion runs this hook by invoking a program
# (script, executable, binary, etc.) named 'pre-commit' (for which
# this file is a template), with the following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] TXN-NAME (the name of the txn about to be committed)
#
# [STDIN] LOCK-TOKENS ** the lock tokens are passed via STDIN.
#
# If STDIN contains the line "LOCK-TOKENS:\n" (the "\n" denotes a
# single newline), the lines following it are the lock tokens for
# this commit. The end of the list is marked by a line containing
# only a newline character.
#
# Each lock token line consists of a URI-escaped path, followed
# by the separator character '|', followed by the lock token string,
# followed by a newline.
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# If the hook program exits with success, the txn is committed; but
# if it exits with failure (non-zero), the txn is aborted, no commit
# takes place, and STDERR is returned to the client. The hook
# program can use the 'svnlook' utility to help it examine the txn.
#
# On a Unix system, the normal procedure is to have 'pre-commit'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# *** NOTE: THE HOOK PROGRAM MUST NOT MODIFY THE TXN, EXCEPT ***
# *** FOR REVISION PROPERTIES (like svn:log or svn:author). ***
#
# This is why we recommend using the read-only 'svnlook' utility.
# In the future, Subversion may enforce the rule that pre-commit
# hooks should not modify the versioned data in txns, or else come
# up with a mechanism to make it safe to do so (by informing the
# committing client of the changes). However, right now neither
# mechanism is implemented, so hook writers just have to be careful.
#
# Note that 'pre-commit' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'pre-commit.bat' or 'pre-commit.exe',
# but the basic idea is the same.
#
# The hook program typically does not inherit the environment of
# its parent process. For example, a common problem is for the
# PATH environment variable to not be set to its usual value, so
# that subprograms fail to launch unless invoked via absolute path.
# If you're having unexpected problems with a hook program, the
# culprit may be unusual (or missing) environment variables.
#
# Here is an example hook script, for a Unix /bin/sh interpreter.
# For more examples and pre-written hooks, see those in
# the Subversion repository at
# http://svn.collab.net/repos/svn/trunk/tools/hook-scripts/ and
# http://svn.collab.net/repos/svn/trunk/contrib/hook-scripts/
 
 
REPOS="$1"
TXN="$2"
 
# Make sure that the log message contains some text.
SVNLOOK=/usr/local/bin/svnlook
$SVNLOOK log -t "$TXN" "$REPOS" | \
grep "[a-zA-Z0-9]" > /dev/null || exit 1
 
# Check that the author of this commit has the rights to perform
# the commit on the files and directories being modified.
commit-access-control.pl "$REPOS" "$TXN" commit-access-control.cfg || exit 1
 
# All checks passed, so allow the commit.
exit 0
/sdcard_mass_storage_controller/hooks/pre-lock.tmpl
0,0 → 1,71
#!/bin/sh
 
# PRE-LOCK HOOK
#
# The pre-lock hook is invoked before an exclusive lock is
# created. Subversion runs this hook by invoking a program
# (script, executable, binary, etc.) named 'pre-lock' (for which
# this file is a template), with the following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] PATH (the path in the repository about to be locked)
# [3] USER (the user creating the lock)
# [4] COMMENT (the comment of the lock)
# [5] STEAL-LOCK (1 if the user is trying to steal the lock, else 0)
#
# If the hook program outputs anything on stdout, the output string will
# be used as the lock token for this lock operation. If you choose to use
# this feature, you must guarantee the tokens generated are unique across
# the repository each time.
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# If the hook program exits with success, the lock is created; but
# if it exits with failure (non-zero), the lock action is aborted
# and STDERR is returned to the client.
 
# On a Unix system, the normal procedure is to have 'pre-lock'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'pre-lock' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'pre-lock.bat' or 'pre-lock.exe',
# but the basic idea is the same.
#
# Here is an example hook script, for a Unix /bin/sh interpreter:
 
REPOS="$1"
PATH="$2"
USER="$3"
 
# If a lock exists and is owned by a different person, don't allow it
# to be stolen (e.g., with 'svn lock --force ...').
 
# (Maybe this script could send email to the lock owner?)
SVNLOOK=/usr/local/bin/svnlook
GREP=/bin/grep
SED=/bin/sed
 
LOCK_OWNER=`$SVNLOOK lock "$REPOS" "$PATH" | \
$GREP '^Owner: ' | $SED 's/Owner: //'`
 
# If we get no result from svnlook, there's no lock, allow the lock to
# happen:
if [ "$LOCK_OWNER" = "" ]; then
exit 0
fi
 
# If the person locking matches the lock's owner, allow the lock to
# happen:
if [ "$LOCK_OWNER" = "$USER" ]; then
exit 0
fi
 
# Otherwise, we've got an owner mismatch, so return failure:
echo "Error: $PATH already locked by ${LOCK_OWNER}." 1>&2
exit 1
/sdcard_mass_storage_controller/hooks/post-unlock.tmpl
0,0 → 1,42
#!/bin/sh
 
# POST-UNLOCK HOOK
#
# The post-unlock hook runs after a path is unlocked. Subversion runs
# this hook by invoking a program (script, executable, binary, etc.)
# named 'post-unlock' (for which this file is a template) with the
# following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] USER (the user who destroyed the lock)
#
# The paths that were just unlocked are passed to the hook via STDIN
# (as of Subversion 1.2, only one path is passed per invocation, but
# the plan is to pass all unlocked paths at once, so the hook program
# should be written accordingly).
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# Because the lock has already been destroyed and cannot be undone,
# the exit code of the hook program is ignored.
#
# On a Unix system, the normal procedure is to have 'post-unlock'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'post-unlock' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'post-unlock.bat' or 'post-unlock.exe',
# but the basic idea is the same.
#
# Here is an example hook script, for a Unix /bin/sh interpreter:
 
REPOS="$1"
USER="$2"
 
# Send email to interested parties, let them know a lock was removed:
mailer.py unlock "$REPOS" "$USER" /path/to/mailer.conf
/sdcard_mass_storage_controller/hooks/pre-unlock.tmpl
0,0 → 1,63
#!/bin/sh
 
# PRE-UNLOCK HOOK
#
# The pre-unlock hook is invoked before an exclusive lock is
# destroyed. Subversion runs this hook by invoking a program
# (script, executable, binary, etc.) named 'pre-unlock' (for which
# this file is a template), with the following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] PATH (the path in the repository about to be unlocked)
# [3] USER (the user destroying the lock)
# [4] TOKEN (the lock token to be destroyed)
# [5] BREAK-UNLOCK (1 if the user is breaking the lock, else 0)
#
# The default working directory for the invocation is undefined, so
# the program should set one explicitly if it cares.
#
# If the hook program exits with success, the lock is destroyed; but
# if it exits with failure (non-zero), the unlock action is aborted
# and STDERR is returned to the client.
 
# On a Unix system, the normal procedure is to have 'pre-unlock'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'pre-unlock' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'pre-unlock.bat' or 'pre-unlock.exe',
# but the basic idea is the same.
#
# Here is an example hook script, for a Unix /bin/sh interpreter:
 
REPOS="$1"
PATH="$2"
USER="$3"
 
# If a lock is owned by a different person, don't allow it be broken.
# (Maybe this script could send email to the lock owner?)
 
SVNLOOK=/usr/local/bin/svnlook
GREP=/bin/grep
SED=/bin/sed
 
LOCK_OWNER=`$SVNLOOK lock "$REPOS" "$PATH" | \
$GREP '^Owner: ' | $SED 's/Owner: //'`
 
# If we get no result from svnlook, there's no lock, return success:
if [ "$LOCK_OWNER" = "" ]; then
exit 0
fi
 
# If the person unlocking matches the lock's owner, return success:
if [ "$LOCK_OWNER" = "$USER" ]; then
exit 0
fi
 
# Otherwise, we've got an owner mismatch, so return failure:
echo "Error: $PATH locked by ${LOCK_OWNER}." 1>&2
exit 1
/sdcard_mass_storage_controller/hooks/post-revprop-change.tmpl
0,0 → 1,56
#!/bin/sh
 
# POST-REVPROP-CHANGE HOOK
#
# The post-revprop-change hook is invoked after a revision property
# has been added, modified or deleted. Subversion runs this hook by
# invoking a program (script, executable, binary, etc.) named
# 'post-revprop-change' (for which this file is a template), with the
# following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] REV (the revision that was tweaked)
# [3] USER (the username of the person tweaking the property)
# [4] PROPNAME (the property that was changed)
# [5] ACTION (the property was 'A'dded, 'M'odified, or 'D'eleted)
#
# [STDIN] PROPVAL ** the old property value is passed via STDIN.
#
# Because the propchange has already completed and cannot be undone,
# the exit code of the hook program is ignored. The hook program
# can use the 'svnlook' utility to help it examine the
# new property value.
#
# On a Unix system, the normal procedure is to have 'post-revprop-change'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'post-revprop-change' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'post-revprop-change.bat' or 'post-revprop-change.exe',
# but the basic idea is the same.
#
# The hook program typically does not inherit the environment of
# its parent process. For example, a common problem is for the
# PATH environment variable to not be set to its usual value, so
# that subprograms fail to launch unless invoked via absolute path.
# If you're having unexpected problems with a hook program, the
# culprit may be unusual (or missing) environment variables.
#
# Here is an example hook script, for a Unix /bin/sh interpreter.
# For more examples and pre-written hooks, see those in
# the Subversion repository at
# http://svn.collab.net/repos/svn/trunk/tools/hook-scripts/ and
# http://svn.collab.net/repos/svn/trunk/contrib/hook-scripts/
 
 
REPOS="$1"
REV="$2"
USER="$3"
PROPNAME="$4"
ACTION="$5"
 
mailer.py propchange2 "$REPOS" "$REV" "$USER" "$PROPNAME" "$ACTION" /path/to/mailer.conf
/sdcard_mass_storage_controller/hooks/start-commit.tmpl
0,0 → 1,65
#!/bin/sh
 
# START-COMMIT HOOK
#
# The start-commit hook is invoked before a Subversion txn is created
# in the process of doing a commit. Subversion runs this hook
# by invoking a program (script, executable, binary, etc.) named
# 'start-commit' (for which this file is a template)
# with the following ordered arguments:
#
# [1] REPOS-PATH (the path to this repository)
# [2] USER (the authenticated user attempting to commit)
# [3] CAPABILITIES (a colon-separated list of capabilities reported
# by the client; see note below)
#
# Note: The CAPABILITIES parameter is new in Subversion 1.5, and 1.5
# clients will typically report at least the "mergeinfo" capability.
# If there are other capabilities, then the list is colon-separated,
# e.g.: "mergeinfo:some-other-capability" (the order is undefined).
#
# The list is self-reported by the client. Therefore, you should not
# make security assumptions based on the capabilities list, nor should
# you assume that clients reliably report every capability they have.
#
# The working directory for this hook program's invocation is undefined,
# so the program should set one explicitly if it cares.
#
# If the hook program exits with success, the commit continues; but
# if it exits with failure (non-zero), the commit is stopped before
# a Subversion txn is created, and STDERR is returned to the client.
#
# On a Unix system, the normal procedure is to have 'start-commit'
# invoke other programs to do the real work, though it may do the
# work itself too.
#
# Note that 'start-commit' must be executable by the user(s) who will
# invoke it (typically the user httpd runs as), and that user must
# have filesystem-level permission to access the repository.
#
# On a Windows system, you should name the hook program
# 'start-commit.bat' or 'start-commit.exe',
# but the basic idea is the same.
#
# The hook program typically does not inherit the environment of
# its parent process. For example, a common problem is for the
# PATH environment variable to not be set to its usual value, so
# that subprograms fail to launch unless invoked via absolute path.
# If you're having unexpected problems with a hook program, the
# culprit may be unusual (or missing) environment variables.
#
# Here is an example hook script, for a Unix /bin/sh interpreter.
# For more examples and pre-written hooks, see those in
# the Subversion repository at
# http://svn.collab.net/repos/svn/trunk/tools/hook-scripts/ and
# http://svn.collab.net/repos/svn/trunk/contrib/hook-scripts/
 
 
REPOS="$1"
USER="$2"
 
commit-allower.pl --repository "$REPOS" --user "$USER" || exit 1
special-auth-check.py --user "$USER" --auth-level 3 || exit 1
 
# All checks passed, so allow the commit.
exit 0
/sdcard_mass_storage_controller/conf/svnserve.conf
0,0 → 1,47
### This file controls the configuration of the svnserve daemon, if you
### use it to allow access to this repository. (If you only allow
### access through http: and/or file: URLs, then this file is
### irrelevant.)
 
### Visit http://subversion.tigris.org/ for more information.
 
[general]
### These options control access to the repository for unauthenticated
### and authenticated users. Valid values are "write", "read",
### and "none". The sample settings below are the defaults.
# anon-access = read
# auth-access = write
### The password-db option controls the location of the password
### database file. Unless you specify a path starting with a /,
### the file's location is relative to the directory containing
### this configuration file.
### If SASL is enabled (see below), this file will NOT be used.
### Uncomment the line below to use the default password file.
# password-db = passwd
### The authz-db option controls the location of the authorization
### rules for path-based access control. Unless you specify a path
### starting with a /, the file's location is relative to the the
### directory containing this file. If you don't specify an
### authz-db, no path-based access control is done.
### Uncomment the line below to use the default authorization file.
# authz-db = authz
### This option specifies the authentication realm of the repository.
### If two repositories have the same authentication realm, they should
### have the same password database, and vice versa. The default realm
### is repository's uuid.
# realm = My First Repository
 
[sasl]
### This option specifies whether you want to use the Cyrus SASL
### library for authentication. Default is false.
### This section will be ignored if svnserve is not built with Cyrus
### SASL support; to check, run 'svnserve --version' and look for a line
### reading 'Cyrus SASL authentication is available.'
# use-sasl = true
### These options specify the desired strength of the security layer
### that you want SASL to provide. 0 means no encryption, 1 means
### integrity-checking only, values larger than 1 are correlated
### to the effective key length for encryption (e.g. 128 means 128-bit
### encryption). The values below are the defaults.
# min-encryption = 0
# max-encryption = 256
/sdcard_mass_storage_controller/conf/passwd
0,0 → 1,8
### This file is an example password file for svnserve.
### Its format is similar to that of svnserve.conf. As shown in the
### example below it contains one section labelled [users].
### The name and password for each user follow, one account per line.
 
[users]
# harry = harryssecret
# sally = sallyssecret
/sdcard_mass_storage_controller/conf/authz
0,0 → 1,32
### This file is an example authorization file for svnserve.
### Its format is identical to that of mod_authz_svn authorization
### files.
### As shown below each section defines authorizations for the path and
### (optional) repository specified by the section name.
### The authorizations follow. An authorization line can refer to:
### - a single user,
### - a group of users defined in a special [groups] section,
### - an alias defined in a special [aliases] section,
### - all authenticated users, using the '$authenticated' token,
### - only anonymous users, using the '$anonymous' token,
### - anyone, using the '*' wildcard.
###
### A match can be inverted by prefixing the rule with '~'. Rules can
### grant read ('r') access, read-write ('rw') access, or no access
### ('').
 
[aliases]
# joe = /C=XZ/ST=Dessert/L=Snake City/O=Snake Oil, Ltd./OU=Research Institute/CN=Joe Average
 
[groups]
# harry_and_sally = harry,sally
# harry_sally_and_joe = harry,sally,&joe
 
# [/foo/bar]
# harry = rw
# &joe = r
# * =
 
# [repository:/baz/fuz]
# @harry_and_sally = rw
# * = r
/sdcard_mass_storage_controller/db/revs/0/0
0,0 → 1,11
PLAIN
END
ENDREP
id: 0.0.r0/17
type: dir
count: 0
text: 0 0 4 4 2d2977d1c96f487abe4a1e202dd03b4e
cpath: /
 
 
17 107
/sdcard_mass_storage_controller/db/txn-current-lock --- sdcard_mass_storage_controller/db/revprops/0/0 (nonexistent) +++ sdcard_mass_storage_controller/db/revprops/0/0 (revision 11) @@ -0,0 +1,5 @@ +K 8 +svn:date +V 27 +2009-04-21T08:43:20.416158Z +END
/sdcard_mass_storage_controller/db/write-lock --- sdcard_mass_storage_controller/db/current (nonexistent) +++ sdcard_mass_storage_controller/db/current (revision 11) @@ -0,0 +1 @@ +0
/sdcard_mass_storage_controller/db/fsfs.conf
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### This file controls the configuration of the FSFS filesystem.
 
[memcached-servers]
### These options name memcached servers used to cache internal FSFS
### data. See http://www.danga.com/memcached/ for more information on
### memcached. To use memcached with FSFS, run one or more memcached
### servers, and specify each of them as an option like so:
# first-server = 127.0.0.1:11211
# remote-memcached = mymemcached.corp.example.com:11212
### The option name is ignored; the value is of the form HOST:PORT.
### memcached servers can be shared between multiple repositories;
### however, if you do this, you *must* ensure that repositories have
### distinct UUIDs and paths, or else cached data from one repository
### might be used by another accidentally. Note also that memcached has
### no authentication for reads or writes, so you must ensure that your
### memcached servers are only accessible by trusted users.
 
[caches]
### When a cache-related error occurs, normally Subversion ignores it
### and continues, logging an error if the server is appropriately
### configured (and ignoring it with file:// access). To make
### Subversion never ignore cache errors, uncomment this line.
# fail-stop = true
 
[rep-sharing]
### To conserve space, the filesystem can optionally avoid storing
### duplicate representations. This comes at a slight cost in performace,
### as maintaining a database of shared representations can increase
### commit times. The space savings are dependent upon the size of the
### repository, the number of objects it contains and the amount of
### duplication between them, usually a function of the branching and
### merging process.
###
### The following parameter enables rep-sharing in the repository. It can
### be switched on and off at will, but for best space-saving results
### should be enabled consistently over the life of the repository.
# enable-rep-sharing = false
/sdcard_mass_storage_controller/db/min-unpacked-rev
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/sdcard_mass_storage_controller/db/uuid
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61037e47-8125-3e46-9efb-f0094a60d259
/sdcard_mass_storage_controller/db/fs-type
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fsfs
/sdcard_mass_storage_controller/db/format
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4
layout sharded 1000
/sdcard_mass_storage_controller/db/txn-current
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/sdcard_mass_storage_controller/db/rep-cache.db Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/sdcard_mass_storage_controller/db/rep-cache.db
sdcard_mass_storage_controller/db/rep-cache.db Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/format =================================================================== --- sdcard_mass_storage_controller/format (nonexistent) +++ sdcard_mass_storage_controller/format (revision 11) @@ -0,0 +1 @@ +5 Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_data_phy.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_data_phy.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_data_phy.v (revision 11) @@ -0,0 +1,444 @@ +//------------------------- +//------------------------- + + + + +`include "SD_defines.v" +`define BUFFER_OFFSET 2 + +module sd_data_phy( +input sd_clk, +input rst, +output reg DAT_oe_o, +output reg[3:0] DAT_dat_o, +input [3:0] DAT_dat_i, + +output [1:0] sd_adr_o, +input [7:0] sd_dat_i, +output reg [7:0] sd_dat_o, +output reg sd_we_o, +output reg sd_re_o, +input [3:4] fifo_full, +input [3:4] fifo_empty, +input [1:0] start_dat, +input fifo_acces + +); + reg [5:0] in_buff_ptr_read; + reg [5:0] out_buff_ptr_read; + reg crc_ok; + reg [3:0] last_din_read; + + + +reg [7:0] tmp_crc_token ; +reg[2:0] crc_read_count; + +//CRC16 +reg [3:0] crc_in_write; +reg crc_en_write; +reg crc_rst_write; +wire [15:0] crc_out_write [3:0]; + +reg [3:0] crc_in_read; +reg crc_en_read; +reg crc_rst_read; +wire [15:0] crc_out_read [3:0]; + + reg[7:0] next_out; + reg data_read_index; + +reg [10:0] transf_cnt_write; +reg [10:0] transf_cnt_read; +parameter SIZE = 6; +reg [SIZE-1:0] state; +reg [SIZE-1:0] next_state; +parameter IDLE = 6'b000001; +parameter WRITE_DAT = 6'b000010; +parameter READ_CRC = 6'b000100; +parameter WRITE_CRC = 6'b001000; +parameter READ_WAIT = 6'b010000; +parameter READ_DAT = 6'b100000; + +reg in_dat_buffer_empty; +reg [2:0] crc_status_token; +reg busy_int; +reg add_token; +genvar i; +generate +for(i=0; i<4; i=i+1) begin:CRC_16_gen_write + CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]); +end +endgenerate + + +generate +for(i=0; i<4; i=i+1) begin:CRC_16_gen_read + CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]); +end +endgenerate + + + +reg q_start_bit; + +always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty ) +begin : FSM_COMBO + next_state = 0; +case(state) + IDLE: begin + if (start_dat == 2'b01) + next_state=WRITE_DAT; + else if (start_dat == 2'b10) + next_state=READ_WAIT; + else + next_state=IDLE; + end + WRITE_DAT: begin + if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET) + next_state= READ_CRC; + else if (start_dat == 2'b11) + next_state=IDLE; + else + next_state=WRITE_DAT; + end + + READ_WAIT: begin + if (DAT_dat_i[0]== 0 ) + next_state= READ_DAT; + else + next_state=READ_WAIT; + end + + + READ_CRC: begin + if ( (crc_read_count == 3'b111) &&(busy_int ==1) ) + next_state= WRITE_CRC; + else + next_state=READ_CRC; + end + WRITE_CRC: begin + + next_state= IDLE; + + end + + + + READ_DAT: begin + if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) //Startbit consumed... + next_state= IDLE; + else if (start_dat == 2'b11) + next_state=IDLE; + else + next_state=READ_DAT; + end + endcase +end + +always @ (posedge sd_clk or posedge rst ) + begin + if (rst ) begin + q_start_bit<=1; + end + else begin + q_start_bit <= DAT_dat_i[0]; + end +end + + +//----------------Seq logic------------ +always @ (posedge sd_clk or posedge rst ) +begin : FSM_SEQ + if (rst ) begin + state <= #1 IDLE; + end + else begin + state <= #1 next_state; + end +end + +reg [4:0] crc_cnt_write; +reg [4:0]crc_cnt_read; +reg [3:0] last_din; +reg [2:0] crc_s ; +reg [7:0] write_buf_0,write_buf_1, sd_data_out; +reg out_buff_ptr,in_buff_ptr; +reg data_send_index; +reg [1:0] sd_adr_o_read; +reg [1:0] sd_adr_o_write; + + +reg read_byte_cnt; +assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write; + + + + +assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write; + +reg [3:0] in_dat_buffer [63:0]; + +always @ (negedge sd_clk or posedge rst ) +begin +if (rst) begin + DAT_oe_o<=0; + crc_en_write<=0; + crc_rst_write<=1; + transf_cnt_write<=0; + crc_cnt_write<=15; + crc_status_token<=7; + + data_send_index<=0; + out_buff_ptr<=0; + in_buff_ptr<=0; + read_byte_cnt<=0; + write_buf_0<=0; + write_buf_1<=0; + sd_re_o<=0; + sd_data_out<=0; + sd_adr_o_write<=0; + crc_in_write<=0; + DAT_dat_o<=0; + last_din<=0; +end +else begin + case(state) + IDLE: begin + DAT_oe_o<=0; + crc_en_write<=0; + crc_rst_write<=1; + crc_cnt_write<=16; + read_byte_cnt<=0; + + crc_status_token<=7; + data_send_index<=0; + out_buff_ptr<=0; + in_buff_ptr<=0; + sd_re_o<=0; + transf_cnt_write<=0; + + end + WRITE_DAT: begin + + transf_cnt_write<=transf_cnt_write+1; + + + if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin + read_byte_cnt<=read_byte_cnt+1; + sd_re_o<=0; + case (read_byte_cnt) + 0:begin + sd_adr_o_write <=2; + sd_re_o<=1; + end + 1:begin + if (!in_buff_ptr) + write_buf_0<=sd_dat_i; + else + write_buf_1 <=sd_dat_i; + in_buff_ptr<=in_buff_ptr+1; + end + endcase + end + + if (!out_buff_ptr) + sd_data_out<=write_buf_0; + else + sd_data_out<=write_buf_1; + + if (transf_cnt_write==1+`BUFFER_OFFSET) begin + + crc_rst_write<=0; + crc_en_write<=1; + last_din <=write_buf_0[3:0]; + DAT_oe_o<=1; + DAT_dat_o<=0; + crc_in_write<= write_buf_0[3:0]; + data_send_index<=1; + out_buff_ptr<=out_buff_ptr+1; + end + else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin + DAT_oe_o<=1; + case (data_send_index) + 0:begin + last_din <=sd_data_out[3:0]; + crc_in_write <=sd_data_out[3:0]; + out_buff_ptr<=out_buff_ptr+1; + end + 1:begin + last_din <=sd_data_out[7:4]; + crc_in_write <=sd_data_out[7:4]; + end + + endcase + data_send_index<=data_send_index+1; + + DAT_dat_o<= last_din; + + if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin + crc_en_write<=0; + end + end + else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin + + crc_en_write<=0; + crc_cnt_write<=crc_cnt_write-1; + DAT_oe_o<=1; + DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1]; + DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1]; + DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1]; + DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1]; + end + else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin + DAT_oe_o<=1; + DAT_dat_o<=4'b1111; + + end + else if (transf_cnt_write !=0) begin + DAT_oe_o<=0; + end + + + end + + + endcase +end +end + + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + add_token<=0; + sd_adr_o_read<=0; + crc_read_count<=0; + sd_we_o<=0; + tmp_crc_token<=0; + crc_rst_read<=0; + crc_en_read<=0; + in_buff_ptr_read<=0; + out_buff_ptr_read<=0; + crc_cnt_read<=0; + transf_cnt_read<=0; + data_read_index<=0; + in_dat_buffer_empty<=0; + + next_out<=0; + busy_int<=0; + sd_dat_o<=0; + end + else begin + case(state) + IDLE: begin + add_token<=0; + crc_read_count<=0; + sd_we_o<=0; + tmp_crc_token<=0; + crc_rst_read<=1; + crc_en_read<=0; + in_buff_ptr_read<=0; + out_buff_ptr_read<=0; + crc_cnt_read<=15; + transf_cnt_read<=0; + data_read_index<=0; + in_dat_buffer_empty<=0; + end + + READ_DAT: begin + add_token<=1; + crc_rst_read<=0; + crc_en_read<=1; + + + + if (fifo_acces) begin + if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin + data_read_index<=~data_read_index; + case(data_read_index) + 0: begin + sd_adr_o_read<=3; + sd_we_o<=0; + next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ]; + next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ]; + end + 1: begin + out_buff_ptr_read<=out_buff_ptr_read+2; + sd_dat_o<=next_out; + sd_we_o<=1; + end + endcase + end + else + in_dat_buffer_empty<=1; + end + + if (transf_cnt_read<`BIT_BLOCK_REC) begin + + in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i; + crc_in_read<=DAT_dat_i; + crc_ok<=1; + transf_cnt_read<=transf_cnt_read+1; + in_buff_ptr_read<=in_buff_ptr_read+1; + end + else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin + transf_cnt_read<=transf_cnt_read+1; + crc_en_read<=0; + last_din_read <=DAT_dat_i; + + if (transf_cnt_read> `BIT_BLOCK_REC) begin + crc_cnt_read <=crc_cnt_read-1; + + + if (crc_out_read[0][crc_cnt_read] != last_din[0]) + crc_ok<=0; + if (crc_out_read[1][crc_cnt_read] != last_din[1]) + crc_ok<=0; + if (crc_out_read[2][crc_cnt_read] != last_din[2]) + crc_ok<=0; + if (crc_out_read[3][crc_cnt_read] != last_din[3]) + crc_ok<=0; + + if (crc_cnt_read==0) begin + //in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok} + end + end + end + + + + end + READ_CRC: begin + if (crc_read_count<3'b111) begin + crc_read_count<=crc_read_count+1; + tmp_crc_token[crc_read_count] <= DAT_dat_i[0]; + end + + busy_int <=DAT_dat_i[0]; + + end + WRITE_CRC: begin + add_token<=1; + sd_adr_o_read<=3; + sd_we_o<=1; + sd_dat_o<=tmp_crc_token; + end + + endcase +end + +end +//Sync + + + + + + + +endmodule + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/versatile_fifo_dptam_dw.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/versatile_fifo_dptam_dw.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/versatile_fifo_dptam_dw.v (revision 11) @@ -0,0 +1,47 @@ +module versatile_fifo_dptam_dw + ( + d_a, + q_a, + adr_a, + we_a, + clk_a, + q_b, + adr_b, + d_b, + we_b, + clk_b + ); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 14; + input [(DATA_WIDTH-1):0] d_a; + input [(ADDR_WIDTH-1):0] adr_a; + input [(ADDR_WIDTH-1):0] adr_b; + input we_a; + output reg[(DATA_WIDTH-1):0] q_b; + input [(DATA_WIDTH-1):0] d_b; + output reg [(DATA_WIDTH-1):0] q_a; + input we_b; + input clk_a, clk_b; + + reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ; + always @ (posedge clk_a) + begin + q_a <= ram[adr_a]; + if (we_a) begin + ram[adr_a] <= d_a; + + end +end + always @ (posedge clk_b) + begin + q_b <= ram[adr_b]; + if (we_b) + begin + ram[adr_b] <= d_b; + + end + + + end +endmodule + \ No newline at end of file Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_16.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_16.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_16.v (revision 11) @@ -0,0 +1,46 @@ +// ========================================================================== +// CRC Generation Unit - Linear Feedback Shift Register implementation +// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL +// https://www.ghsi.de/CRC/index.php? +// ========================================================================= +module CRC_16(BITVAL, Enable, CLK, RST, CRC); + input BITVAL;// Next input bit + input Enable; + input CLK; // Current bit valid (Clock) + input RST; // Init CRC value + output reg [15:0] CRC; // Current output CRC value + + + // We need output registers + wire inv; + + assign inv = BITVAL ^ CRC[15]; // XOR required? + + always @(posedge CLK or posedge RST) begin + if (RST) begin + CRC = 0; + + end + else begin + if (Enable==1) begin + CRC[15] = CRC[14]; + CRC[14] = CRC[13]; + CRC[13] = CRC[12]; + CRC[12] = CRC[11] ^ inv; + CRC[11] = CRC[10]; + CRC[10] = CRC[9]; + CRC[9] = CRC[8]; + CRC[8] = CRC[7]; + CRC[7] = CRC[6]; + CRC[6] = CRC[5]; + CRC[5] = CRC[4] ^ inv; + CRC[4] = CRC[3]; + CRC[3] = CRC[2]; + CRC[2] = CRC[1]; + CRC[1] = CRC[0]; + CRC[0] = inv; + end + end + end + +endmodule Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_7.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_7.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_crc_7.v (revision 11) @@ -0,0 +1,34 @@ +module CRC_7(BITVAL, Enable, CLK, RST, CRC); + input BITVAL;// Next input bit + input Enable; + input CLK; // Current bit valid (Clock) + input RST; // Init CRC value + output [6:0] CRC; // Current output CRC value + + reg [6:0] CRC; + // We need output registers + wire inv; + + assign inv = BITVAL ^ CRC[6]; // XOR required? + + + always @(posedge CLK or posedge RST) begin + if (RST) begin + CRC = 0; + + end + else begin + if (Enable==1) begin + CRC[6] = CRC[5]; + CRC[5] = CRC[4]; + CRC[4] = CRC[3]; + CRC[3] = CRC[2] ^ inv; + CRC[2] = CRC[1]; + CRC[1] = CRC[0]; + CRC[0] = inv; + end + end + end + +endmodule + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_defines.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_defines.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/SD_defines.v (revision 11) @@ -0,0 +1,53 @@ +`define BIG_ENDIAN +`define TIME_OUT_TIME 255 + +//OBS komihåg Master SEL to 1111 vid port dek + +//`define SIM +`define SYN + +`define ACTEL + +`ifdef SYN +`define RESET_CLK_DIV 2 +`define MEM_OFFSET 4 +`endif + +`ifdef SIM +`define RESET_CLK_DIV 0 +`define MEM_OFFSET 1 +`endif + + +//SD-Clock Defines --------- +//Use bus clock or a seperate clock? +`define SD_CLK_BUS_CLK +//`define SD_CLK_SEP + +// Use internal clock divider? +`define SD_CLK_STATIC +//`define SD_CLK_DYNAMIC + + +//SD DATA-transfer defines--- +`define BLOCK_SIZE 512 +`define SD_BUS_WIDTH_4 +`define SD_BUS_W 4 + +//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. +//Add 18 for crc, endbit and z. +`define BIT_BLOCK 1044 +`define CRC_OFF 19 +`define BIT_BLOCK_REC 1024 + +`define BIT_CRC_CYCLE 16 + +//FIFO defines--------------- + + + + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_controller_fifo_wb.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_controller_fifo_wb.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_controller_fifo_wb.v (revision 11) @@ -0,0 +1,317 @@ +`include "SD_defines.v" + +module sd_controller_fifo_wba +( + + + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, + m_wb_cti_o, m_wb_bte_o, + //SD BUS + sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o, + sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad + //PLL CLK_IN + // sd_clk_i_pad + +); +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [7:0] wb_dat_i; // WISHBONE data input +output [7:0] wb_dat_o; // WISHBONE data output + // WISHBONE error output + +// WISHBONE slave +input [2:0] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input + +output reg wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; + +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +output [2:0] m_wb_cti_o; +output [1:0] m_wb_bte_o; + +input wire [3:0] sd_dat_dat_i; +output wire [3:0] sd_dat_out_o; +output wire sd_dat_oe_o; + +input wire sd_cmd_dat_i; +output wire sd_cmd_out_o; +output wire sd_cmd_oe_o; + +output sd_clk_o_pad; +wire sd_clk_i; +//input sd_clk_i_pad; + +`define tx_cmd_fifo 4'h0 +`define rx_cmd_fifo 4'h1 +`define tx_data_fifo 4'h2 +`define rx_data_fifo 4'h3 +`define status 4'h4 +`define controll 4'h5 +`define timer 4'h6 + +reg [7:0] controll_reg; +reg [7:0] status_reg; +reg [7:0] command_timeout_reg; + +`ifdef SD_CLK_BUS_CLK + assign sd_clk_i = wb_clk_i; +`endif + +`ifdef SD_CLK_SEP + //assign sd_clk_i = sd_clk_i_pad; +`endif +assign sd_clk_o=sd_clk_i; + +reg [1:0] wb_fifo_adr_i_writer; +reg [1:0] wb_fifo_adr_i_reader; +wire [1:0] wb_fifo_adr_i; +reg add_token_read; +wire [7:0] wb_fifo_dat_i; +wire [7:0] wb_fifo_dat_o; +reg [7:0] wb_dat_i_storage; +reg [7:0] wb_dat_o_i; +reg time_enable; +assign sd_clk_o_pad = sd_clk_i ; + + +assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer; +assign wb_fifo_dat_i =wb_dat_i_storage; +assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ; + + + +wire [1:4]fifo_full ; +wire [1:4]fifo_empty; +reg wb_fifo_we_i; +reg wb_fifo_re_i; +wire [1:0] sd_adr_o; +wire [7:0] sd_dat_o; +wire [7:0] sd_dat_i; +sd_fifo sd_fifo_0 +( + .wb_adr_i (wb_fifo_adr_i ), + .wb_dat_i (wb_fifo_dat_i), + .wb_dat_o (wb_fifo_dat_o ), + .wb_we_i (wb_fifo_we_i), + .wb_re_i (wb_fifo_re_i), + .wb_clk (wb_clk_i), + .sd_adr_i (sd_adr_o ), + .sd_dat_i (sd_dat_o), + .sd_dat_o (sd_dat_i ), + .sd_we_i (sd_we_o), + .sd_re_i (sd_re_o), + .sd_clk (sd_clk_o), + .fifo_full ( fifo_full ), + .fifo_empty (fifo_empty ), + .rst (wb_rst_i) // | controll_reg[0]) + ) ; + +wire [1:0] sd_adr_o_cmd; +wire [7:0] sd_dat_i_cmd; +wire [7:0] sd_dat_o_cmd; + +wire [1:0] sd_adr_o_dat; +wire [7:0] sd_dat_i_dat; +wire [7:0] sd_dat_o_dat; +wire [1:0] st_dat_t; +sd_cmd_phy sdc_cmd_phy_0 +( + .sd_clk (sd_clk_o), + .rst (wb_rst_i ),//| controll_reg[0]), + .cmd_dat_i ( sd_cmd_dat_i ), + .cmd_dat_o (sd_cmd_out_o ), + .cmd_oe_o (sd_cmd_oe_o ), + .sd_adr_o (sd_adr_o_cmd), + .sd_dat_i (sd_dat_i_cmd), + .sd_dat_o (sd_dat_o_cmd), + .sd_we_o (sd_we_o_cmd), + .sd_re_o (sd_re_o_cmd), + .fifo_full ( fifo_full[1:2] ), + .fifo_empty ( fifo_empty [1:2]), + .start_dat_t (st_dat_t), + .fifo_acces_token (fifo_acces_token) + ); + + + sd_data_phy sd_data_phy_0 ( + .sd_clk (sd_clk_o), + .rst (wb_rst_i | controll_reg[0]), + .DAT_oe_o ( sd_dat_oe_o ), + .DAT_dat_o (sd_dat_out_o), + .DAT_dat_i (sd_dat_dat_i ), + .sd_adr_o (sd_adr_o_dat ), + .sd_dat_i (sd_dat_i_dat ), + .sd_dat_o (sd_dat_o_dat ), + .sd_we_o (sd_we_o_dat), + .sd_re_o (sd_re_o_dat), + .fifo_full ( fifo_full[3:4] ), + .fifo_empty ( fifo_empty [3:4]), + .start_dat (st_dat_t), + .fifo_acces (~fifo_acces_token) + ); + + + assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat; + assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat; + assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat; + assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat; + + assign sd_dat_i_dat = sd_dat_i; + assign sd_dat_i_cmd = sd_dat_i; + + + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + status_reg<=0; + else begin + status_reg[0] <= fifo_full[1]; + status_reg[1] <= fifo_empty[2]; + status_reg[2] <= fifo_full[3]; + status_reg[3] <= fifo_empty[4]; + end + end + + reg delayed_ack; + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + + if (wb_rst_i) + wb_ack_o <=0; + else + wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack; + + end + + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + + + if ( wb_rst_i )begin + command_timeout_reg<=`TIME_OUT_TIME; + wb_dat_i_storage<=0; + controll_reg<=0; + + wb_fifo_we_i<=0; + wb_fifo_adr_i_writer<=0; + time_enable<=0; + end + else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin //CS + + + if (wb_we_i) begin + case (wb_adr_i) + `tx_cmd_fifo : begin + wb_fifo_adr_i_writer<=0; + wb_fifo_we_i<=1&!delayed_ack; + wb_dat_i_storage<=wb_dat_i; + command_timeout_reg<=`TIME_OUT_TIME; + time_enable<=1; + end + `tx_data_fifo : begin + wb_fifo_adr_i_writer<=2; + wb_fifo_we_i<=1&!delayed_ack; + wb_dat_i_storage<=wb_dat_i; + command_timeout_reg<=`TIME_OUT_TIME; + time_enable<=0; + end + `controll : controll_reg <= wb_dat_i; + endcase + end + end + else begin + // wb_fifo_adr_i_writer<=0; + wb_fifo_we_i<=0; + + if (!status_reg[1]) + time_enable<=0; + + if ((command_timeout_reg!=0) && (time_enable)) + command_timeout_reg<=command_timeout_reg-1; + end +end + + +always @(posedge wb_clk_i or posedge wb_rst_i )begin + + + if ( wb_rst_i) begin + add_token_read<=0; + delayed_ack<=0; + wb_fifo_re_i<=0; + wb_fifo_adr_i_reader<=0; + wb_dat_o_i<=0; + end + else begin + delayed_ack<=0; + wb_fifo_re_i<=0; + if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin //C + delayed_ack<=delayed_ack+1; + add_token_read<=0; + if (!wb_we_i) begin + + case (wb_adr_i) + `rx_cmd_fifo : begin + + add_token_read<=1; + wb_fifo_adr_i_reader<=1; + wb_fifo_re_i<=1&delayed_ack; + + end + `rx_data_fifo :begin + add_token_read<=1; + wb_fifo_adr_i_reader<=3; + wb_fifo_re_i<=1 & delayed_ack; + + end + `status : wb_dat_o_i <= status_reg; + `timer : wb_dat_o_i <= command_timeout_reg; + + + endcase + end + end +end +end + + +//just to get rid of warnings.... + assign m_wb_adr_o =0; + assign m_wb_sel_o =0; + assign m_wb_we_o=0; + assign m_wb_dat_o =0; + + assign m_wb_cyc_o=0; + assign m_wb_stb_o=0; + assign m_wb_cti_o=0; + assign m_wb_bte_o=0; + + + +endmodule + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_counter.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_counter.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_counter.v (revision 11) @@ -0,0 +1,184 @@ +// module name +//`define CNT_MODULE_NAME sd_counter + +// counter type = [BINARY, GRAY, LFSR] +//`define CNT_TYPE_BINARY +`define CNT_TYPE_GRAY +//`define CNT_TYPE_LFSR + +// q as output +`define CNT_Q +// for gray type counter optional binary output +`define CNT_Q_BIN + +// number of CNT bins +`define CNT_LENGTH 9 + +// clear +//`define CNT_CLEAR + +// set +//`define CNT_SET +`define CNT_SET_VALUE `CNT_LENGTH'h9 + +// wrap around creates shorter cycle than maximum length +//`define CNT_WRAP +`define CNT_WRAP_VALUE `CNT_LENGTH'h9 + +// clock enable +`define CNT_CE + +// q_next as an output +//`define CNT_QNEXT + +// q=0 as an output +//`define CNT_Z + +// q_next=0 as a registered output +//`define CNT_ZQ + + +`define LFSR_LENGTH `CNT_LENGTH + +module sd_counter + ( +`ifdef CNT_TYPE_GRAY + output reg [`CNT_LENGTH:1] q, +`ifdef CNT_Q_BIN + output [`CNT_LENGTH:1] q_bin, +`endif +`else +`ifdef CNT_Q + output [`CNT_LENGTH:1] q, +`endif +`endif +`ifdef CNT_CLEAR + input clear, +`endif +`ifdef CNT_SET + input set, +`endif +`ifdef CNT_REW + input rew, +`endif +`ifdef CNT_CE + input cke, +`endif +`ifdef CNT_QNEXT + output [`CNT_LENGTH:1] q_next, +`endif +`ifdef CNT_Z + output z, +`endif +`ifdef CNT_ZQ + output reg zq, +`endif + input clk, + input rst + ); + +`ifdef CNT_SET + parameter set_value = `CNT_SET_VALUE; +`endif +`ifdef CNT_WRAP + parameter wrap_value = `CNT_WRAP_VALUE; +`endif + + // internal q reg + reg [`CNT_LENGTH:1] qi; + +`ifdef CNT_QNEXT +`else + wire [`CNT_LENGTH:1] q_next; +`endif +`ifdef CNT_REW + wire [`CNT_LENGTH:1] q_next_fw; + wire [`CNT_LENGTH:1] q_next_rew; +`endif + +`ifdef CNT_REW +`else + assign q_next = +`endif +`ifdef CNT_REW + assign q_next_fw = +`endif +`ifdef CNT_CLEAR + clear ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_SET + set ? set_value : +`endif +`ifdef CNT_WRAP + (qi == wrap_value) ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_TYPE_LFSR + {qi[8:1],~(q[`LFSR_LENGTH]^q[1])}; +`else + qi + `CNT_LENGTH'd1; +`endif + +`ifdef CNT_REW + assign q_next_rew = +`ifdef CNT_CLEAR + clear ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_SET + set ? set_value : +`endif +`ifdef CNT_WRAP + (qi == `CNT_LENGTH'd0) ? wrap_value : +`endif +`ifdef CNT_TYPE_LFSR + {~(q[1]^q[2]),qi[`CNT_LENGTH:2]}; +`else + qi - `CNT_LENGTH'd1; +`endif +`endif + +`ifdef CNT_REW + assign q_next = rew ? q_next_rew : q_next_fw; +`endif + + always @ (posedge clk or posedge rst) + if (rst) + qi <= `CNT_LENGTH'd0; + else +`ifdef CNT_CE + if (cke) +`endif + qi <= q_next; + +`ifdef CNT_Q +`ifdef CNT_TYPE_GRAY + always @ (posedge clk or posedge rst) + if (rst) + q <= `CNT_LENGTH'd0; + else +`ifdef CNT_CE + if (cke) +`endif + q <= (q_next>>1) ^ q_next; +`ifdef CNT_Q_BIN + assign q_bin = qi; +`endif +`else + assign q = q_next; +`endif +`endif + +`ifdef CNT_Z + assign z = (q == `CNT_LENGTH'd0); +`endif + +`ifdef CNT_ZQ + always @ (posedge clk or posedge rst) + if (rst) + zq <= 1'b1; + else +`ifdef CNT_CE + if (cke) +`endif + zq <= q_next == `CNT_LENGTH'd0; +`endif +endmodule Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_cmd_phy.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_cmd_phy.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_cmd_phy.v (revision 11) @@ -0,0 +1,430 @@ +`include "SD_defines.v" +//------------------------- +//------------------------- +module sd_cmd_phy ( +input sd_clk, +input rst, +input cmd_dat_i, +output reg cmd_dat_o, +output reg cmd_oe_o, + +output [1:0] sd_adr_o, +input [7:0] sd_dat_i, +output reg [7:0] sd_dat_o, +output reg sd_we_o, +output reg sd_re_o, +input [1:2] fifo_full, +input [1:2] fifo_empty, +output [1:0] start_dat_t, +output fifo_acces_token + +); +//---------------Input ports--------------- + `define WRITE_CMD 32'h18 +`define READ_CMD 32'h11 +reg [6:0] Response_Size; +`ifdef SIM + `define INIT_DELAY 64 +`else + `define INIT_DELAY 64 + `endif + + `define tx_cmd_fifo_empty fifo_empty [1] + +parameter SEND_SIZE = 48; +parameter CONTENT_SIZE = 40; +parameter NCR = 2 ; + +`define Vector_Index_Write (CONTENT_SIZE-1-cmd_flow_cnt_write) +`define Bit_Nr_Write (SEND_SIZE-cmd_flow_cnt_write) +//FSM +parameter SIZE = 5; +parameter +INIT = 5'b00001, +IDLE = 5'b00010, +WRITE = 5'b00100, +BUFFER_WRITE = 5'b01000, +READ = 5'b10000; + +reg [SIZE-1:0] state; +reg [SIZE-1:0] next_state; + +reg [1:0] start_dat_t_read; +reg [1:0] start_dat_t_write; + +reg [39:0] in_buffer; +reg [2:0] read_byte_cnt; +// +reg [7:0] cmd_flow_cnt_write; +reg [7:0] cmd_flow_cnt_read; + +reg cmd_dat_internal; +// +reg big_resp; + +reg crc_rst_write; +reg crc_en_write; +reg crc_in_write; +wire [6:0] crc_val_write; + +reg [1:0] sd_adr_o_read; +reg [1:0] sd_adr_o_write; + +reg crc_rst_read; +reg crc_en_read; +reg crc_in_read; +wire [6:0] crc_val_read; + +reg crc_buffering_write; +reg block_write; +reg block_read; + +reg in_buff_ptr; +reg out_buff_ptr; +reg [2:0] read_index_cnt; +reg [7:0] in_buff_0; +reg [7:0] in_buff_1; +reg [6:0] crc_in_buff; +reg [7:0] response_status; +reg [6:0] index_check; + +reg add_token_read; + +CRC_7 CRC_7_WRITE( +.BITVAL (crc_in_write), +.Enable (crc_en_write), +.CLK (sd_clk), +.RST (crc_rst_write), +.CRC (crc_val_write)); + + +CRC_7 CRC_7_READ( +.BITVAL (crc_in_read), +.Enable (crc_en_read), +.CLK (sd_clk), +.RST (crc_rst_read), +.CRC (crc_val_read)); + + + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + + cmd_dat_internal <=1'b1; + end + else begin + cmd_dat_internal<=cmd_dat_i; + end + + +end + +always @ (state or cmd_flow_cnt_write or cmd_dat_internal or `tx_cmd_fifo_empty or read_byte_cnt or cmd_flow_cnt_write or cmd_flow_cnt_read ) + +begin : FSM_COMBO + next_state = 0; +case(state) +INIT: begin + if (cmd_flow_cnt_write >= `INIT_DELAY )begin + next_state = IDLE; + end + else begin + next_state = INIT; + end +end +IDLE: begin + if (!`tx_cmd_fifo_empty) + next_state =BUFFER_WRITE; + else if (!cmd_dat_internal) + next_state =READ; + else + next_state =IDLE; + + +end +BUFFER_WRITE: begin + if (read_byte_cnt>=5) + next_state = WRITE; + else + next_state =BUFFER_WRITE; +end + +WRITE : begin + if (cmd_flow_cnt_write >= SEND_SIZE) + next_state = IDLE; + else + next_state = WRITE; + +end +READ : begin + if (cmd_flow_cnt_read >= Response_Size+7) + next_state = IDLE; + else + next_state = READ; + +end + + +default : next_state = INIT; + + endcase +end + + +always @ (posedge sd_clk or posedge rst ) +begin : FSM_SEQ + if (rst ) begin + state <= #1 INIT; + end + else begin + state <= #1 next_state; + end +end +reg fifo_acces_read,fifo_acces_write; +assign fifo_acces_token = fifo_acces_read | fifo_acces_write; +assign sd_adr_o = add_token_read ? sd_adr_o_read : sd_adr_o_write; +assign start_dat_t = add_token_read ? start_dat_t_read : start_dat_t_write; +reg tx_cmd_fifo_empty_tmp; + + +always @ (negedge sd_clk or posedge rst ) +begin : OUTPUT_LOGIC + if (rst ) begin + crc_in_write=0; + crc_en_write=0; + crc_rst_write=0; + fifo_acces_write=0; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_buffering_write=0; + sd_re_o<=0; + read_byte_cnt<=0; + block_read<=0; + sd_adr_o_write<=0; + cmd_flow_cnt_write=0; + start_dat_t_write<=0; + in_buffer<=0; + tx_cmd_fifo_empty_tmp<=0; + Response_Size<=40; + end + else begin + case(state) + INIT : begin + cmd_flow_cnt_write=cmd_flow_cnt_write+1; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_buffering_write=0; + start_dat_t_write<=0; + end + IDLE: begin + cmd_flow_cnt_write=0; + cmd_oe_o=0; + // cmd_dat_o = 0; + start_dat_t_write<=0; + crc_in_write=0; + crc_en_write=0; + crc_rst_write=1; + read_byte_cnt<=0; + block_read<=0; + fifo_acces_write=0; + in_buffer<=0; + end + BUFFER_WRITE : begin + sd_re_o<=0; + fifo_acces_write=1; + tx_cmd_fifo_empty_tmp<=`tx_cmd_fifo_empty; + if (!tx_cmd_fifo_empty_tmp) begin + if(sd_re_o) + read_byte_cnt <= read_byte_cnt+1; + sd_adr_o_write <=0; + sd_re_o<=1; + if(sd_re_o) begin + case (read_byte_cnt) //If data is Avaible next cycle? + 0: in_buffer[39:32] <=sd_dat_i; + 1: in_buffer[31:24] <=sd_dat_i; + 2: in_buffer[23:16] <=sd_dat_i; + 3: in_buffer[15:8] <=sd_dat_i; + 4: in_buffer[7:0] <=sd_dat_i; + endcase + if (in_buffer[39]) + Response_Size<=127; + else + Response_Size<=40; + + if (in_buffer[37:32] == `READ_CMD) + block_read<=1; + end + + end + end + WRITE: begin + sd_re_o<=0; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_en_write =0; + crc_rst_write=0; + crc_en_write=1; + + + if (crc_buffering_write==1) begin + cmd_oe_o =1; + if (`Bit_Nr_Write > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit + if (cmd_flow_cnt_write==0) + cmd_dat_o = 0; + else + cmd_dat_o = in_buffer[`Vector_Index_Write]; + + if (`Bit_Nr_Write > 9 ) begin //1 step ahead + crc_in_write = in_buffer[`Vector_Index_Write-1]; + end else begin + crc_en_write=0; + end + end + else if ( (`Bit_Nr_Write <=8) && (`Bit_Nr_Write >=2) ) begin + crc_en_write=0; + cmd_dat_o = crc_val_write[(`Bit_Nr_Write)-2]; + if (block_read) + start_dat_t_write<=2'b10; + + end + else begin + cmd_dat_o =1'b1; + + end + cmd_flow_cnt_write=cmd_flow_cnt_write+1; + end + + else begin //Pre load CRC + crc_buffering_write=1; + + crc_in_write = 0; + end + + + + end + + endcase + end +end + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + crc_rst_read=1; + crc_en_read=0; + crc_in_read=0; + cmd_flow_cnt_read=0; + response_status =0; + block_write=0; + index_check=0; + in_buff_ptr=0; + out_buff_ptr=0; + sd_adr_o_read<=0; + add_token_read=0; + in_buff_0<=0; + in_buff_1<=0; + read_index_cnt=0; + fifo_acces_read=0; + sd_dat_o<=0; + start_dat_t_read<=0; + sd_we_o<=0; + crc_in_buff=0; + end + else begin + case (state) + IDLE : begin + crc_en_read=0; + crc_rst_read=1; + cmd_flow_cnt_read=1; + index_check=0; + block_write=0; + in_buff_ptr=0; + out_buff_ptr=0; + add_token_read=0; + read_index_cnt=0; + sd_we_o<=0; + add_token_read=0; + fifo_acces_read=0; + start_dat_t_read<=0; + end + READ : begin + fifo_acces_read=1; + add_token_read=1; //Takes command over addres + crc_en_read=1; + crc_rst_read=0; + sd_we_o<=0; + if (in_buff_ptr != out_buff_ptr) begin + sd_adr_o_read <=1; + sd_we_o<=1; + if (in_buff_ptr) + sd_dat_o <=in_buff_0; + else + sd_dat_o <=in_buff_1; + + out_buff_ptr=out_buff_ptr+1; + end + + if (cmd_flow_cnt_read < (Response_Size))begin //40 First Bits + crc_in_read = cmd_dat_internal; + if (cmd_flow_cnt_read<8 ) begin //1+1+6 (S,T,Index) + + index_check[7-cmd_flow_cnt_read] = cmd_dat_internal; + if (index_check[5:0] == `WRITE_CMD) begin + block_write=1; + end + end + else begin + if (!in_buff_ptr) begin + in_buff_0[7-read_index_cnt]<=cmd_dat_internal; + end + else begin + in_buff_1[7-read_index_cnt]<=cmd_dat_internal; + end + read_index_cnt=read_index_cnt+1; + if (read_index_cnt==0) + in_buff_ptr=in_buff_ptr+1; + end + end + else if ( cmd_flow_cnt_read - Response_Size <=6 ) begin //7-Crc Bit + crc_in_buff [(Response_Size+6)-(cmd_flow_cnt_read)] = cmd_dat_internal; + crc_en_read=0; + end + else begin //Commpare CRC read with calcualted. + if ((crc_in_buff != crc_val_read)) begin + response_status[0]=1; + end + else begin + response_status[0]=0; + end + sd_adr_o_read <=1; + sd_we_o<=1; + sd_dat_o<=response_status; + + if (block_write) + start_dat_t_read<=2'b01; + + end + + cmd_flow_cnt_read = cmd_flow_cnt_read+1; + end + + + + + endcase + end + +end + + + + + + + +endmodule + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_fifo.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_fifo.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/sd_fifo.v (revision 11) @@ -0,0 +1,196 @@ + +module sd_fifo + ( + input [1:0] wb_adr_i, + input [7:0] wb_dat_i, + output [7:0] wb_dat_o, + input wb_we_i, + input wb_re_i, + input wb_clk, + input [1:0] sd_adr_i, + input [7:0] sd_dat_i, + output [7:0] sd_dat_o, + input sd_we_i, + input sd_re_i, + input sd_clk, + output [1:4] fifo_full, + output [1:4] fifo_empty, + input rst + ); + + wire [8:0] wptr1, rptr1, wptr2, rptr2, wptr3, rptr3, wptr4, rptr4; + wire [8:0] wadr1, radr1, wadr2, radr2, wadr3, radr3, wadr4, radr4; + + wire dpram_we_a, dpram_we_b; + wire [10:0] dpram_a_a, dpram_a_b; + + sd_counter wptr1a + ( + .q(wptr1), + .q_bin(wadr1), + .cke((wb_adr_i==2'd0) & wb_we_i & !fifo_full[1]), + .clk(wb_clk), + .rst(rst) + ); + + sd_counter rptr1a + ( + .q(rptr1), + .q_bin(radr1), + .cke((sd_adr_i==2'd0) & sd_re_i & !fifo_empty[1]), + .clk(sd_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp1 + ( + .wptr(wptr1), + .rptr(rptr1), + .fifo_empty(fifo_empty[1]), + .fifo_full(fifo_full[1]), + .wclk(wb_clk), + .rclk(sd_clk), + .rst(rst) + ); + + sd_counter wptr2a + ( + .q(wptr2), + .q_bin(wadr2), + .cke((sd_adr_i==2'd1) & sd_we_i & !fifo_full[2]), + .clk(sd_clk), + .rst(rst) + ); + + sd_counter rptr2a + ( + .q(rptr2), + .q_bin(radr2), + .cke((wb_adr_i==2'd1) & wb_re_i & !fifo_empty[2]), + .clk(wb_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp2 + ( + .wptr(wptr2), + .rptr(rptr2), + .fifo_empty(fifo_empty[2]), + .fifo_full(fifo_full[2]), + .wclk(sd_clk), + .rclk(wb_clk), + .rst(rst) + ); + + sd_counter wptr3a + ( + .q(wptr3), + .q_bin(wadr3), + .cke((wb_adr_i==2'd2) & wb_we_i & !fifo_full[3]), + .clk(wb_clk), + .rst(rst) + ); + + sd_counter rptr3a + ( + .q(rptr3), + .q_bin(radr3), + .cke((sd_adr_i==2'd2) & sd_re_i & !fifo_empty[3]), + .clk(sd_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp3 + ( + .wptr(wptr3), + .rptr(rptr3), + .fifo_empty(fifo_empty[3]), + .fifo_full(fifo_full[3]), + .wclk(wb_clk), + .rclk(sd_clk), + .rst(rst) + ); + + sd_counter wptr4a + ( + .q(wptr4), + .q_bin(wadr4), + .cke((sd_adr_i==2'd3) & sd_we_i & !fifo_full[4]), + .clk(sd_clk), + .rst(rst) + ); + + sd_counter rptr4a + ( + .q(rptr4), + .q_bin(radr4), + .cke((wb_adr_i==2'd3) & wb_re_i & !fifo_empty[4]), + .clk(wb_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp4 + ( + .wptr(wptr4), + .rptr(rptr4), + .fifo_empty(fifo_empty[4]), + .fifo_full(fifo_full[4]), + .wclk(sd_clk), + .rclk(wb_clk), + .rst(rst) + ); + + assign dpram_we_a = ((wb_adr_i==2'd0) & !fifo_full[1]) ? wb_we_i : + ((wb_adr_i==2'd2) & !fifo_full[3]) ? wb_we_i : + 1'b0; + assign dpram_we_b = ((sd_adr_i==2'd1) & !fifo_full[2]) ? sd_we_i : + ((sd_adr_i==2'd3) & !fifo_full[4]) ? sd_we_i : + 1'b0; + assign dpram_a_a = (wb_adr_i==2'd0) ? {wb_adr_i,wadr1} : + (wb_adr_i==2'd1) ? {wb_adr_i,radr2} : + (wb_adr_i==2'd2) ? {wb_adr_i,wadr3} : + {wb_adr_i,radr4}; + assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} : + (sd_adr_i==2'd1) ? {sd_adr_i,wadr2} : + (sd_adr_i==2'd2) ? {sd_adr_i,radr3} : //(sd_adr_i==2'd3) ? {sd_adr_i,radr3} :--->(sd_adr_i==2'd2) ? {sd_adr_i,radr3} : + {sd_adr_i,wadr4}; + + //versatile_fifo_dual_port_ram_dc_dw + versatile_fifo_dptam_dw + dpram + ( + .d_a(wb_dat_i), + .q_a(wb_dat_o), + .adr_a(dpram_a_a), + .we_a(dpram_we_a), + .clk_a(wb_clk), + .q_b(sd_dat_o), + .adr_b(dpram_a_b), + .d_b(sd_dat_i), + .we_b(dpram_we_b), + .clk_b(sd_clk) + ); + +endmodule // sd_fifo + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_data_phy.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_data_phy.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_data_phy.v (revision 11) @@ -0,0 +1,444 @@ +//------------------------- +//------------------------- + + + + +`include "SD_defines.v" +`define BUFFER_OFFSET 2 + +module sd_data_phy( +input sd_clk, +input rst, +output reg DAT_oe_o, +output reg[3:0] DAT_dat_o, +input [3:0] DAT_dat_i, + +output [1:0] sd_adr_o, +input [7:0] sd_dat_i, +output reg [7:0] sd_dat_o, +output reg sd_we_o, +output reg sd_re_o, +input [3:4] fifo_full, +input [3:4] fifo_empty, +input [1:0] start_dat, +input fifo_acces + +); + reg [5:0] in_buff_ptr_read; + reg [5:0] out_buff_ptr_read; + reg crc_ok; + reg [3:0] last_din_read; + + + +reg [7:0] tmp_crc_token ; +reg[2:0] crc_read_count; + +//CRC16 +reg [3:0] crc_in_write; +reg crc_en_write; +reg crc_rst_write; +wire [15:0] crc_out_write [3:0]; + +reg [3:0] crc_in_read; +reg crc_en_read; +reg crc_rst_read; +wire [15:0] crc_out_read [3:0]; + + reg[7:0] next_out; + reg data_read_index; + +reg [10:0] transf_cnt_write; +reg [10:0] transf_cnt_read; +parameter SIZE = 6; +reg [SIZE-1:0] state; +reg [SIZE-1:0] next_state; +parameter IDLE = 6'b000001; +parameter WRITE_DAT = 6'b000010; +parameter READ_CRC = 6'b000100; +parameter WRITE_CRC = 6'b001000; +parameter READ_WAIT = 6'b010000; +parameter READ_DAT = 6'b100000; + +reg in_dat_buffer_empty; +reg [2:0] crc_status_token; +reg busy_int; +reg add_token; +genvar i; +generate +for(i=0; i<4; i=i+1) begin:CRC_16_gen_write + CRC_16 CRC_16_i (crc_in_write[i],crc_en_write, sd_clk, crc_rst_write, crc_out_write[i]); +end +endgenerate + + +generate +for(i=0; i<4; i=i+1) begin:CRC_16_gen_read + CRC_16 CRC_16_i (crc_in_read[i],crc_en_read, sd_clk, crc_rst_read, crc_out_read[i]); +end +endgenerate + + + +reg q_start_bit; + +always @ (state or start_dat or DAT_dat_i[0] or transf_cnt_write or transf_cnt_read or busy_int or crc_read_count or sd_we_o or in_dat_buffer_empty ) +begin : FSM_COMBO + next_state = 0; +case(state) + IDLE: begin + if (start_dat == 2'b01) + next_state=WRITE_DAT; + else if (start_dat == 2'b10) + next_state=READ_WAIT; + else + next_state=IDLE; + end + WRITE_DAT: begin + if (transf_cnt_write >= `BIT_BLOCK+`BUFFER_OFFSET) + next_state= READ_CRC; + else if (start_dat == 2'b11) + next_state=IDLE; + else + next_state=WRITE_DAT; + end + + READ_WAIT: begin + if (DAT_dat_i[0]== 0 ) + next_state= READ_DAT; + else + next_state=READ_WAIT; + end + + + READ_CRC: begin + if ( (crc_read_count == 3'b111) &&(busy_int ==1) ) + next_state= WRITE_CRC; + else + next_state=READ_CRC; + end + WRITE_CRC: begin + + next_state= IDLE; + + end + + + + READ_DAT: begin + if ((transf_cnt_read >= `BIT_BLOCK-3) && (in_dat_buffer_empty)) //Startbit consumed... + next_state= IDLE; + else if (start_dat == 2'b11) + next_state=IDLE; + else + next_state=READ_DAT; + end + endcase +end + +always @ (posedge sd_clk or posedge rst ) + begin + if (rst ) begin + q_start_bit<=1; + end + else begin + q_start_bit <= DAT_dat_i[0]; + end +end + + +//----------------Seq logic------------ +always @ (posedge sd_clk or posedge rst ) +begin : FSM_SEQ + if (rst ) begin + state <= #1 IDLE; + end + else begin + state <= #1 next_state; + end +end + +reg [4:0] crc_cnt_write; +reg [4:0]crc_cnt_read; +reg [3:0] last_din; +reg [2:0] crc_s ; +reg [7:0] write_buf_0,write_buf_1, sd_data_out; +reg out_buff_ptr,in_buff_ptr; +reg data_send_index; +reg [1:0] sd_adr_o_read; +reg [1:0] sd_adr_o_write; + + +reg read_byte_cnt; +assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write; + + + + +assign sd_adr_o = add_token ? sd_adr_o_read : sd_adr_o_write; + +reg [3:0] in_dat_buffer [63:0]; + +always @ (negedge sd_clk or posedge rst ) +begin +if (rst) begin + DAT_oe_o<=0; + crc_en_write<=0; + crc_rst_write<=1; + transf_cnt_write<=0; + crc_cnt_write<=15; + crc_status_token<=7; + + data_send_index<=0; + out_buff_ptr<=0; + in_buff_ptr<=0; + read_byte_cnt<=0; + write_buf_0<=0; + write_buf_1<=0; + sd_re_o<=0; + sd_data_out<=0; + sd_adr_o_write<=0; + crc_in_write<=0; + DAT_dat_o<=0; + last_din<=0; +end +else begin + case(state) + IDLE: begin + DAT_oe_o<=0; + crc_en_write<=0; + crc_rst_write<=1; + crc_cnt_write<=16; + read_byte_cnt<=0; + + crc_status_token<=7; + data_send_index<=0; + out_buff_ptr<=0; + in_buff_ptr<=0; + sd_re_o<=0; + transf_cnt_write<=0; + + end + WRITE_DAT: begin + + transf_cnt_write<=transf_cnt_write+1; + + + if ( (in_buff_ptr != out_buff_ptr) || (transf_cnt_write<2) ) begin + read_byte_cnt<=read_byte_cnt+1; + sd_re_o<=0; + case (read_byte_cnt) + 0:begin + sd_adr_o_write <=2; + sd_re_o<=1; + end + 1:begin + if (!in_buff_ptr) + write_buf_0<=sd_dat_i; + else + write_buf_1 <=sd_dat_i; + in_buff_ptr<=in_buff_ptr+1; + end + endcase + end + + if (!out_buff_ptr) + sd_data_out<=write_buf_0; + else + sd_data_out<=write_buf_1; + + if (transf_cnt_write==1+`BUFFER_OFFSET) begin + + crc_rst_write<=0; + crc_en_write<=1; + last_din <=write_buf_0[3:0]; + DAT_oe_o<=1; + DAT_dat_o<=0; + crc_in_write<= write_buf_0[3:0]; + data_send_index<=1; + out_buff_ptr<=out_buff_ptr+1; + end + else if ( (transf_cnt_write>=2+`BUFFER_OFFSET) && (transf_cnt_write<=`BIT_BLOCK-`CRC_OFF+`BUFFER_OFFSET )) begin + DAT_oe_o<=1; + case (data_send_index) + 0:begin + last_din <=sd_data_out[3:0]; + crc_in_write <=sd_data_out[3:0]; + out_buff_ptr<=out_buff_ptr+1; + end + 1:begin + last_din <=sd_data_out[7:4]; + crc_in_write <=sd_data_out[7:4]; + end + + endcase + data_send_index<=data_send_index+1; + + DAT_dat_o<= last_din; + + if ( transf_cnt_write >=`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET) begin + crc_en_write<=0; + end + end + else if (transf_cnt_write>`BIT_BLOCK-`CRC_OFF +`BUFFER_OFFSET & crc_cnt_write!=0) begin + + crc_en_write<=0; + crc_cnt_write<=crc_cnt_write-1; + DAT_oe_o<=1; + DAT_dat_o[0]<=crc_out_write[0][crc_cnt_write-1]; + DAT_dat_o[1]<=crc_out_write[1][crc_cnt_write-1]; + DAT_dat_o[2]<=crc_out_write[2][crc_cnt_write-1]; + DAT_dat_o[3]<=crc_out_write[3][crc_cnt_write-1]; + end + else if (transf_cnt_write==`BIT_BLOCK-2+`BUFFER_OFFSET) begin + DAT_oe_o<=1; + DAT_dat_o<=4'b1111; + + end + else if (transf_cnt_write !=0) begin + DAT_oe_o<=0; + end + + + end + + + endcase +end +end + + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + add_token<=0; + sd_adr_o_read<=0; + crc_read_count<=0; + sd_we_o<=0; + tmp_crc_token<=0; + crc_rst_read<=0; + crc_en_read<=0; + in_buff_ptr_read<=0; + out_buff_ptr_read<=0; + crc_cnt_read<=0; + transf_cnt_read<=0; + data_read_index<=0; + in_dat_buffer_empty<=0; + + next_out<=0; + busy_int<=0; + sd_dat_o<=0; + end + else begin + case(state) + IDLE: begin + add_token<=0; + crc_read_count<=0; + sd_we_o<=0; + tmp_crc_token<=0; + crc_rst_read<=1; + crc_en_read<=0; + in_buff_ptr_read<=0; + out_buff_ptr_read<=0; + crc_cnt_read<=15; + transf_cnt_read<=0; + data_read_index<=0; + in_dat_buffer_empty<=0; + end + + READ_DAT: begin + add_token<=1; + crc_rst_read<=0; + crc_en_read<=1; + + + + if (fifo_acces) begin + if ( (in_buff_ptr_read - out_buff_ptr_read) >=2) begin + data_read_index<=~data_read_index; + case(data_read_index) + 0: begin + sd_adr_o_read<=3; + sd_we_o<=0; + next_out[3:0]<=in_dat_buffer[out_buff_ptr_read ]; + next_out[7:4]<=in_dat_buffer[out_buff_ptr_read+1 ]; + end + 1: begin + out_buff_ptr_read<=out_buff_ptr_read+2; + sd_dat_o<=next_out; + sd_we_o<=1; + end + endcase + end + else + in_dat_buffer_empty<=1; + end + + if (transf_cnt_read<`BIT_BLOCK_REC) begin + + in_dat_buffer[in_buff_ptr_read]<=DAT_dat_i; + crc_in_read<=DAT_dat_i; + crc_ok<=1; + transf_cnt_read<=transf_cnt_read+1; + in_buff_ptr_read<=in_buff_ptr_read+1; + end + else if ( transf_cnt_read <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin + transf_cnt_read<=transf_cnt_read+1; + crc_en_read<=0; + last_din_read <=DAT_dat_i; + + if (transf_cnt_read> `BIT_BLOCK_REC) begin + crc_cnt_read <=crc_cnt_read-1; + + + if (crc_out_read[0][crc_cnt_read] != last_din[0]) + crc_ok<=0; + if (crc_out_read[1][crc_cnt_read] != last_din[1]) + crc_ok<=0; + if (crc_out_read[2][crc_cnt_read] != last_din[2]) + crc_ok<=0; + if (crc_out_read[3][crc_cnt_read] != last_din[3]) + crc_ok<=0; + + if (crc_cnt_read==0) begin + //in_dat_buffer[in_buff_ptr_read] <= {7'b0,crc_ok} + end + end + end + + + + end + READ_CRC: begin + if (crc_read_count<3'b111) begin + crc_read_count<=crc_read_count+1; + tmp_crc_token[crc_read_count] <= DAT_dat_i[0]; + end + + busy_int <=DAT_dat_i[0]; + + end + WRITE_CRC: begin + add_token<=1; + sd_adr_o_read<=3; + sd_we_o<=1; + sd_dat_o<=tmp_crc_token; + end + + endcase +end + +end +//Sync + + + + + + + +endmodule + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/versatile_fifo_dptam_dw.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/versatile_fifo_dptam_dw.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/versatile_fifo_dptam_dw.v (revision 11) @@ -0,0 +1,47 @@ +module versatile_fifo_dptam_dw + ( + d_a, + q_a, + adr_a, + we_a, + clk_a, + q_b, + adr_b, + d_b, + we_b, + clk_b + ); + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 14; + input [(DATA_WIDTH-1):0] d_a; + input [(ADDR_WIDTH-1):0] adr_a; + input [(ADDR_WIDTH-1):0] adr_b; + input we_a; + output reg[(DATA_WIDTH-1):0] q_b; + input [(DATA_WIDTH-1):0] d_b; + output reg [(DATA_WIDTH-1):0] q_a; + input we_b; + input clk_a, clk_b; + + reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0] ; + always @ (posedge clk_a) + begin + q_a <= ram[adr_a]; + if (we_a) begin + ram[adr_a] <= d_a; + + end +end + always @ (posedge clk_b) + begin + q_b <= ram[adr_b]; + if (we_b) + begin + ram[adr_b] <= d_b; + + end + + + end +endmodule + \ No newline at end of file Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_16.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_16.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_16.v (revision 11) @@ -0,0 +1,46 @@ +// ========================================================================== +// CRC Generation Unit - Linear Feedback Shift Register implementation +// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL +// https://www.ghsi.de/CRC/index.php? +// ========================================================================= +module CRC_16(BITVAL, Enable, CLK, RST, CRC); + input BITVAL;// Next input bit + input Enable; + input CLK; // Current bit valid (Clock) + input RST; // Init CRC value + output reg [15:0] CRC; // Current output CRC value + + + // We need output registers + wire inv; + + assign inv = BITVAL ^ CRC[15]; // XOR required? + + always @(posedge CLK or posedge RST) begin + if (RST) begin + CRC = 0; + + end + else begin + if (Enable==1) begin + CRC[15] = CRC[14]; + CRC[14] = CRC[13]; + CRC[13] = CRC[12]; + CRC[12] = CRC[11] ^ inv; + CRC[11] = CRC[10]; + CRC[10] = CRC[9]; + CRC[9] = CRC[8]; + CRC[8] = CRC[7]; + CRC[7] = CRC[6]; + CRC[6] = CRC[5]; + CRC[5] = CRC[4] ^ inv; + CRC[4] = CRC[3]; + CRC[3] = CRC[2]; + CRC[2] = CRC[1]; + CRC[1] = CRC[0]; + CRC[0] = inv; + end + end + end + +endmodule Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_7.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_7.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_crc_7.v (revision 11) @@ -0,0 +1,34 @@ +module CRC_7(BITVAL, Enable, CLK, RST, CRC); + input BITVAL;// Next input bit + input Enable; + input CLK; // Current bit valid (Clock) + input RST; // Init CRC value + output [6:0] CRC; // Current output CRC value + + reg [6:0] CRC; + // We need output registers + wire inv; + + assign inv = BITVAL ^ CRC[6]; // XOR required? + + + always @(posedge CLK or posedge RST) begin + if (RST) begin + CRC = 0; + + end + else begin + if (Enable==1) begin + CRC[6] = CRC[5]; + CRC[5] = CRC[4]; + CRC[4] = CRC[3]; + CRC[3] = CRC[2] ^ inv; + CRC[2] = CRC[1]; + CRC[1] = CRC[0]; + CRC[0] = inv; + end + end + end + +endmodule + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_defines.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_defines.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/SD_defines.v (revision 11) @@ -0,0 +1,53 @@ +`define BIG_ENDIAN +`define TIME_OUT_TIME 255 + +//OBS komihåg Master SEL to 1111 vid port dek + +//`define SIM +`define SYN + +`define ACTEL + +`ifdef SYN +`define RESET_CLK_DIV 2 +`define MEM_OFFSET 4 +`endif + +`ifdef SIM +`define RESET_CLK_DIV 0 +`define MEM_OFFSET 1 +`endif + + +//SD-Clock Defines --------- +//Use bus clock or a seperate clock? +`define SD_CLK_BUS_CLK +//`define SD_CLK_SEP + +// Use internal clock divider? +`define SD_CLK_STATIC +//`define SD_CLK_DYNAMIC + + +//SD DATA-transfer defines--- +`define BLOCK_SIZE 512 +`define SD_BUS_WIDTH_4 +`define SD_BUS_W 4 + +//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit. +//Add 18 for crc, endbit and z. +`define BIT_BLOCK 1044 +`define CRC_OFF 19 +`define BIT_BLOCK_REC 1024 + +`define BIT_CRC_CYCLE 16 + +//FIFO defines--------------- + + + + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_controller_fifo_wb.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_controller_fifo_wb.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_controller_fifo_wb.v (revision 11) @@ -0,0 +1,317 @@ +`include "SD_defines.v" + +module sd_controller_fifo_wba +( + + + // WISHBONE common + wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o, + + // WISHBONE slave + wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, + + // WISHBONE master + m_wb_adr_o, m_wb_sel_o, m_wb_we_o, + m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, + m_wb_stb_o, m_wb_ack_i, + m_wb_cti_o, m_wb_bte_o, + //SD BUS + sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o, + sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad + //PLL CLK_IN + // sd_clk_i_pad + +); +input wb_clk_i; // WISHBONE clock +input wb_rst_i; // WISHBONE reset +input [7:0] wb_dat_i; // WISHBONE data input +output [7:0] wb_dat_o; // WISHBONE data output + // WISHBONE error output + +// WISHBONE slave +input [2:0] wb_adr_i; // WISHBONE address input +input [3:0] wb_sel_i; // WISHBONE byte select input +input wb_we_i; // WISHBONE write enable input +input wb_cyc_i; // WISHBONE cycle input +input wb_stb_i; // WISHBONE strobe input + +output reg wb_ack_o; // WISHBONE acknowledge output + +// WISHBONE master +output [31:0] m_wb_adr_o; +output [3:0] m_wb_sel_o; +output m_wb_we_o; + +input [31:0] m_wb_dat_i; +output [31:0] m_wb_dat_o; +output m_wb_cyc_o; +output m_wb_stb_o; +input m_wb_ack_i; +output [2:0] m_wb_cti_o; +output [1:0] m_wb_bte_o; + +input wire [3:0] sd_dat_dat_i; +output wire [3:0] sd_dat_out_o; +output wire sd_dat_oe_o; + +input wire sd_cmd_dat_i; +output wire sd_cmd_out_o; +output wire sd_cmd_oe_o; + +output sd_clk_o_pad; +wire sd_clk_i; +//input sd_clk_i_pad; + +`define tx_cmd_fifo 4'h0 +`define rx_cmd_fifo 4'h1 +`define tx_data_fifo 4'h2 +`define rx_data_fifo 4'h3 +`define status 4'h4 +`define controll 4'h5 +`define timer 4'h6 + +reg [7:0] controll_reg; +reg [7:0] status_reg; +reg [7:0] command_timeout_reg; + +`ifdef SD_CLK_BUS_CLK + assign sd_clk_i = wb_clk_i; +`endif + +`ifdef SD_CLK_SEP + //assign sd_clk_i = sd_clk_i_pad; +`endif +assign sd_clk_o=sd_clk_i; + +reg [1:0] wb_fifo_adr_i_writer; +reg [1:0] wb_fifo_adr_i_reader; +wire [1:0] wb_fifo_adr_i; +reg add_token_read; +wire [7:0] wb_fifo_dat_i; +wire [7:0] wb_fifo_dat_o; +reg [7:0] wb_dat_i_storage; +reg [7:0] wb_dat_o_i; +reg time_enable; +assign sd_clk_o_pad = sd_clk_i ; + + +assign wb_fifo_adr_i = add_token_read ? wb_fifo_adr_i_reader : wb_fifo_adr_i_writer; +assign wb_fifo_dat_i =wb_dat_i_storage; +assign wb_dat_o = wb_adr_i[0] ? wb_fifo_dat_o : wb_dat_o_i ; + + + +wire [1:4]fifo_full ; +wire [1:4]fifo_empty; +reg wb_fifo_we_i; +reg wb_fifo_re_i; +wire [1:0] sd_adr_o; +wire [7:0] sd_dat_o; +wire [7:0] sd_dat_i; +sd_fifo sd_fifo_0 +( + .wb_adr_i (wb_fifo_adr_i ), + .wb_dat_i (wb_fifo_dat_i), + .wb_dat_o (wb_fifo_dat_o ), + .wb_we_i (wb_fifo_we_i), + .wb_re_i (wb_fifo_re_i), + .wb_clk (wb_clk_i), + .sd_adr_i (sd_adr_o ), + .sd_dat_i (sd_dat_o), + .sd_dat_o (sd_dat_i ), + .sd_we_i (sd_we_o), + .sd_re_i (sd_re_o), + .sd_clk (sd_clk_o), + .fifo_full ( fifo_full ), + .fifo_empty (fifo_empty ), + .rst (wb_rst_i) // | controll_reg[0]) + ) ; + +wire [1:0] sd_adr_o_cmd; +wire [7:0] sd_dat_i_cmd; +wire [7:0] sd_dat_o_cmd; + +wire [1:0] sd_adr_o_dat; +wire [7:0] sd_dat_i_dat; +wire [7:0] sd_dat_o_dat; +wire [1:0] st_dat_t; +sd_cmd_phy sdc_cmd_phy_0 +( + .sd_clk (sd_clk_o), + .rst (wb_rst_i ),//| controll_reg[0]), + .cmd_dat_i ( sd_cmd_dat_i ), + .cmd_dat_o (sd_cmd_out_o ), + .cmd_oe_o (sd_cmd_oe_o ), + .sd_adr_o (sd_adr_o_cmd), + .sd_dat_i (sd_dat_i_cmd), + .sd_dat_o (sd_dat_o_cmd), + .sd_we_o (sd_we_o_cmd), + .sd_re_o (sd_re_o_cmd), + .fifo_full ( fifo_full[1:2] ), + .fifo_empty ( fifo_empty [1:2]), + .start_dat_t (st_dat_t), + .fifo_acces_token (fifo_acces_token) + ); + + + sd_data_phy sd_data_phy_0 ( + .sd_clk (sd_clk_o), + .rst (wb_rst_i | controll_reg[0]), + .DAT_oe_o ( sd_dat_oe_o ), + .DAT_dat_o (sd_dat_out_o), + .DAT_dat_i (sd_dat_dat_i ), + .sd_adr_o (sd_adr_o_dat ), + .sd_dat_i (sd_dat_i_dat ), + .sd_dat_o (sd_dat_o_dat ), + .sd_we_o (sd_we_o_dat), + .sd_re_o (sd_re_o_dat), + .fifo_full ( fifo_full[3:4] ), + .fifo_empty ( fifo_empty [3:4]), + .start_dat (st_dat_t), + .fifo_acces (~fifo_acces_token) + ); + + + assign sd_adr_o = fifo_acces_token ? sd_adr_o_cmd : sd_adr_o_dat; + assign sd_dat_o = fifo_acces_token ? sd_dat_o_cmd : sd_dat_o_dat; + assign sd_we_o = fifo_acces_token ? sd_we_o_cmd : sd_we_o_dat; + assign sd_re_o = fifo_acces_token ? sd_re_o_cmd : sd_re_o_dat; + + assign sd_dat_i_dat = sd_dat_i; + assign sd_dat_i_cmd = sd_dat_i; + + + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + if (wb_rst_i) + status_reg<=0; + else begin + status_reg[0] <= fifo_full[1]; + status_reg[1] <= fifo_empty[2]; + status_reg[2] <= fifo_full[3]; + status_reg[3] <= fifo_empty[4]; + end + end + + reg delayed_ack; + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + + if (wb_rst_i) + wb_ack_o <=0; + else + wb_ack_o <=wb_stb_i & wb_cyc_i & ~wb_ack_o & delayed_ack; + + end + + always @(posedge wb_clk_i or posedge wb_rst_i) + begin + + + if ( wb_rst_i )begin + command_timeout_reg<=`TIME_OUT_TIME; + wb_dat_i_storage<=0; + controll_reg<=0; + + wb_fifo_we_i<=0; + wb_fifo_adr_i_writer<=0; + time_enable<=0; + end + else if (wb_stb_i & wb_cyc_i & (~wb_ack_o))begin //CS + + + if (wb_we_i) begin + case (wb_adr_i) + `tx_cmd_fifo : begin + wb_fifo_adr_i_writer<=0; + wb_fifo_we_i<=1&!delayed_ack; + wb_dat_i_storage<=wb_dat_i; + command_timeout_reg<=`TIME_OUT_TIME; + time_enable<=1; + end + `tx_data_fifo : begin + wb_fifo_adr_i_writer<=2; + wb_fifo_we_i<=1&!delayed_ack; + wb_dat_i_storage<=wb_dat_i; + command_timeout_reg<=`TIME_OUT_TIME; + time_enable<=0; + end + `controll : controll_reg <= wb_dat_i; + endcase + end + end + else begin + // wb_fifo_adr_i_writer<=0; + wb_fifo_we_i<=0; + + if (!status_reg[1]) + time_enable<=0; + + if ((command_timeout_reg!=0) && (time_enable)) + command_timeout_reg<=command_timeout_reg-1; + end +end + + +always @(posedge wb_clk_i or posedge wb_rst_i )begin + + + if ( wb_rst_i) begin + add_token_read<=0; + delayed_ack<=0; + wb_fifo_re_i<=0; + wb_fifo_adr_i_reader<=0; + wb_dat_o_i<=0; + end + else begin + delayed_ack<=0; + wb_fifo_re_i<=0; + if (wb_stb_i & wb_cyc_i & (~wb_ack_o)) begin //C + delayed_ack<=delayed_ack+1; + add_token_read<=0; + if (!wb_we_i) begin + + case (wb_adr_i) + `rx_cmd_fifo : begin + + add_token_read<=1; + wb_fifo_adr_i_reader<=1; + wb_fifo_re_i<=1&delayed_ack; + + end + `rx_data_fifo :begin + add_token_read<=1; + wb_fifo_adr_i_reader<=3; + wb_fifo_re_i<=1 & delayed_ack; + + end + `status : wb_dat_o_i <= status_reg; + `timer : wb_dat_o_i <= command_timeout_reg; + + + endcase + end + end +end +end + + +//just to get rid of warnings.... + assign m_wb_adr_o =0; + assign m_wb_sel_o =0; + assign m_wb_we_o=0; + assign m_wb_dat_o =0; + + assign m_wb_cyc_o=0; + assign m_wb_stb_o=0; + assign m_wb_cti_o=0; + assign m_wb_bte_o=0; + + + +endmodule + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_counter.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_counter.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_counter.v (revision 11) @@ -0,0 +1,184 @@ +// module name +//`define CNT_MODULE_NAME sd_counter + +// counter type = [BINARY, GRAY, LFSR] +//`define CNT_TYPE_BINARY +`define CNT_TYPE_GRAY +//`define CNT_TYPE_LFSR + +// q as output +`define CNT_Q +// for gray type counter optional binary output +`define CNT_Q_BIN + +// number of CNT bins +`define CNT_LENGTH 9 + +// clear +//`define CNT_CLEAR + +// set +//`define CNT_SET +`define CNT_SET_VALUE `CNT_LENGTH'h9 + +// wrap around creates shorter cycle than maximum length +//`define CNT_WRAP +`define CNT_WRAP_VALUE `CNT_LENGTH'h9 + +// clock enable +`define CNT_CE + +// q_next as an output +//`define CNT_QNEXT + +// q=0 as an output +//`define CNT_Z + +// q_next=0 as a registered output +//`define CNT_ZQ + + +`define LFSR_LENGTH `CNT_LENGTH + +module sd_counter + ( +`ifdef CNT_TYPE_GRAY + output reg [`CNT_LENGTH:1] q, +`ifdef CNT_Q_BIN + output [`CNT_LENGTH:1] q_bin, +`endif +`else +`ifdef CNT_Q + output [`CNT_LENGTH:1] q, +`endif +`endif +`ifdef CNT_CLEAR + input clear, +`endif +`ifdef CNT_SET + input set, +`endif +`ifdef CNT_REW + input rew, +`endif +`ifdef CNT_CE + input cke, +`endif +`ifdef CNT_QNEXT + output [`CNT_LENGTH:1] q_next, +`endif +`ifdef CNT_Z + output z, +`endif +`ifdef CNT_ZQ + output reg zq, +`endif + input clk, + input rst + ); + +`ifdef CNT_SET + parameter set_value = `CNT_SET_VALUE; +`endif +`ifdef CNT_WRAP + parameter wrap_value = `CNT_WRAP_VALUE; +`endif + + // internal q reg + reg [`CNT_LENGTH:1] qi; + +`ifdef CNT_QNEXT +`else + wire [`CNT_LENGTH:1] q_next; +`endif +`ifdef CNT_REW + wire [`CNT_LENGTH:1] q_next_fw; + wire [`CNT_LENGTH:1] q_next_rew; +`endif + +`ifdef CNT_REW +`else + assign q_next = +`endif +`ifdef CNT_REW + assign q_next_fw = +`endif +`ifdef CNT_CLEAR + clear ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_SET + set ? set_value : +`endif +`ifdef CNT_WRAP + (qi == wrap_value) ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_TYPE_LFSR + {qi[8:1],~(q[`LFSR_LENGTH]^q[1])}; +`else + qi + `CNT_LENGTH'd1; +`endif + +`ifdef CNT_REW + assign q_next_rew = +`ifdef CNT_CLEAR + clear ? `CNT_LENGTH'd0 : +`endif +`ifdef CNT_SET + set ? set_value : +`endif +`ifdef CNT_WRAP + (qi == `CNT_LENGTH'd0) ? wrap_value : +`endif +`ifdef CNT_TYPE_LFSR + {~(q[1]^q[2]),qi[`CNT_LENGTH:2]}; +`else + qi - `CNT_LENGTH'd1; +`endif +`endif + +`ifdef CNT_REW + assign q_next = rew ? q_next_rew : q_next_fw; +`endif + + always @ (posedge clk or posedge rst) + if (rst) + qi <= `CNT_LENGTH'd0; + else +`ifdef CNT_CE + if (cke) +`endif + qi <= q_next; + +`ifdef CNT_Q +`ifdef CNT_TYPE_GRAY + always @ (posedge clk or posedge rst) + if (rst) + q <= `CNT_LENGTH'd0; + else +`ifdef CNT_CE + if (cke) +`endif + q <= (q_next>>1) ^ q_next; +`ifdef CNT_Q_BIN + assign q_bin = qi; +`endif +`else + assign q = q_next; +`endif +`endif + +`ifdef CNT_Z + assign z = (q == `CNT_LENGTH'd0); +`endif + +`ifdef CNT_ZQ + always @ (posedge clk or posedge rst) + if (rst) + zq <= 1'b1; + else +`ifdef CNT_CE + if (cke) +`endif + zq <= q_next == `CNT_LENGTH'd0; +`endif +endmodule Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_cmd_phy.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_cmd_phy.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_cmd_phy.v (revision 11) @@ -0,0 +1,430 @@ +`include "SD_defines.v" +//------------------------- +//------------------------- +module sd_cmd_phy ( +input sd_clk, +input rst, +input cmd_dat_i, +output reg cmd_dat_o, +output reg cmd_oe_o, + +output [1:0] sd_adr_o, +input [7:0] sd_dat_i, +output reg [7:0] sd_dat_o, +output reg sd_we_o, +output reg sd_re_o, +input [1:2] fifo_full, +input [1:2] fifo_empty, +output [1:0] start_dat_t, +output fifo_acces_token + +); +//---------------Input ports--------------- + `define WRITE_CMD 32'h18 +`define READ_CMD 32'h11 +reg [6:0] Response_Size; +`ifdef SIM + `define INIT_DELAY 64 +`else + `define INIT_DELAY 64 + `endif + + `define tx_cmd_fifo_empty fifo_empty [1] + +parameter SEND_SIZE = 48; +parameter CONTENT_SIZE = 40; +parameter NCR = 2 ; + +`define Vector_Index_Write (CONTENT_SIZE-1-cmd_flow_cnt_write) +`define Bit_Nr_Write (SEND_SIZE-cmd_flow_cnt_write) +//FSM +parameter SIZE = 5; +parameter +INIT = 5'b00001, +IDLE = 5'b00010, +WRITE = 5'b00100, +BUFFER_WRITE = 5'b01000, +READ = 5'b10000; + +reg [SIZE-1:0] state; +reg [SIZE-1:0] next_state; + +reg [1:0] start_dat_t_read; +reg [1:0] start_dat_t_write; + +reg [39:0] in_buffer; +reg [2:0] read_byte_cnt; +// +reg [7:0] cmd_flow_cnt_write; +reg [7:0] cmd_flow_cnt_read; + +reg cmd_dat_internal; +// +reg big_resp; + +reg crc_rst_write; +reg crc_en_write; +reg crc_in_write; +wire [6:0] crc_val_write; + +reg [1:0] sd_adr_o_read; +reg [1:0] sd_adr_o_write; + +reg crc_rst_read; +reg crc_en_read; +reg crc_in_read; +wire [6:0] crc_val_read; + +reg crc_buffering_write; +reg block_write; +reg block_read; + +reg in_buff_ptr; +reg out_buff_ptr; +reg [2:0] read_index_cnt; +reg [7:0] in_buff_0; +reg [7:0] in_buff_1; +reg [6:0] crc_in_buff; +reg [7:0] response_status; +reg [6:0] index_check; + +reg add_token_read; + +CRC_7 CRC_7_WRITE( +.BITVAL (crc_in_write), +.Enable (crc_en_write), +.CLK (sd_clk), +.RST (crc_rst_write), +.CRC (crc_val_write)); + + +CRC_7 CRC_7_READ( +.BITVAL (crc_in_read), +.Enable (crc_en_read), +.CLK (sd_clk), +.RST (crc_rst_read), +.CRC (crc_val_read)); + + + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + + cmd_dat_internal <=1'b1; + end + else begin + cmd_dat_internal<=cmd_dat_i; + end + + +end + +always @ (state or cmd_flow_cnt_write or cmd_dat_internal or `tx_cmd_fifo_empty or read_byte_cnt or cmd_flow_cnt_write or cmd_flow_cnt_read ) + +begin : FSM_COMBO + next_state = 0; +case(state) +INIT: begin + if (cmd_flow_cnt_write >= `INIT_DELAY )begin + next_state = IDLE; + end + else begin + next_state = INIT; + end +end +IDLE: begin + if (!`tx_cmd_fifo_empty) + next_state =BUFFER_WRITE; + else if (!cmd_dat_internal) + next_state =READ; + else + next_state =IDLE; + + +end +BUFFER_WRITE: begin + if (read_byte_cnt>=5) + next_state = WRITE; + else + next_state =BUFFER_WRITE; +end + +WRITE : begin + if (cmd_flow_cnt_write >= SEND_SIZE) + next_state = IDLE; + else + next_state = WRITE; + +end +READ : begin + if (cmd_flow_cnt_read >= Response_Size+7) + next_state = IDLE; + else + next_state = READ; + +end + + +default : next_state = INIT; + + endcase +end + + +always @ (posedge sd_clk or posedge rst ) +begin : FSM_SEQ + if (rst ) begin + state <= #1 INIT; + end + else begin + state <= #1 next_state; + end +end +reg fifo_acces_read,fifo_acces_write; +assign fifo_acces_token = fifo_acces_read | fifo_acces_write; +assign sd_adr_o = add_token_read ? sd_adr_o_read : sd_adr_o_write; +assign start_dat_t = add_token_read ? start_dat_t_read : start_dat_t_write; +reg tx_cmd_fifo_empty_tmp; + + +always @ (negedge sd_clk or posedge rst ) +begin : OUTPUT_LOGIC + if (rst ) begin + crc_in_write=0; + crc_en_write=0; + crc_rst_write=0; + fifo_acces_write=0; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_buffering_write=0; + sd_re_o<=0; + read_byte_cnt<=0; + block_read<=0; + sd_adr_o_write<=0; + cmd_flow_cnt_write=0; + start_dat_t_write<=0; + in_buffer<=0; + tx_cmd_fifo_empty_tmp<=0; + Response_Size<=40; + end + else begin + case(state) + INIT : begin + cmd_flow_cnt_write=cmd_flow_cnt_write+1; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_buffering_write=0; + start_dat_t_write<=0; + end + IDLE: begin + cmd_flow_cnt_write=0; + cmd_oe_o=0; + // cmd_dat_o = 0; + start_dat_t_write<=0; + crc_in_write=0; + crc_en_write=0; + crc_rst_write=1; + read_byte_cnt<=0; + block_read<=0; + fifo_acces_write=0; + in_buffer<=0; + end + BUFFER_WRITE : begin + sd_re_o<=0; + fifo_acces_write=1; + tx_cmd_fifo_empty_tmp<=`tx_cmd_fifo_empty; + if (!tx_cmd_fifo_empty_tmp) begin + if(sd_re_o) + read_byte_cnt <= read_byte_cnt+1; + sd_adr_o_write <=0; + sd_re_o<=1; + if(sd_re_o) begin + case (read_byte_cnt) //If data is Avaible next cycle? + 0: in_buffer[39:32] <=sd_dat_i; + 1: in_buffer[31:24] <=sd_dat_i; + 2: in_buffer[23:16] <=sd_dat_i; + 3: in_buffer[15:8] <=sd_dat_i; + 4: in_buffer[7:0] <=sd_dat_i; + endcase + if (in_buffer[39]) + Response_Size<=127; + else + Response_Size<=40; + + if (in_buffer[37:32] == `READ_CMD) + block_read<=1; + end + + end + end + WRITE: begin + sd_re_o<=0; + cmd_oe_o=1; + cmd_dat_o = 1; + crc_en_write =0; + crc_rst_write=0; + crc_en_write=1; + + + if (crc_buffering_write==1) begin + cmd_oe_o =1; + if (`Bit_Nr_Write > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit + if (cmd_flow_cnt_write==0) + cmd_dat_o = 0; + else + cmd_dat_o = in_buffer[`Vector_Index_Write]; + + if (`Bit_Nr_Write > 9 ) begin //1 step ahead + crc_in_write = in_buffer[`Vector_Index_Write-1]; + end else begin + crc_en_write=0; + end + end + else if ( (`Bit_Nr_Write <=8) && (`Bit_Nr_Write >=2) ) begin + crc_en_write=0; + cmd_dat_o = crc_val_write[(`Bit_Nr_Write)-2]; + if (block_read) + start_dat_t_write<=2'b10; + + end + else begin + cmd_dat_o =1'b1; + + end + cmd_flow_cnt_write=cmd_flow_cnt_write+1; + end + + else begin //Pre load CRC + crc_buffering_write=1; + + crc_in_write = 0; + end + + + + end + + endcase + end +end + +always @ (posedge sd_clk or posedge rst ) +begin + if (rst) begin + crc_rst_read=1; + crc_en_read=0; + crc_in_read=0; + cmd_flow_cnt_read=0; + response_status =0; + block_write=0; + index_check=0; + in_buff_ptr=0; + out_buff_ptr=0; + sd_adr_o_read<=0; + add_token_read=0; + in_buff_0<=0; + in_buff_1<=0; + read_index_cnt=0; + fifo_acces_read=0; + sd_dat_o<=0; + start_dat_t_read<=0; + sd_we_o<=0; + crc_in_buff=0; + end + else begin + case (state) + IDLE : begin + crc_en_read=0; + crc_rst_read=1; + cmd_flow_cnt_read=1; + index_check=0; + block_write=0; + in_buff_ptr=0; + out_buff_ptr=0; + add_token_read=0; + read_index_cnt=0; + sd_we_o<=0; + add_token_read=0; + fifo_acces_read=0; + start_dat_t_read<=0; + end + READ : begin + fifo_acces_read=1; + add_token_read=1; //Takes command over addres + crc_en_read=1; + crc_rst_read=0; + sd_we_o<=0; + if (in_buff_ptr != out_buff_ptr) begin + sd_adr_o_read <=1; + sd_we_o<=1; + if (in_buff_ptr) + sd_dat_o <=in_buff_0; + else + sd_dat_o <=in_buff_1; + + out_buff_ptr=out_buff_ptr+1; + end + + if (cmd_flow_cnt_read < (Response_Size))begin //40 First Bits + crc_in_read = cmd_dat_internal; + if (cmd_flow_cnt_read<8 ) begin //1+1+6 (S,T,Index) + + index_check[7-cmd_flow_cnt_read] = cmd_dat_internal; + if (index_check[5:0] == `WRITE_CMD) begin + block_write=1; + end + end + else begin + if (!in_buff_ptr) begin + in_buff_0[7-read_index_cnt]<=cmd_dat_internal; + end + else begin + in_buff_1[7-read_index_cnt]<=cmd_dat_internal; + end + read_index_cnt=read_index_cnt+1; + if (read_index_cnt==0) + in_buff_ptr=in_buff_ptr+1; + end + end + else if ( cmd_flow_cnt_read - Response_Size <=6 ) begin //7-Crc Bit + crc_in_buff [(Response_Size+6)-(cmd_flow_cnt_read)] = cmd_dat_internal; + crc_en_read=0; + end + else begin //Commpare CRC read with calcualted. + if ((crc_in_buff != crc_val_read)) begin + response_status[0]=1; + end + else begin + response_status[0]=0; + end + sd_adr_o_read <=1; + sd_we_o<=1; + sd_dat_o<=response_status; + + if (block_write) + start_dat_t_read<=2'b01; + + end + + cmd_flow_cnt_read = cmd_flow_cnt_read+1; + end + + + + + endcase + end + +end + + + + + + + +endmodule + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_fifo.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_fifo.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/rtl/sdc_fifo/sd_fifo.v (revision 11) @@ -0,0 +1,196 @@ + +module sd_fifo + ( + input [1:0] wb_adr_i, + input [7:0] wb_dat_i, + output [7:0] wb_dat_o, + input wb_we_i, + input wb_re_i, + input wb_clk, + input [1:0] sd_adr_i, + input [7:0] sd_dat_i, + output [7:0] sd_dat_o, + input sd_we_i, + input sd_re_i, + input sd_clk, + output [1:4] fifo_full, + output [1:4] fifo_empty, + input rst + ); + + wire [8:0] wptr1, rptr1, wptr2, rptr2, wptr3, rptr3, wptr4, rptr4; + wire [8:0] wadr1, radr1, wadr2, radr2, wadr3, radr3, wadr4, radr4; + + wire dpram_we_a, dpram_we_b; + wire [10:0] dpram_a_a, dpram_a_b; + + sd_counter wptr1a + ( + .q(wptr1), + .q_bin(wadr1), + .cke((wb_adr_i==2'd0) & wb_we_i & !fifo_full[1]), + .clk(wb_clk), + .rst(rst) + ); + + sd_counter rptr1a + ( + .q(rptr1), + .q_bin(radr1), + .cke((sd_adr_i==2'd0) & sd_re_i & !fifo_empty[1]), + .clk(sd_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp1 + ( + .wptr(wptr1), + .rptr(rptr1), + .fifo_empty(fifo_empty[1]), + .fifo_full(fifo_full[1]), + .wclk(wb_clk), + .rclk(sd_clk), + .rst(rst) + ); + + sd_counter wptr2a + ( + .q(wptr2), + .q_bin(wadr2), + .cke((sd_adr_i==2'd1) & sd_we_i & !fifo_full[2]), + .clk(sd_clk), + .rst(rst) + ); + + sd_counter rptr2a + ( + .q(rptr2), + .q_bin(radr2), + .cke((wb_adr_i==2'd1) & wb_re_i & !fifo_empty[2]), + .clk(wb_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp2 + ( + .wptr(wptr2), + .rptr(rptr2), + .fifo_empty(fifo_empty[2]), + .fifo_full(fifo_full[2]), + .wclk(sd_clk), + .rclk(wb_clk), + .rst(rst) + ); + + sd_counter wptr3a + ( + .q(wptr3), + .q_bin(wadr3), + .cke((wb_adr_i==2'd2) & wb_we_i & !fifo_full[3]), + .clk(wb_clk), + .rst(rst) + ); + + sd_counter rptr3a + ( + .q(rptr3), + .q_bin(radr3), + .cke((sd_adr_i==2'd2) & sd_re_i & !fifo_empty[3]), + .clk(sd_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp3 + ( + .wptr(wptr3), + .rptr(rptr3), + .fifo_empty(fifo_empty[3]), + .fifo_full(fifo_full[3]), + .wclk(wb_clk), + .rclk(sd_clk), + .rst(rst) + ); + + sd_counter wptr4a + ( + .q(wptr4), + .q_bin(wadr4), + .cke((sd_adr_i==2'd3) & sd_we_i & !fifo_full[4]), + .clk(sd_clk), + .rst(rst) + ); + + sd_counter rptr4a + ( + .q(rptr4), + .q_bin(radr4), + .cke((wb_adr_i==2'd3) & wb_re_i & !fifo_empty[4]), + .clk(wb_clk), + .rst(rst) + ); + + versatile_fifo_async_cmp + # + ( + .ADDR_WIDTH(9) + ) + cmp4 + ( + .wptr(wptr4), + .rptr(rptr4), + .fifo_empty(fifo_empty[4]), + .fifo_full(fifo_full[4]), + .wclk(sd_clk), + .rclk(wb_clk), + .rst(rst) + ); + + assign dpram_we_a = ((wb_adr_i==2'd0) & !fifo_full[1]) ? wb_we_i : + ((wb_adr_i==2'd2) & !fifo_full[3]) ? wb_we_i : + 1'b0; + assign dpram_we_b = ((sd_adr_i==2'd1) & !fifo_full[2]) ? sd_we_i : + ((sd_adr_i==2'd3) & !fifo_full[4]) ? sd_we_i : + 1'b0; + assign dpram_a_a = (wb_adr_i==2'd0) ? {wb_adr_i,wadr1} : + (wb_adr_i==2'd1) ? {wb_adr_i,radr2} : + (wb_adr_i==2'd2) ? {wb_adr_i,wadr3} : + {wb_adr_i,radr4}; + assign dpram_a_b = (sd_adr_i==2'd0) ? {sd_adr_i,radr1} : + (sd_adr_i==2'd1) ? {sd_adr_i,wadr2} : + (sd_adr_i==2'd2) ? {sd_adr_i,radr3} : //(sd_adr_i==2'd3) ? {sd_adr_i,radr3} :--->(sd_adr_i==2'd2) ? {sd_adr_i,radr3} : + {sd_adr_i,wadr4}; + + //versatile_fifo_dual_port_ram_dc_dw + versatile_fifo_dptam_dw + dpram + ( + .d_a(wb_dat_i), + .q_a(wb_dat_o), + .adr_a(dpram_a_a), + .we_a(dpram_we_a), + .clk_a(wb_clk), + .q_b(sd_dat_o), + .adr_b(dpram_a_b), + .d_b(sd_dat_i), + .we_b(dpram_we_b), + .clk_b(sd_clk) + ); + +endmodule // sd_fifo + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/backend/proasic3_redused.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/backend/proasic3_redused.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/backend/proasic3_redused.v (revision 11) @@ -0,0 +1,2423 @@ +/******************************************************************** + Actel ProASIC3 Verilog Library + NAME: proasic3.v + DATE: Oct 31, 2006 +*********************************************************************/ + +`timescale 1 ns / 100 ps + +//---------------------------------------------------------------------- +//--- VERILOG LIBRRAY PRIMITIVE SECTION +//---------------------------------------------------------------------- + + + +primitive Dffpr (Q, D, CLK, CLR, PRE, E, NOTIFIER_REG); + output Q; + input NOTIFIER_REG; + input D, CLK, E, CLR, PRE; + reg Q; + + table + + // D CLK CLR PRE E NOTIFIER_REG : Qt : Qt+1 + + 1 (01) 1 1 0 ? : ? : 1; // clocked data + 0 (01) 1 1 0 ? : ? : 0; // clocked data + 1 (01) 1 1 x ? : 1 : 1; // clocked data + 0 (01) 1 1 x ? : 0 : 0; + 0 (01) 1 1 x ? : 1 : x; + 1 (01) 1 1 x ? : 0 : x; + 0 (01) x 1 0 ? : ? : 0; // pessimism + 1 (01) 1 x 0 ? : ? : 1; // pessimism + ? ? 1 x ? ? : 1 : 1; // pessimism + 0 ? 1 x ? ? : x : x; // pessimism + ? ? 1 x ? ? : 0 : x; + ? ? x x ? ? : ? : x; + ? ? x 0 ? ? : ? : x; + ? ? x 1 ? ? : 0 : 0; + ? ? x 1 ? ? : 1 : x; + ? ? 0 ? ? ? : ? : 0; + ? ? 1 0 ? ? : ? : 1; + 1 (x1) 1 1 0 ? : 1 : 1; // reducing pessimism + 0 (x1) 1 1 0 ? : 0 : 0; + 1 (0x) 1 1 0 ? : 1 : 1; + 0 (0x) 1 1 0 ? : 0 : 0; + 1 (x1) 1 1 x ? : 1 : 1; // reducing pessimism + 0 (x1) 1 1 x ? : 0 : 0; + 1 (0x) 1 1 x ? : 1 : 1; + 0 (0x) 1 1 x ? : 0 : 0; + ? (?1) 1 1 1 ? : ? : -; //no action for CE = 1 + ? (0x) 1 1 1 ? : ? : -; //no action for CE = 1 + ? ? ? ? * ? : ? : -; + ? (?0) ? ? ? ? : ? : -; // ignore falling clock + ? (1x) ? ? ? ? : ? : -; // ignore falling clock + * ? ? ? ? ? : ? : -; // ignore data edges + ? ? (?1) ? ? ? : ? : -; // ignore the edges on + ? ? ? (?1) ? ? : ? : -; // set and clear + ? ? ? ? ? * : ? : x; + + endtable + endprimitive + + +primitive UDP_MUX2 (Q, A, B, SL); +output Q; +input A, B, SL; + +// FUNCTION : TWO TO ONE MULTIPLEXER + + table + // A B SL : Q + 0 0 ? : 0 ; + 1 1 ? : 1 ; + + 0 ? 1 : 0 ; + 1 ? 1 : 1 ; + + ? 0 0 : 0 ; + ? 1 0 : 1 ; + + endtable +endprimitive + + + +primitive UDPN_MUX2 (Q, A, B, SL); +output Q; +input A, B, SL; + +// FUNCTION : TWO TO ONE MULTIPLEXER + + table + // A B SL : Q + 0 0 ? : 1 ; + 1 1 ? : 0 ; + + 0 ? 1 : 1 ; + 1 ? 1 : 0 ; + + ? 0 0 : 1 ; + ? 1 0 : 0 ; + + endtable +endprimitive + + +primitive UFPRB (Q, D, CP, RB, NOTIFIER_REG); + + output Q; + input NOTIFIER_REG, + D, CP, RB; + reg Q; + +// FUNCTION : POSITIVE EDGE TRIGGERED D FLIP-FLOP WITH ACTIVE LOW +// ASYNCHRONOUS CLEAR ( Q OUTPUT UDP ). + + table + // D CP RB NOTIFIER_REG : Qt : Qt+1 + + 1 (01) 1 ? : ? : 1; // clocked data + 0 (01) 1 ? : ? : 0; + + 0 (01) x ? : ? : 0; // pessimism + 0 ? x ? : 0 : 0; // pessimism + + 1 0 x ? : 0 : 0; // pessimism + 1 x (?x) ? : 0 : 0; // pessimism + 1 1 (?x) ? : 0 : 0; // pessimism + x 0 x ? : 0 : 0; // pessimism + x x (?x) ? : 0 : 0; // pessimism + x 1 (?x) ? : 0 : 0; // pessimism + 1 (x1) 1 ? : 1 : 1; // reducing pessimism + 0 (x1) 1 ? : 0 : 0; + 1 (0x) 1 ? : 1 : 1; + 0 (0x) 1 ? : 0 : 0; + ? ? 0 ? : ? : 0; // asynchronous clear + ? (?0) ? ? : ? : -; // ignore falling clock + ? (1x) ? ? : ? : -; // ignore falling clock + * ? ? ? : ? : -; // ignore the edges on data + ? ? (?1) ? : ? : -; // ignore the edges on clear + ? ? ? * : ? : x; + endtable +endprimitive + + + + +//---------------------------------------------------------------------- +//--- VERILOG LIBRRAY MODULES SECTION +//---------------------------------------------------------------------- + + + + +/*-------------------------------------------------------------------- + CELL NAME : AND2 + CELL TYPE : comb + CELL LOGIC : Y = A & B +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AND2(Y,A,B); + input A,B; + output Y; + + and U2(Y, A, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------------- + CELL NAME : AO1 + CELL TYPE : comb + CELL LOGIC : Y = (A & B) + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AO1(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + and U142(NET_0_0, A, B); + or U143(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AO1A + CELL TYPE : comb + CELL LOGIC : Y = (!A & B) + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AO1A(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_31(A_, A); + and U147(NET_0_0, A_, B); + or U148(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + +/*-------------------------------------------------------------------- + CELL NAME : AO1B + CELL TYPE : comb + CELL LOGIC : Y = (A & B) + !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AO1B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_32(C_, C); + and U152(NET_0_0, A, B); + or U153(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AO1D + CELL TYPE : comb + CELL LOGIC : Y = (!A & !B) + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AO1D(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_35(A_, A); + not INV_36(B_, B); + and U162(NET_0_0, A_, B_); + or U163(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AOI1 + CELL TYPE : comb + CELL LOGIC : Y = !(A & B + C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AOI1(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + and U192(NET_0_0, A, B); + nor U193(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------------- + CELL NAME : AOI1B + CELL TYPE : comb + CELL LOGIC : Y = !(A & B + !C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AOI1B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_45(C_, C); + and U202(NET_0_0, A, B); + nor U203(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AO1C + CELL TYPE : comb + CELL LOGIC : Y = (!A & B) + !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AO1C(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_33(A_, A); + not INV_34(C_, C); + and U157(NET_0_0, A_, B); + or U158(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + +/*-------------------------------------------------------------------- + CELL NAME : AX1 + CELL TYPE : comb + CELL LOGIC : Y = (!A & B) ^ C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AX1(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_57(A_, A); + and U245(NET_0_0, A_, B); + xor U246(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------------- + CELL NAME : AX1B + CELL TYPE : comb + CELL LOGIC : Y = (!A & !B) ^ C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AX1B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_59(A_, A); + not INV_60(B_, B); + and U255(NET_0_0, A_, B_); + xor U256(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + + +/*-------------------------------------------------------------------- + CELL NAME : AX1C + CELL TYPE : comb + CELL LOGIC : Y = (A & B) ^ C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AX1C(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + and U260(NET_0_0, A, B); + xor U261(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AX1D + CELL TYPE : comb + CELL LOGIC : Y = !((!A & !B) ^ C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AX1D(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_61(A_, A); + not INV_62(B_, B); + and U265(NET_0_0, A_, B_); + xnor U266(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : AX1E + CELL TYPE : comb + CELL LOGIC : Y = !((A & B) ^ C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module AX1E(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + and U270(NET_0_0, A, B); + xnor U271(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + +/*-------------------------------------------------------------------- + CELL NAME : CLKINT + CELL TYPE : comb + CELL LOGIC : Y = A +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module CLKINT(Y,A); + input A; + output Y; + + assign Y = A; + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------- + CELL NAME : DFN1C1 + CELL TYPE : sequential Logic + CELL SEQ EQN : DFF[Q=Q,CLK =CLK, CLR=CLR, D=D ]; +----------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module DFN1C1(CLR, CLK, Q,D); + input D,CLR,CLK; + output Q; + reg NOTIFY_REG; + + not INV_CLR_0(CLR_0, CLR); + + UFPRB DF_0( Q, D, CLK, CLR_0, NOTIFY_REG ); + +// some temp signals created for timing checking sections + + not U0_I2 (_CLR0, CLR); + buf U_c0 (Enable01,_CLR0); + buf U_c2 (Enable02, _CLR0); + buf U_c6 (Enable05, _CLR0); + +//-------------------------------------------------------------- +// Timing Checking Section +//------------------------------------------------------------- + + specify + + specparam tpdLH_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdLH_CLR_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLR_to_Q = (0.1:0.1:0.1); + + + + //check timing delay for output + + (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q); + (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q); + + //checking setup and hold timing for inputs + + $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG); + + //checking timing for control signals + + $hold(posedge CLK, negedge CLR,0.0, NOTIFY_REG); + + //checking the pulse width + + $width(posedge CLK &&& Enable05 ,0, 0, NOTIFY_REG); + $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG); + $width(posedge CLR, 0.0, 0, NOTIFY_REG); + + //checing the recovery data + + $recovery(negedge CLR, posedge CLK, 0.0, NOTIFY_REG); + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + +/*-------------------------------------------------------------- + CELL NAME : DFN1E1C1 + CELL TYPE : sequential Logic + CELL SEQ EQN : DFF[Q=Q,CLK =CLK, E=E, CLR=CLR, D=D ]; +----------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module DFN1E1C1(CLR, E, CLK, Q,D); + input D,CLR,E,CLK; + output Q; + supply1 VCC_0; + reg NOTIFY_REG; + + not INV_CLR_0(CLR_0, CLR); + not INV_EN_0(E_0, E); + + Dffpr DF_0(Q, D,CLK,CLR_0, VCC_0, E_0, NOTIFY_REG); + +// some temp signals created for timing checking sections + + not U0_I2 (_CLR0, CLR); + and U_c0 (Enable01, E, _CLR0); + and U_c2 (Enable02, E, _CLR0); + buf U_c4 (Enable04, E); + buf U_c6 (Enable05, _CLR0); + +//-------------------------------------------------------------- +// Timing Checking Section +//------------------------------------------------------------- + + specify + + specparam tpdLH_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdLH_CLR_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLR_to_Q = (0.1:0.1:0.1); + + + + //check timing delay for output + + (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q); + (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q); + + //checking setup and hold timing for inputs + + $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG); + + //checking timing for control signals + + $setup(posedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG); + $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable04, negedge CLR,0.0, NOTIFY_REG); + + //checking the pulse width + + $width(posedge CLK &&& Enable05 ,0, 0, NOTIFY_REG); + $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG); + $width(posedge CLR, 0.0, 0, NOTIFY_REG); + + //checing the recovery data + + $recovery(negedge CLR, posedge CLK &&& Enable04, 0.0, NOTIFY_REG); + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------- + CELL NAME : DFN1E0C1 + CELL TYPE : sequential Logic + CELL SEQ EQN : DFF[Q=Q,CLK =CLK, _E=E, CLR=CLR, D=D ]; +----------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module DFN1E0C1(CLR, E, CLK, Q,D); + input D,CLR,E,CLK; + output Q; + supply1 VCC_0; + reg NOTIFY_REG; + + not INV_CLR_0(CLR_0, CLR); + + Dffpr DF_0(Q, D,CLK,CLR_0, VCC_0, E, NOTIFY_REG); + +// some temp signals created for timing checking sections + + not U0_I2 (_CLR0, CLR); + not U0_I3 (_E0, E); + and U_c0 (Enable01, _E0, _CLR0); + and U_c2 (Enable02, _E0, _CLR0); + buf U_c4 (Enable04, _E0); + buf U_c6 (Enable05, _CLR0); + +//-------------------------------------------------------------- +// Timing Checking Section +//------------------------------------------------------------- + + specify + + specparam tpdLH_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdLH_CLR_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLR_to_Q = (0.1:0.1:0.1); + + + + //check timing delay for output + + (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q); + (posedge CLR => (Q +: 1'b0)) = (tpdLH_CLR_to_Q, tpdHL_CLR_to_Q); + + //checking setup and hold timing for inputs + + $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG); + + //checking timing for control signals + + $setup(posedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG); + $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable04, negedge CLR,0.0, NOTIFY_REG); + + //checking the pulse width + + $width(posedge CLK &&& Enable05 ,0, 0, NOTIFY_REG); + $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG); + $width(posedge CLR, 0.0, 0, NOTIFY_REG); + + //checing the recovery data + + $recovery(negedge CLR, posedge CLK &&& Enable04, 0.0, NOTIFY_REG); + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------- + CELL NAME : DFN1E1P1 + CELL TYPE : sequential Logic + CELL SEQ EQN : DFF[Q=Q,CLK =CLK, E=E, PRE=PRE, D=D ]; +----------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module DFN1E1P1(PRE, E, CLK, Q,D); + input D,PRE,E,CLK; + output Q; + supply1 VCC_0; + reg NOTIFY_REG; + + not INV_PRE_0(PRE_0, PRE); + not INV_EN_0(E_0, E); + + Dffpr DF_0(Q, D,CLK,VCC_0, PRE_0, E_0, NOTIFY_REG); + +// some temp signals created for timing checking sections + + not U0_I1 (_PRE0, PRE); + and U_c0 (Enable01, E, _PRE0); + buf U_c2 (Enable02, E); + and U_c4 (Enable04, E, _PRE0); + buf U_c6 (Enable05, _PRE0); + +//-------------------------------------------------------------- +// Timing Checking Section +//------------------------------------------------------------- + + specify + + specparam tpdLH_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdLH_PRE_to_Q = (0.1:0.1:0.1); + specparam tpdHL_PRE_to_Q = (0.1:0.1:0.1); + + + + //check timing delay for output + + (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q); + (posedge PRE => (Q +: 1'b1)) = (tpdLH_PRE_to_Q, tpdHL_PRE_to_Q); + + //checking setup and hold timing for inputs + + $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG); + + //checking timing for control signals + + $setup(posedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, posedge E,0.0, NOTIFY_REG); + $setup(negedge E,posedge CLK &&& Enable05, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable05, negedge E,0.0, NOTIFY_REG); + + $hold(posedge CLK &&& Enable02, negedge PRE,0.0, NOTIFY_REG); + + //checking the pulse width + + $width(posedge CLK &&& Enable05 ,0, 0, NOTIFY_REG); + $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG); + $width(posedge PRE, 0.0, 0, NOTIFY_REG); + + //checing the recovery data + + $recovery(negedge PRE, posedge CLK &&& Enable02, 0.0, NOTIFY_REG); + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------- + CELL NAME : DFN1P1 + CELL TYPE : sequential Logic + CELL SEQ EQN : DFF[Q=Q,CLK =CLK, PRE=PRE, D=D ]; +----------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module DFN1P1(PRE, CLK, Q,D); + input D,PRE,CLK; + output Q; + supply1 VCC_0; + supply0 GND_0; + reg NOTIFY_REG; + + not INV_PRE_0(PRE_0, PRE); + + Dffpr DF_0(Q, D,CLK,VCC_0, PRE_0, GND_0, NOTIFY_REG); + +// some temp signals created for timing checking sections + + not U0_I1 (_PRE0, PRE); + buf U_c0 (Enable01, _PRE0); + buf U_c4 (Enable04, _PRE0); + buf U_c6 (Enable05, _PRE0); + +//-------------------------------------------------------------- +// Timing Checking Section +//------------------------------------------------------------- + + specify + + specparam tpdLH_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdHL_CLK_to_Q = (0.1:0.1:0.1); + specparam tpdLH_PRE_to_Q = (0.1:0.1:0.1); + specparam tpdHL_PRE_to_Q = (0.1:0.1:0.1); + + + + //check timing delay for output + + (posedge CLK => (Q +: D))=(tpdLH_CLK_to_Q, tpdHL_CLK_to_Q); + (posedge PRE => (Q +: 1'b1)) = (tpdLH_PRE_to_Q, tpdHL_PRE_to_Q); + + //checking setup and hold timing for inputs + + $setup(posedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $setup(negedge D,posedge CLK &&& Enable01, 0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, posedge D,0.0, NOTIFY_REG); + $hold(posedge CLK &&& Enable01, negedge D,0.0, NOTIFY_REG); + + //checking timing for control signals + + + $hold(posedge CLK, negedge PRE,0.0, NOTIFY_REG); + + //checking the pulse width + + $width(posedge CLK &&& Enable05 ,0, 0, NOTIFY_REG); + $width(negedge CLK &&& Enable05, 0, 0, NOTIFY_REG); + $width(posedge PRE, 0.0, 0, NOTIFY_REG); + + //checing the recovery data + + $recovery(negedge PRE, posedge CLK, 0.0, NOTIFY_REG); + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + +/*-------------------------------------------------------------------- + CELL NAME : GND + CELL TYPE : comb + CELL LOGIC : Y=0 +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module GND(Y); + output Y; + + supply0 Y; + + specify + + specparam MacroType = "comb"; + + //pin to pin path delay + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------------- + CELL NAME : MX2 + CELL TYPE : comb + CELL LOGIC : Y = (A & !S) + (B & S) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module MX2(Y,A,S,B); + input A,S,B; + output Y; + wire NET_0_0, NET_0_1; + + not INV_110(S_, S); + UDP_MUX2 U594(Y, A, B, S_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_S_to_Y = (0.1:0.1:0.1); + specparam tpdHL_S_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (S => Y ) = ( tpdLH_S_to_Y, tpdHL_S_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NAND2 + CELL TYPE : comb + CELL LOGIC : Y = !(A & B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NAND2(Y,A,B); + input A,B; + output Y; + + nand U610(Y, A, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR2 + CELL TYPE : comb + CELL LOGIC : Y = !(A + B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR2(Y,A,B); + input A,B; + output Y; + + nor U649(Y, A, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR2A + CELL TYPE : comb + CELL LOGIC : Y = !(!A + B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR2A(Y,A,B); + input A,B; + output Y; + + not INV_130(A_, A); + nor U652(Y, A_, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR2B + CELL TYPE : comb + CELL LOGIC : Y = !(!A + !B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR2B(Y,A,B); + input A,B; + output Y; + + not INV_131(A_, A); + not INV_132(B_, B); + nor U655(Y, A_, B_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR3 + CELL TYPE : comb + CELL LOGIC : Y = !(A + B + C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR3(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + or U662(NET_0_0, A, B); + nor U663(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR3A + CELL TYPE : comb + CELL LOGIC : Y = !(!A + B + C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR3A(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_134(A_, A); + or U667(NET_0_0, A_, B); + nor U668(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR3B + CELL TYPE : comb + CELL LOGIC : Y = !(!A + !B + C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR3B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_135(A_, A); + not INV_136(B_, B); + or U672(NET_0_0, A_, B_); + nor U673(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : NOR3C + CELL TYPE : comb + CELL LOGIC : Y = !(!A + !B + !C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module NOR3C(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_137(A_, A); + not INV_138(B_, B); + not INV_139(C_, C); + or U677(NET_0_0, A_, B_); + nor U678(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OA1 + CELL TYPE : comb + CELL LOGIC : Y = (A + B) & C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OA1(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + or U692(NET_0_0, A, B); + and U693(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OA1A + CELL TYPE : comb + CELL LOGIC : Y = (!A + B) & C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OA1A(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_143(A_, A); + or U697(NET_0_0, A_, B); + and U698(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OA1B + CELL TYPE : comb + CELL LOGIC : Y = !C & (A + B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OA1B(Y,C,A,B); + input C,A,B; + output Y; + wire NET_0_0; + + not INV_144(C_, C); + and U701(Y, C_, NET_0_0); + or U703(NET_0_0, A, B); + + specify + + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OA1C + CELL TYPE : comb + CELL LOGIC : Y = (!A + B) & !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OA1C(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_145(A_, A); + not INV_146(C_, C); + or U707(NET_0_0, A_, B); + and U708(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR2 + CELL TYPE : comb + CELL LOGIC : Y = A + B +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR2(Y,A,B); + input A,B; + output Y; + + or U756(Y, A, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR2A + CELL TYPE : comb + CELL LOGIC : Y = !A + B +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR2A(Y,A,B); + input A,B; + output Y; + + not INV_156(A_, A); + or U759(Y, A_, B); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR2B + CELL TYPE : comb + CELL LOGIC : Y = !A + !B +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR2B(Y,A,B); + input A,B; + output Y; + + not INV_157(A_, A); + not INV_158(B_, B); + or U762(Y, A_, B_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR3 + CELL TYPE : comb + CELL LOGIC : Y = A + B + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR3(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + or U769(NET_0_0, A, B); + or U770(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR3A + CELL TYPE : comb + CELL LOGIC : Y = !A + B + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR3A(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_160(A_, A); + or U774(NET_0_0, A_, B); + or U775(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR3B + CELL TYPE : comb + CELL LOGIC : Y = !A + !B + C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR3B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_161(A_, A); + not INV_162(B_, B); + or U779(NET_0_0, A_, B_); + or U780(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : OR3C + CELL TYPE : comb + CELL LOGIC : Y = !A + !B + !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OR3C(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_163(A_, A); + not INV_164(B_, B); + not INV_165(C_, C); + or U784(NET_0_0, A_, B_); + or U785(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------------- + CELL NAME : OAI1 + CELL TYPE : comb + CELL LOGIC : Y = !((A + B) & C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module OAI1(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + or U732(NET_0_0, A, B); + nand U733(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + + +/*-------------------------------------------------------------------- + CELL NAME : VCC + CELL TYPE : comb + CELL LOGIC : Y=1 +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module VCC(Y); + output Y; + + supply1 Y; + + specify + + specparam MacroType = "comb"; + + //pin to pin path delay + + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : XA1B + CELL TYPE : comb + CELL LOGIC : Y = (A ^ B) & !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module XA1B(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_173(A_, A); + not INV_174(B_, B); + not INV_175(C_, C); + UDP_MUX2 U949(NET_0_0, B, B_, A_); + and U951(Y, NET_0_0, C_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + + +/*-------------------------------------------------------------------- + CELL NAME : XNOR2 + CELL TYPE : comb + CELL LOGIC : Y = !(A ^ B) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module XNOR2(Y,A,B); + input A,B; + output Y; + + not INV_183(A_, A); + not INV_184(B_, B); + UDPN_MUX2 U972(Y, B, B_, A_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : XNOR3 + CELL TYPE : comb + CELL LOGIC : Y = !(A ^ B ^ C) +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module XNOR3(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0; + + not INV_187(A_, A); + not INV_188(B_, B); + UDP_MUX2 U981(NET_0_0, B, B_, A_); + xnor U983(Y, NET_0_0, C); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : XOR2 + CELL TYPE : comb + CELL LOGIC : Y = A ^ B +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module XOR2(Y,A,B); + input A,B; + output Y; + + not INV_193(A_, A); + not INV_194(B_, B); + UDP_MUX2 U998(Y, B, B_, A_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + + +/*-------------------------------------------------------------------- + CELL NAME : ZOR3 + CELL TYPE : comb + CELL LOGIC : Y = A & B & C + !A & !B & !C +---------------------------------------------------------------------*/ + +`suppress_faults +`enable_portfaults +`celldefine +`delay_mode_path +`timescale 1 ns / 100 ps + +module ZOR3(Y,A,B,C); + input A,B,C; + output Y; + wire NET_0_0, NET_0_1, NET_0_2, NET_0_3; + + not INV_199(A_, A); + not INV_200(B_, B); + not INV_201(C_, C); + and U1013(NET_0_0, A, B); + UDP_MUX2 U1014(Y, NET_0_0, NET_0_2, C); + and U1017(NET_0_2, A_, B_); + + specify + + specparam tpdLH_A_to_Y = (0.1:0.1:0.1); + specparam tpdHL_A_to_Y = (0.1:0.1:0.1); + specparam tpdLH_B_to_Y = (0.1:0.1:0.1); + specparam tpdHL_B_to_Y = (0.1:0.1:0.1); + specparam tpdLH_C_to_Y = (0.1:0.1:0.1); + specparam tpdHL_C_to_Y = (0.1:0.1:0.1); + specparam MacroType = "comb"; + + //pin to pin path delay + + (A => Y ) = ( tpdLH_A_to_Y, tpdHL_A_to_Y ); + (B => Y ) = ( tpdLH_B_to_Y, tpdHL_B_to_Y ); + (C => Y ) = ( tpdLH_C_to_Y, tpdHL_C_to_Y ); + endspecify + +endmodule + +`endcelldefine +`disable_portfaults +`nosuppress_faults + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/vlogfmt_mem.v =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/vlogfmt_mem.v (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/vlogfmt_mem.v (revision 11) @@ -0,0 +1,129 @@ +//Formatted flash ROM generation: +memory_array[0] = 8'b00000000; +memory_array[1] = 8'b00000000; +memory_array[2] = 8'b00000000; +memory_array[3] = 8'b00011000; +memory_array[4] = 8'b00000000; +memory_array[5] = 8'b00000000; +memory_array[6] = 8'b00100000; +memory_array[7] = 8'b10101000; +memory_array[8] = 8'b00000000; +memory_array[9] = 8'b10110000; +memory_array[10] = 8'b10000000; +memory_array[11] = 8'b00011000; +memory_array[12] = 8'b00100000; +memory_array[13] = 8'b00000101; +memory_array[14] = 8'b10100000; +memory_array[15] = 8'b10101000; +memory_array[16] = 8'b00000001; +memory_array[17] = 8'b00000000; +memory_array[18] = 8'b01100000; +memory_array[19] = 8'b10101000; +memory_array[20] = 8'b00010100; +memory_array[21] = 8'b00000000; +memory_array[22] = 8'b00000000; +memory_array[23] = 8'b00000100; +memory_array[24] = 8'b00011000; +memory_array[25] = 8'b00011000; +memory_array[26] = 8'b00000100; +memory_array[27] = 8'b11010100; +memory_array[28] = 8'b00010010; +memory_array[29] = 8'b00000000; +memory_array[30] = 8'b00000000; +memory_array[31] = 8'b00000100; +memory_array[32] = 8'b00000000; +memory_array[33] = 8'b00000000; +memory_array[34] = 8'b00000100; +memory_array[35] = 8'b11010100; +memory_array[36] = 8'b00000100; +memory_array[37] = 8'b00011000; +memory_array[38] = 8'b01000011; +memory_array[39] = 8'b11100000; +memory_array[40] = 8'b00001111; +memory_array[41] = 8'b00000000; +memory_array[42] = 8'b00000000; +memory_array[43] = 8'b00000100; +memory_array[44] = 8'b00001000; +memory_array[45] = 8'b00000000; +memory_array[46] = 8'b00100001; +memory_array[47] = 8'b10011100; +memory_array[48] = 8'b00001101; +memory_array[49] = 8'b00000000; +memory_array[50] = 8'b00000000; +memory_array[51] = 8'b00000100; +memory_array[52] = 8'b00000100; +memory_array[53] = 8'b00011000; +memory_array[54] = 8'b00000011; +memory_array[55] = 8'b11100001; +memory_array[56] = 8'b00000000; +memory_array[57] = 8'b00000000; +memory_array[58] = 8'b00001000; +memory_array[59] = 8'b11100100; +memory_array[60] = 8'b11111011; +memory_array[61] = 8'b11111111; +memory_array[62] = 8'b11111111; +memory_array[63] = 8'b00001111; +memory_array[64] = 8'b00000000; +memory_array[65] = 8'b00011000; +memory_array[66] = 8'b00001000; +memory_array[67] = 8'b11010100; +memory_array[68] = 8'b00001000; +memory_array[69] = 8'b00000000; +memory_array[70] = 8'b00000000; +memory_array[71] = 8'b00000100; +memory_array[72] = 8'b00000100; +memory_array[73] = 8'b00000000; +memory_array[74] = 8'b00100001; +memory_array[75] = 8'b10011100; +memory_array[76] = 8'b00000000; +memory_array[77] = 8'b00011000; +memory_array[78] = 8'b00000001; +memory_array[79] = 8'b11010100; +memory_array[80] = 8'b00000000; +memory_array[81] = 8'b00010000; +memory_array[82] = 8'b00000001; +memory_array[83] = 8'b11100100; +memory_array[84] = 8'b11111100; +memory_array[85] = 8'b11111111; +memory_array[86] = 8'b11111111; +memory_array[87] = 8'b00001111; +memory_array[88] = 8'b00000000; +memory_array[89] = 8'b00000001; +memory_array[90] = 8'b11000000; +memory_array[91] = 8'b10101000; +memory_array[92] = 8'b00000000; +memory_array[93] = 8'b00110000; +memory_array[94] = 8'b00000000; +memory_array[95] = 8'b01000100; +memory_array[96] = 8'b00011000; +memory_array[97] = 8'b00000000; +memory_array[98] = 8'b00000100; +memory_array[99] = 8'b11010100; +memory_array[100] = 8'b00010000; +memory_array[101] = 8'b00101000; +memory_array[102] = 8'b00000100; +memory_array[103] = 8'b11010100; +memory_array[104] = 8'b00010000; +memory_array[105] = 8'b00000000; +memory_array[106] = 8'b01100100; +memory_array[107] = 8'b10000100; +memory_array[108] = 8'b00100000; +memory_array[109] = 8'b00000101; +memory_array[110] = 8'b00000011; +memory_array[111] = 8'b10111100; +memory_array[112] = 8'b11111110; +memory_array[113] = 8'b11111111; +memory_array[114] = 8'b11111111; +memory_array[115] = 8'b00010011; +memory_array[116] = 8'b00000000; +memory_array[117] = 8'b00000000; +memory_array[118] = 8'b00000000; +memory_array[119] = 8'b00010101; +memory_array[120] = 8'b00000000; +memory_array[121] = 8'b01001000; +memory_array[122] = 8'b00000000; +memory_array[123] = 8'b01000100; +memory_array[124] = 8'b00000000; +memory_array[125] = 8'b00000000; +memory_array[126] = 8'b01100100; +memory_array[127] = 8'b10000100; Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/flash.mem =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/flash.mem (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/flash.mem (revision 11) @@ -0,0 +1,128 @@ +00000000 +00000000 +00000000 +00011000 +00000000 +00000000 +00100000 +10101000 +00000000 +10110000 +10000000 +00011000 +00100000 +00000101 +10100000 +10101000 +00000001 +00000000 +01100000 +10101000 +00010100 +00000000 +00000000 +00000100 +00011000 +00011000 +00000100 +11010100 +00010010 +00000000 +00000000 +00000100 +00000000 +00000000 +00000100 +11010100 +00000100 +00011000 +01000011 +11100000 +00001111 +00000000 +00000000 +00000100 +00001000 +00000000 +00100001 +10011100 +00001101 +00000000 +00000000 +00000100 +00000100 +00011000 +00000011 +11100001 +00000000 +00000000 +00001000 +11100100 +11111011 +11111111 +11111111 +00001111 +00000000 +00011000 +00001000 +11010100 +00001000 +00000000 +00000000 +00000100 +00000100 +00000000 +00100001 +10011100 +00000000 +00011000 +00000001 +11010100 +00000000 +00010000 +00000001 +11100100 +11111100 +11111111 +11111111 +00001111 +00000000 +00000001 +11000000 +10101000 +00000000 +00110000 +00000000 +01000100 +00011000 +00000000 +00000100 +11010100 +00010000 +00101000 +00000100 +11010100 +00010000 +00000000 +01100100 +10000100 +00100000 +00000101 +00000011 +10111100 +11111110 +11111111 +11111111 +00010011 +00000000 +00000000 +00000000 +00010101 +00000000 +01001000 +00000000 +01000100 +00000000 +00000000 +01100100 +10000100 Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/wavedump.lxt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/wavedump.lxt =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/wavedump.lxt (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/wavedump.lxt (revision 11)
sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/run/wavedump.lxt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/iver.cmd =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/iver.cmd (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/iver.cmd (revision 11) @@ -0,0 +1,33 @@ +../../../backend/proasic3_redused.v +../../../rtl/verilog/wb_synt.v +../../../rtl/verilog/soc.v +../../../bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/ + +#AT26DFxxx.v +../../../bench/verilog/mt48lc16m16a2.v +../../../bench/verilog/s25fl032a.v +../../../bench/verilog/CPUboard_tb.v + +-y ../../../backend +-y ../../../rtl/verilog +-y ../../../bench/verilog +-y ../../../bench/ATMEL_FLASH/flash_verilog/flash_verilog_w_wo_hold/ + + +../../../rtl/verilog/SD_host_top.v +../../../rtl/verilog/SD_cmd_master.v +../../../rtl/verilog/SD_cmd_serial_host.v +../../../rtl/verilog/SD_crc_n.v +../../../rtl/verilog/SD_clock_divider.v +../../../rtl/verilog/clk_gen.v + + + +-y ../../../rtl/verilog +-y ../../../bench/verilog +-y ../run + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/wave_signals.sav =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/wave_signals.sav (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/wave_signals.sav (revision 11) @@ -0,0 +1,51 @@ +[size] 1280 721 +[pos] 167 52 +*-5.000000 1070 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +command_tb.CLK_t +command_tb.CMD_t +command_tb.OE_t +command_tb.OUT_t +command_tb.RST_t +command_tb.SD_CLK_t +@200 +- +@28 +command_tb.Test_0.Cmd_DE[10:0] +command_tb.Test_0.Cmd_Out[39:0] +command_tb.Test_0.Req_Out_c +command_tb.Test_0.Ack_In_c +command_tb.Test_0.Req_In_c +command_tb.Test_0.Ack_Out_c +@22 +command_tb.Test_0.Cmd_In[127:0] +@28 +command_tb.Test_0.state[20:0] +command_tb.Test_0.next_state[20:0] +@22 +command_tb.Test_0.DELAY_CNT[7:0] +@200 +- +@28 +command_tb.Test_0.Serial_1.REQ_IN +command_tb.Test_0.Serial_1.ACK_OUT +command_tb.Test_0.Serial_1.REQ_OUT +command_tb.Test_0.Serial_1.ACK_IN +@25 +command_tb.Test_0.Serial_1.Sent_Cnt[5:0] +@22 +command_tb.Test_0.Serial_1.Rec_Cnt[7:0] +command_tb.Test_0.Serial_1.state[8:0] +@28 +command_tb.Test_0.Serial_1.next_state[8:0] +command_tb.Test_0.Serial_1.Delay_Cycler[2:0] +command_tb.Test_0.Serial_1.Response_Size[7:0] +@200 +- +- +- +@28 +command_tb.Test_0.Serial_1.CMD +command_tb.Test_0.Serial_1.CRC_7.BITVAL +command_tb.Test_0.Serial_1.CRC_7.CRC[6:0] +command_tb.Test_0.Serial_1.CRC_7.Enable Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/Makefile =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/Makefile (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sim/rtl_sim/bin/Makefile (revision 11) @@ -0,0 +1,17 @@ +# Icarus Verilog simulation defaults to LXT - but cannot be watched +# live in GTK wave though - thus VCD option included +sim: + iverilog -D LXT -osim.out -s CPUboard_tb -c ../bin/iver.cmd + ./sim.out -lxt + gtkwave ./wavedump.lxt ../bin/wave_signals.sav & + +sim_vcd: + iverilog -D VCD -osim.out -s CPUboard_tb -c ../bin/iver.cmd + ./sim.out + gtkwave ./wavedump.vcd ../bin/wave_signals.sav & + +clean: + rm -rf *.key *.log *.shm INCA* .simvision *.out *.vcd *.lxt *~ + +all: clean sim + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller_regs.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller_regs.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller_regs.h (revision 11) @@ -0,0 +1,29 @@ +#ifndef __sd_controleer_regs_h__ +#define __sd_controleer_regs_h__ + +#define SD_CONTROLLER_BASE +#define SD_CONTROLLER_ARG_REG 0x0000 +#define SD_CONTROLLER_COMMAND_REG 0x0004 +#define SD_CONTROLLER_STATUS_REG 0x0006 +#define SD_CONTROLLER_RESP_1_REG 0x000a +#define SD_CONTROLLER_RESP_2_REG 0x000e +#define SD_CONTROLLER_RESP_3_REG 0x0012 +#define SD_CONTROLLER_RESP_4_REG 0x0016 +#define SD_CONTROLLER_CONTROLL_SET_REG 0x001a +#define SD_CONTROLLER_BLOCK_SIZE_REG 0x001c +#define SD_CONTROLLER_POWER_SET_REG 0x001e +#define SD_CONTROLLER_SOFTWARE_RST_REG 0x001f +#define SD_CONTROLLER_TIMEOUT_REG 0x0020 +#define SD_CONTROLLER_NORMAL_INS_REG 0x0021 +#define SD_CONTROLLER_ERROR_INTS_REG 0x0023 +#define SD_CONTROLLER_NORMAL_INTS_EN_REG 0x0025 +#define SD_CONTROLLER_ERROR_INTS_EN_REG 0x0027 +#define SD_CONTROLLER_NORMAL_ISIGER_EN_REG 0x0029 +#define SD_CONTROLLER_ERROR_ISIGER_EN_REG 0x002b +#define SD_CONTROLLER_CAPABILITI_REG 0x002d +#define SD_CONTROLLER_CLOCK_DIV_REG 0x002f + + + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil (revision 11) @@ -0,0 +1,327 @@ +******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : main.c +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Perform some simple functions, used as an example when first using the +// debug cable and proxy with GDB. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#define INCLUDED_FROM_C_FILE + +#include "orsocdef.h" +#include "board.h" +#include "uart.h" +#include "sd_controller.h" +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +/*$$GLOBAL VARIABLES*/ +/******************************************************************************/ +/* */ +/* G L O B A L V A R I A B L E S */ +/* */ +/******************************************************************************/ + +/*$$PRIVATE VARIABLES*/ +/******************************************************************************/ +/* */ +/* P R I V A T E V A R I A B L E S */ +/* */ +/******************************************************************************/ + + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + uint32 i; + uint32 read; + uint32 range; + uint32 adr_offset; + + range = 0x7ff; // Max range: 0x7fffff + adr_offset = 0x00000000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + if (read != (adr_offset + i)) { + while(TRUE){ //ERROR=HALT PROCESSOR + } + } + } +} + + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + + +void external_exeption() +{ + REG uint8 i; + REG uint32 PicSr,sr; + +} + +/*$$MAIN*/ +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ +typdef struct { +unsigned int RCA; +unsigned long Voltage_window; +bool HCS; +bool Active; +bool phys_spec_2_0; +sd_card_cid * cid_reg; +sd_card_csd * csd_reg; + +} sd_card; + + +typdef struct { +unsigned short int MID; +unsigned char OID[2]; +unsigned char PNM[5]; +unsigned short int BCD; +unsigned short int MDT; +unsigned long PSN; +} sd_card_cid; + +typdef struct { + + +} sd_card_csd; + + +typdef struct { +unsigned int CMDI:6; +unsigned int CMDT:2; +unsigned int DPS:1; +unsigned int CICE:1; +unsigned int CRCE:1; +unsigned int RSVD:1; +unsigned int RTS:2; +} sd_controller_csr; + + +sd_card* sd_controller_init () +{ +sd_card dev; + +return dev; + +} + + +send_cmd (unsigned long *arg, sd_controller_csr *set) +{ + + +} + +void Start() +{ + sd_card *sd_card_0; + *sd_card_0 = sd_controller_init(); + + + volatile unsigned long rtn_reg=0; + volatile unsigned long rtn_reg1=0; + + unsigned long a=0x80000000; + unsigned long b=0x0001; + + unsigned long test=0x0000F0FF; + // Send out something over UART + uart_init(); + if ( (a & b) == 0x80000000) + uart_print_str("Hello mask\n"); + + + uart_print_str("Hello World5!\n"); + uart_print_str("Echoing received chars...\n\r"); + uart_print_str("Print long \n"); + + uart_print_str("Status Reg \n"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_STATUS) ; + uart_print_long(rtn_reg); + uart_print_str("\n"); + + uart_print_str("Normal status Reg \n"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS ); + uart_print_long(rtn_reg); + uart_print_str("\n"); + + REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x0000007F; + + /* CMD08 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000081A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x000001AA; + + + + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + + + uart_print_str("1Response inc"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + uart_print_long(rtn_reg); + uart_print_str("\n"); + + */ + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x000; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + + + rtn_reg=0; + while ((rtn_reg & 0x80000000) != 0x80000000) + { + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000371A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000FFFF; + REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS) =0; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + //Put some CRC, timeout and indexcheck here + + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000291A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x00000000; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + + } + + + rtn_reg=0; + + REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS)=0; + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x00000209; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x00000000; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + uart_print_str("cid crc"); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r1 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r2 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP2) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r3 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP3) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r4 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP4) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + + + + while(1){ + + } + + +} + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/boot.or32 =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/boot.or32 =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/boot.or32 (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/boot.or32 (revision 11)
sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/boot.or32 Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.c (revision 11) @@ -0,0 +1,181 @@ + +#include "orsocdef.h" +#include "board.h" +#include "sd_controller.h" + +#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG) + + +/* +int sd_get_cid(sd_card *d) //ADD CRC check + { + uint32 rtn_reg=0; + SD_REG(SD_COMMAND) =CMD2|RSP_146; + SD_REG(SD_ARG) =0; + if (sd_wait_rsp() == 0) { + + return 0; } + else{ + + uart_print_str("cidreg rec"); + rtn_reg = SD_REG(SD_RESP4); + + + d->cid_reg->mid = rtn_reg & CID_MID_MASK; + d->cid_reg->oid= (rtn_reg & CID_OID_MASK)<<1; + + rtn_reg = SD_REG(SD_RESP3); + d->cid_reg->pnm[0] = rtn_reg & CID_B1; + d->cid_reg->pnm[1] = rtn_reg & CID_B2; + d->cid_reg->pnm[2] = rtn_reg & CID_B3; + d->cid_reg->pnm[3] = rtn_reg & CID_B4; + } + return 1; + } +*/ +int sd_get_rca(sd_card *d) +{ + uint32 rtn_reg=0; + SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=0; + + if (sd_wait_rsp() == 0) + return 0; + else{ + rtn_reg = SD_REG(SD_NORMAL_INT_STATUS); + if ( (rtn_reg & EI) == EI) //Error in response, init failed return. + return 0; + rtn_reg = SD_REG(SD_RESP1); + d->rca=((rtn_reg&RCA_RCA_MASK)>>16); + uart_print_str("rca fine"); + + } + return 1; + +} + + +//return 0 if no response else return 1. +uint8 sd_wait_rsp() +{ + volatile unsigned long r1, r2; + + //Polling for timeout and command complete + while (1 ) + { + r1= SD_REG(SD_ERROR_INT_STATUS); + r2= SD_REG(SD_NORMAL_INT_STATUS) ; + + if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT) + return 0; + else if ((r2 & CMD_COMPLETE ) == CMD_COMPLETE) + return 1; + + } + //Later Exception restart module + return 0; + +} + +unsigned long sd_ocr_set (unsigned long cmd1, unsigned long arg1, unsigned long cmd2, unsigned long arg2) +{ + static unsigned long rtn_r =0; + + while ((rtn_r & BUSY) != BUSY) + { + SD_REG(SD_NORMAL_INT_STATUS)=0; + SD_REG(SD_ERROR_INT_STATUS)=0; + + SD_REG(SD_COMMAND) = cmd1; + SD_REG(SD_ARG) = arg1; + if (sd_wait_rsp() == 0) + return 0; + else{ + SD_REG (SD_COMMAND) =cmd2; + SD_REG (SD_ARG) =arg2; + } + if (sd_wait_rsp() == 0) + return 0; + else + rtn_r= SD_REG(SD_RESP1); + + + } + + return rtn_r; +} + +//int sd_cmd_free() //Return 1 if CMD is busy +//{ + // unsigned int a= SD_REG(SD_STATUS); + //return (a & 1); +// + + sd_card sd_controller_init () +{ + sd_card dev; + + volatile unsigned long rtn_reg=0; + volatile unsigned long rtn_reg1=0; + + REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x000077F; + + + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + + SD_REG(SD_COMMAND) = ( CMD8 | CICE | CRCE | RSP_48); + SD_REG(SD_ARG) = VHS|CHECK_PATTERN; + + dev.phys_spec_2_0 = sd_wait_rsp(); + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + if (dev.phys_spec_2_0) + { + uart_print_str("2_0 CARD /n"); + + } + else + { + + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {} + + + rtn_reg=0; + while ((rtn_reg & BUSY) != BUSY) + { + REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + if (!sd_wait_rsp()) + return dev; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =ACMD41 | RSP_48; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + if (!sd_wait_rsp()) + return dev; + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + } + dev.Voltage_window=rtn_reg&VOLTAGE_MASK; + dev.HCS_s = 0; + + } + + + //GET CID + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =CMD2 | RSP_146; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + if (!sd_wait_rsp()) + return dev; + //Get RCA + SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=0; + if (!sd_wait_rsp()) + return dev; + rtn_reg = SD_REG(SD_RESP1); + dev.rca = ((rtn_reg&RCA_RCA_MASK)); + + dev.Active=1; + return dev; + +} Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/orsocdef.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/orsocdef.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/orsocdef.h (revision 11) @@ -0,0 +1,136 @@ +#ifndef __orsocdef_h_ +#define __orsocdef_h_ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : orsocdef.h +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Define some types used in our project. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$GENERAL PARTS*/ +/******************************************************************************/ +/* */ +/* G E N E R A L P A R T S */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* T Y P E D E F S */ +/******************************************************************************/ + +typedef unsigned int uint; + +/******************************************************************************/ +/* M A C R O S */ +/******************************************************************************/ + +/* Max and min functions */ + +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) + +/* the nuldelimiter of a string */ + +#define NUL3 '\n' + +#define OK 1 +#define NOK 0 + +/* nullpointer is defined if not already done */ + +#ifndef NULL + #define NULL (void *)0 +#endif + +/* define min and max for all types */ + +#define INT8_MAX 0x7F +#define UINT8_MAX 0xFF +#define INT16_MAX 0x7FFF +#define UINT16_MAX 0xFFFF +#define INT32_MAX 0x7FFFFFFF +#define UINT32_MAX 0xFFFFFFFF +#define FALSE 0 +#define TRUE !FALSE + +/******************************************************************************/ +/* R E G I S T E R A C C E S S M A C R O S */ +/******************************************************************************/ + +#define REG8(add) *((volatile unsigned char *) (add)) +#define REG16(add) *((volatile unsigned short *) (add)) +#define REG32(add) *((volatile unsigned long *) (add)) + + +/******************************************************************************/ +/* G C C C O M P I L E R */ +/******************************************************************************/ + +#if defined (__GNUC__) + + typedef unsigned char bool; + + typedef signed char int8; + typedef signed short int16; + typedef signed long int32; + + typedef unsigned char uint8; + typedef unsigned short uint16; + typedef unsigned long uint32; + + typedef unsigned char char8; + typedef unsigned short char16; + + + #else + + #error Undefined compiler used ! + +#endif + +#endif + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/spr_defs.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/spr_defs.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/spr_defs.h (revision 11) @@ -0,0 +1,473 @@ + +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : BootReset.S +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + + + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// spr_defs.h -- Defines OR1K architecture specific special-purpose registers + + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000001 +#define SPR_DCR_CC_LESS 0x00000002 +#define SPR_DCR_CC_LESSE 0x00000003 +#define SPR_DCR_CC_GREAT 0x00000004 +#define SPR_DCR_CC_GREATE 0x00000005 +#define SPR_DCR_CC_NEQUAL 0x00000006 + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit definitions for Tick Timer Control Register + * + */ +#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ +#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD +#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ +#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ +#define SPR_TTMR_RT 0x40000000 /* Restart tick */ +#define SPR_TTMR_SR 0x80000000 /* Single run */ +#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ +#define SPR_TTMR_M 0xc0000000 /* Tick mode */ + +/* + * l.nop constants + * + */ +#define NOP_NOP 0x0000 /* Normal nop instruction */ +#define NOP_EXIT 0x0001 /* End of simulation */ +#define NOP_REPORT 0x0002 /* Simple report */ +#define NOP_PRINTF 0x0003 /* Simprintf instruction */ +#define NOP_REPORT_FIRST 0x0400 /* Report with number */ +#define NOP_REPORT_LAST 0x03ff /* Report with number */ Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.c (revision 11) @@ -0,0 +1,209 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : uart.c +// Prepared By : jb +// Project Start : 2009-01-01 +// Sourced from OpenCores : http://opencores.org/cvsweb.shtml/or1k/orp/orp_soc/sw/uart/uart.c + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version, commented out main() jb + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// UART initialisation and usage functions + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#include "orsocdef.h" +#include "board.h" +#include "uart.h" + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) + +#define WAIT_FOR_XMITR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY) + +#define WAIT_FOR_THRE \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE) + +#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR) + +#define WAIT_FOR_CHAR \ + do { \ + lsr = REG8(UART_BASE + UART_LSR); \ + } while ((lsr & UART_LSR_DR) != UART_LSR_DR) + +#define UART_TX_BUFF_LEN 32 +#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1) + +/*$$GLOBAL VARIABLES*/ +/******************************************************************************/ +/* */ +/* G L O B A L V A R I A B L E S */ +/* */ +/******************************************************************************/ + +char tx_buff[UART_TX_BUFF_LEN]; +volatile int tx_level, rx_level; + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ +/* */ +/******************************************************************************/ + +void uart_init(void) +{ + int devisor; + + /* Reset receiver and transmiter */ + REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14; + + /* Disable all interrupts */ + REG8(UART_BASE + UART_IER) = 0x00; + + /* Set 8 bit char, 1 stop bit, no parity */ + REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY); + + /* Set baud rate */ + devisor = IN_CLK/(16 * UART_BAUD_RATE); + REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB; + REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff; + REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff; + REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB); + + return; +} + +void uart_putc(char c) +{ + unsigned char lsr; + + WAIT_FOR_THRE; + REG8(UART_BASE + UART_TX) = c; + if(c == '\n') { + WAIT_FOR_THRE; + REG8(UART_BASE + UART_TX) = '\r'; + } + WAIT_FOR_XMITR; +} + +void uart_print_str(char *p) +{ + while(*p != 0) { + uart_putc(*p); + p++; + } +} + + +void uart_print_long(unsigned long ul) +{ + int i; + char c; + + uart_print_str(""); + + for(i=0; i<8; i++) { + c = (char) (ul>>((7-i)*4)) & 0xf; + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + uart_putc(c); + } +} + + +void uart_print_short(unsigned long ul) +{ + int i; + char c; + char flag=0; + + uart_print_str(""); + + for(i=0; i<8; i++) { + c = (char) (ul>>((7-i)*4)) & 0xf; + + if(c >= 0x0 && c<=0x9) + c += '0'; + else + c += 'a' - 10; + + if ((c != '0') || (i==7)) + flag=1; + + if(flag) + uart_putc(c); + } +} + + + +char uart_getc() +{ + unsigned char lsr; + char c; + + WAIT_FOR_CHAR; + + c = REG8(UART_BASE + UART_RX); + + return c; +} + +/******************************************************************************/ +/* */ +/* E X A M P L E U S A G E */ +/* */ +/******************************************************************************/ +/* +int main() +{ + uart_init(); + + // We can't use printf because in this simple example + // we don't link C library. + uart_print_str("Hello World.\n\r"); + + report(0xdeaddead); + exit(0); +} +*/ Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/sd_controller.h (revision 11) @@ -0,0 +1,153 @@ +#ifndef __sd_controller_h_ +#define __sd_controller_h_ + + +//SD_CONTROLLER Register +uint32 test_readwrite(unsigned long arg, unsigned short reg); + +#define WORD_0 0x00 +#define WORD_1 0x40 +#define WORD_2 0x80 +#define WORD_3 0xC0 + + +#define SD_ARG 0x00 +#define SD_COMMAND 0x04 +#define SD_STATUS 0x08 +#define SD_RESP1 0x0c + +#define SD_CTRL 0x1c +#define SD_BLOCK 0x20 +#define SD_POWER 0x24 +#define SD_SOFTWARE_RST 0x28 +#define SD_TIMEOUT 0x2c +#define SD_NORMAL_INT_STATUS 0x30 +#define SD_ERROR_INT_STATUS 0x34 +#define SD_NORMAL_INT_STATUS_ENABLE 0x38 +#define SD_ERROR_INT_STATUS_ENABLE 0x3c +#define SD_NOMAL_INT_SIGNAL_ENABLE 0x40 +#define SD_ERROR_INT_SIGNAL_ENABLE 0x44 +#define SD_CAPABILITY 0x48 +#define SD_CLOCK_D 0x4c +#define BD_STATUS 0x50 +#define BD_ISR 0x54 +#define BD_RX 0x60 +#define BD_TX 0x80 + + +#define CLK_CARD 25000000 +#define CLK_CPU 50000000 +#define CMD_TIMEOUT_MS ((CLK_CPU/CLK_CARD) * 512) +#define MAX_POL 1000 +#define SD_REG(REG) REG32(SD_CONTROLLER_BASE+REG) + + + +//Commands +#define CMD2 0x200 +#define CMD3 0x300 +#define CMD7 0x700 +#define CMD8 0x800 +#define CMD9 0x900 +#define CMD16 0x1000 +#define CMD17 0x1100 + +#define ACMD41 0x2900 +#define ACMD6 0x600 +#define CMD55 0x3700 + +//CMD ARG +//CMD8 +#define VHS 0x100 //2.7-3.6V +#define CHECK_PATTERN 0xAA +//ACMD41 +#define BUSY 0x80000000 +#define HCS 0x40000000 +#define VOLTAGE_MASK 0xFFFFFF + +//CMD7 +#define READY_FOR_DATA 0x100 +#define CARD_STATUS_STB 0x600 + +//Command setting +#define CICE 0x10 +#define CRCE 0x08 +#define RSP_48 0x2 +#define RSP_146 0x1 + +//Status Mask +//Normal interupt status +#define CMD_COMPLETE 0x1 +#define EI 0x8000 + +//Error interupt status +#define CMD_TIMEOUT 0x1 +#define CCRC 0x1 +#define CIE 0x8 + +#define CID_MID_MASK 0x7F8000 +#define CID_OID_MASK 0x7FFF +#define CID_B1 0x7F800000 +#define CID_B2 0x7F8000 +#define CID_B3 0x7F80 +#define CID_B4 0x7F + +#define RCA_RCA_MASK 0xFFFF0000 + + +typedef struct { + unsigned int pad:18; + unsigned int cmdi:6; + unsigned int cmdt:2; + unsigned int dps:1; + unsigned int cice:1; + unsigned int crce:1; + unsigned int rsvd:1; + unsigned int rts:2; +}sd_controller_csr ; + + +typedef struct { + uint8 mid:8; + uint16 oid:16; + unsigned char pnm[5]; + uint8 prv:8; + uint32 psn:32; + uint8 rsv:4; + uint16 mdt:12; +}sd_card_cid; + +typedef struct { +}sd_card_csd; + +typedef struct { + uint32 rca; + uint32 Voltage_window; + uint8 HCS_s; + uint8 Active; + uint8 phys_spec_2_0; + sd_card_cid * cid_reg; + sd_card_csd * csd_reg; + +}sd_card ; + + + + + + + + + +int sd_cmd_free(); +int sd_get_cid(sd_card *d); +int sd_get_rca(sd_card *d); +uint8 sd_wait_rsp(); +unsigned long sd_ocr_set (unsigned long cmd1, unsigned long arg1, unsigned long cmd2, unsigned long arg2); +sd_card sd_controller_init (); + + + + +#endif + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/revision.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/revision.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/revision.c (revision 11) @@ -0,0 +1,126 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : revision.c +// Prepared By : +// Project Start : 2008-07-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + + +/*$$TYPEDEFS*/ +/******************************************************************************/ +/* */ +/* T Y P E D E F S */ +/* */ +/******************************************************************************/ + + +typedef struct load_info +{ + unsigned long boardtype; // BOOT_ID + unsigned long decompressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long compressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long decompressed_size; // Filled in by ext. program for generating SRecord file + unsigned long compressed_size; // Filled in by ext. program for generating SRecord file + unsigned long extra_pad[23]; // Extra padding + unsigned char boardName[12]; // + unsigned char caaName[20]; // + unsigned char caaRev[8]; // + unsigned char addInfo[16]; // + +} LOAD_INFO; + + +/*$$PUBLIC VARIABLES*/ +/******************************************************************************/ +/* */ +/* P U B L I C V A R I A B L E S */ +/* */ +/******************************************************************************/ + + +LOAD_INFO load_info_values = { + + 0x00000D90, + 0x930000E8, + 0x40000000, + 0x930000E4, + 0x00000001, + 0x930000E8, + 0x50000000, + 0x930000E4, + 0x00000001, + 0x930000E8, + 0x60000000, + 0x930000E4, + 0x00000001, + 0x930000E4, + 0x00000001, + 0x930000E8, + 0x7E000023, + 0x930000E4, + 0x00000001, + 0x930000A0, + 0xC03E0310, + 0x00000000, + 0xDEADBEEF, + 0xDEADBEEF, + 0xDEADBEEF, + 0xDEADBEEF, + 0xDEADBEEF, + 0xDEADBEEF, + + "BOOT ", // Boardname, must be fixed 12 bytes + " ", // Add. info, must be fixed 20 bytes + "R1A ", // Revision , must be fixed 8 bytes + " " // Add. info, must be fixed 16 bytes + +}; + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/gen_memory_text.pl =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/gen_memory_text.pl (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/gen_memory_text.pl (revision 11) @@ -0,0 +1,44 @@ +#!/usr/bin/perl + +@data = (); + +# Intel HEX format interpreter +while(<>) { + if (m/\:([A-F0-9]{2})([A-F0-9]{4})([A-F0-9]{2})([A-F0-9]+)([A-F0-9]{2})/) { + $vec = $4; + $len = hex $1; + $rec_type = $3; + $byte_addr = (hex $2); + if ($len > 0) { + for (my($i)=0; $i < $len*2; $i+=2) { + $data[$byte_addr++] = hex substr($vec, $i, 2); + } + } + } +} + +use Shell; +#Execute a command which parses the System.map file and determines the address +#of the boot code, and thus the total size of it that will be loaded from the +#SPI flash. +$code_size_cmd = "tail -n 1 System.map | sed 's/:.*//g' | sed 's/^[ ]*//'"; +$code_size = hex(qx{ $code_size_cmd }); + +#The following doesn't want to play for some reason; unrolling... +#for(my($j)=0; $j < 4; $j++){ +# $size_bytes[$j] = $code_size & (hex(ff)<<($j*2)) / (hex(1)<<($j*2)); +#} + +$size_bytes[0] = $code_size & hex(ff) / hex(1); +$size_bytes[1] = ($code_size & hex(ff00)) / hex(100); +$size_bytes[2] = ($code_size & hex(ff0000)) / hex(10000); +$size_bytes[3] = ($code_size & hex(ff000000)) / hex(1000000); +printf("//SPI Flash ROM data, byte per line. First word is length of ROM\n"); +for(my($j)=0; $j < 4; $j++){ + printf("%2.2x\n",$size_bytes[3-$j]); +} +$i =4; +while($i <= $#data) { + printf ("%2.2x\n", $data[$i]); + $i+=1; +} Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spi.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spi.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spi.h (revision 11) @@ -0,0 +1,121 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : spi.h +// Prepared By : +// Project Start : 2008-07-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + + + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* S P I D E F I N E S */ +/* */ +/******************************************************************************/ + + +#define SPI2_BASE 0xb1000000 +#define SPI2_DR0 SPI2_BASE // Data Receive bit 0 - 31 +#define SPI2_DR1 SPI2_BASE + 0x00000004 // Data Receive bit 32 - 63 +#define SPI2_DR2 SPI2_BASE + 0x00000008 // Data Receive bit 64 - 95 +#define SPI2_DR3 SPI2_BASE + 0x0000000C // Data Receive bit 96 - 127 +#define SPI2_TX0 SPI2_BASE // Data Transmit bit 0 - 31 +#define SPI2_TX1 SPI2_BASE + 0x00000004 // Data Transmit bit 32 - 63 +#define SPI2_TX2 SPI2_BASE + 0x00000008 // Data Transmit bit 64 - 95 +#define SPI2_TX3 SPI2_BASE + 0x0000000C // Data Transmit bit 96 - 127 + +#define SPI2_CTRL SPI2_BASE + 0x00000010 // Control and Status Reg +#define SPI2_DIVIDER SPI2_BASE + 0x00000014 // Clock Divider Register +#define SPI2_SS SPI2_BASE + 0x00000018 // Slave Select Register + + + +#define SPI3_BASE 0xb2000000 +#define SPI3_DR0 SPI3_BASE // Data Receive bit 0 - 31 +#define SPI3_DR1 SPI3_BASE + 0x00000004 // Data Receive bit 32 - 63 +#define SPI3_DR2 SPI3_BASE + 0x00000008 // Data Receive bit 64 - 95 +#define SPI3_DR3 SPI3_BASE + 0x0000000C // Data Receive bit 96 - 127 +#define SPI3_TX0 SPI3_BASE // Data Transmit bit 0 - 31 +#define SPI3_TX1 SPI3_BASE + 0x00000004 // Data Transmit bit 32 - 63 +#define SPI3_TX2 SPI3_BASE + 0x00000008 // Data Transmit bit 64 - 95 +#define SPI3_TX3 SPI3_BASE + 0x0000000C // Data Transmit bit 96 - 127 + +#define SPI3_CTRL SPI3_BASE + 0x00000010 // Control and Status Reg +#define SPI3_DIVIDER SPI3_BASE + 0x00000014 // Clock Divider Register +#define SPI3_SS SPI3_BASE + 0x00000018 // Slave Select Register + + + +/******************************************************************************/ +/* C O N T R O L A N D S T A T U S R E G I S T E R S */ +/******************************************************************************/ + +#define SPI_CTRL_GO 1 << 8 +#define SPI_CTRL_BSY 1 << 8 +#define CTRL_Rx_NEG 1 << 9 +#define CTRL_Tx_NEG 1 << 10 +#define CTRL_CHAR_LEN(a) (a & 0x0000007f) +#define CTRL_LSB 1 << 11 +#define CTRL_IE 1 << 12 +#define CTRL_ASS 1 << 13 + +#define SPI2_DIV_BIT 3 // +#define SPI3_DIV_BIT 4 // +#define MAX_SPI_WAIT 10000 // +#define SPI2_REG_LEN 16 // 16 bits +#define SPI3_REG_LEN 16 // 16 bits + +/*$$PUBLIC FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* P U B L I C F U N C T I O N S */ +/* */ +/******************************************************************************/ + +void vSPI_Config (unsigned char); +unsigned char uwire_access (unsigned char, unsigned char); + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/flash.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/flash.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/flash.h (revision 11) @@ -0,0 +1,101 @@ +/***************************************************************************** +* COPYRIGHT(C) FLEXTRONICS INTERNATIONAL +****************************************************************************** +* +* PROJECT: Arnold +* +* FILENAME: flash.h +* +* $Revision:: 1 $ +* +* DESCRIPTION: +* +* PREPARED BY: Jonas Rosén +* +* DATE: 2004-04-23 +* +****************************************************************************** +* +* The flash memory map looks like following: +* = SECTOR = ======= RANGE ========= === SIZE === === COMMENT === +* SECTOR_SA0 0xF0000000 - 0xF0003FFF 16 384 bytes Boot code +* SECTOR_SA1 0xF0004000 - 0xF0007FFF 16 384 bytes Strings, parameters etc. +* SECTOR_SA3 0xF0008000 - 0xF007FFFF 425 984 bytes Application code +* +****************************************************************************** +* REVISION HISTORY: +*****************************************************************************/ +/* $Log:: /ELUD_ELUA/FPGA2/flash.h $ + * + * 1 06-11-27 14:02 Knansand + * LCA test ver 10 + * + * 7 04-06-08 12:32 Knajrose + * Info added. + * + * 6 04-05-17 13:41 Knajrose + * Sectors updated! + * + * 5 04-05-17 10:20 Knajrose + * Boot and appl. sectors changed. + * + * 4 04-04-27 10:50 Jolsson + * struct changed. + * + * 3 04-04-26 12:15 Jolsson + * Macro ARNOLD_ID removed. + * + * 2 04-04-23 15:19 Jolsson + * Definitions for flash. +*/ + +#ifndef _FLASH_H +#define _FLASH_H + + +typedef struct FWDL_PROG_STR +{ + unsigned long ID; + unsigned long decompressed_crc; + unsigned long compressed_crc; + unsigned long decompressed_size; + unsigned long compressed_size; + unsigned char str[240]; + void (*prog_start)(); //Shall be at 0x?0000100 ! + +}fwdl_prog_str; + + +#define FLASH_AUTOSELECT 0x90 +#define WRITE 0xA0 +#define ERASE 0x80 +#define ERASE_CHIP 0x10 +#define FMODE_ENABLE 0x20 +#define ERASE_SECTOR 0x30 +#define AUTO_SELECT 0x90 +#define READ_RESET 0xF0 + +#define VERIFY_OFF 0x00 +#define VERIFY_ON 0x01 + +#define BOOT_START SECTOR_SA0 +#define BOOT_END SECTOR_SA1 +#define APPL_START SECTOR_SA3 +#define APPL_END SECTOR_SA10 + +/* The flash AM29LV400B is bottom boot */ +/* Sector base Sector range Size kB */ +/* ---------- ------------ ----- */ +#define SECTOR_SA0 0x00000000 /* 00000h-03FFFh 16/8 */ +#define SECTOR_SA1 0x00004000 /* 04000h-05FFFh 8/4 */ +#define SECTOR_SA2 0x00006000 /* 06000h-07FFFh 8/4 */ +#define SECTOR_SA3 0x00008000 /* 08000h-0FFFFh 32/16 */ +#define SECTOR_SA4 0x00010000 /* 10000h-1FFFFh 64/32 */ +#define SECTOR_SA5 0x00020000 /* 20000h-2FFFFh 64/32 */ +#define SECTOR_SA6 0x00030000 /* 30000h-3FFFFh 64/32 */ +#define SECTOR_SA7 0x00040000 /* 40000h-4FFFFh 64/32 */ +#define SECTOR_SA8 0x00050000 /* 50000h-5FFFFh 64/32 */ +#define SECTOR_SA9 0x00060000 /* 60000h-6FFFFh 64/32 */ +#define SECTOR_SA10 0x00070000 /* 70000h-7FFFFh 64/32 */ + +#endif /* _FLASH_H */ Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.or32 =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.or32 =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.or32 (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.or32 (revision 11)
sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.or32 Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/orsocdef.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/orsocdef.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/orsocdef.h (revision 11) @@ -0,0 +1,134 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : orsocdef.h +// Prepared By : +// Project Start : 2008-07-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + + + +/*$$GENERAL PARTS*/ +/******************************************************************************/ +/* */ +/* G E N E R A L P A R T S */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* T Y P E D E F S */ +/******************************************************************************/ + +typedef unsigned int uint; + +/******************************************************************************/ +/* M A C R O S */ +/******************************************************************************/ + +/* Max and min functions */ + +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) + +/* the nuldelimiter of a string */ + +#define NUL3 '\n' + +#define OK 1 +#define NOK 0 + +/* nullpointer is defined if not already done */ + +#ifndef NULL + #define NULL (void *)0 +#endif + +/* define min and max for all types */ + +#define INT8_MAX 0x7F +#define UINT8_MAX 0xFF +#define INT16_MAX 0x7FFF +#define UINT16_MAX 0xFFFF +#define INT32_MAX 0x7FFFFFFF +#define UINT32_MAX 0xFFFFFFFF + +#define FALSE 0 +#define TRUE !FALSE + +/******************************************************************************/ +/* R E G I S T E R A C C E S S M A C R O S */ +/******************************************************************************/ + +#define REG8(add) *((volatile unsigned char *) (add)) +#define REG16(add) *((volatile unsigned short *) (add)) +#define REG32(add) *((volatile unsigned long *) (add)) + + +/******************************************************************************/ +/* G C C C O M P I L E R */ +/******************************************************************************/ + +#if defined (__GNUC__) + + typedef unsigned char bool; + + typedef signed char int8; + typedef signed short int16; + typedef signed long int32; + + typedef unsigned char uint8; + typedef unsigned short uint16; + typedef unsigned long uint32; + + typedef unsigned char char8; + typedef unsigned short char16; + + + #else + + #error Undefined compiler used ! + +#endif + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spr_defs.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spr_defs.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/spr_defs.h (revision 11) @@ -0,0 +1,478 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : spr_defs.h +// Prepared By : +// Project Start : 2008-07-01 + + + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + + + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + + +// spr_defs.h -- Defines OR1K architecture specific special-purpose registers +// Copyright (C) 1999 Damjan Lampret, lampret@opencores.org + +// This file is part of OpenRISC 1000 Architectural Simulator. + +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. + +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. + +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ + +// This file is also used by microkernel test bench. Among +// others it is also used in assembly file(s). + + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +#define MAX_GRPS (32) +#define MAX_SPRS_PER_GRP_BITS (11) +#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) +#define MAX_SPRS (0x10000) + +/* Base addresses for the groups */ +#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) +#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) + +/* System control and status group */ +#define SPR_VR (SPRGROUP_SYS + 0) +#define SPR_UPR (SPRGROUP_SYS + 1) +#define SPR_CPUCFGR (SPRGROUP_SYS + 2) +#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) +#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) +#define SPR_DCCFGR (SPRGROUP_SYS + 5) +#define SPR_ICCFGR (SPRGROUP_SYS + 6) +#define SPR_DCFGR (SPRGROUP_SYS + 7) +#define SPR_PCCFGR (SPRGROUP_SYS + 8) +#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ +#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ +#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ +#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ +#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ +#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) +#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) +#define SPR_ESR_BASE (SPRGROUP_SYS + 64) +#define SPR_ESR_LAST (SPRGROUP_SYS + 79) + +/* Data MMU group */ +#define SPR_DMMUCR (SPRGROUP_DMMU + 0) +#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x200) +#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x200) +#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x300 + (WAY) * 0x200) +#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x3ff + (WAY) * 0x200) + +/* Instruction MMU group */ +#define SPR_IMMUCR (SPRGROUP_IMMU + 0) +#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x200) +#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x200) +#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x300 + (WAY) * 0x200) +#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x3ff + (WAY) * 0x200) + +/* Data cache group */ +#define SPR_DCCR (SPRGROUP_DC + 0) +#define SPR_DCBPR (SPRGROUP_DC + 1) +#define SPR_DCBFR (SPRGROUP_DC + 2) +#define SPR_DCBIR (SPRGROUP_DC + 3) +#define SPR_DCBWR (SPRGROUP_DC + 4) +#define SPR_DCBLR (SPRGROUP_DC + 5) +#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) +#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) + +/* Instruction cache group */ +#define SPR_ICCR (SPRGROUP_IC + 0) +#define SPR_ICBPR (SPRGROUP_IC + 1) +#define SPR_ICBIR (SPRGROUP_IC + 2) +#define SPR_ICBLR (SPRGROUP_IC + 3) +#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) +#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) + +/* MAC group */ +#define SPR_MACLO (SPRGROUP_MAC + 1) +#define SPR_MACHI (SPRGROUP_MAC + 2) + +/* Debug group */ +#define SPR_DVR(N) (SPRGROUP_D + (N)) +#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) +#define SPR_DMR1 (SPRGROUP_D + 16) +#define SPR_DMR2 (SPRGROUP_D + 17) +#define SPR_DWCR0 (SPRGROUP_D + 18) +#define SPR_DWCR1 (SPRGROUP_D + 19) +#define SPR_DSR (SPRGROUP_D + 20) +#define SPR_DRR (SPRGROUP_D + 21) + +/* Performance counters group */ +#define SPR_PCCR(N) (SPRGROUP_PC + (N)) +#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) + +/* Power management group */ +#define SPR_PMR (SPRGROUP_PM + 0) + +/* PIC group */ +#define SPR_PICMR (SPRGROUP_PIC + 0) +#define SPR_PICPR (SPRGROUP_PIC + 1) +#define SPR_PICSR (SPRGROUP_PIC + 2) + +/* Tick Timer group */ +#define SPR_TTMR (SPRGROUP_TT + 0) +#define SPR_TTCR (SPRGROUP_TT + 1) + +/* + * Bit definitions for the Version Register + * + */ +#define SPR_VR_VER 0xffff0000 /* Processor version */ +#define SPR_VR_REV 0x0000003f /* Processor revision */ + +/* + * Bit definitions for the Unit Present Register + * + */ +#define SPR_UPR_UP 0x00000001 /* UPR present */ +#define SPR_UPR_DCP 0x00000002 /* Data cache present */ +#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ +#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ +#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ +#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ +#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ +#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ +#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ +#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ +#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ +#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ +#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ +#define SPR_UPR_PMP 0x00002000 /* Power management present */ +#define SPR_UPR_PICP 0x00004000 /* PIC present */ +#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ +#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ +#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ +#define SPR_UPR_CUST 0xff000000 /* Custom units */ + +/* + * Bit definitions for the Supervision Register + * + */ +#define SPR_SR_CID 0xf0000000 /* Context ID */ +#define SPR_SR_FO 0x00008000 /* Fixed one */ +#define SPR_SR_EPH 0x00004000 /* Exception Prefixi High */ +#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ +#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ +#define SPR_SR_OV 0x00000800 /* Overflow flag */ +#define SPR_SR_CY 0x00000400 /* Carry flag */ +#define SPR_SR_F 0x00000200 /* Condition Flag */ +#define SPR_SR_CE 0x00000100 /* CID Enable */ +#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ +#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ +#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ +#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ +#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ +#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ +#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ +#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ + +/* + * Bit definitions for the Data MMU Control Register + * + */ +#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Instruction MMU Control Register + * + */ +#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ +#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ +#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ +#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ + +/* + * Bit definitions for the Data TLB Match Register + * + */ +#define SPR_DTLBMR_V 0x00000001 /* Valid */ +#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ +#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Data TLB Translate Register + * + */ +#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_DTLBTR_A 0x00000010 /* Accessed */ +#define SPR_DTLBTR_D 0x00000020 /* Dirty */ +#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ +#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ +#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ +#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ +#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for the Instruction TLB Match Register + * + */ +#define SPR_ITLBMR_V 0x00000001 /* Valid */ +#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ +#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ +#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ +#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ + +/* + * Bit definitions for the Instruction TLB Translate Register + * + */ +#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ +#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ +#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ +#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ +#define SPR_ITLBTR_A 0x00000010 /* Accessed */ +#define SPR_ITLBTR_D 0x00000020 /* Dirty */ +#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ +#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ +#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ + +/* + * Bit definitions for Data Cache Control register + * + */ +#define SPR_DCCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Insn Cache Control register + * + */ +#define SPR_ICCR_EW 0x000000ff /* Enable ways */ + +/* + * Bit definitions for Debug Control registers + * + */ +#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ +#define SPR_DCR_CC 0x0000000e /* Compare condition */ +#define SPR_DCR_SC 0x00000010 /* Signed compare */ +#define SPR_DCR_CT 0x000000e0 /* Compare to */ + +/* Bit results with SPR_DCR_CC mask */ +#define SPR_DCR_CC_MASKED 0x00000000 +#define SPR_DCR_CC_EQUAL 0x00000001 +#define SPR_DCR_CC_LESS 0x00000002 +#define SPR_DCR_CC_LESSE 0x00000003 +#define SPR_DCR_CC_GREAT 0x00000004 +#define SPR_DCR_CC_GREATE 0x00000005 +#define SPR_DCR_CC_NEQUAL 0x00000006 + +/* Bit results with SPR_DCR_CT mask */ +#define SPR_DCR_CT_DISABLED 0x00000000 +#define SPR_DCR_CT_IFEA 0x00000020 +#define SPR_DCR_CT_LEA 0x00000040 +#define SPR_DCR_CT_SEA 0x00000060 +#define SPR_DCR_CT_LD 0x00000080 +#define SPR_DCR_CT_SD 0x000000a0 +#define SPR_DCR_CT_LSEA 0x000000c0 + +/* + * Bit definitions for Debug Mode 1 register + * + */ +#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ +#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ +#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ +#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ +#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ +#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ +#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ +#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ +#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ +#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ +#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ +#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ +#define SPR_DMR1_BT 0x00800000 /* Branch trace */ +#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ + +/* + * Bit definitions for Debug Mode 2 register + * + */ +#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ +#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ +#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ + +/* + * Bit definitions for Debug watchpoint counter registers + * + */ +#define SPR_DWCR_COUNT 0x0000ffff /* Count */ +#define SPR_DWCR_MATCH 0xffff0000 /* Match */ + +/* + * Bit definitions for Debug stop register + * + */ +#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ +#define SPR_DSR_AE 0x00000020 /* Alignment exception */ +#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DSR_RE 0x00000400 /* Range exception */ +#define SPR_DSR_SCE 0x00000800 /* System call exception */ +#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ +#define SPR_DSR_TE 0x00002000 /* Trap exception */ + +/* + * Bit definitions for Debug reason register + * + */ +#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ +#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ +#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ +#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ +#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ +#define SPR_DRR_AE 0x00000020 /* Alignment exception */ +#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ +#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ +#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ +#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ +#define SPR_DRR_RE 0x00000400 /* Range exception */ +#define SPR_DRR_SCE 0x00000800 /* System call exception */ +#define SPR_DRR_TE 0x00001000 /* Trap exception */ + +/* + * Bit definitions for Performance counters mode registers + * + */ +#define SPR_PCMR_CP 0x00000001 /* Counter present */ +#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ +#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ +#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ +#define SPR_PCMR_LA 0x00000010 /* Load access event */ +#define SPR_PCMR_SA 0x00000020 /* Store access event */ +#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ +#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ +#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ +#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ +#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ +#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ +#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ +#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ +#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ +#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ + +/* + * Bit definitions for the Power management register + * + */ +#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ +#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ +#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ +#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ +#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ + +/* + * Bit definitions for PICMR + * + */ +#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ + +/* + * Bit definitions for PICPR + * + */ +#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ + +/* + * Bit definitions for PICSR + * + */ +#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ + +/* + * Bit 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+:100F2000D40520009C8000009C600001D4062000B5 +:100F300007FFFFC61500000007FFFF721500000045 +:100F400007FFFFC29C60000207FFFF7E1500000044 +:100F500007FFFFBE9C60000307FFFF8A9C60002222 +:100F600007FFFFBA9C60000407FFFF9F9C600033EF +:100F700007FFFFB69C60000507FFFFBD15000000DE +:100F800007FFFFB29C6000FF03FFFFFE150000009B +:100F90008521000084410004440048009C21000891 +:0400000300000D00EC +:00000001FF Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/System.map =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/System.map (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/System.map (revision 11) @@ -0,0 +1,773 @@ + +Memory Configuration + +Name Origin Length Attributes +ld_info 0x00000000 0x000000f0 +vectors 0x00000100 0x00000c00 +flash 0x00000d00 0x00001600 +ram 0x00003000 0x00001000 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD BootReset.o +LOAD main.o +LOAD revision.o + +.ld_info 0x00000000 0xa8 + revision.o(.data) + .data 0x00000000 0xa8 revision.o + 0x00000000 _load_info_values + +.vectors 0x00000100 0x900 + *(.vectors) + .vectors 0x00000100 0x900 BootReset.o + 0x00000400 __exception_instruction_page_fault + 0x00000800 __external_IRQ + 0x00000200 __exception_bus_error + 0x00000300 __exception_data_page_fault + 0x00000600 __exception_unaligned_access + 0x00000700 __exception_illegal_instruction + 0x00000500 __exception_tick_timer + +.text 0x00000d00 0x2a0 + *(.text) + .text 0x00000d00 0x0 BootReset.o + .text 0x00000d00 0x2a0 main.o + 0x00000ee8 _external_exeption + 0x00000d40 _SPI3_Config + 0x00000d80 _SPI2_Send_Receive_Data + 0x00000f00 _Start + 0x00000e6c _Write_External_SDRAM_1 + 0x00000de4 _SPI3_Send_Receive_Data + 0x00000d00 _SPI2_Config + 0x00000e48 _GPIO_Write + .text 0x00000fa0 0x0 revision.o + +.rodata + *(.rodata) + +.data 0x00003000 0x0 + *(.data) + .data 0x00003000 0x0 BootReset.o + .data 0x00003000 0x0 main.o + +.bss 0x00003000 0x0 + *(.bss) + .bss 0x00003000 0x0 BootReset.o + .bss 0x00003000 0x0 main.o + .bss 0x00003000 0x0 revision.o + +.stack 0x00003000 0x500 + 0x00003000 __STACK_TOP = . + 0x00003500 . = (. + 0x500) + *fill* 0x00003000 0x500 00 + 0x00003500 __STACK_BOTTOM = . + 0x00000d00 __CODE_START = ADDR (.text) + 0x00000fa0 __CODE_END = (ADDR (.text) + SIZEOF (.text)) + 0x00003000 __DATA_START = ADDR (.bss) + 0x00003000 __DATA_END = (ADDR (.bss) + SIZEOF (.bss)) +OUTPUT(boot.or32 elf32-or32) + +.stab 0x00000000 0x870 + .stab 0x00000000 0x75c main.o + .stab 0x0000075c 0x114 revision.o + +.stabstr 0x00000000 0xb4b + .stabstr 0x00000000 0x6ae main.o + .stabstr 0x000006ae 0x49d revision.o + +.comment 0x00000000 0x24 + .comment 0x00000000 0x12 main.o + .comment 0x00000012 0x12 revision.o +00000000 t _reset +00000100 T __exception_bus_error +00000200 T __exception_data_page_fault +00000300 T __exception_instruction_page_fault +00000400 T __exception_tick_timer +00000500 T __exception_unaligned_access +00000600 T __exception_illegal_instruction +00000700 T __external_IRQ +00000724 t JUMP +00000740 t save_state +000007b8 t restore_state + +boot.or32: file format elf32-or32 +boot.or32 +architecture: or32, flags 0x00000113: +HAS_RELOC, EXEC_P, HAS_SYMS, D_PAGED +start address 0x00000d00 + +Program Header: + LOAD off 0x00002000 vaddr 0x00000000 paddr 0x00000000 align 2**13 + filesz 0x000000a8 memsz 0x000000a8 flags rw- + LOAD off 0x00002100 vaddr 0x00000100 paddr 0x00000100 align 2**13 + filesz 0x00000900 memsz 0x00000900 flags r-x + LOAD off 0x00002d00 vaddr 0x00000d00 paddr 0x00000d00 align 2**13 + filesz 0x000002a0 memsz 0x000002a0 flags r-x + LOAD off 0x00003000 vaddr 0x00003000 paddr 0x00003000 align 2**13 + filesz 0x00000000 memsz 0x00000500 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .ld_info 000000a8 00000000 00000000 00002000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 1 .vectors 00000900 00000100 00000100 00002100 2**8 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 2 .text 000002a0 00000d00 00000d00 00002d00 2**2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .stack 00000500 00003000 00003000 00003000 2**0 + ALLOC + 4 .stab 00000870 00000000 00000000 00002fa0 2**2 + CONTENTS, RELOC, READONLY, DEBUGGING + 5 .stabstr 00000b4b 00000000 00000000 00003810 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .comment 00000024 00000000 00000000 0000435b 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +00000d00 l d .text 00000000 .text +00000100 l d .vectors 00000000 .vectors +00000100 l .vectors 00000000 _reset +00003560 l *ABS* 00000000 sp +00000840 l .vectors 00000000 save_state +00000824 l .vectors 00000000 JUMP +000008b8 l .vectors 00000000 restore_state +00000000 l df *ABS* 00000000 main.c +00000d00 l d .text 00000000 .text +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000000 l d .comment 00000000 .comment +00000000 l df *ABS* 00000000 revision.c +00000000 l d .ld_info 00000000 .ld_info +00003000 l d .stack 00000000 .stack +00000fa0 g *ABS* 00000000 __CODE_END +00000400 g .vectors 00000000 __exception_instruction_page_fault +00000800 g .vectors 00000000 __external_IRQ +00000200 g .vectors 00000000 __exception_bus_error +00003000 g .stack 00000000 __DATA_START +00003000 g .stack 00000000 __STACK_TOP +00003500 g .stack 00000000 __STACK_BOTTOM +00000ee8 g F .text 00000018 _external_exeption +00000d40 g F .text 00000040 _SPI3_Config +00000d80 g F .text 00000064 _SPI2_Send_Receive_Data +00000300 g .vectors 00000000 __exception_data_page_fault +00000600 g .vectors 00000000 __exception_unaligned_access +00000000 g O .ld_info 000000a8 _load_info_values +00000700 g .vectors 00000000 __exception_illegal_instruction +00000500 g .vectors 00000000 __exception_tick_timer +00000f00 g F .text 000000a0 _Start +00003000 g *ABS* 00000000 __DATA_END +00000e6c g F .text 0000007c _Write_External_SDRAM_1 +00000de4 g F .text 00000064 _SPI3_Send_Receive_Data +00000d00 g F .text 00000040 _SPI2_Config +00000d00 g .text 00000000 __CODE_START +00000e48 g F .text 00000024 _GPIO_Write + + + +Disassembly of section .vectors: + +00000100 <_reset>: + 100: 18 00 00 00 l.movhi r0,0x0 + 104: a8 00 00 00 l.ori r0,r0,0x0 + 108: 18 20 00 00 l.movhi r1,0x0 + 10c: a8 21 35 60 l.ori r1,r1,0x3560 + 110: e0 40 00 04 l.or r2,r0,r0 + 114: e0 60 00 04 l.or r3,r0,r0 + 118: e0 80 00 04 l.or r4,r0,r0 + 11c: e0 a0 00 04 l.or r5,r0,r0 + 120: e0 c0 00 04 l.or r6,r0,r0 + 124: e0 e0 00 04 l.or r7,r0,r0 + 128: e1 00 00 04 l.or r8,r0,r0 + 12c: e1 20 00 04 l.or r9,r0,r0 + 130: e1 40 00 04 l.or r10,r0,r0 + 134: e1 60 00 04 l.or r11,r0,r0 + 138: e1 80 00 04 l.or r12,r0,r0 + 13c: e1 a0 00 04 l.or r13,r0,r0 + 140: e1 c0 00 04 l.or r14,r0,r0 + 144: e1 e0 00 04 l.or r15,r0,r0 + 148: e2 00 00 04 l.or r16,r0,r0 + 14c: e2 20 00 04 l.or r17,r0,r0 + 150: e2 40 00 04 l.or r18,r0,r0 + 154: e2 60 00 04 l.or r19,r0,r0 + 158: e2 80 00 04 l.or r20,r0,r0 + 15c: e2 a0 00 04 l.or r21,r0,r0 + 160: e2 c0 00 04 l.or r22,r0,r0 + 164: e2 e0 00 04 l.or r23,r0,r0 + 168: e3 00 00 04 l.or r24,r0,r0 + 16c: e3 20 00 04 l.or r25,r0,r0 + 170: e3 40 00 04 l.or r26,r0,r0 + 174: e3 60 00 04 l.or r27,r0,r0 + 178: e3 80 00 04 l.or r28,r0,r0 + 17c: e3 a0 00 04 l.or r29,r0,r0 + 180: e3 c0 00 04 l.or r30,r0,r0 + 184: e3 e0 00 04 l.or r31,r0,r0 + 188: 18 40 00 00 l.movhi r2,0x0 + 18c: a8 42 0f 00 l.ori r2,r2,0xf00 + 190: 44 00 10 00 l.jr r2 + 194: 15 00 00 00 l.nop 0x0 + ... + +00000200 <__exception_bus_error>: + 200: 00 00 00 00 l.j 200 <__exception_bus_error> + 204: 15 00 00 00 l.nop 0x0 + ... + +00000300 <__exception_data_page_fault>: + 300: 00 00 00 00 l.j 300 <__exception_data_page_fault> + 304: 15 00 00 00 l.nop 0x0 + ... + +00000400 <__exception_instruction_page_fault>: + 400: 00 00 00 00 l.j 400 <__exception_instruction_page_fault> + 404: 15 00 00 00 l.nop 0x0 + ... + +00000500 <__exception_tick_timer>: + 500: 00 00 00 00 l.j 500 <__exception_tick_timer> + 504: 15 00 00 00 l.nop 0x0 + ... + +00000600 <__exception_unaligned_access>: + 600: 00 00 00 00 l.j 600 <__exception_unaligned_access> + 604: 15 00 00 00 l.nop 0x0 + ... + +00000700 <__exception_illegal_instruction>: + 700: 00 00 00 00 l.j 700 <__exception_illegal_instruction> + 704: 15 00 00 00 l.nop 0x0 + ... + +00000800 <__external_IRQ>: + 800: 9c 21 ff 88 l.addi r1,r1,0xffffff88 + 804: d4 01 48 1c l.sw 0x1c(r1),r9 + 808: 04 00 00 0e l.jal 840 + 80c: 15 00 00 00 l.nop 0x0 + 810: b4 60 00 40 l.mfspr r3,r0,0x40 + 814: a4 83 00 04 l.andi r4,r3,0x4 + 818: bc 04 00 00 l.sfeqi r4,0x0 + 81c: 0c 00 00 02 l.bnf 824 + 820: 15 00 00 00 l.nop 0x0 + +00000824 : + 824: 04 00 01 b1 l.jal ee8 <_external_exeption> + 828: 15 00 00 00 l.nop 0x0 + 82c: 04 00 00 23 l.jal 8b8 + 830: 15 00 00 00 l.nop 0x0 + 834: 85 21 00 1c l.lwz r9,0x1c(r1) + 838: 9c 21 00 78 l.addi r1,r1,0x78 + 83c: 24 00 00 00 l.rfe + +00000840 : + 840: d4 01 10 00 l.sw 0x0(r1),r2 + 844: d4 01 18 04 l.sw 0x4(r1),r3 + 848: d4 01 20 08 l.sw 0x8(r1),r4 + 84c: d4 01 28 0c l.sw 0xc(r1),r5 + 850: d4 01 30 10 l.sw 0x10(r1),r6 + 854: d4 01 38 14 l.sw 0x14(r1),r7 + 858: d4 01 40 18 l.sw 0x18(r1),r8 + 85c: d4 01 50 20 l.sw 0x20(r1),r10 + 860: d4 01 58 24 l.sw 0x24(r1),r11 + 864: d4 01 60 28 l.sw 0x28(r1),r12 + 868: d4 01 68 2c l.sw 0x2c(r1),r13 + 86c: d4 01 70 30 l.sw 0x30(r1),r14 + 870: d4 01 78 34 l.sw 0x34(r1),r15 + 874: d4 01 80 38 l.sw 0x38(r1),r16 + 878: d4 01 88 3c l.sw 0x3c(r1),r17 + 87c: d4 01 90 40 l.sw 0x40(r1),r18 + 880: d4 01 98 44 l.sw 0x44(r1),r19 + 884: d4 01 a0 48 l.sw 0x48(r1),r20 + 888: d4 01 a8 4c l.sw 0x4c(r1),r21 + 88c: d4 01 b0 50 l.sw 0x50(r1),r22 + 890: d4 01 b8 54 l.sw 0x54(r1),r23 + 894: d4 01 c0 58 l.sw 0x58(r1),r24 + 898: d4 01 c8 5c l.sw 0x5c(r1),r25 + 89c: d4 01 d0 60 l.sw 0x60(r1),r26 + 8a0: d4 01 d8 64 l.sw 0x64(r1),r27 + 8a4: d4 01 e0 68 l.sw 0x68(r1),r28 + 8a8: d4 01 e8 6c l.sw 0x6c(r1),r29 + 8ac: d4 01 f0 70 l.sw 0x70(r1),r30 + 8b0: 44 00 48 00 l.jr r9 + 8b4: 15 00 00 00 l.nop 0x0 + +000008b8 : + 8b8: 84 41 00 00 l.lwz r2,0x0(r1) + 8bc: 84 61 00 04 l.lwz r3,0x4(r1) + 8c0: 84 81 00 08 l.lwz r4,0x8(r1) + 8c4: 84 a1 00 0c l.lwz r5,0xc(r1) + 8c8: 84 c1 00 10 l.lwz r6,0x10(r1) + 8cc: 84 e1 00 14 l.lwz r7,0x14(r1) + 8d0: 85 01 00 18 l.lwz r8,0x18(r1) + 8d4: 85 41 00 20 l.lwz r10,0x20(r1) + 8d8: 85 61 00 24 l.lwz r11,0x24(r1) + 8dc: 85 81 00 28 l.lwz r12,0x28(r1) + 8e0: 85 a1 00 2c l.lwz r13,0x2c(r1) + 8e4: 85 c1 00 30 l.lwz r14,0x30(r1) + 8e8: 85 e1 00 34 l.lwz r15,0x34(r1) + 8ec: 86 01 00 38 l.lwz r16,0x38(r1) + 8f0: 86 21 00 3c l.lwz r17,0x3c(r1) + 8f4: 86 41 00 40 l.lwz r18,0x40(r1) + 8f8: 86 61 00 44 l.lwz r19,0x44(r1) + 8fc: 86 81 00 48 l.lwz r20,0x48(r1) + 900: 86 a1 00 4c l.lwz r21,0x4c(r1) + 904: 86 c1 00 50 l.lwz r22,0x50(r1) + 908: 86 e1 00 54 l.lwz r23,0x54(r1) + 90c: 87 01 00 58 l.lwz r24,0x58(r1) + 910: 87 21 00 5c l.lwz r25,0x5c(r1) + 914: 87 41 00 60 l.lwz r26,0x60(r1) + 918: 87 61 00 64 l.lwz r27,0x64(r1) + 91c: 87 81 00 68 l.lwz r28,0x68(r1) + 920: 87 a1 00 6c l.lwz r29,0x6c(r1) + 924: 87 c1 00 70 l.lwz r30,0x70(r1) + 928: 44 00 48 00 l.jr r9 + 92c: 15 00 00 00 l.nop 0x0 + ... + +Disassembly of section .text: + +00000d00 <_SPI2_Config>: +// Globals : None +// Side Effects : +// Configuration Data : spi.h + +void SPI2_Config() +{ + d00: 9c 21 ff fc l.addi r1,r1,0xfffffffc + d04: d4 01 10 00 l.sw 0x0(r1),r2 + d08: 9c 41 00 04 l.addi r2,r1,0x4 + uint32 ctrl_word; + REG32(SPI2_DIVIDER) = SPI2_DIV_BIT; // Set SPI clock divider + d0c: 18 80 b1 00 l.movhi r4,0xb100 + d10: 9c 60 00 03 l.addi r3,r0,0x3 + d14: a8 a4 00 14 l.ori r5,r4,0x14 + | CTRL_ASS // When set will generate a slave select automatically + | CTRL_CHAR_LEN(SPI2_REG_LEN) // Number of bits to transfer + | CTRL_Rx_NEG // Master input slave output signal will change + // on negative SCLK. + ); + REG32(SPI2_CTRL) = ctrl_word; + d18: a8 c4 00 10 l.ori r6,r4,0x10 +// Configuration Data : spi.h + +void SPI2_Config() +{ + uint32 ctrl_word; + REG32(SPI2_DIVIDER) = SPI2_DIV_BIT; // Set SPI clock divider + d1c: d4 05 18 00 l.sw 0x0(r5),r3 + | CTRL_ASS // When set will generate a slave select automatically + | CTRL_CHAR_LEN(SPI2_REG_LEN) // Number of bits to transfer + | CTRL_Rx_NEG // Master input slave output signal will change + // on negative SCLK. + ); + REG32(SPI2_CTRL) = ctrl_word; + d20: 9c 60 22 10 l.addi r3,r0,0x2210 + REG32(SPI2_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + d24: a8 84 00 18 l.ori r4,r4,0x18 + | CTRL_ASS // When set will generate a slave select automatically + | CTRL_CHAR_LEN(SPI2_REG_LEN) // Number of bits to transfer + | CTRL_Rx_NEG // Master input slave output signal will change + // on negative SCLK. + ); + REG32(SPI2_CTRL) = ctrl_word; + d28: d4 06 18 00 l.sw 0x0(r6),r3 + REG32(SPI2_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + d2c: 9c 60 00 01 l.addi r3,r0,0x1 + d30: d4 04 18 00 l.sw 0x0(r4),r3 + d34: 84 41 00 00 l.lwz r2,0x0(r1) + d38: 44 00 48 00 l.jr r9 + d3c: 9c 21 00 04 l.addi r1,r1,0x4 + +00000d40 <_SPI3_Config>: +// Globals : None +// Side Effects : +// Configuration Data : spi.h + +void SPI3_Config() +{ + d40: 9c 21 ff fc l.addi r1,r1,0xfffffffc + d44: d4 01 10 00 l.sw 0x0(r1),r2 + d48: 9c 41 00 04 l.addi r2,r1,0x4 + uint32 ctrl_word; + + REG32(SPI3_DIVIDER) = SPI3_DIV_BIT; // Set SPI clock divider + d4c: 18 80 b2 00 l.movhi r4,0xb200 + d50: 9c 60 00 04 l.addi r3,r0,0x4 + d54: a8 a4 00 14 l.ori r5,r4,0x14 + | CTRL_CHAR_LEN(SPI3_REG_LEN) // Number of bits to transfer + | CTRL_Tx_NEG // Master output slave input signal will change + // on negative SCLK. + ); + + REG32(SPI3_CTRL) = ctrl_word; + d58: a8 c4 00 10 l.ori r6,r4,0x10 + +void SPI3_Config() +{ + uint32 ctrl_word; + + REG32(SPI3_DIVIDER) = SPI3_DIV_BIT; // Set SPI clock divider + d5c: d4 05 18 00 l.sw 0x0(r5),r3 + | CTRL_CHAR_LEN(SPI3_REG_LEN) // Number of bits to transfer + | CTRL_Tx_NEG // Master output slave input signal will change + // on negative SCLK. + ); + + REG32(SPI3_CTRL) = ctrl_word; + d60: 9c 60 24 10 l.addi r3,r0,0x2410 + REG32(SPI3_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + d64: a8 84 00 18 l.ori r4,r4,0x18 + | CTRL_CHAR_LEN(SPI3_REG_LEN) // Number of bits to transfer + | CTRL_Tx_NEG // Master output slave input signal will change + // on negative SCLK. + ); + + REG32(SPI3_CTRL) = ctrl_word; + d68: d4 06 18 00 l.sw 0x0(r6),r3 + REG32(SPI3_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + d6c: 9c 60 00 01 l.addi r3,r0,0x1 + d70: d4 04 18 00 l.sw 0x0(r4),r3 + d74: 84 41 00 00 l.lwz r2,0x0(r1) + d78: 44 00 48 00 l.jr r9 + d7c: 9c 21 00 04 l.addi r1,r1,0x4 + +00000d80 <_SPI2_Send_Receive_Data>: +// Globals : NONE +// Configuration Data : spi.h +// Calling : receive_data = (uint16)SPI2_Send_Receive_Data(send_data); + +uint32 SPI2_Send_Receive_Data(uint32 transmit_data) +{ + d80: 9c 21 ff fc l.addi r1,r1,0xfffffffc + d84: d4 01 10 00 l.sw 0x0(r1),r2 + d88: 9c 41 00 04 l.addi r2,r1,0x4 + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI2_TX0) = transmit_data; // Put your data in tx reg + d8c: 18 a0 b1 00 l.movhi r5,0xb100 + REG32(SPI2_CTRL) |= SPI_CTRL_GO; // Start the transfer |= or + d90: 9c 80 00 00 l.addi r4,r0,0x0 +uint32 SPI2_Send_Receive_Data(uint32 transmit_data) +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI2_TX0) = transmit_data; // Put your data in tx reg + d94: d4 05 18 00 l.sw 0x0(r5),r3 + REG32(SPI2_CTRL) |= SPI_CTRL_GO; // Start the transfer |= or + d98: a8 c5 00 10 l.ori r6,r5,0x10 + d9c: 84 66 00 00 l.lwz r3,0x0(r6) + while(REG32(SPI2_CTRL) & SPI_CTRL_BSY) // Do the transmit + da0: a8 a6 00 00 l.ori r5,r6,0x0 +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI2_TX0) = transmit_data; // Put your data in tx reg + REG32(SPI2_CTRL) |= SPI_CTRL_GO; // Start the transfer |= or + da4: a8 63 01 00 l.ori r3,r3,0x100 + da8: d4 06 18 00 l.sw 0x0(r6),r3 + dac: 00 00 00 04 l.j dbc <_SPI2_Send_Receive_Data+0x3c> + db0: 15 00 00 00 l.nop 0x0 + while(REG32(SPI2_CTRL) & SPI_CTRL_BSY) // Do the transmit + { + if(no_response++ >= MAX_SPI_WAIT) { + db4: 10 00 00 07 l.bf dd0 <_SPI2_Send_Receive_Data+0x50> + db8: 9c 84 00 01 l.addi r4,r4,0x1 + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI2_TX0) = transmit_data; // Put your data in tx reg + REG32(SPI2_CTRL) |= SPI_CTRL_GO; // Start the transfer |= or + while(REG32(SPI2_CTRL) & SPI_CTRL_BSY) // Do the transmit + dbc: 84 65 00 00 l.lwz r3,0x0(r5) + dc0: a4 63 01 00 l.andi r3,r3,0x100 + dc4: bc 23 00 00 l.sfnei r3,0x0 + dc8: 13 ff ff fb l.bf db4 <_SPI2_Send_Receive_Data+0x34> + dcc: bc 04 27 10 l.sfeqi r4,0x2710 + if(no_response++ >= MAX_SPI_WAIT) { + break; } + } + return(REG32(SPI2_DR0)); // Return receive reg + +} + dd0: 19 60 b1 00 l.movhi r11,0xb100 + dd4: 85 6b 00 00 l.lwz r11,0x0(r11) + dd8: 84 41 00 00 l.lwz r2,0x0(r1) + ddc: 44 00 48 00 l.jr r9 + de0: 9c 21 00 04 l.addi r1,r1,0x4 + +00000de4 <_SPI3_Send_Receive_Data>: +// Side Effects : +// Configuration Data : spi.h +// Calling : receive_data = (uint16)SPI3_Send_Receive_Data(send_data); + +uint32 SPI3_Send_Receive_Data(uint32 transmitt_data) +{ + de4: 9c 21 ff fc l.addi r1,r1,0xfffffffc + de8: d4 01 10 00 l.sw 0x0(r1),r2 + dec: 9c 41 00 04 l.addi r2,r1,0x4 + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI3_TX0) = transmitt_data; // Put your data in tx reg + df0: 18 a0 b2 00 l.movhi r5,0xb200 + REG32(SPI3_CTRL) |= SPI_CTRL_GO; //Start the transfer |= or + df4: 9c 80 00 00 l.addi r4,r0,0x0 +uint32 SPI3_Send_Receive_Data(uint32 transmitt_data) +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI3_TX0) = transmitt_data; // Put your data in tx reg + df8: d4 05 18 00 l.sw 0x0(r5),r3 + REG32(SPI3_CTRL) |= SPI_CTRL_GO; //Start the transfer |= or + dfc: a8 c5 00 10 l.ori r6,r5,0x10 + e00: 84 66 00 00 l.lwz r3,0x0(r6) + while(REG32(SPI3_CTRL) & SPI_CTRL_BSY) // Do the transmit + e04: a8 a6 00 00 l.ori r5,r6,0x0 +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI3_TX0) = transmitt_data; // Put your data in tx reg + REG32(SPI3_CTRL) |= SPI_CTRL_GO; //Start the transfer |= or + e08: a8 63 01 00 l.ori r3,r3,0x100 + e0c: d4 06 18 00 l.sw 0x0(r6),r3 + e10: 00 00 00 04 l.j e20 <_SPI3_Send_Receive_Data+0x3c> + e14: 15 00 00 00 l.nop 0x0 + while(REG32(SPI3_CTRL) & SPI_CTRL_BSY) // Do the transmit + { + if(no_response++ >= MAX_SPI_WAIT) { + e18: 10 00 00 07 l.bf e34 <_SPI3_Send_Receive_Data+0x50> + e1c: 9c 84 00 01 l.addi r4,r4,0x1 + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI3_TX0) = transmitt_data; // Put your data in tx reg + REG32(SPI3_CTRL) |= SPI_CTRL_GO; //Start the transfer |= or + while(REG32(SPI3_CTRL) & SPI_CTRL_BSY) // Do the transmit + e20: 84 65 00 00 l.lwz r3,0x0(r5) + e24: a4 63 01 00 l.andi r3,r3,0x100 + e28: bc 23 00 00 l.sfnei r3,0x0 + e2c: 13 ff ff fb l.bf e18 <_SPI3_Send_Receive_Data+0x34> + e30: bc 04 27 10 l.sfeqi r4,0x2710 + break; } + } + + return(REG32(SPI3_DR0)); // Return receive reg + + } + e34: 19 60 b2 00 l.movhi r11,0xb200 + e38: 85 6b 00 00 l.lwz r11,0x0(r11) + e3c: 84 41 00 00 l.lwz r2,0x0(r1) + e40: 44 00 48 00 l.jr r9 + e44: 9c 21 00 04 l.addi r1,r1,0x4 + +00000e48 <_GPIO_Write>: +/******************************************************************************/ + +// Write to the GPIO (32 bits) + +void GPIO_Write(uint32 GPIO_data) +{ + e48: 9c 21 ff fc l.addi r1,r1,0xfffffffc + e4c: d4 01 10 00 l.sw 0x0(r1),r2 + e50: 9c 41 00 04 l.addi r2,r1,0x4 + REG32(GPIO_BASE + RGPIO_OUT) = GPIO_data; + e54: 18 80 9a 00 l.movhi r4,0x9a00 + e58: a8 84 00 04 l.ori r4,r4,0x4 + e5c: d4 04 18 00 l.sw 0x0(r4),r3 + e60: 84 41 00 00 l.lwz r2,0x0(r1) + e64: 44 00 48 00 l.jr r9 + e68: 9c 21 00 04 l.addi r1,r1,0x4 + +00000e6c <_Write_External_SDRAM_1>: +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + e6c: 9c 21 ff f8 l.addi r1,r1,0xfffffff8 + e70: d4 01 10 04 l.sw 0x4(r1),r2 + e74: 9c 41 00 08 l.addi r2,r1,0x8 + e78: d4 01 48 00 l.sw 0x0(r1),r9 + + range = 0x100; //0x100; + adr_offset = 0x00010000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + e7c: 18 60 00 01 l.movhi r3,0x1 + e80: d4 03 18 00 l.sw 0x0(r3),r3 + e84: a8 63 00 04 l.ori r3,r3,0x4 + error_report_offset = 0x2000; + + range = 0x100; //0x100; + adr_offset = 0x00010000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + e88: 18 80 00 01 l.movhi r4,0x1 + REG32(adr_offset + i) = (adr_offset + i); + e8c: d4 03 18 00 l.sw 0x0(r3),r3 + error_report_offset = 0x2000; + + range = 0x100; //0x100; + adr_offset = 0x00010000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + e90: a8 84 01 00 l.ori r4,r4,0x100 + REG32(adr_offset + i) = (adr_offset + i); + e94: 9c 63 00 04 l.addi r3,r3,0x4 + error_report_offset = 0x2000; + + range = 0x100; //0x100; + adr_offset = 0x00010000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + e98: e4 23 20 00 l.sfne r3,r4 + e9c: 13 ff ff fb l.bf e88 <_Write_External_SDRAM_1+0x1c> + ea0: 18 80 00 01 l.movhi r4,0x1 + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + ea4: 84 64 00 00 l.lwz r3,0x0(r4) + if (read != (adr_offset + i)) { + ea8: e4 03 20 00 l.sfeq r3,r4 + eac: 10 00 00 06 l.bf ec4 <_Write_External_SDRAM_1+0x58> + eb0: 9c 84 00 04 l.addi r4,r4,0x4 + GPIO_Write(0x55); + eb4: 07 ff ff e5 l.jal e48 <_GPIO_Write> + eb8: 9c 60 00 55 l.addi r3,r0,0x55 + ebc: 00 00 00 00 l.j ebc <_Write_External_SDRAM_1+0x50> + ec0: 15 00 00 00 l.nop 0x0 + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + ec4: 18 60 00 01 l.movhi r3,0x1 + ec8: a8 63 01 00 l.ori r3,r3,0x100 + ecc: e4 24 18 00 l.sfne r4,r3 + ed0: 13 ff ff f5 l.bf ea4 <_Write_External_SDRAM_1+0x38> + ed4: 15 00 00 00 l.nop 0x0 + ed8: 85 21 00 00 l.lwz r9,0x0(r1) + edc: 84 41 00 04 l.lwz r2,0x4(r1) + ee0: 44 00 48 00 l.jr r9 + ee4: 9c 21 00 08 l.addi r1,r1,0x8 + +00000ee8 <_external_exeption>: +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + +void external_exeption() +{ + ee8: 9c 21 ff fc l.addi r1,r1,0xfffffffc + eec: d4 01 10 00 l.sw 0x0(r1),r2 + ef0: 9c 41 00 04 l.addi r2,r1,0x4 + ef4: 84 41 00 00 l.lwz r2,0x0(r1) + ef8: 44 00 48 00 l.jr r9 + efc: 9c 21 00 04 l.addi r1,r1,0x4 + +00000f00 <_Start>: +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ + +void Start() +{ + f00: 9c 21 ff f8 l.addi r1,r1,0xfffffff8 + f04: d4 01 10 04 l.sw 0x4(r1),r2 + f08: 9c 41 00 08 l.addi r2,r1,0x8 + f0c: d4 01 48 00 l.sw 0x0(r1),r9 + uint32 i; + + // Configure GPIO + REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs + f10: 18 60 9a 00 l.movhi r3,0x9a00 + f14: 9c 80 00 ff l.addi r4,r0,0xff + f18: a8 a3 00 08 l.ori r5,r3,0x8 + REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO + f1c: a8 c3 00 0c l.ori r6,r3,0xc +void Start() +{ + uint32 i; + + // Configure GPIO + REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs + f20: d4 05 20 00 l.sw 0x0(r5),r4 + REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO + f24: 9c 80 00 00 l.addi r4,r0,0x0 + + GPIO_Write(0x1); + f28: 9c 60 00 01 l.addi r3,r0,0x1 +{ + uint32 i; + + // Configure GPIO + REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs + REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO + f2c: d4 06 20 00 l.sw 0x0(r6),r4 + + GPIO_Write(0x1); + f30: 07 ff ff c6 l.jal e48 <_GPIO_Write> + f34: 15 00 00 00 l.nop 0x0 + + // Setup SPI 2 + SPI2_Config(); + f38: 07 ff ff 72 l.jal d00 <_SPI2_Config> + f3c: 15 00 00 00 l.nop 0x0 + + GPIO_Write(0x2); + f40: 07 ff ff c2 l.jal e48 <_GPIO_Write> + f44: 9c 60 00 02 l.addi r3,r0,0x2 + + // Setup SPI 3 + SPI3_Config(); + f48: 07 ff ff 7e l.jal d40 <_SPI3_Config> + f4c: 15 00 00 00 l.nop 0x0 + + GPIO_Write(0x3); + f50: 07 ff ff be l.jal e48 <_GPIO_Write> + f54: 9c 60 00 03 l.addi r3,r0,0x3 + + // Send 0x22 on SPI 2 + SPI2_Send_Receive_Data(0x22); + f58: 07 ff ff 8a l.jal d80 <_SPI2_Send_Receive_Data> + f5c: 9c 60 00 22 l.addi r3,r0,0x22 + + GPIO_Write(0x4); + f60: 07 ff ff ba l.jal e48 <_GPIO_Write> + f64: 9c 60 00 04 l.addi r3,r0,0x4 + + // Send 0x33 on SPI 3 + SPI3_Send_Receive_Data(0x33); + f68: 07 ff ff 9f l.jal de4 <_SPI3_Send_Receive_Data> + f6c: 9c 60 00 33 l.addi r3,r0,0x33 + + GPIO_Write(0x5); + f70: 07 ff ff b6 l.jal e48 <_GPIO_Write> + f74: 9c 60 00 05 l.addi r3,r0,0x5 + + // Tests a few external SDRAM addresses + Write_External_SDRAM_1(); + f78: 07 ff ff bd l.jal e6c <_Write_External_SDRAM_1> + f7c: 15 00 00 00 l.nop 0x0 + + + while(TRUE) { + + GPIO_Write(0xFF); // Test finished + f80: 07 ff ff b2 l.jal e48 <_GPIO_Write> + f84: 9c 60 00 ff l.addi r3,r0,0xff + f88: 03 ff ff fe l.j f80 <_Start+0x80> + f8c: 15 00 00 00 l.nop 0x0 + f90: 85 21 00 00 l.lwz r9,0x0(r1) + f94: 84 41 00 04 l.lwz r2,0x4(r1) + f98: 44 00 48 00 l.jr r9 + f9c: 9c 21 00 08 l.addi r1,r1,0x8 Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/main.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/main.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/main.c (revision 11) @@ -0,0 +1,336 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : main.c +// Prepared By : +// Project Start : 2008-07-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + + + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#define INCLUDED_FROM_C_FILE + +#include "orsocdef.h" +#include "board.h" +#include "spi.h" + + +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + + +/*$$GLOBAL VARIABLES*/ +/******************************************************************************/ +/* */ +/* G L O B A L V A R I A B L E S */ +/* */ +/******************************************************************************/ + + + +/*$$PRIVATE VARIABLES*/ +/******************************************************************************/ +/* */ +/* P R I V A T E V A R I A B L E S */ +/* */ +/******************************************************************************/ + + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ +/* */ +/******************************************************************************/ + + + + + + +/******************************************************************************/ +/* C O N F I G U R E S P I 2 */ +/******************************************************************************/ + +// Function : SPI2_Config +// Description : Routine used to configure the SPI 2 interface +// Arguments : None +// Returns : None +// Globals : None +// Side Effects : +// Configuration Data : spi.h + +void SPI2_Config() +{ + uint32 ctrl_word; + REG32(SPI2_DIVIDER) = SPI2_DIV_BIT; // Set SPI clock divider + ctrl_word = (0 + | CTRL_ASS // When set will generate a slave select automatically + | CTRL_CHAR_LEN(SPI2_REG_LEN) // Number of bits to transfer + | CTRL_Rx_NEG // Master input slave output signal will change + // on negative SCLK. + ); + REG32(SPI2_CTRL) = ctrl_word; + REG32(SPI2_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + // setting this bit will drive the slave select output + // to the active state during the duration of the file + // transfer. + } + + + +/******************************************************************************/ +/* C O N F I G U R E S P I 3 */ +/******************************************************************************/ + +// Function : SPI3_Config (Flash communication) +// Description : Routine used to configure the SPI 3 interface +// Arguments : None +// Returns : None +// Globals : None +// Side Effects : +// Configuration Data : spi.h + +void SPI3_Config() +{ + uint32 ctrl_word; + + REG32(SPI3_DIVIDER) = SPI3_DIV_BIT; // Set SPI clock divider + ctrl_word = (0 + | CTRL_ASS // When set will generate a slave select automatically + | CTRL_CHAR_LEN(SPI3_REG_LEN) // Number of bits to transfer + | CTRL_Tx_NEG // Master output slave input signal will change + // on negative SCLK. + ); + + REG32(SPI3_CTRL) = ctrl_word; + REG32(SPI3_SS) = 0x1; // Slave select line 1 set. If the ASS bit is set + // setting this bit will drive the slave select output + // to the active state during the duration of the file + // transfer. +} + + + +/******************************************************************************/ +/* S P I 2 S E N D / R E C E I V E D A T A */ +/******************************************************************************/ + +// Function : SPI2_Send_Receive_Data +// Description : Routine used to transmit/receive SPI data +// Arguments : SPI transmitt data +// Returns : Data from SPI receive register +// Globals : NONE +// Configuration Data : spi.h +// Calling : receive_data = (uint16)SPI2_Send_Receive_Data(send_data); + +uint32 SPI2_Send_Receive_Data(uint32 transmit_data) +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI2_TX0) = transmit_data; // Put your data in tx reg + REG32(SPI2_CTRL) |= SPI_CTRL_GO; // Start the transfer |= or + while(REG32(SPI2_CTRL) & SPI_CTRL_BSY) // Do the transmit + { + if(no_response++ >= MAX_SPI_WAIT) { + break; } + } + return(REG32(SPI2_DR0)); // Return receive reg + +} + + + +/******************************************************************************/ +/* S P I 3 S E N D / R E C E I V E D A T A */ +/******************************************************************************/ + +// Function : SPI3_Send_Receive_Data +// Description : Routine used to transmit/receive data +// Arguments : SPI transmitt data +// Returns : Data from SPI receive register +// Globals : NONE +// Side Effects : +// Configuration Data : spi.h +// Calling : receive_data = (uint16)SPI3_Send_Receive_Data(send_data); + +uint32 SPI3_Send_Receive_Data(uint32 transmitt_data) +{ + uint32 ctrl_word; + + REG unsigned long no_response = 0; + REG32(SPI3_TX0) = transmitt_data; // Put your data in tx reg + REG32(SPI3_CTRL) |= SPI_CTRL_GO; //Start the transfer |= or + while(REG32(SPI3_CTRL) & SPI_CTRL_BSY) // Do the transmit + { + if(no_response++ >= MAX_SPI_WAIT) { + break; } + } + + return(REG32(SPI3_DR0)); // Return receive reg + + } + + + +/******************************************************************************/ +/* G P I O W R I T E */ +/******************************************************************************/ + +// Write to the GPIO (32 bits) + +void GPIO_Write(uint32 GPIO_data) +{ + REG32(GPIO_BASE + RGPIO_OUT) = GPIO_data; +} + + + +/******************************************************************************/ +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + uint32 i; + uint32 read; + uint32 range; + uint32 adr_offset; + uint32 error_counter; + uint32 error_report_offset; + + error_counter = 0; + error_report_offset = 0x2000; + + range = 0x100; //0x100; + adr_offset = 0x00010000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + if (read != (adr_offset + i)) { + GPIO_Write(0x55); + while(TRUE){} //ERROR + } + } +} + + + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + +void external_exeption() +{ + REG uint8 i; + REG uint32 PicSr,sr; +} + + +/*$$MAIN*/ +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ + +void Start() +{ + uint32 i; + + // Configure GPIO + REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs + REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO + + GPIO_Write(0x1); + + // Setup SPI 2 + SPI2_Config(); + + GPIO_Write(0x2); + + // Setup SPI 3 + SPI3_Config(); + + GPIO_Write(0x3); + + // Send 0x22 on SPI 2 + SPI2_Send_Receive_Data(0x22); + + GPIO_Write(0x4); + + // Send 0x33 on SPI 3 + SPI3_Send_Receive_Data(0x33); + + GPIO_Write(0x5); + + // Tests a few external SDRAM addresses + Write_External_SDRAM_1(); + + + while(TRUE) { + + GPIO_Write(0xFF); // Test finished + + } + + +} Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/hex2v.pl =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/hex2v.pl (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/hex2v.pl (revision 11) @@ -0,0 +1,22 @@ +#!/usr/bin/perl + +@data = (); + +while(<>) { + if (m/\:([A-F0-9]{2})([A-F0-9]{4})([A-F0-9]{2})([A-F0-9]+)([A-F0-9]{2})/) { + $vec = $4; + $len = hex $1; + $rec_type = $3; + $byte_addr = (hex $2); + if ($len > 0) { + for (my($i)=0; $i < $len*2; $i+=2) { + $data[$byte_addr++] = hex substr($vec, $i, 2); + } + } + } +} +$i =0; +while($i <= $#data) { + printf ("%2.2x%2.2x%2.2x%2.2x\n", $data[$i], $data[$i+1], $data[$i+2], $data[$i+3]); + $i+=4; +} Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/BootReset.S =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/BootReset.S (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/BootReset.S (revision 11) @@ -0,0 +1,325 @@ + + /*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : BootReset.S +// Prepared By : +// Project Start : 2008-07-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + + + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#include "board.h" +#include "spr_defs.h" + +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +#define KALLE 0x12345678 + +/******************************************************************************/ +/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */ +/******************************************************************************/ + +.macro load32i reg const + l.movhi \reg,hi(\const) + l.ori \reg,\reg,lo(\const) +.endm + +/******************************************************************************/ +/* S E T U P E X C E P T I O N V E C T O R */ +/******************************************************************************/ + +.macro exception_vector name org + .org \org + .p2align 8 + .global __exception_\name +__exception_\name: + + l.j __exception_\name + l.nop +.endm + +/******************************************************************************/ +/* B R A N C H T O N A M E */ +/******************************************************************************/ + + +.macro BSR name + l.j \name + l.nop +ret_\name: +.endm + + +/*$$RESET START*/ +/******************************************************************************/ +/* */ +/* R E S E T S T A R T */ +/* */ +/******************************************************************************/ + +.section .vectors, "ax" + +.org 0x100 - 0x100 // Sector .vectors start at 0x100 + + +_reset: + +// Set stack pointer (r1) to 00003560 +// Clear all other registers + + .equ sp,0x00003560 ; + l.movhi r0,0x0000 ; #r0 = 0 + l.ori r0,r0,0x0000 ; + l.movhi r1,hi(sp) ; #r1 = sp + l.ori r1,r1,lo(sp) ; + l.or r2,r0,r0 ; #clear r2 + l.or r3,r0,r0 ; #clear r3 + l.or r4,r0,r0 ; #clear r4 + l.or r5,r0,r0 ; #clear r5 + l.or r6,r0,r0 ; #clear r6 + l.or r7,r0,r0 ; #clear r7 + l.or r8,r0,r0 ; #clear r8 + l.or r9,r0,r0 ; #clear r9 + l.or r10,r0,r0 ; #clear r10 + l.or r11,r0,r0 ; #clear r11 + l.or r12,r0,r0 ; #clear r12 + l.or r13,r0,r0 ; #clear r13 + l.or r14,r0,r0 ; #clear r14 + l.or r15,r0,r0 ; #clear r15 + l.or r16,r0,r0 ; #clear r16 + l.or r17,r0,r0 ; #clear r17 + l.or r18,r0,r0 ; #clear r18 + l.or r19,r0,r0 ; #clear r19 + l.or r20,r0,r0 ; #clear r20 + l.or r21,r0,r0 ; #clear r21 + l.or r22,r0,r0 ; #clear r22 + l.or r23,r0,r0 ; #clear r23 + l.or r24,r0,r0 ; #clear r24 + l.or r25,r0,r0 ; #clear r25 + l.or r26,r0,r0 ; #clear r26 + l.or r27,r0,r0 ; #clear r27 + l.or r28,r0,r0 ; #clear r28 + l.or r29,r0,r0 ; #clear r29 + l.or r30,r0,r0 ; #clear r30 + l.or r31,r0,r0 ; #clear r31 + + +#if IC_ENABLE == 1 /* INSTRUCTION CACHE */ + BSR ic_enable +#endif + + +// Jump to start of program + + load32i r2, (_Start) + l.jr r2 + l.nop + + exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100 + exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100 + exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100 + exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100 + exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100 + exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100 + + +// Defines what will happen when an external interrupt occurs + +.org 0x800 - 0x100 + + .global __external_IRQ + +__external_IRQ: + l.addi r1,r1,-30*4 //move SP 30*4 adresses lower + + l.sw 0x1c(r1),r9 + + l.jal (save_state) + l.nop + + // we mess with r3, r4 and r9 + // + l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt + l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled + l.sfeqi r4,0 + l.bnf JUMP // external irq enabled, all ok. + l.nop + +JUMP: l.jal (_external_exeption) + l.nop + + l.jal (restore_state) + l.nop + + l.lwz r9 ,0x1c(r1) + l.addi r1,r1,30*4 //move SP 30*4 adresses lower + + //Return from exception + l.rfe + + +// Save current state (all general purpose registers) + +save_state: + l.sw 0x0(r1),r2 + l.sw 0x4(r1),r3 + l.sw 0x8(r1),r4 + l.sw 0xc(r1),r5 + l.sw 0x10(r1),r6 + l.sw 0x14(r1),r7 + l.sw 0x18(r1),r8 + l.sw 0x20(r1),r10 + l.sw 0x24(r1),r11 + l.sw 0x28(r1),r12 + l.sw 0x2c(r1),r13 + l.sw 0x30(r1),r14 + l.sw 0x34(r1),r15 + l.sw 0x38(r1),r16 + l.sw 0x3c(r1),r17 + l.sw 0x40(r1),r18 + l.sw 0x44(r1),r19 + l.sw 0x48(r1),r20 + l.sw 0x4c(r1),r21 + l.sw 0x50(r1),r22 + l.sw 0x54(r1),r23 + l.sw 0x58(r1),r24 + l.sw 0x5c(r1),r25 + l.sw 0x60(r1),r26 + l.sw 0x64(r1),r27 + l.sw 0x68(r1),r28 + l.sw 0x6c(r1),r29 + l.sw 0x70(r1),r30 + l.jr r9 + l.nop + +// Restore current state + +restore_state: + // disable interrupts (if needed) + l.lwz r2,0x0(r1) + l.lwz r3 ,0x4(r1) + l.lwz r4 ,0x8(r1) + l.lwz r5 ,0xc(r1) + l.lwz r6 ,0x10(r1) + l.lwz r7 ,0x14(r1) + l.lwz r8 ,0x18(r1) + l.lwz r10,0x20(r1) + l.lwz r11,0x24(r1) + l.lwz r12,0x28(r1) + l.lwz r13,0x2c(r1) + l.lwz r14,0x30(r1) + l.lwz r15,0x34(r1) + l.lwz r16,0x38(r1) + l.lwz r17,0x3c(r1) + l.lwz r18,0x40(r1) + l.lwz r19,0x44(r1) + l.lwz r20,0x48(r1) + l.lwz r21,0x4c(r1) + l.lwz r22,0x50(r1) + l.lwz r23,0x54(r1) + l.lwz r24,0x58(r1) + l.lwz r25,0x5c(r1) + l.lwz r26,0x60(r1) + l.lwz r27,0x64(r1) + l.lwz r28,0x68(r1) + l.lwz r29,0x6c(r1) + l.lwz r30,0x70(r1) + l.jr r9 + l.nop + + + +/*************************** + * Instruction cache enable + */ +#if IC_ENABLE == 1 +ic_enable: + + /* Disable IC */ + l.mfspr r6,r0,SPR_SR + l.addi r5,r0,-1 + l.xori r5,r5,SPR_SR_ICE + l.and r5,r6,r5 + l.mtspr r0,r5,SPR_SR + + /* Invalidate IC */ + l.addi r6,r0,0 + l.addi r5,r0,IC_SIZE +1: + l.mtspr r0,r6,SPR_ICBIR + l.sfne r6,r5 + l.bf 1b + l.addi r6,r6,IC_LINE + + /* Enable IC */ + l.mfspr r6,r0,SPR_SR + l.ori r6,r6,SPR_SR_ICE + l.mtspr r0,r6,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.j ret_ic_enable + l.nop +#endif + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.dat =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.dat (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/boot.dat (revision 11) @@ -0,0 +1,1000 @@ +00000d00 +930000e8 +40000000 +930000e4 +00000001 +930000e8 +50000000 +930000e4 +00000001 +930000e8 +60000000 +930000e4 +00000001 +930000e4 +00000001 +930000e8 +7e000023 +930000e4 +00000001 +930000a0 +c03e0310 +00000000 +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +424f4f54 +20202020 +20202020 +20202020 +20202020 +20202020 +20202020 +20202020 +52314120 +20202020 +20202020 +20202020 +20202020 +20202020 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +18000000 +a8000000 +18200000 +a8213560 +e0400004 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PREPARED BY: Jonas Rosén +* +* DATE: 2004-06-28 +* +****************************************************************************** +* REVISION HISTORY: +*****************************************************************************/ +/* $Log:: /ELUD_ELUA/FPGA2/spi.c $ + * + * 1 06-11-27 14:02 Knansand + * LCA test ver 10 + * + * 2 04-06-28 15:01 Knajrose + * Don't hang forever in while case. + * + * 3 05-07-12 10:01 knamsnil + * TX_Neg enabled, signal is changed on falling edge instead. + * This creates stable timing when accessing QDASL:s +*/ + +/********************************************************************* +* INCLUDE FILES +**********************************************************************/ +#include "board.h" +#include "spi.h" + +/********************************************************************* +* PRIVATE MACROS +**********************************************************************/ +#define MAX_SPI_WAIT 10000 + +/********************************************************************* +* PUBLIC VARIABLES +**********************************************************************/ + +/********************************************************************* +* PRIVATE VARIABLES +**********************************************************************/ + +/********************************************************************* +* PRIVATE FUNCTIONS +**********************************************************************/ + +/********************************************************************* +* EXTERNAL VARIABLES +**********************************************************************/ + +/********************************************************************* +* EXTERNAL FUNCTIONS +**********************************************************************/ + +/********************************************************************* +* +* Function: vSPI_Config +* +* Description: Configure the SPI +* +* Arguments: SPI number +* +* Returns: NONE +* +* Globals: NONE +* +* Side Effects: +* +**********************************************************************/ + +void vSPI_Config(unsigned char u8SpiNum) +{ + REG32(OR32SPI_DIVIDER(u8SpiNum)) = SPI_DIV_BIT; /*Set CCKL to 2MHz*/ // 0x400;// + REG32(OR32SPI_CTRL(u8SpiNum)) = 0x00000608; //408 here!!!! /*Set charlen = 8 byte and Rx_Neg*/ + //REG32(OR32SPI_SS(u8SpiNum)) = 0x00000001; +} + +/********************************************************************* +* +* Function: u32uwire_access +* +* Description: routine used to transmit read the SPI +* +* Arguments: SPI number and data +* +* Returns: Data from SPI receive rgister +* +* Globals: NONE +* +* Side Effects: +* +**********************************************************************/ +unsigned char uwire_access(unsigned char u8SpiNum, unsigned char data) +{ + REG unsigned long error=0; + + REG32(OR32SPI_TX0(u8SpiNum)) = data; /*Put your data in tx reg*/ + REG32(OR32SPI_CTRL(u8SpiNum)) |= SPI_CTRL_GO; + + while(REG32(OR32SPI_CTRL(u8SpiNum)) & SPI_CTRL_BSY) /*Do the transmit*/ + { + if(error++ >= MAX_SPI_WAIT) + break; + } + + return(REG32(OR32SPI_DR0(u8SpiNum)) & 0x000000FF); /*Return receivereg*/ +} Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/ram.ld =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/ram.ld (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/ram.ld (revision 11) @@ -0,0 +1,53 @@ +/* Use internal memory*/ + +MEMORY +{ + ld_info : ORIGIN = 0x00000000, LENGTH = 0x000000F0 + vectors : ORIGIN = 0x00000100, LENGTH = 0x00000D00 - 0x100 + flash : ORIGIN = 0x00000D00, LENGTH = 0x00002000 - 0x0A00 + ram : ORIGIN = 0x00003000, LENGTH = 0x00001000 +} + +/* + The following section defines where to put the different input sections. + .text contains the code. + .data contains the initialized data. + .bss contains uninitialized data. + .sdata contains small constant data. +*/ + +SECTIONS +{ + + .ld_info : + { + revision.o(.data) + } > ld_info + + .vectors : { *(.vectors) } > vectors + + .text : { *(.text) } > flash + .rodata : { *(.rodata)} > flash + .data : { *(.data) } > ram + .bss : { *(.bss) } > ram + + .stack : + { + __STACK_TOP = . ; + . = . + 0x00000500; + __STACK_BOTTOM = . ; + } > ram +} + +/* + Definitions of identifiers that control initialization and memory allocation: + These two symbols must be present. + __BSS_START : Start of uninitialized data + __BSS_END : End of data to be cleared +*/ + +__CODE_START = ADDR( .text ); +__CODE_END = ADDR( .text ) + SIZEOF( .text ); + +__DATA_START = ADDR( .bss ); +__DATA_END = ADDR( .bss ) + SIZEOF( .bss ); Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/Makefile =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/Makefile (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/Makefile (revision 11) @@ -0,0 +1,64 @@ +ifndef CROSS_COMPILE +#CROSS_COMPILE = or32-elf- +CROSS_COMPILE = or32-uclinux- +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +NM = $(CROSS_COMPILE)nm +OBJ = $(CROSS_COMPILE)objdump +OBJC = $(CROSS_COMPILE)objcopy +endif + +CFLAGS = -O2 -g -c -Wunknown-pragmas -mhard-mul -msoft-div -msoft-float +LD_FLAGS= --stats -Tram.ld +INCL = board.h spr_defs.h spi.h +OBJECTS = BootReset.o main.o revision.o +LIBS = + +export CROSS_COMPILE + +all: boot.or32 boot.ihex System.map + +boot.or32: $(OBJECTS) Makefile + @printf "\r\n\t--- Linking ---\r\n" + $(LD) -Map System.map -Bstatic $(OBJECTS) $(LIBS) $(LD_FLAGS) -o $@ + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort >> System.map + $(OBJ) -x -d -S boot.or32 >> System.map + +boot.ihex: boot.or32 Makefile + @printf "\r\n\t--- Creating Ihex file: $@ ---\r\n" + $(OBJC) -O ihex boot.or32 boot.ihex + perl gen_memory_text.pl < boot.ihex > ../../sim/rtl_sim/run/memory.txt + perl hex2v.pl < boot.ihex > boot.dat + cp boot.dat '../../sim/rtl_sim/run/.' + + +%.o:%.S $(INCL) Makefile + @printf "\r\n\t--- Assembling $(<) ---\r\n" + $(CC) $(CFLAGS) -o $@ $(<) + +%.o:%.c $(INCL) Makefile + @printf "\r\n\t--- Compiling $(<) ---\r\n" + $(CC) $(CFLAGS) -o $@ $(<) + + +######################################################################### + +clean: + @rm *.o + @rm *.exe + @rm *.BIN + @rm boot.* + @rm System.map + + +distclean: clean + find . -type f \ + \( -name .depend -o -name '*.srec' -o -name '*.bin' \ + -o -name '*.pdf' \) \ + -print | xargs rm -f + rm -f $(OBJS) *.bak tags TAGS + rm -fr *.*~ + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/board.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/board.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/test_app_1/board.h (revision 11) @@ -0,0 +1,127 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : +// File Name : board.h +// Prepared By : +// Project Start : 2007-11-19 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2008 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// This file contains definitions for the eASIC board used. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 080701 1.0 First version marcus + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +#define IC_ENABLE 0 +#define IC_SIZE 8192 +#define IC_LINE 16 + + +/******************************************************************************/ +/* F L O P P Y F L A S H D R I V E */ +/******************************************************************************/ + +//#define BASE_ADDRESS 0x3000C000 +//#define TRACK_SIZE 0x186A //6250 +//#define FLOPPY_SIZE 0xF42240 //0x186A * 0xA0 = 0xF42240 + +/******************************************************************************/ +/* G P I O */ +/******************************************************************************/ + +#define GPIO_BASE 0x9A000000 // General purpose IO base address +#define RGPIO_IN 0x0 // GPIO input data +#define RGPIO_OUT 0x4 // GPIO output data +#define RGPIO_OE 0x8 // GPIO output enable +#define RGPIO_INTE 0xC // GPIO interrupt enable +#define RGPIO_PTRIG 0x10 // Type of event that triggers an IRQ +#define RGPIO_AUX 0x14 // +#define RGPIO_CTRL 0x18 // GPIO control register +#define RGPIO_INTS 0x1C // Interupt status +#define RGPIO_ECLK 0x20 // Enable gpio_eclk to latch RGPIO_IN +#define RGPIO_NEC 0x24 // Select active edge of gpio_eclk + +/******************************************************************************/ +/* S P I */ +/******************************************************************************/ + +// See file spi.h +/*$$TYPEDEFS*/ +/******************************************************************************/ +/* */ +/* T Y P E D E F S */ +/* */ +/******************************************************************************/ + +#ifdef INCLUDED_FROM_C_FILE + + #define LOAD_INFO_STR + + typedef struct load_info + { + unsigned long boardtype; // + unsigned long decompressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long compressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long decompressed_size; // Filled in by ext. program for generating SRecord file + unsigned long compressed_size; // Filled in by ext. program for generating SRecord file + unsigned long extra_pad[23]; // Extra padding + unsigned char boardName[12]; // + unsigned char caaName[20]; // + unsigned char caaRev[8]; // + unsigned char addInfo[16]; // + + } LOAD_INFO; + + + typedef unsigned char BYTE; /* 8 bits */ + typedef unsigned short WORD; /* 16 bits */ + typedef unsigned long LONG_WORD; /* 32 bits */ + +#endif + +#ifndef REG + #define REG register +#endif Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/System.map =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/System.map (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/System.map (revision 11) @@ -0,0 +1,2806 @@ + +Allocating common symbols +Common symbol size file + +_rx_level 0x4 uart.o +_tx_buff 0x20 uart.o +_tx_level 0x4 uart.o + +Memory Configuration + +Name Origin Length Attributes +ld_info 0x01000000 0x000000f0 +vectors 0x01000100 0x00000c00 +flash 0x01000d00 0x00001600 +ram 0x01003000 0x00fffff0 +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD BootReset.o +LOAD main.o +LOAD uart.o +LOAD sd_controller.o + +.vectors 0x01000100 0x900 + *(.vectors) + .vectors 0x01000100 0x900 BootReset.o + 0x01000400 __exception_instruction_page_fault + 0x01000800 __external_IRQ + 0x01000200 __exception_bus_error + 0x01000300 __exception_data_page_fault + 0x01000600 __exception_unaligned_access + 0x01000700 __exception_illegal_instruction + 0x01000500 __exception_tick_timer + +.text 0x01003000 0x1ddc + *(.text) + .text 0x01003000 0x0 BootReset.o + .text 0x01003000 0xaa0 main.o + 0x010031a4 _external_exeption + 0x010031bc _Start + 0x01003000 _Write_External_SDRAM_1 + .text 0x01003aa0 0x864 uart.o + 0x0100404c _uart_print_short + 0x01003cac _uart_putc + 0x01003eb0 _uart_print_long + 0x01003aa0 _uart_init + 0x01003e1c _uart_print_str + 0x01004260 _uart_getc + .text 0x01004304 0xad8 sd_controller.o + 0x01004770 _sd_controller_init + 0x01004304 _sd_get_rca + 0x0100457c _sd_ocr_set + 0x01004480 _sd_wait_rsp + +.rodata 0x01004ddc 0x162 + *(.rodata) + .rodata 0x01004ddc 0x14c main.o + .rodata 0x01004f28 0x1 uart.o + .rodata 0x01004f29 0x15 sd_controller.o + +.data 0x01004f3e 0x0 + *(.data) + .data 0x01004f3e 0x0 BootReset.o + .data 0x01004f3e 0x0 main.o + .data 0x01004f3e 0x0 uart.o + .data 0x01004f3e 0x0 sd_controller.o + +.bss 0x01004f40 0x44 + *(.bss) + .bss 0x01004f40 0x0 BootReset.o + .bss 0x01004f40 0x0 main.o + .bss 0x01004f40 0x0 uart.o + .bss 0x01004f40 0x4 sd_controller.o + *fill* 0x01004f44 0xc 00 + COMMON 0x01004f50 0x34 uart.o + 0x01004f50 _rx_level + 0x01004f60 _tx_buff + 0x01004f80 _tx_level + +.stack 0x01004f84 0x500 + 0x01004f84 __STACK_TOP = . + 0x01005484 . = (. + 0x500) + *fill* 0x01004f84 0x500 00 + 0x01005484 __STACK_BOTTOM = . + 0x01003000 __CODE_START = ADDR (.text) + 0x01004ddc __CODE_END = (ADDR (.text) + SIZEOF (.text)) + 0x01004f40 __DATA_START = ADDR (.bss) + 0x01004f84 __DATA_END = (ADDR (.bss) + SIZEOF (.bss)) +OUTPUT(boot.or32 elf32-or32) + +.stab 0x00000000 0x15c0 + .stab 0x00000000 0x834 main.o + .stab 0x00000834 0x630 uart.o + .stab 0x00000e64 0x75c sd_controller.o + +.stabstr 0x00000000 0x1577 + .stabstr 0x00000000 0x991 main.o + .stabstr 0x00000991 0x500 uart.o + .stabstr 0x00000e91 0x6e6 sd_controller.o + +.comment 0x00000000 0x36 + .comment 0x00000000 0x12 main.o + .comment 0x00000012 0x12 uart.o + .comment 0x00000024 0x12 sd_controller.o +00000000 t _reset +00000100 T __exception_bus_error +00000200 T __exception_data_page_fault +00000300 T __exception_instruction_page_fault +00000400 T __exception_tick_timer +00000500 T __exception_unaligned_access +00000600 T __exception_illegal_instruction +00000700 T __external_IRQ +00000724 t JUMP +00000740 t save_state +000007b8 t restore_state + +boot.or32: file format elf32-or32 +boot.or32 +architecture: or32, flags 0x00000113: +HAS_RELOC, EXEC_P, HAS_SYMS, D_PAGED +start address 0x01000100 + +Program Header: + LOAD off 0x00000000 vaddr 0x01000000 paddr 0x01000000 align 2**13 + filesz 0x00000a00 memsz 0x00000a00 flags r-x + LOAD off 0x00001000 vaddr 0x01003000 paddr 0x01003000 align 2**13 + filesz 0x00001f3e memsz 0x00002484 flags rwx + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .vectors 00000900 01000100 01000100 00000100 2**8 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 .text 00001ddc 01003000 01003000 00001000 2**2 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 2 .rodata 00000162 01004ddc 01004ddc 00002ddc 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .bss 00000044 01004f40 01004f40 00002f3e 2**4 + ALLOC + 4 .stack 00000500 01004f84 01004f84 00002f3e 2**0 + ALLOC + 5 .stab 000015c0 00000000 00000000 00002f40 2**2 + CONTENTS, RELOC, READONLY, DEBUGGING + 6 .stabstr 00001577 00000000 00000000 00004500 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .comment 00000036 00000000 00000000 00005a77 2**0 + CONTENTS, READONLY +SYMBOL TABLE: +01003000 l d .text 00000000 .text +01004f40 l d .bss 00000000 .bss +01000100 l d .vectors 00000000 .vectors +01000100 l .vectors 00000000 _reset +00003560 l *ABS* 00000000 sp +01000840 l .vectors 00000000 save_state +01000824 l .vectors 00000000 JUMP +010008b8 l .vectors 00000000 restore_state +00000000 l df *ABS* 00000000 main.c +01003000 l d .text 00000000 .text +01004f40 l d .bss 00000000 .bss +01004ddc l d .rodata 00000000 .rodata +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000000 l d .comment 00000000 .comment +00000000 l df *ABS* 00000000 uart.c +01004f40 l d .bss 00000000 .bss +00000000 l df *ABS* 00000000 sd_controller.c +01004f40 l d .bss 00000000 .bss +01004f40 l O .bss 00000004 _rtn_r.1505 +01004f84 l d .stack 00000000 .stack +01004ddc g *ABS* 00000000 __CODE_END +01000400 g .vectors 00000000 __exception_instruction_page_fault +01004770 g F .text 0000066c _sd_controller_init +01000800 g .vectors 00000000 __external_IRQ +0100404c g F .text 00000214 _uart_print_short +01000200 g .vectors 00000000 __exception_bus_error +01004f40 g .bss 00000000 __DATA_START +01004f84 g .stack 00000000 __STACK_TOP +01004304 g F .text 0000017c _sd_get_rca +01005484 g .stack 00000000 __STACK_BOTTOM +01003cac g F .text 00000170 _uart_putc +010031a4 g F .text 00000018 _external_exeption +01003eb0 g F .text 0000019c _uart_print_long +01004f50 g O .bss 00000004 _rx_level +01003aa0 g F .text 0000020c _uart_init +01000300 g .vectors 00000000 __exception_data_page_fault +01000600 g .vectors 00000000 __exception_unaligned_access +01004f60 g O .bss 00000020 _tx_buff +01000700 g .vectors 00000000 __exception_illegal_instruction +01000500 g .vectors 00000000 __exception_tick_timer +010031bc g F .text 000008e4 _Start +01004f84 g *ABS* 00000000 __DATA_END +01004f80 g O .bss 00000004 _tx_level +01003000 g F .text 000001a4 _Write_External_SDRAM_1 +0100457c g F .text 000001f4 _sd_ocr_set +01003000 g .text 00000000 __CODE_START +01003e1c g F .text 00000094 _uart_print_str +01004480 g F .text 000000fc _sd_wait_rsp +01004260 g F .text 000000a4 _uart_getc + + + +Disassembly of section .vectors: + +01000100 <_reset>: + 1000100: 18 00 00 00 l.movhi r0,0x0 + 1000104: a8 00 00 00 l.ori r0,r0,0x0 + 1000108: 18 20 00 00 l.movhi r1,0x0 + 100010c: a8 21 35 60 l.ori r1,r1,0x3560 + 1000110: e0 40 00 04 l.or r2,r0,r0 + 1000114: e0 60 00 04 l.or r3,r0,r0 + 1000118: e0 80 00 04 l.or r4,r0,r0 + 100011c: e0 a0 00 04 l.or r5,r0,r0 + 1000120: e0 c0 00 04 l.or r6,r0,r0 + 1000124: e0 e0 00 04 l.or r7,r0,r0 + 1000128: e1 00 00 04 l.or r8,r0,r0 + 100012c: e1 20 00 04 l.or r9,r0,r0 + 1000130: e1 40 00 04 l.or r10,r0,r0 + 1000134: e1 60 00 04 l.or r11,r0,r0 + 1000138: e1 80 00 04 l.or r12,r0,r0 + 100013c: e1 a0 00 04 l.or r13,r0,r0 + 1000140: e1 c0 00 04 l.or r14,r0,r0 + 1000144: e1 e0 00 04 l.or r15,r0,r0 + 1000148: e2 00 00 04 l.or r16,r0,r0 + 100014c: e2 20 00 04 l.or r17,r0,r0 + 1000150: e2 40 00 04 l.or r18,r0,r0 + 1000154: e2 60 00 04 l.or r19,r0,r0 + 1000158: e2 80 00 04 l.or r20,r0,r0 + 100015c: e2 a0 00 04 l.or r21,r0,r0 + 1000160: e2 c0 00 04 l.or r22,r0,r0 + 1000164: e2 e0 00 04 l.or r23,r0,r0 + 1000168: e3 00 00 04 l.or r24,r0,r0 + 100016c: e3 20 00 04 l.or r25,r0,r0 + 1000170: e3 40 00 04 l.or r26,r0,r0 + 1000174: e3 60 00 04 l.or r27,r0,r0 + 1000178: e3 80 00 04 l.or r28,r0,r0 + 100017c: e3 a0 00 04 l.or r29,r0,r0 + 1000180: e3 c0 00 04 l.or r30,r0,r0 + 1000184: e3 e0 00 04 l.or r31,r0,r0 + 1000188: 18 40 01 00 l.movhi r2,0x100 + 100018c: a8 42 31 bc l.ori r2,r2,0x31bc + 1000190: 44 00 10 00 l.jr r2 + 1000194: 15 00 00 00 l.nop 0x0 + ... + +01000200 <__exception_bus_error>: + 1000200: 00 00 00 00 l.j 1000200 <__exception_bus_error> + 1000204: 15 00 00 00 l.nop 0x0 + ... + +01000300 <__exception_data_page_fault>: + 1000300: 00 00 00 00 l.j 1000300 <__exception_data_page_fault> + 1000304: 15 00 00 00 l.nop 0x0 + ... + +01000400 <__exception_instruction_page_fault>: + 1000400: 00 00 00 00 l.j 1000400 <__exception_instruction_page_fault> + 1000404: 15 00 00 00 l.nop 0x0 + ... + +01000500 <__exception_tick_timer>: + 1000500: 00 00 00 00 l.j 1000500 <__exception_tick_timer> + 1000504: 15 00 00 00 l.nop 0x0 + ... + +01000600 <__exception_unaligned_access>: + 1000600: 00 00 00 00 l.j 1000600 <__exception_unaligned_access> + 1000604: 15 00 00 00 l.nop 0x0 + ... + +01000700 <__exception_illegal_instruction>: + 1000700: 00 00 00 00 l.j 1000700 <__exception_illegal_instruction> + 1000704: 15 00 00 00 l.nop 0x0 + ... + +01000800 <__external_IRQ>: + 1000800: 9c 21 ff 88 l.addi r1,r1,0xffffff88 + 1000804: d4 01 48 1c l.sw 0x1c(r1),r9 + 1000808: 04 00 00 0e l.jal 1000840 + 100080c: 15 00 00 00 l.nop 0x0 + 1000810: b4 60 00 40 l.mfspr r3,r0,0x40 + 1000814: a4 83 00 04 l.andi r4,r3,0x4 + 1000818: bc 04 00 00 l.sfeqi r4,0x0 + 100081c: 0c 00 00 02 l.bnf 1000824 + 1000820: 15 00 00 00 l.nop 0x0 + +01000824 : + 1000824: 04 00 0a 60 l.jal 10031a4 <_external_exeption> + 1000828: 15 00 00 00 l.nop 0x0 + 100082c: 04 00 00 23 l.jal 10008b8 + 1000830: 15 00 00 00 l.nop 0x0 + 1000834: 85 21 00 1c l.lwz r9,0x1c(r1) + 1000838: 9c 21 00 78 l.addi r1,r1,0x78 + 100083c: 24 00 00 00 l.rfe + +01000840 : + 1000840: d4 01 10 00 l.sw 0x0(r1),r2 + 1000844: d4 01 18 04 l.sw 0x4(r1),r3 + 1000848: d4 01 20 08 l.sw 0x8(r1),r4 + 100084c: d4 01 28 0c l.sw 0xc(r1),r5 + 1000850: d4 01 30 10 l.sw 0x10(r1),r6 + 1000854: d4 01 38 14 l.sw 0x14(r1),r7 + 1000858: d4 01 40 18 l.sw 0x18(r1),r8 + 100085c: d4 01 50 20 l.sw 0x20(r1),r10 + 1000860: d4 01 58 24 l.sw 0x24(r1),r11 + 1000864: d4 01 60 28 l.sw 0x28(r1),r12 + 1000868: d4 01 68 2c l.sw 0x2c(r1),r13 + 100086c: d4 01 70 30 l.sw 0x30(r1),r14 + 1000870: d4 01 78 34 l.sw 0x34(r1),r15 + 1000874: d4 01 80 38 l.sw 0x38(r1),r16 + 1000878: d4 01 88 3c l.sw 0x3c(r1),r17 + 100087c: d4 01 90 40 l.sw 0x40(r1),r18 + 1000880: d4 01 98 44 l.sw 0x44(r1),r19 + 1000884: d4 01 a0 48 l.sw 0x48(r1),r20 + 1000888: d4 01 a8 4c l.sw 0x4c(r1),r21 + 100088c: d4 01 b0 50 l.sw 0x50(r1),r22 + 1000890: d4 01 b8 54 l.sw 0x54(r1),r23 + 1000894: d4 01 c0 58 l.sw 0x58(r1),r24 + 1000898: d4 01 c8 5c l.sw 0x5c(r1),r25 + 100089c: d4 01 d0 60 l.sw 0x60(r1),r26 + 10008a0: d4 01 d8 64 l.sw 0x64(r1),r27 + 10008a4: d4 01 e0 68 l.sw 0x68(r1),r28 + 10008a8: d4 01 e8 6c l.sw 0x6c(r1),r29 + 10008ac: d4 01 f0 70 l.sw 0x70(r1),r30 + 10008b0: 44 00 48 00 l.jr r9 + 10008b4: 15 00 00 00 l.nop 0x0 + +010008b8 : + 10008b8: 84 41 00 00 l.lwz r2,0x0(r1) + 10008bc: 84 61 00 04 l.lwz r3,0x4(r1) + 10008c0: 84 81 00 08 l.lwz r4,0x8(r1) + 10008c4: 84 a1 00 0c l.lwz r5,0xc(r1) + 10008c8: 84 c1 00 10 l.lwz r6,0x10(r1) + 10008cc: 84 e1 00 14 l.lwz r7,0x14(r1) + 10008d0: 85 01 00 18 l.lwz r8,0x18(r1) + 10008d4: 85 41 00 20 l.lwz r10,0x20(r1) + 10008d8: 85 61 00 24 l.lwz r11,0x24(r1) + 10008dc: 85 81 00 28 l.lwz r12,0x28(r1) + 10008e0: 85 a1 00 2c l.lwz r13,0x2c(r1) + 10008e4: 85 c1 00 30 l.lwz r14,0x30(r1) + 10008e8: 85 e1 00 34 l.lwz r15,0x34(r1) + 10008ec: 86 01 00 38 l.lwz r16,0x38(r1) + 10008f0: 86 21 00 3c l.lwz r17,0x3c(r1) + 10008f4: 86 41 00 40 l.lwz r18,0x40(r1) + 10008f8: 86 61 00 44 l.lwz r19,0x44(r1) + 10008fc: 86 81 00 48 l.lwz r20,0x48(r1) + 1000900: 86 a1 00 4c l.lwz r21,0x4c(r1) + 1000904: 86 c1 00 50 l.lwz r22,0x50(r1) + 1000908: 86 e1 00 54 l.lwz r23,0x54(r1) + 100090c: 87 01 00 58 l.lwz r24,0x58(r1) + 1000910: 87 21 00 5c l.lwz r25,0x5c(r1) + 1000914: 87 41 00 60 l.lwz r26,0x60(r1) + 1000918: 87 61 00 64 l.lwz r27,0x64(r1) + 100091c: 87 81 00 68 l.lwz r28,0x68(r1) + 1000920: 87 a1 00 6c l.lwz r29,0x6c(r1) + 1000924: 87 c1 00 70 l.lwz r30,0x70(r1) + 1000928: 44 00 48 00 l.jr r9 + 100092c: 15 00 00 00 l.nop 0x0 + ... + +Disassembly of section .text: + +01003000 <_Write_External_SDRAM_1>: +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + 1003000: 9c 21 ff 88 l.addi r1,r1,0xffffff88 + 1003004: d4 01 10 00 l.sw 0x0(r1),r2 + 1003008: 9c 41 00 78 l.addi r2,r1,0x78 + uint32 i; + uint32 read; + uint32 range; + uint32 adr_offset; + + range = 0x7ff; // Max range: 0x7fffff + 100300c: 9c 60 07 ff l.addi r3,r0,0x7ff + 1003010: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3 + 1003014: 84 82 ff d4 l.lwz r4,0xffffffd4(r2) + 1003018: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 + adr_offset = 0x00000000; // External memory offset + 100301c: 9c 60 00 00 l.addi r3,r0,0x0 + 1003020: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 + + for (i=0x0; i < range; i=i+4) { + 1003024: 9c 80 00 00 l.addi r4,r0,0x0 + 1003028: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 + 100302c: 00 00 00 1e l.j 10030a4 <_Write_External_SDRAM_1+0xa4> + 1003030: 15 00 00 00 l.nop 0x0 + REG32(adr_offset + i) = (adr_offset + i); + 1003034: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003038: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 + 100303c: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 1003040: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 + 1003044: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 1003048: 84 82 ff cc l.lwz r4,0xffffffcc(r2) + 100304c: e0 63 20 00 l.add r3,r3,r4 + 1003050: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 1003054: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) + 1003058: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 100305c: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 1003060: d7 e2 27 c8 l.sw 0xffffffc8(r2),r4 + 1003064: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1003068: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 100306c: 84 82 ff c8 l.lwz r4,0xffffffc8(r2) + 1003070: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) + 1003074: e0 84 18 00 l.add r4,r4,r3 + 1003078: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 100307c: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 1003080: 84 82 ff dc l.lwz r4,0xffffffdc(r2) + 1003084: d4 04 18 00 l.sw 0x0(r4),r3 + uint32 adr_offset; + + range = 0x7ff; // Max range: 0x7fffff + adr_offset = 0x00000000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + 1003088: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 100308c: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 1003090: 84 62 ff c0 l.lwz r3,0xffffffc0(r2) + 1003094: 9c 63 00 04 l.addi r3,r3,0x4 + 1003098: d7 e2 1f bc l.sw 0xffffffbc(r2),r3 + 100309c: 84 82 ff bc l.lwz r4,0xffffffbc(r2) + 10030a0: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 + 10030a4: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 10030a8: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 + 10030ac: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 10030b0: d7 e2 27 b4 l.sw 0xffffffb4(r2),r4 + 10030b4: 84 62 ff b8 l.lwz r3,0xffffffb8(r2) + 10030b8: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 10030bc: e4 83 20 00 l.sfltu r3,r4 + 10030c0: 13 ff ff dd l.bf 1003034 <_Write_External_SDRAM_1+0x34> + 10030c4: 15 00 00 00 l.nop 0x0 + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + 10030c8: 9c 60 00 00 l.addi r3,r0,0x0 + 10030cc: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 10030d0: 00 00 00 29 l.j 1003174 <_Write_External_SDRAM_1+0x174> + 10030d4: 15 00 00 00 l.nop 0x0 + read = REG32(adr_offset + i); + 10030d8: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 10030dc: d7 e2 27 b0 l.sw 0xffffffb0(r2),r4 + 10030e0: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 10030e4: d7 e2 1f ac l.sw 0xffffffac(r2),r3 + 10030e8: 84 82 ff b0 l.lwz r4,0xffffffb0(r2) + 10030ec: 84 62 ff ac l.lwz r3,0xffffffac(r2) + 10030f0: e0 84 18 00 l.add r4,r4,r3 + 10030f4: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + 10030f8: 84 82 ff e4 l.lwz r4,0xffffffe4(r2) + 10030fc: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + 1003100: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1003104: 84 63 00 00 l.lwz r3,0x0(r3) + 1003108: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 100310c: 84 82 ff a8 l.lwz r4,0xffffffa8(r2) + 1003110: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + if (read != (adr_offset + i)) { + 1003114: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003118: d7 e2 1f a4 l.sw 0xffffffa4(r2),r3 + 100311c: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 1003120: d7 e2 27 a0 l.sw 0xffffffa0(r2),r4 + 1003124: 84 62 ff a4 l.lwz r3,0xffffffa4(r2) + 1003128: 84 82 ff a0 l.lwz r4,0xffffffa0(r2) + 100312c: e0 63 20 00 l.add r3,r3,r4 + 1003130: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 1003134: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003138: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 + 100313c: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1003140: 84 62 ff 9c l.lwz r3,0xffffff9c(r2) + 1003144: e4 04 18 00 l.sfeq r4,r3 + 1003148: 10 00 00 04 l.bf 1003158 <_Write_External_SDRAM_1+0x158> + 100314c: 15 00 00 00 l.nop 0x0 + while(TRUE){ //ERROR=HALT PROCESSOR + } + 1003150: 00 00 00 00 l.j 1003150 <_Write_External_SDRAM_1+0x150> + 1003154: 15 00 00 00 l.nop 0x0 + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + 1003158: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 100315c: d7 e2 27 98 l.sw 0xffffff98(r2),r4 + 1003160: 84 62 ff 98 l.lwz r3,0xffffff98(r2) + 1003164: 9c 63 00 04 l.addi r3,r3,0x4 + 1003168: d7 e2 1f 94 l.sw 0xffffff94(r2),r3 + 100316c: 84 82 ff 94 l.lwz r4,0xffffff94(r2) + 1003170: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 + 1003174: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1003178: d7 e2 1f 90 l.sw 0xffffff90(r2),r3 + 100317c: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 1003180: d7 e2 27 8c l.sw 0xffffff8c(r2),r4 + 1003184: 84 62 ff 90 l.lwz r3,0xffffff90(r2) + 1003188: 84 82 ff 8c l.lwz r4,0xffffff8c(r2) + 100318c: e4 83 20 00 l.sfltu r3,r4 + 1003190: 13 ff ff d2 l.bf 10030d8 <_Write_External_SDRAM_1+0xd8> + 1003194: 15 00 00 00 l.nop 0x0 + 1003198: 84 41 00 00 l.lwz r2,0x0(r1) + 100319c: 44 00 48 00 l.jr r9 + 10031a0: 9c 21 00 78 l.addi r1,r1,0x78 + +010031a4 <_external_exeption>: +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + + +void external_exeption() +{ + 10031a4: 9c 21 ff fc l.addi r1,r1,0xfffffffc + 10031a8: d4 01 10 00 l.sw 0x0(r1),r2 + 10031ac: 9c 41 00 04 l.addi r2,r1,0x4 + 10031b0: 84 41 00 00 l.lwz r2,0x0(r1) + 10031b4: 44 00 48 00 l.jr r9 + 10031b8: 9c 21 00 04 l.addi r1,r1,0x4 + +010031bc <_Start>: +#define RX +//#define BOTH +//#define DB_BOTH + +void Start() +{ + 10031bc: 9c 21 f2 14 l.addi r1,r1,0xfffff214 + 10031c0: d4 01 10 04 l.sw 0x4(r1),r2 + 10031c4: 9c 41 0d ec l.addi r2,r1,0xdec + 10031c8: d4 01 48 00 l.sw 0x0(r1),r9 + struct sd_card_csr *sd_set_reg = (struct sd_card_csr *) (SD_CONTROLLER_BASE+SD_COMMAND); + 10031cc: 18 60 a0 00 l.movhi r3,0xa000 + 10031d0: d7 c2 1a c8 l.sw 0xfffff2c8(r2),r3 + 10031d4: 84 82 f2 c8 l.lwz r4,0xfffff2c8(r2) + 10031d8: a8 84 00 04 l.ori r4,r4,0x4 + 10031dc: d7 c2 22 cc l.sw 0xfffff2cc(r2),r4 + 10031e0: 84 62 f2 cc l.lwz r3,0xfffff2cc(r2) + 10031e4: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + + volatile unsigned long rtn_reg=0; + 10031e8: 9c 80 00 00 l.addi r4,r0,0x0 + 10031ec: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + volatile unsigned long rtn_reg1=0; + 10031f0: 9c 60 00 00 l.addi r3,r0,0x0 + 10031f4: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + unsigned char rec_block[512]; + unsigned char rec_blocka[512]; + unsigned char rec_blockb[512]; + + #ifdef RX + for (i =0; i<512;i++) + 10031f8: 9c 80 00 00 l.addi r4,r0,0x0 + 10031fc: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + 1003200: 00 00 00 18 l.j 1003260 <_Start+0xa4> + 1003204: 15 00 00 00 l.nop 0x0 + block[i]=0; + 1003208: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 100320c: d7 c2 1a d0 l.sw 0xfffff2d0(r2),r3 + 1003210: 9c 82 fd e8 l.addi r4,r2,0xfffffde8 + 1003214: d7 c2 22 c4 l.sw 0xfffff2c4(r2),r4 + 1003218: 84 62 f2 c4 l.lwz r3,0xfffff2c4(r2) + 100321c: 84 82 f2 d0 l.lwz r4,0xfffff2d0(r2) + 1003220: e0 63 20 00 l.add r3,r3,r4 + 1003224: d7 c2 1a c0 l.sw 0xfffff2c0(r2),r3 + 1003228: 9c 60 00 00 l.addi r3,r0,0x0 + 100322c: d7 c2 1a bc l.sw 0xfffff2bc(r2),r3 + 1003230: 84 82 f2 bc l.lwz r4,0xfffff2bc(r2) + 1003234: db c2 22 bb l.sb 0xfffff2bb(r2),r4 + 1003238: 8c 82 f2 bb l.lbz r4,0xfffff2bb(r2) + 100323c: 84 62 f2 c0 l.lwz r3,0xfffff2c0(r2) + 1003240: d8 03 20 00 l.sb 0x0(r3),r4 + unsigned char rec_block[512]; + unsigned char rec_blocka[512]; + unsigned char rec_blockb[512]; + + #ifdef RX + for (i =0; i<512;i++) + 1003244: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003248: d7 c2 1a b4 l.sw 0xfffff2b4(r2),r3 + 100324c: 84 82 f2 b4 l.lwz r4,0xfffff2b4(r2) + 1003250: 9c 84 00 01 l.addi r4,r4,0x1 + 1003254: d7 c2 22 b0 l.sw 0xfffff2b0(r2),r4 + 1003258: 84 62 f2 b0 l.lwz r3,0xfffff2b0(r2) + 100325c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + 1003260: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1003264: d7 c2 22 ac l.sw 0xfffff2ac(r2),r4 + 1003268: 84 62 f2 ac l.lwz r3,0xfffff2ac(r2) + 100326c: bd a3 01 ff l.sflesi r3,0x1ff + 1003270: 13 ff ff e6 l.bf 1003208 <_Start+0x4c> + 1003274: 15 00 00 00 l.nop 0x0 + blockb[i]=0xad; + + #endif + + + unsigned long b=0x0001; + 1003278: 9c 80 00 01 l.addi r4,r0,0x1 + 100327c: d7 c2 22 a8 l.sw 0xfffff2a8(r2),r4 + 1003280: 84 62 f2 a8 l.lwz r3,0xfffff2a8(r2) + 1003284: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + sd_card sd_card_0; + + + uart_init(); + 1003288: 04 00 02 06 l.jal 1003aa0 <_uart_init> + 100328c: 15 00 00 00 l.nop 0x0 + sd_card_0 = sd_controller_init(); + 1003290: 9c 82 f3 d4 l.addi r4,r2,0xfffff3d4 + 1003294: d7 c2 22 a4 l.sw 0xfffff2a4(r2),r4 + 1003298: 84 62 f2 a4 l.lwz r3,0xfffff2a4(r2) + 100329c: 04 00 05 35 l.jal 1004770 <_sd_controller_init> + 10032a0: 15 00 00 00 l.nop 0x0 + // Send out something over UART + + + if (sd_card_0.Active==1) + 10032a4: 8c 62 f3 dd l.lbz r3,0xfffff3dd(r2) + 10032a8: d7 c2 1a d4 l.sw 0xfffff2d4(r2),r3 + 10032ac: 84 82 f2 d4 l.lwz r4,0xfffff2d4(r2) + 10032b0: bc 24 00 01 l.sfnei r4,0x1 + 10032b4: 10 00 00 34 l.bf 1003384 <_Start+0x1c8> + 10032b8: 15 00 00 00 l.nop 0x0 + { + uart_print_str("Init 2 succes!\n"); + 10032bc: 18 60 01 00 l.movhi r3,0x100 + 10032c0: a8 63 4d dc l.ori r3,r3,0x4ddc + 10032c4: 04 00 02 d6 l.jal 1003e1c <_uart_print_str> + 10032c8: 15 00 00 00 l.nop 0x0 + uart_print_str("\nvoltage_windows:\n"); + 10032cc: 18 60 01 00 l.movhi r3,0x100 + 10032d0: a8 63 4d ec l.ori r3,r3,0x4dec + 10032d4: 04 00 02 d2 l.jal 1003e1c <_uart_print_str> + 10032d8: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.Voltage_window); + 10032dc: 84 62 f3 d8 l.lwz r3,0xfffff3d8(r2) + 10032e0: d7 c2 1a d8 l.sw 0xfffff2d8(r2),r3 + 10032e4: 84 62 f2 d8 l.lwz r3,0xfffff2d8(r2) + 10032e8: 04 00 02 f2 l.jal 1003eb0 <_uart_print_long> + 10032ec: 15 00 00 00 l.nop 0x0 + uart_print_str("\nRCA_Nr:\n"); + 10032f0: 18 60 01 00 l.movhi r3,0x100 + 10032f4: a8 63 4d ff l.ori r3,r3,0x4dff + 10032f8: 04 00 02 c9 l.jal 1003e1c <_uart_print_str> + 10032fc: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.rca); + 1003300: 84 82 f3 d4 l.lwz r4,0xfffff3d4(r2) + 1003304: d7 c2 22 dc l.sw 0xfffff2dc(r2),r4 + 1003308: 84 62 f2 dc l.lwz r3,0xfffff2dc(r2) + 100330c: 04 00 02 e9 l.jal 1003eb0 <_uart_print_long> + 1003310: 15 00 00 00 l.nop 0x0 + uart_print_str("\nphys_spec_2_0 Y/N 1/0? :\n"); + 1003314: 18 60 01 00 l.movhi r3,0x100 + 1003318: a8 63 4e 09 l.ori r3,r3,0x4e09 + 100331c: 04 00 02 c0 l.jal 1003e1c <_uart_print_str> + 1003320: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.phys_spec_2_0); + 1003324: 8c 62 f3 de l.lbz r3,0xfffff3de(r2) + 1003328: d7 c2 1a e0 l.sw 0xfffff2e0(r2),r3 + 100332c: 84 82 f2 e0 l.lwz r4,0xfffff2e0(r2) + 1003330: d7 c2 22 e4 l.sw 0xfffff2e4(r2),r4 + 1003334: 84 62 f2 e4 l.lwz r3,0xfffff2e4(r2) + 1003338: 04 00 02 de l.jal 1003eb0 <_uart_print_long> + 100333c: 15 00 00 00 l.nop 0x0 + uart_print_str("\nHCS? :\n"); + 1003340: 18 60 01 00 l.movhi r3,0x100 + 1003344: a8 63 4e 24 l.ori r3,r3,0x4e24 + 1003348: 04 00 02 b5 l.jal 1003e1c <_uart_print_str> + 100334c: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.phys_spec_2_0); + 1003350: 8c 62 f3 de l.lbz r3,0xfffff3de(r2) + 1003354: d7 c2 1a e8 l.sw 0xfffff2e8(r2),r3 + 1003358: 84 82 f2 e8 l.lwz r4,0xfffff2e8(r2) + 100335c: d7 c2 22 ec l.sw 0xfffff2ec(r2),r4 + 1003360: 84 62 f2 ec l.lwz r3,0xfffff2ec(r2) + 1003364: 04 00 02 d3 l.jal 1003eb0 <_uart_print_long> + 1003368: 15 00 00 00 l.nop 0x0 + uart_print_str(":\n"); + 100336c: 18 60 01 00 l.movhi r3,0x100 + 1003370: a8 63 4e 2d l.ori r3,r3,0x4e2d + 1003374: 04 00 02 aa l.jal 1003e1c <_uart_print_str> + 1003378: 15 00 00 00 l.nop 0x0 + 100337c: 00 00 00 06 l.j 1003394 <_Start+0x1d8> + 1003380: 15 00 00 00 l.nop 0x0 + } + else + uart_print_str("Init2 failed :/!\n"); + 1003384: 18 60 01 00 l.movhi r3,0x100 + 1003388: a8 63 4e 30 l.ori r3,r3,0x4e30 + 100338c: 04 00 02 a4 l.jal 1003e1c <_uart_print_str> + 1003390: 15 00 00 00 l.nop 0x0 + + /*SD_REG(SD_SOFTWARE_RST) =1; + SD_REG(SD_SOFTWARE_RST) =0; + sd_card_0 = sd_controller_init(); +*/ + if (sd_card_0.Active==1) + 1003394: 8c 62 f3 dd l.lbz r3,0xfffff3dd(r2) + 1003398: d7 c2 1a f0 l.sw 0xfffff2f0(r2),r3 + 100339c: 84 82 f2 f0 l.lwz r4,0xfffff2f0(r2) + 10033a0: bc 24 00 01 l.sfnei r4,0x1 + 10033a4: 10 00 00 34 l.bf 1003474 <_Start+0x2b8> + 10033a8: 15 00 00 00 l.nop 0x0 + { + uart_print_str("Init 2 succes!\n"); + 10033ac: 18 60 01 00 l.movhi r3,0x100 + 10033b0: a8 63 4d dc l.ori r3,r3,0x4ddc + 10033b4: 04 00 02 9a l.jal 1003e1c <_uart_print_str> + 10033b8: 15 00 00 00 l.nop 0x0 + uart_print_str("\nvoltage_windows:\n"); + 10033bc: 18 60 01 00 l.movhi r3,0x100 + 10033c0: a8 63 4d ec l.ori r3,r3,0x4dec + 10033c4: 04 00 02 96 l.jal 1003e1c <_uart_print_str> + 10033c8: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.Voltage_window); + 10033cc: 84 62 f3 d8 l.lwz r3,0xfffff3d8(r2) + 10033d0: d7 c2 1a f4 l.sw 0xfffff2f4(r2),r3 + 10033d4: 84 62 f2 f4 l.lwz r3,0xfffff2f4(r2) + 10033d8: 04 00 02 b6 l.jal 1003eb0 <_uart_print_long> + 10033dc: 15 00 00 00 l.nop 0x0 + uart_print_str("\nRCA_Nr:\n"); + 10033e0: 18 60 01 00 l.movhi r3,0x100 + 10033e4: a8 63 4d ff l.ori r3,r3,0x4dff + 10033e8: 04 00 02 8d l.jal 1003e1c <_uart_print_str> + 10033ec: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.rca); + 10033f0: 84 82 f3 d4 l.lwz r4,0xfffff3d4(r2) + 10033f4: d7 c2 22 f8 l.sw 0xfffff2f8(r2),r4 + 10033f8: 84 62 f2 f8 l.lwz r3,0xfffff2f8(r2) + 10033fc: 04 00 02 ad l.jal 1003eb0 <_uart_print_long> + 1003400: 15 00 00 00 l.nop 0x0 + uart_print_str("\nphys_spec_2_0 Y/N 1/0? :\n"); + 1003404: 18 60 01 00 l.movhi r3,0x100 + 1003408: a8 63 4e 09 l.ori r3,r3,0x4e09 + 100340c: 04 00 02 84 l.jal 1003e1c <_uart_print_str> + 1003410: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.phys_spec_2_0); + 1003414: 8c 62 f3 de l.lbz r3,0xfffff3de(r2) + 1003418: d7 c2 1a fc l.sw 0xfffff2fc(r2),r3 + 100341c: 84 82 f2 fc l.lwz r4,0xfffff2fc(r2) + 1003420: d7 c2 23 00 l.sw 0xfffff300(r2),r4 + 1003424: 84 62 f3 00 l.lwz r3,0xfffff300(r2) + 1003428: 04 00 02 a2 l.jal 1003eb0 <_uart_print_long> + 100342c: 15 00 00 00 l.nop 0x0 + uart_print_str("\nHCS? :\n"); + 1003430: 18 60 01 00 l.movhi r3,0x100 + 1003434: a8 63 4e 24 l.ori r3,r3,0x4e24 + 1003438: 04 00 02 79 l.jal 1003e1c <_uart_print_str> + 100343c: 15 00 00 00 l.nop 0x0 + uart_print_long(sd_card_0.phys_spec_2_0); + 1003440: 8c 62 f3 de l.lbz r3,0xfffff3de(r2) + 1003444: d7 c2 1b 04 l.sw 0xfffff304(r2),r3 + 1003448: 84 82 f3 04 l.lwz r4,0xfffff304(r2) + 100344c: d7 c2 23 08 l.sw 0xfffff308(r2),r4 + 1003450: 84 62 f3 08 l.lwz r3,0xfffff308(r2) + 1003454: 04 00 02 97 l.jal 1003eb0 <_uart_print_long> + 1003458: 15 00 00 00 l.nop 0x0 + uart_print_str(":\n"); + 100345c: 18 60 01 00 l.movhi r3,0x100 + 1003460: a8 63 4e 2d l.ori r3,r3,0x4e2d + 1003464: 04 00 02 6e l.jal 1003e1c <_uart_print_str> + 1003468: 15 00 00 00 l.nop 0x0 + 100346c: 00 00 00 06 l.j 1003484 <_Start+0x2c8> + 1003470: 15 00 00 00 l.nop 0x0 + } + else + uart_print_str("Init2 failed :/!\n"); + 1003474: 18 60 01 00 l.movhi r3,0x100 + 1003478: a8 63 4e 30 l.ori r3,r3,0x4e30 + 100347c: 04 00 02 68 l.jal 1003e1c <_uart_print_str> + 1003480: 15 00 00 00 l.nop 0x0 + + + SD_REG(SD_COMMAND) = CMD9 |WORD_0| CICE | CRCE | RSP_146; + 1003484: 18 60 a0 00 l.movhi r3,0xa000 + 1003488: d7 c2 1a a0 l.sw 0xfffff2a0(r2),r3 + 100348c: 84 82 f2 a0 l.lwz r4,0xfffff2a0(r2) + 1003490: a8 84 00 04 l.ori r4,r4,0x4 + 1003494: d7 c2 23 0c l.sw 0xfffff30c(r2),r4 + 1003498: 9c 60 09 19 l.addi r3,r0,0x919 + 100349c: d7 c2 1a 9c l.sw 0xfffff29c(r2),r3 + 10034a0: 84 62 f2 9c l.lwz r3,0xfffff29c(r2) + 10034a4: 84 82 f3 0c l.lwz r4,0xfffff30c(r2) + 10034a8: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0; + 10034ac: 18 80 a0 00 l.movhi r4,0xa000 + 10034b0: d7 c2 23 10 l.sw 0xfffff310(r2),r4 + 10034b4: 84 62 f3 d4 l.lwz r3,0xfffff3d4(r2) + 10034b8: d7 c2 1b 14 l.sw 0xfffff314(r2),r3 + 10034bc: 84 82 f3 14 l.lwz r4,0xfffff314(r2) + 10034c0: a8 84 f0 f0 l.ori r4,r4,0xf0f0 + 10034c4: d7 c2 23 18 l.sw 0xfffff318(r2),r4 + 10034c8: 84 82 f3 18 l.lwz r4,0xfffff318(r2) + 10034cc: 84 62 f3 10 l.lwz r3,0xfffff310(r2) + 10034d0: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 10034d4: 04 00 03 eb l.jal 1004480 <_sd_wait_rsp> + 10034d8: 15 00 00 00 l.nop 0x0 + 10034dc: d7 c2 5a 98 l.sw 0xfffff298(r2),r11 + 10034e0: 84 62 f2 98 l.lwz r3,0xfffff298(r2) + 10034e4: d7 c2 1b 1c l.sw 0xfffff31c(r2),r3 + 10034e8: 84 82 f3 1c l.lwz r4,0xfffff31c(r2) + 10034ec: bc 24 00 00 l.sfnei r4,0x0 + 10034f0: 10 00 00 08 l.bf 1003510 <_Start+0x354> + 10034f4: 15 00 00 00 l.nop 0x0 + uart_print_str(" send failed :/!\n"); + 10034f8: 18 60 01 00 l.movhi r3,0x100 + 10034fc: a8 63 4e 43 l.ori r3,r3,0x4e43 + 1003500: 04 00 02 47 l.jal 1003e1c <_uart_print_str> + 1003504: 15 00 00 00 l.nop 0x0 + 1003508: 00 00 00 15 l.j 100355c <_Start+0x3a0> + 100350c: 15 00 00 00 l.nop 0x0 + else{ + uart_print_str("CSD 0 \n"); + 1003510: 18 60 01 00 l.movhi r3,0x100 + 1003514: a8 63 4e 55 l.ori r3,r3,0x4e55 + 1003518: 04 00 02 41 l.jal 1003e1c <_uart_print_str> + 100351c: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + 1003520: 18 60 a0 00 l.movhi r3,0xa000 + 1003524: d7 c2 1a 94 l.sw 0xfffff294(r2),r3 + 1003528: 84 82 f2 94 l.lwz r4,0xfffff294(r2) + 100352c: a8 84 00 0c l.ori r4,r4,0xc + 1003530: d7 c2 23 20 l.sw 0xfffff320(r2),r4 + 1003534: 84 62 f3 20 l.lwz r3,0xfffff320(r2) + 1003538: 84 63 00 00 l.lwz r3,0x0(r3) + 100353c: d7 c2 1b 24 l.sw 0xfffff324(r2),r3 + 1003540: 84 62 f3 24 l.lwz r3,0xfffff324(r2) + 1003544: 04 00 02 5b l.jal 1003eb0 <_uart_print_long> + 1003548: 15 00 00 00 l.nop 0x0 + uart_print_str(" \n"); + 100354c: 18 60 01 00 l.movhi r3,0x100 + 1003550: a8 63 4e 5d l.ori r3,r3,0x4e5d + 1003554: 04 00 02 32 l.jal 1003e1c <_uart_print_str> + 1003558: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + uart_print_str(" \n"); + } */ + + + uart_print_str("error? \n"); + 100355c: 18 60 01 00 l.movhi r3,0x100 + 1003560: a8 63 4e 61 l.ori r3,r3,0x4e61 + 1003564: 04 00 02 2e l.jal 1003e1c <_uart_print_str> + 1003568: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG( SD_ERROR_INT_STATUS) ) ; + 100356c: 18 80 a0 00 l.movhi r4,0xa000 + 1003570: d7 c2 22 90 l.sw 0xfffff290(r2),r4 + 1003574: 84 62 f2 90 l.lwz r3,0xfffff290(r2) + 1003578: a8 63 00 34 l.ori r3,r3,0x34 + 100357c: d7 c2 1b 28 l.sw 0xfffff328(r2),r3 + 1003580: 84 82 f3 28 l.lwz r4,0xfffff328(r2) + 1003584: 84 84 00 00 l.lwz r4,0x0(r4) + 1003588: d7 c2 23 2c l.sw 0xfffff32c(r2),r4 + 100358c: 84 62 f3 2c l.lwz r3,0xfffff32c(r2) + 1003590: 04 00 02 48 l.jal 1003eb0 <_uart_print_long> + 1003594: 15 00 00 00 l.nop 0x0 + + + //Put in transfer state, select card + set block size + + + SD_REG(SD_COMMAND) = CMD7 | CICE | CRCE | RSP_48; + 1003598: 18 60 a0 00 l.movhi r3,0xa000 + 100359c: d7 c2 1a 8c l.sw 0xfffff28c(r2),r3 + 10035a0: 84 82 f2 8c l.lwz r4,0xfffff28c(r2) + 10035a4: a8 84 00 04 l.ori r4,r4,0x4 + 10035a8: d7 c2 23 30 l.sw 0xfffff330(r2),r4 + 10035ac: 9c 60 07 1a l.addi r3,r0,0x71a + 10035b0: d7 c2 1a 88 l.sw 0xfffff288(r2),r3 + 10035b4: 84 62 f2 88 l.lwz r3,0xfffff288(r2) + 10035b8: 84 82 f3 30 l.lwz r4,0xfffff330(r2) + 10035bc: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0; + 10035c0: 18 80 a0 00 l.movhi r4,0xa000 + 10035c4: d7 c2 23 34 l.sw 0xfffff334(r2),r4 + 10035c8: 84 62 f3 d4 l.lwz r3,0xfffff3d4(r2) + 10035cc: d7 c2 1b 38 l.sw 0xfffff338(r2),r3 + 10035d0: 84 82 f3 38 l.lwz r4,0xfffff338(r2) + 10035d4: a8 84 f0 f0 l.ori r4,r4,0xf0f0 + 10035d8: d7 c2 23 3c l.sw 0xfffff33c(r2),r4 + 10035dc: 84 82 f3 3c l.lwz r4,0xfffff33c(r2) + 10035e0: 84 62 f3 34 l.lwz r3,0xfffff334(r2) + 10035e4: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 10035e8: 04 00 03 a6 l.jal 1004480 <_sd_wait_rsp> + 10035ec: 15 00 00 00 l.nop 0x0 + 10035f0: d7 c2 5a 84 l.sw 0xfffff284(r2),r11 + 10035f4: 84 62 f2 84 l.lwz r3,0xfffff284(r2) + 10035f8: d7 c2 1b 40 l.sw 0xfffff340(r2),r3 + 10035fc: 84 82 f3 40 l.lwz r4,0xfffff340(r2) + 1003600: bc 24 00 00 l.sfnei r4,0x0 + 1003604: 10 00 00 08 l.bf 1003624 <_Start+0x468> + 1003608: 15 00 00 00 l.nop 0x0 + uart_print_str("Go send failed :/!\n"); + 100360c: 18 60 01 00 l.movhi r3,0x100 + 1003610: a8 63 4e 6b l.ori r3,r3,0x4e6b + 1003614: 04 00 02 02 l.jal 1003e1c <_uart_print_str> + 1003618: 15 00 00 00 l.nop 0x0 + 100361c: 00 00 00 12 l.j 1003664 <_Start+0x4a8> + 1003620: 15 00 00 00 l.nop 0x0 + + else if ( SD_REG(SD_RESP1) == (CARD_STATUS_STB | READY_FOR_DATA ) ) + 1003624: 18 60 a0 00 l.movhi r3,0xa000 + 1003628: d7 c2 1a 80 l.sw 0xfffff280(r2),r3 + 100362c: 84 82 f2 80 l.lwz r4,0xfffff280(r2) + 1003630: a8 84 00 0c l.ori r4,r4,0xc + 1003634: d7 c2 23 44 l.sw 0xfffff344(r2),r4 + 1003638: 84 62 f3 44 l.lwz r3,0xfffff344(r2) + 100363c: 84 63 00 00 l.lwz r3,0x0(r3) + 1003640: d7 c2 1b 48 l.sw 0xfffff348(r2),r3 + 1003644: 84 82 f3 48 l.lwz r4,0xfffff348(r2) + 1003648: bc 24 07 00 l.sfnei r4,0x700 + 100364c: 10 00 00 06 l.bf 1003664 <_Start+0x4a8> + 1003650: 15 00 00 00 l.nop 0x0 + uart_print_str("Ready to transfer data!\n"); + 1003654: 18 60 01 00 l.movhi r3,0x100 + 1003658: a8 63 4e 7f l.ori r3,r3,0x4e7f + 100365c: 04 00 01 f0 l.jal 1003e1c <_uart_print_str> + 1003660: 15 00 00 00 l.nop 0x0 + + + SD_REG(SD_COMMAND) = CMD16 | CICE | CRCE | RSP_48; + 1003664: 18 60 a0 00 l.movhi r3,0xa000 + 1003668: d7 c2 1a 7c l.sw 0xfffff27c(r2),r3 + 100366c: 84 82 f2 7c l.lwz r4,0xfffff27c(r2) + 1003670: a8 84 00 04 l.ori r4,r4,0x4 + 1003674: d7 c2 23 4c l.sw 0xfffff34c(r2),r4 + 1003678: 9c 60 10 1a l.addi r3,r0,0x101a + 100367c: d7 c2 1a 78 l.sw 0xfffff278(r2),r3 + 1003680: 84 62 f2 78 l.lwz r3,0xfffff278(r2) + 1003684: 84 82 f3 4c l.lwz r4,0xfffff34c(r2) + 1003688: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG(SD_ARG)=512; + 100368c: 18 80 a0 00 l.movhi r4,0xa000 + 1003690: d7 c2 23 50 l.sw 0xfffff350(r2),r4 + 1003694: 9c 60 02 00 l.addi r3,r0,0x200 + 1003698: d7 c2 1a 74 l.sw 0xfffff274(r2),r3 + 100369c: 84 62 f2 74 l.lwz r3,0xfffff274(r2) + 10036a0: 84 82 f3 50 l.lwz r4,0xfffff350(r2) + 10036a4: d4 04 18 00 l.sw 0x0(r4),r3 + if (!sd_wait_rsp()) + 10036a8: 04 00 03 76 l.jal 1004480 <_sd_wait_rsp> + 10036ac: 15 00 00 00 l.nop 0x0 + 10036b0: d7 c2 5a 70 l.sw 0xfffff270(r2),r11 + 10036b4: 84 82 f2 70 l.lwz r4,0xfffff270(r2) + 10036b8: d7 c2 23 54 l.sw 0xfffff354(r2),r4 + 10036bc: 84 62 f3 54 l.lwz r3,0xfffff354(r2) + 10036c0: bc 23 00 00 l.sfnei r3,0x0 + 10036c4: 10 00 00 06 l.bf 10036dc <_Start+0x520> + 10036c8: 15 00 00 00 l.nop 0x0 + uart_print_str("Go send failed :/!\n"); + 10036cc: 18 60 01 00 l.movhi r3,0x100 + 10036d0: a8 63 4e 6b l.ori r3,r3,0x4e6b + 10036d4: 04 00 01 d2 l.jal 1003e1c <_uart_print_str> + 10036d8: 15 00 00 00 l.nop 0x0 + + uart_print_str("Card Status reg CMD16: \n"); + 10036dc: 18 60 01 00 l.movhi r3,0x100 + 10036e0: a8 63 4e 98 l.ori r3,r3,0x4e98 + 10036e4: 04 00 01 ce l.jal 1003e1c <_uart_print_str> + 10036e8: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + 10036ec: 18 80 a0 00 l.movhi r4,0xa000 + 10036f0: d7 c2 22 6c l.sw 0xfffff26c(r2),r4 + 10036f4: 84 62 f2 6c l.lwz r3,0xfffff26c(r2) + 10036f8: a8 63 00 0c l.ori r3,r3,0xc + 10036fc: d7 c2 1b 58 l.sw 0xfffff358(r2),r3 + 1003700: 84 82 f3 58 l.lwz r4,0xfffff358(r2) + 1003704: 84 84 00 00 l.lwz r4,0x0(r4) + 1003708: d7 c2 23 5c l.sw 0xfffff35c(r2),r4 + 100370c: 84 62 f3 5c l.lwz r3,0xfffff35c(r2) + 1003710: 04 00 01 e8 l.jal 1003eb0 <_uart_print_long> + 1003714: 15 00 00 00 l.nop 0x0 + //Set Bus width to 4, CMD55 followed by ACMD 6 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48; + 1003718: 18 60 a0 00 l.movhi r3,0xa000 + 100371c: d7 c2 1a 68 l.sw 0xfffff268(r2),r3 + 1003720: 84 82 f2 68 l.lwz r4,0xfffff268(r2) + 1003724: a8 84 00 04 l.ori r4,r4,0x4 + 1003728: d7 c2 23 60 l.sw 0xfffff360(r2),r4 + 100372c: 9c 60 37 02 l.addi r3,r0,0x3702 + 1003730: d7 c2 1a 64 l.sw 0xfffff264(r2),r3 + 1003734: 84 62 f2 64 l.lwz r3,0xfffff264(r2) + 1003738: 84 82 f3 60 l.lwz r4,0xfffff360(r2) + 100373c: d4 04 18 00 l.sw 0x0(r4),r3 + REG32(SD_CONTROLLER_BASE+SD_ARG) =sd_card_0.rca | 0xf0f0; + 1003740: 18 80 a0 00 l.movhi r4,0xa000 + 1003744: d7 c2 23 64 l.sw 0xfffff364(r2),r4 + 1003748: 84 62 f3 d4 l.lwz r3,0xfffff3d4(r2) + 100374c: d7 c2 1b 68 l.sw 0xfffff368(r2),r3 + 1003750: 84 82 f3 68 l.lwz r4,0xfffff368(r2) + 1003754: a8 84 f0 f0 l.ori r4,r4,0xf0f0 + 1003758: d7 c2 23 6c l.sw 0xfffff36c(r2),r4 + 100375c: 84 82 f3 6c l.lwz r4,0xfffff36c(r2) + 1003760: 84 62 f3 64 l.lwz r3,0xfffff364(r2) + 1003764: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 1003768: 04 00 03 46 l.jal 1004480 <_sd_wait_rsp> + 100376c: 15 00 00 00 l.nop 0x0 + 1003770: d7 c2 5a 60 l.sw 0xfffff260(r2),r11 + 1003774: 84 62 f2 60 l.lwz r3,0xfffff260(r2) + 1003778: d7 c2 1b 70 l.sw 0xfffff370(r2),r3 + 100377c: 84 82 f3 70 l.lwz r4,0xfffff370(r2) + 1003780: bc 24 00 00 l.sfnei r4,0x0 + 1003784: 10 00 00 06 l.bf 100379c <_Start+0x5e0> + 1003788: 15 00 00 00 l.nop 0x0 + uart_print_str("CMD55 send failed :/!\n"); + 100378c: 18 60 01 00 l.movhi r3,0x100 + 1003790: a8 63 4e b1 l.ori r3,r3,0x4eb1 + 1003794: 04 00 01 a2 l.jal 1003e1c <_uart_print_str> + 1003798: 15 00 00 00 l.nop 0x0 + + uart_print_str("Card Status reg CMD55: \n"); + 100379c: 18 60 01 00 l.movhi r3,0x100 + 10037a0: a8 63 4e c8 l.ori r3,r3,0x4ec8 + 10037a4: 04 00 01 9e l.jal 1003e1c <_uart_print_str> + 10037a8: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + 10037ac: 18 60 a0 00 l.movhi r3,0xa000 + 10037b0: d7 c2 1a 5c l.sw 0xfffff25c(r2),r3 + 10037b4: 84 82 f2 5c l.lwz r4,0xfffff25c(r2) + 10037b8: a8 84 00 0c l.ori r4,r4,0xc + 10037bc: d7 c2 23 74 l.sw 0xfffff374(r2),r4 + 10037c0: 84 62 f3 74 l.lwz r3,0xfffff374(r2) + 10037c4: 84 63 00 00 l.lwz r3,0x0(r3) + 10037c8: d7 c2 1b 78 l.sw 0xfffff378(r2),r3 + 10037cc: 84 62 f3 78 l.lwz r3,0xfffff378(r2) + 10037d0: 04 00 01 b8 l.jal 1003eb0 <_uart_print_long> + 10037d4: 15 00 00 00 l.nop 0x0 + + SD_REG(SD_COMMAND) = ACMD6 | CICE | CRCE | RSP_48; + 10037d8: 18 80 a0 00 l.movhi r4,0xa000 + 10037dc: d7 c2 22 58 l.sw 0xfffff258(r2),r4 + 10037e0: 84 62 f2 58 l.lwz r3,0xfffff258(r2) + 10037e4: a8 63 00 04 l.ori r3,r3,0x4 + 10037e8: d7 c2 1b 7c l.sw 0xfffff37c(r2),r3 + 10037ec: 9c 80 06 1a l.addi r4,r0,0x61a + 10037f0: d7 c2 22 54 l.sw 0xfffff254(r2),r4 + 10037f4: 84 82 f2 54 l.lwz r4,0xfffff254(r2) + 10037f8: 84 62 f3 7c l.lwz r3,0xfffff37c(r2) + 10037fc: d4 03 20 00 l.sw 0x0(r3),r4 + SD_REG(SD_ARG)=0x2; + 1003800: 18 60 a0 00 l.movhi r3,0xa000 + 1003804: d7 c2 1b 80 l.sw 0xfffff380(r2),r3 + 1003808: 9c 80 00 02 l.addi r4,r0,0x2 + 100380c: d7 c2 22 50 l.sw 0xfffff250(r2),r4 + 1003810: 84 82 f2 50 l.lwz r4,0xfffff250(r2) + 1003814: 84 62 f3 80 l.lwz r3,0xfffff380(r2) + 1003818: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 100381c: 04 00 03 19 l.jal 1004480 <_sd_wait_rsp> + 1003820: 15 00 00 00 l.nop 0x0 + 1003824: d7 c2 5a 4c l.sw 0xfffff24c(r2),r11 + 1003828: 84 62 f2 4c l.lwz r3,0xfffff24c(r2) + 100382c: d7 c2 1b 84 l.sw 0xfffff384(r2),r3 + 1003830: 84 82 f3 84 l.lwz r4,0xfffff384(r2) + 1003834: bc 24 00 00 l.sfnei r4,0x0 + 1003838: 10 00 00 06 l.bf 1003850 <_Start+0x694> + 100383c: 15 00 00 00 l.nop 0x0 + uart_print_str("ACMD6 send failed :/!\n"); + 1003840: 18 60 01 00 l.movhi r3,0x100 + 1003844: a8 63 4e e1 l.ori r3,r3,0x4ee1 + 1003848: 04 00 01 75 l.jal 1003e1c <_uart_print_str> + 100384c: 15 00 00 00 l.nop 0x0 + + uart_print_str("Card Status reg ACMD6: \n"); + 1003850: 18 60 01 00 l.movhi r3,0x100 + 1003854: a8 63 4e f8 l.ori r3,r3,0x4ef8 + 1003858: 04 00 01 71 l.jal 1003e1c <_uart_print_str> + 100385c: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + 1003860: 18 60 a0 00 l.movhi r3,0xa000 + 1003864: d7 c2 1a 48 l.sw 0xfffff248(r2),r3 + 1003868: 84 82 f2 48 l.lwz r4,0xfffff248(r2) + 100386c: a8 84 00 0c l.ori r4,r4,0xc + 1003870: d7 c2 23 88 l.sw 0xfffff388(r2),r4 + 1003874: 84 62 f3 88 l.lwz r3,0xfffff388(r2) + 1003878: 84 63 00 00 l.lwz r3,0x0(r3) + 100387c: d7 c2 1b 8c l.sw 0xfffff38c(r2),r3 + 1003880: 84 62 f3 8c l.lwz r3,0xfffff38c(r2) + 1003884: 04 00 01 8b l.jal 1003eb0 <_uart_print_long> + 1003888: 15 00 00 00 l.nop 0x0 + uart_print_str("\n"); + 100388c: 18 60 01 00 l.movhi r3,0x100 + 1003890: a8 63 4f 11 l.ori r3,r3,0x4f11 + 1003894: 04 00 01 62 l.jal 1003e1c <_uart_print_str> + 1003898: 15 00 00 00 l.nop 0x0 + + int cnt=0; + 100389c: 9c 80 00 00 l.addi r4,r0,0x0 + 10038a0: d7 e2 27 fc l.sw 0xfffffffc(r2),r4 + #endif + + #ifdef RX + + + SD_REG(BD_RX) = &blockb; + 10038a4: 18 60 a0 00 l.movhi r3,0xa000 + 10038a8: d7 c2 1a 44 l.sw 0xfffff244(r2),r3 + 10038ac: 84 82 f2 44 l.lwz r4,0xfffff244(r2) + 10038b0: a8 84 00 60 l.ori r4,r4,0x60 + 10038b4: d7 c2 23 90 l.sw 0xfffff390(r2),r4 + 10038b8: 9c 62 f9 e8 l.addi r3,r2,0xfffff9e8 + 10038bc: d7 c2 1b 94 l.sw 0xfffff394(r2),r3 + 10038c0: 84 82 f3 94 l.lwz r4,0xfffff394(r2) + 10038c4: d7 c2 23 98 l.sw 0xfffff398(r2),r4 + 10038c8: 84 82 f3 98 l.lwz r4,0xfffff398(r2) + 10038cc: 84 62 f3 90 l.lwz r3,0xfffff390(r2) + 10038d0: d4 03 20 00 l.sw 0x0(r3),r4 + SD_REG(BD_RX) =0; + 10038d4: 18 60 a0 00 l.movhi r3,0xa000 + 10038d8: d7 c2 1a 40 l.sw 0xfffff240(r2),r3 + 10038dc: 84 82 f2 40 l.lwz r4,0xfffff240(r2) + 10038e0: a8 84 00 60 l.ori r4,r4,0x60 + 10038e4: d7 c2 23 9c l.sw 0xfffff39c(r2),r4 + 10038e8: 9c 80 00 00 l.addi r4,r0,0x0 + 10038ec: 84 62 f3 9c l.lwz r3,0xfffff39c(r2) + 10038f0: d4 03 20 00 l.sw 0x0(r3),r4 + while ( ((rtn_reg ) !=0x20 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + + } */ + + while ( ((rtn_reg &1) !=1 ) ){ + 10038f4: 00 00 00 0c l.j 1003924 <_Start+0x768> + 10038f8: 15 00 00 00 l.nop 0x0 + rtn_reg= SD_REG(BD_ISR) ; + 10038fc: 18 60 a0 00 l.movhi r3,0xa000 + 1003900: d7 c2 1a 3c l.sw 0xfffff23c(r2),r3 + 1003904: 84 82 f2 3c l.lwz r4,0xfffff23c(r2) + 1003908: a8 84 00 54 l.ori r4,r4,0x54 + 100390c: d7 c2 23 a0 l.sw 0xfffff3a0(r2),r4 + 1003910: 84 62 f3 a0 l.lwz r3,0xfffff3a0(r2) + 1003914: 84 63 00 00 l.lwz r3,0x0(r3) + 1003918: d7 c2 1b a4 l.sw 0xfffff3a4(r2),r3 + 100391c: 84 82 f3 a4 l.lwz r4,0xfffff3a4(r2) + 1003920: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + while ( ((rtn_reg ) !=0x20 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + + } */ + + while ( ((rtn_reg &1) !=1 ) ){ + 1003924: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1003928: d7 c2 1b a8 l.sw 0xfffff3a8(r2),r3 + 100392c: 84 82 f3 a8 l.lwz r4,0xfffff3a8(r2) + 1003930: a4 84 00 01 l.andi r4,r4,0x1 + 1003934: d7 c2 23 ac l.sw 0xfffff3ac(r2),r4 + 1003938: 84 62 f3 ac l.lwz r3,0xfffff3ac(r2) + 100393c: bc 03 00 00 l.sfeqi r3,0x0 + 1003940: 13 ff ff ef l.bf 10038fc <_Start+0x740> + 1003944: 15 00 00 00 l.nop 0x0 + rtn_reg= SD_REG(BD_ISR) ; + } + + uart_print_long( SD_REG(BD_ISR) ) ; + 1003948: 18 80 a0 00 l.movhi r4,0xa000 + 100394c: d7 c2 22 38 l.sw 0xfffff238(r2),r4 + 1003950: 84 62 f2 38 l.lwz r3,0xfffff238(r2) + 1003954: a8 63 00 54 l.ori r3,r3,0x54 + 1003958: d7 c2 1b b0 l.sw 0xfffff3b0(r2),r3 + 100395c: 84 82 f3 b0 l.lwz r4,0xfffff3b0(r2) + 1003960: 84 84 00 00 l.lwz r4,0x0(r4) + 1003964: d7 c2 23 b4 l.sw 0xfffff3b4(r2),r4 + 1003968: 84 62 f3 b4 l.lwz r3,0xfffff3b4(r2) + 100396c: 04 00 01 51 l.jal 1003eb0 <_uart_print_long> + 1003970: 15 00 00 00 l.nop 0x0 + uart_print_str("Card Status reg: \n"); + 1003974: 18 60 01 00 l.movhi r3,0x100 + 1003978: a8 63 4f 13 l.ori r3,r3,0x4f13 + 100397c: 04 00 01 28 l.jal 1003e1c <_uart_print_str> + 1003980: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + 1003984: 18 60 a0 00 l.movhi r3,0xa000 + 1003988: d7 c2 1a 34 l.sw 0xfffff234(r2),r3 + 100398c: 84 82 f2 34 l.lwz r4,0xfffff234(r2) + 1003990: a8 84 00 0c l.ori r4,r4,0xc + 1003994: d7 c2 23 b8 l.sw 0xfffff3b8(r2),r4 + 1003998: 84 62 f3 b8 l.lwz r3,0xfffff3b8(r2) + 100399c: 84 63 00 00 l.lwz r3,0x0(r3) + 10039a0: d7 c2 1b bc l.sw 0xfffff3bc(r2),r3 + 10039a4: 84 62 f3 bc l.lwz r3,0xfffff3bc(r2) + 10039a8: 04 00 01 42 l.jal 1003eb0 <_uart_print_long> + 10039ac: 15 00 00 00 l.nop 0x0 + uart_print_str("\n"); + 10039b0: 18 60 01 00 l.movhi r3,0x100 + 10039b4: a8 63 4f 11 l.ori r3,r3,0x4f11 + 10039b8: 04 00 01 19 l.jal 1003e1c <_uart_print_str> + 10039bc: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(BD_ISR) ) ; + 10039c0: 18 80 a0 00 l.movhi r4,0xa000 + 10039c4: d7 c2 22 30 l.sw 0xfffff230(r2),r4 + 10039c8: 84 62 f2 30 l.lwz r3,0xfffff230(r2) + 10039cc: a8 63 00 54 l.ori r3,r3,0x54 + 10039d0: d7 c2 1b c0 l.sw 0xfffff3c0(r2),r3 + 10039d4: 84 82 f3 c0 l.lwz r4,0xfffff3c0(r2) + 10039d8: 84 84 00 00 l.lwz r4,0x0(r4) + 10039dc: d7 c2 23 c4 l.sw 0xfffff3c4(r2),r4 + 10039e0: 84 62 f3 c4 l.lwz r3,0xfffff3c4(r2) + 10039e4: 04 00 01 33 l.jal 1003eb0 <_uart_print_long> + 10039e8: 15 00 00 00 l.nop 0x0 + uart_print_str("\n"); + 10039ec: 18 60 01 00 l.movhi r3,0x100 + 10039f0: a8 63 4f 11 l.ori r3,r3,0x4f11 + 10039f4: 04 00 01 0a l.jal 1003e1c <_uart_print_str> + 10039f8: 15 00 00 00 l.nop 0x0 + + for (i =0; i<512;i++) { + 10039fc: 9c 60 00 00 l.addi r3,r0,0x0 + 1003a00: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + 1003a04: 00 00 00 1d l.j 1003a78 <_Start+0x8bc> + 1003a08: 15 00 00 00 l.nop 0x0 + uart_print_short (blockb[i]); + 1003a0c: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1003a10: d7 c2 23 c8 l.sw 0xfffff3c8(r2),r4 + 1003a14: 9c 62 f9 e8 l.addi r3,r2,0xfffff9e8 + 1003a18: d7 c2 1a 2c l.sw 0xfffff22c(r2),r3 + 1003a1c: 84 82 f2 2c l.lwz r4,0xfffff22c(r2) + 1003a20: 84 62 f3 c8 l.lwz r3,0xfffff3c8(r2) + 1003a24: e0 84 18 00 l.add r4,r4,r3 + 1003a28: d7 c2 22 28 l.sw 0xfffff228(r2),r4 + 1003a2c: 84 82 f2 28 l.lwz r4,0xfffff228(r2) + 1003a30: 8c 84 00 00 l.lbz r4,0x0(r4) + 1003a34: d7 c2 23 cc l.sw 0xfffff3cc(r2),r4 + 1003a38: 84 62 f3 cc l.lwz r3,0xfffff3cc(r2) + 1003a3c: d7 c2 1b d0 l.sw 0xfffff3d0(r2),r3 + 1003a40: 84 62 f3 d0 l.lwz r3,0xfffff3d0(r2) + 1003a44: 04 00 01 82 l.jal 100404c <_uart_print_short> + 1003a48: 15 00 00 00 l.nop 0x0 + uart_print_str("."); + 1003a4c: 18 60 01 00 l.movhi r3,0x100 + 1003a50: a8 63 4f 26 l.ori r3,r3,0x4f26 + 1003a54: 04 00 00 f2 l.jal 1003e1c <_uart_print_str> + 1003a58: 15 00 00 00 l.nop 0x0 + uart_print_long( SD_REG(SD_RESP1) ) ; + uart_print_str("\n"); + uart_print_long( SD_REG(BD_ISR) ) ; + uart_print_str("\n"); + + for (i =0; i<512;i++) { + 1003a5c: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1003a60: d7 c2 22 24 l.sw 0xfffff224(r2),r4 + 1003a64: 84 62 f2 24 l.lwz r3,0xfffff224(r2) + 1003a68: 9c 63 00 01 l.addi r3,r3,0x1 + 1003a6c: d7 c2 1a 20 l.sw 0xfffff220(r2),r3 + 1003a70: 84 82 f2 20 l.lwz r4,0xfffff220(r2) + 1003a74: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + 1003a78: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003a7c: d7 c2 1a 1c l.sw 0xfffff21c(r2),r3 + 1003a80: 84 82 f2 1c l.lwz r4,0xfffff21c(r2) + 1003a84: bd a4 01 ff l.sflesi r4,0x1ff + 1003a88: 13 ff ff e1 l.bf 1003a0c <_Start+0x850> + 1003a8c: 15 00 00 00 l.nop 0x0 + 1003a90: 85 21 00 00 l.lwz r9,0x0(r1) + 1003a94: 84 41 00 04 l.lwz r2,0x4(r1) + 1003a98: 44 00 48 00 l.jr r9 + 1003a9c: 9c 21 0d ec l.addi r1,r1,0xdec + +01003aa0 <_uart_init>: + + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ + 1003aa0: 9c 21 ff 54 l.addi r1,r1,0xffffff54 + 1003aa4: d4 01 10 00 l.sw 0x0(r1),r2 + 1003aa8: 9c 41 00 ac l.addi r2,r1,0xac +/* */ +/******************************************************************************/ + + + 1003aac: 18 60 90 00 l.movhi r3,0x9000 + 1003ab0: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 + 1003ab4: 84 82 ff b8 l.lwz r4,0xffffffb8(r2) + 1003ab8: a8 84 00 02 l.ori r4,r4,0x2 + 1003abc: d7 e2 27 bc l.sw 0xffffffbc(r2),r4 + 1003ac0: 9c 60 ff c7 l.addi r3,r0,0xffffffc7 + 1003ac4: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 1003ac8: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 1003acc: db e2 27 b3 l.sb 0xffffffb3(r2),r4 + 1003ad0: 8c 82 ff b3 l.lbz r4,0xffffffb3(r2) + 1003ad4: 84 62 ff bc l.lwz r3,0xffffffbc(r2) + 1003ad8: d8 03 20 00 l.sb 0x0(r3),r4 +/******************************************************************************/ +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + 1003adc: 18 60 90 00 l.movhi r3,0x9000 + 1003ae0: d7 e2 1f ac l.sw 0xffffffac(r2),r3 + 1003ae4: 84 82 ff ac l.lwz r4,0xffffffac(r2) + 1003ae8: a8 84 00 01 l.ori r4,r4,0x1 + 1003aec: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 1003af0: 9c 60 00 00 l.addi r3,r0,0x0 + 1003af4: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 1003af8: 84 82 ff a8 l.lwz r4,0xffffffa8(r2) + 1003afc: db e2 27 a7 l.sb 0xffffffa7(r2),r4 + 1003b00: 8c 82 ff a7 l.lbz r4,0xffffffa7(r2) + 1003b04: 84 62 ff c0 l.lwz r3,0xffffffc0(r2) + 1003b08: d8 03 20 00 l.sb 0x0(r3),r4 + +// Write to External SDRAM +void Write_External_SDRAM_1(void) + 1003b0c: 18 60 90 00 l.movhi r3,0x9000 + 1003b10: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3 + 1003b14: 84 82 ff a0 l.lwz r4,0xffffffa0(r2) + 1003b18: a8 84 00 03 l.ori r4,r4,0x3 + 1003b1c: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 + 1003b20: 9c 60 00 03 l.addi r3,r0,0x3 + 1003b24: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 + 1003b28: 84 82 ff 9c l.lwz r4,0xffffff9c(r2) + 1003b2c: db e2 27 9b l.sb 0xffffff9b(r2),r4 + 1003b30: 8c 82 ff 9b l.lbz r4,0xffffff9b(r2) + 1003b34: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) + 1003b38: d8 03 20 00 l.sb 0x0(r3),r4 +{ + uint32 i; + uint32 read; + 1003b3c: 9c 60 00 0d l.addi r3,r0,0xd + 1003b40: d7 e2 1f 94 l.sw 0xffffff94(r2),r3 + 1003b44: 84 82 ff 94 l.lwz r4,0xffffff94(r2) + 1003b48: d7 e2 27 fc l.sw 0xfffffffc(r2),r4 + uint32 range; + 1003b4c: 18 60 90 00 l.movhi r3,0x9000 + 1003b50: d7 e2 1f 90 l.sw 0xffffff90(r2),r3 + 1003b54: 84 82 ff 90 l.lwz r4,0xffffff90(r2) + 1003b58: a8 84 00 03 l.ori r4,r4,0x3 + 1003b5c: d7 e2 27 c8 l.sw 0xffffffc8(r2),r4 + 1003b60: 18 60 90 00 l.movhi r3,0x9000 + 1003b64: d7 e2 1f 8c l.sw 0xffffff8c(r2),r3 + 1003b68: 84 82 ff 8c l.lwz r4,0xffffff8c(r2) + 1003b6c: a8 84 00 03 l.ori r4,r4,0x3 + 1003b70: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 + 1003b74: 84 62 ff cc l.lwz r3,0xffffffcc(r2) + 1003b78: 8c 63 00 00 l.lbz r3,0x0(r3) + 1003b7c: db e2 1f 8b l.sb 0xffffff8b(r2),r3 + 1003b80: 8c 82 ff 8b l.lbz r4,0xffffff8b(r2) + 1003b84: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1003b88: 9c 80 ff 80 l.addi r4,r0,0xffffff80 + 1003b8c: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 1003b90: e0 83 20 04 l.or r4,r3,r4 + 1003b94: d7 e2 27 84 l.sw 0xffffff84(r2),r4 + 1003b98: 84 62 ff 84 l.lwz r3,0xffffff84(r2) + 1003b9c: a4 63 00 ff l.andi r3,r3,0xff + 1003ba0: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3 + 1003ba4: 84 82 ff d4 l.lwz r4,0xffffffd4(r2) + 1003ba8: db e2 27 83 l.sb 0xffffff83(r2),r4 + 1003bac: 8c 82 ff 83 l.lbz r4,0xffffff83(r2) + 1003bb0: 84 62 ff c8 l.lwz r3,0xffffffc8(r2) + 1003bb4: d8 03 20 00 l.sb 0x0(r3),r4 + uint32 adr_offset; + 1003bb8: 18 60 90 00 l.movhi r3,0x9000 + 1003bbc: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 1003bc0: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 1003bc4: d7 e2 27 7c l.sw 0xffffff7c(r2),r4 + 1003bc8: 84 62 ff 7c l.lwz r3,0xffffff7c(r2) + 1003bcc: a4 63 00 ff l.andi r3,r3,0xff + 1003bd0: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 1003bd4: 84 82 ff dc l.lwz r4,0xffffffdc(r2) + 1003bd8: db e2 27 7b l.sb 0xffffff7b(r2),r4 + 1003bdc: 8c 82 ff 7b l.lbz r4,0xffffff7b(r2) + 1003be0: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) + 1003be4: d8 03 20 00 l.sb 0x0(r3),r4 + + 1003be8: 18 60 90 00 l.movhi r3,0x9000 + 1003bec: d7 e2 1f 74 l.sw 0xffffff74(r2),r3 + 1003bf0: 84 82 ff 74 l.lwz r4,0xffffff74(r2) + 1003bf4: a8 84 00 01 l.ori r4,r4,0x1 + 1003bf8: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 1003bfc: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003c00: d7 e2 1f 70 l.sw 0xffffff70(r2),r3 + 1003c04: 84 82 ff 70 l.lwz r4,0xffffff70(r2) + 1003c08: b8 84 00 88 l.srai r4,r4,0x8 + 1003c0c: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + 1003c10: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1003c14: a4 63 00 ff l.andi r3,r3,0xff + 1003c18: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + 1003c1c: 84 82 ff e8 l.lwz r4,0xffffffe8(r2) + 1003c20: db e2 27 6f l.sb 0xffffff6f(r2),r4 + 1003c24: 8c 82 ff 6f l.lbz r4,0xffffff6f(r2) + 1003c28: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 1003c2c: d8 03 20 00 l.sb 0x0(r3),r4 + range = 0x7ff; // Max range: 0x7fffff + 1003c30: 18 60 90 00 l.movhi r3,0x9000 + 1003c34: d7 e2 1f 68 l.sw 0xffffff68(r2),r3 + 1003c38: 84 82 ff 68 l.lwz r4,0xffffff68(r2) + 1003c3c: a8 84 00 03 l.ori r4,r4,0x3 + 1003c40: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + 1003c44: 18 60 90 00 l.movhi r3,0x9000 + 1003c48: d7 e2 1f 64 l.sw 0xffffff64(r2),r3 + 1003c4c: 84 82 ff 64 l.lwz r4,0xffffff64(r2) + 1003c50: a8 84 00 03 l.ori r4,r4,0x3 + 1003c54: d7 e2 27 f0 l.sw 0xfffffff0(r2),r4 + 1003c58: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1003c5c: 8c 63 00 00 l.lbz r3,0x0(r3) + 1003c60: db e2 1f 63 l.sb 0xffffff63(r2),r3 + 1003c64: 8c 82 ff 63 l.lbz r4,0xffffff63(r2) + 1003c68: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + 1003c6c: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003c70: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + 1003c74: 9c 80 00 7f l.addi r4,r0,0x7f + 1003c78: d7 e2 27 5c l.sw 0xffffff5c(r2),r4 + 1003c7c: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1003c80: 84 82 ff 5c l.lwz r4,0xffffff5c(r2) + 1003c84: e0 63 20 03 l.and r3,r3,r4 + 1003c88: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + 1003c8c: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1003c90: db e2 1f 5b l.sb 0xffffff5b(r2),r3 + 1003c94: 8c 62 ff 5b l.lbz r3,0xffffff5b(r2) + 1003c98: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1003c9c: d8 04 18 00 l.sb 0x0(r4),r3 + 1003ca0: 84 41 00 00 l.lwz r2,0x0(r1) + 1003ca4: 44 00 48 00 l.jr r9 + 1003ca8: 9c 21 00 ac l.addi r1,r1,0xac + +01003cac <_uart_putc>: + adr_offset = 0x00000000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + 1003cac: 9c 21 ff 98 l.addi r1,r1,0xffffff98 + 1003cb0: d4 01 10 00 l.sw 0x0(r1),r2 + 1003cb4: 9c 41 00 68 l.addi r2,r1,0x68 + 1003cb8: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 1003cbc: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) + 1003cc0: db e2 1f c3 l.sb 0xffffffc3(r2),r3 + 1003cc4: 8c 82 ff c3 l.lbz r4,0xffffffc3(r2) + 1003cc8: db e2 27 f8 l.sb 0xfffffff8(r2),r4 + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + if (read != (adr_offset + i)) { + 1003ccc: 18 60 90 00 l.movhi r3,0x9000 + 1003cd0: d7 e2 1f bc l.sw 0xffffffbc(r2),r3 + 1003cd4: 84 82 ff bc l.lwz r4,0xffffffbc(r2) + 1003cd8: a8 84 00 05 l.ori r4,r4,0x5 + 1003cdc: d7 e2 27 c8 l.sw 0xffffffc8(r2),r4 + 1003ce0: 84 62 ff c8 l.lwz r3,0xffffffc8(r2) + 1003ce4: 8c 63 00 00 l.lbz r3,0x0(r3) + 1003ce8: db e2 1f bb l.sb 0xffffffbb(r2),r3 + 1003cec: 8c 82 ff bb l.lbz r4,0xffffffbb(r2) + 1003cf0: db e2 27 ff l.sb 0xffffffff(r2),r4 + 1003cf4: 8c 62 ff ff l.lbz r3,0xffffffff(r2) + 1003cf8: d7 e2 1f cc l.sw 0xffffffcc(r2),r3 + 1003cfc: 84 82 ff cc l.lwz r4,0xffffffcc(r2) + 1003d00: a4 84 00 20 l.andi r4,r4,0x20 + 1003d04: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1003d08: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 1003d0c: bc 03 00 00 l.sfeqi r3,0x0 + 1003d10: 13 ff ff ef l.bf 1003ccc <_uart_putc+0x20> + 1003d14: 15 00 00 00 l.nop 0x0 + while(TRUE){ //ERROR=HALT PROCESSOR + 1003d18: 18 80 90 00 l.movhi r4,0x9000 + 1003d1c: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4 + 1003d20: 8c 62 ff f8 l.lbz r3,0xfffffff8(r2) + 1003d24: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 1003d28: 84 82 ff d8 l.lwz r4,0xffffffd8(r2) + 1003d2c: db e2 27 ba l.sb 0xffffffba(r2),r4 + 1003d30: 8c 82 ff ba l.lbz r4,0xffffffba(r2) + 1003d34: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) + 1003d38: d8 03 20 00 l.sb 0x0(r3),r4 + } + 1003d3c: 90 62 ff f8 l.lbs r3,0xfffffff8(r2) + 1003d40: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 1003d44: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 1003d48: bc 24 00 0a l.sfnei r4,0xa + 1003d4c: 10 00 00 1e l.bf 1003dc4 <_uart_putc+0x118> + 1003d50: 15 00 00 00 l.nop 0x0 + } + 1003d54: 18 60 90 00 l.movhi r3,0x9000 + 1003d58: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 + 1003d5c: 84 82 ff b0 l.lwz r4,0xffffffb0(r2) + 1003d60: a8 84 00 05 l.ori r4,r4,0x5 + 1003d64: d7 e2 27 dc l.sw 0xffffffdc(r2),r4 + 1003d68: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 1003d6c: 8c 63 00 00 l.lbz r3,0x0(r3) + 1003d70: db e2 1f af l.sb 0xffffffaf(r2),r3 + 1003d74: 8c 82 ff af l.lbz r4,0xffffffaf(r2) + 1003d78: db e2 27 ff l.sb 0xffffffff(r2),r4 + 1003d7c: 8c 62 ff ff l.lbz r3,0xffffffff(r2) + 1003d80: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + 1003d84: 84 82 ff e0 l.lwz r4,0xffffffe0(r2) + 1003d88: a4 84 00 20 l.andi r4,r4,0x20 + 1003d8c: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + 1003d90: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1003d94: bc 03 00 00 l.sfeqi r3,0x0 + 1003d98: 13 ff ff ef l.bf 1003d54 <_uart_putc+0xa8> + 1003d9c: 15 00 00 00 l.nop 0x0 + } + 1003da0: 18 80 90 00 l.movhi r4,0x9000 + 1003da4: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + 1003da8: 9c 60 00 0d l.addi r3,r0,0xd + 1003dac: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 1003db0: 84 82 ff a8 l.lwz r4,0xffffffa8(r2) + 1003db4: db e2 27 a7 l.sb 0xffffffa7(r2),r4 + 1003db8: 8c 82 ff a7 l.lbz r4,0xffffffa7(r2) + 1003dbc: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1003dc0: d8 03 20 00 l.sb 0x0(r3),r4 +} + + 1003dc4: 18 60 90 00 l.movhi r3,0x9000 + 1003dc8: d7 e2 1f a0 l.sw 0xffffffa0(r2),r3 + 1003dcc: 84 82 ff a0 l.lwz r4,0xffffffa0(r2) + 1003dd0: a8 84 00 05 l.ori r4,r4,0x5 + 1003dd4: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + 1003dd8: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1003ddc: 8c 63 00 00 l.lbz r3,0x0(r3) + 1003de0: db e2 1f 9f l.sb 0xffffff9f(r2),r3 + 1003de4: 8c 82 ff 9f l.lbz r4,0xffffff9f(r2) + 1003de8: db e2 27 ff l.sb 0xffffffff(r2),r4 + 1003dec: 8c 62 ff ff l.lbz r3,0xffffffff(r2) + 1003df0: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 1003df4: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 1003df8: a4 84 00 60 l.andi r4,r4,0x60 + 1003dfc: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + 1003e00: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003e04: bc 23 00 60 l.sfnei r3,0x60 + 1003e08: 13 ff ff ef l.bf 1003dc4 <_uart_putc+0x118> + 1003e0c: 15 00 00 00 l.nop 0x0 + 1003e10: 84 41 00 00 l.lwz r2,0x0(r1) + 1003e14: 44 00 48 00 l.jr r9 + 1003e18: 9c 21 00 68 l.addi r1,r1,0x68 + +01003e1c <_uart_print_str>: + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ + 1003e1c: 9c 21 ff d8 l.addi r1,r1,0xffffffd8 + 1003e20: d4 01 10 04 l.sw 0x4(r1),r2 + 1003e24: 9c 41 00 28 l.addi r2,r1,0x28 + 1003e28: d4 01 48 00 l.sw 0x0(r1),r9 + 1003e2c: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 +/******************************************************************************/ + 1003e30: 00 00 00 13 l.j 1003e7c <_uart_print_str+0x60> + 1003e34: 15 00 00 00 l.nop 0x0 + + 1003e38: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003e3c: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 1003e40: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1003e44: 90 63 00 00 l.lbs r3,0x0(r3) + 1003e48: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 1003e4c: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1003e50: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + 1003e54: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003e58: 07 ff ff 95 l.jal 1003cac <_uart_putc> + 1003e5c: 15 00 00 00 l.nop 0x0 + + 1003e60: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003e64: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + 1003e68: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1003e6c: 9c 63 00 01 l.addi r3,r3,0x1 + 1003e70: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + 1003e74: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1003e78: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 + + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + 1003e7c: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1003e80: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + 1003e84: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 1003e88: 90 63 00 00 l.lbs r3,0x0(r3) + 1003e8c: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + 1003e90: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1003e94: bc 23 00 00 l.sfnei r3,0x0 + 1003e98: 13 ff ff e8 l.bf 1003e38 <_uart_print_str+0x1c> + 1003e9c: 15 00 00 00 l.nop 0x0 + 1003ea0: 85 21 00 00 l.lwz r9,0x0(r1) + 1003ea4: 84 41 00 04 l.lwz r2,0x4(r1) + 1003ea8: 44 00 48 00 l.jr r9 + 1003eac: 9c 21 00 28 l.addi r1,r1,0x28 + +01003eb0 <_uart_print_long>: +void external_exeption() +{ + REG uint8 i; + REG uint32 PicSr,sr; + +} + 1003eb0: 9c 21 ff 8c l.addi r1,r1,0xffffff8c + 1003eb4: d4 01 10 04 l.sw 0x4(r1),r2 + 1003eb8: 9c 41 00 74 l.addi r2,r1,0x74 + 1003ebc: d4 01 48 00 l.sw 0x0(r1),r9 + 1003ec0: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + +/*$$MAIN*/ +/******************************************************************************/ +/* */ + 1003ec4: 18 60 01 00 l.movhi r3,0x100 + 1003ec8: a8 63 4f 28 l.ori r3,r3,0x4f28 + 1003ecc: 07 ff ff d4 l.jal 1003e1c <_uart_print_str> + 1003ed0: 15 00 00 00 l.nop 0x0 +/* M A I N P R O G R A M */ +/* */ + 1003ed4: 9c 60 00 00 l.addi r3,r0,0x0 + 1003ed8: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + 1003edc: 00 00 00 52 l.j 1004024 <_uart_print_long+0x174> + 1003ee0: 15 00 00 00 l.nop 0x0 +/******************************************************************************/ + 1003ee4: 9c 80 00 07 l.addi r4,r0,0x7 + 1003ee8: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 + 1003eec: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1003ef0: d7 e2 1f c8 l.sw 0xffffffc8(r2),r3 + 1003ef4: 84 82 ff cc l.lwz r4,0xffffffcc(r2) + 1003ef8: 84 62 ff c8 l.lwz r3,0xffffffc8(r2) + 1003efc: e0 84 18 02 l.sub r4,r4,r3 + 1003f00: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1003f04: 84 82 ff d0 l.lwz r4,0xffffffd0(r2) + 1003f08: b8 84 00 02 l.slli r4,r4,0x2 + 1003f0c: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4 + 1003f10: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1003f14: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 1003f18: 84 82 ff c4 l.lwz r4,0xffffffc4(r2) + 1003f1c: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) + 1003f20: e0 84 18 48 l.srl r4,r4,r3 + 1003f24: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4 + 1003f28: 84 82 ff d8 l.lwz r4,0xffffffd8(r2) + 1003f2c: b8 84 00 18 l.slli r4,r4,0x18 + 1003f30: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 1003f34: 84 62 ff c0 l.lwz r3,0xffffffc0(r2) + 1003f38: b8 63 00 98 l.srai r3,r3,0x18 + 1003f3c: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 1003f40: 84 82 ff dc l.lwz r4,0xffffffdc(r2) + 1003f44: a4 84 00 0f l.andi r4,r4,0xf + 1003f48: d7 e2 27 bc l.sw 0xffffffbc(r2),r4 + 1003f4c: 84 62 ff bc l.lwz r3,0xffffffbc(r2) + 1003f50: db e2 1f bb l.sb 0xffffffbb(r2),r3 + 1003f54: 8c 82 ff bb l.lbz r4,0xffffffbb(r2) + 1003f58: db e2 27 ff l.sb 0xffffffff(r2),r4 + + 1003f5c: 90 62 ff ff l.lbs r3,0xffffffff(r2) + 1003f60: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 1003f64: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 1003f68: bd 84 00 00 l.sfltsi r4,0x0 + 1003f6c: 10 00 00 16 l.bf 1003fc4 <_uart_print_long+0x114> + 1003f70: 15 00 00 00 l.nop 0x0 + 1003f74: 90 62 ff ff l.lbs r3,0xffffffff(r2) + 1003f78: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 + 1003f7c: 84 82 ff b0 l.lwz r4,0xffffffb0(r2) + 1003f80: bd 44 00 09 l.sfgtsi r4,0x9 + 1003f84: 10 00 00 10 l.bf 1003fc4 <_uart_print_long+0x114> + 1003f88: 15 00 00 00 l.nop 0x0 +struct sd_card_csr { + 1003f8c: 8c 62 ff ff l.lbz r3,0xffffffff(r2) + 1003f90: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + 1003f94: 84 82 ff e0 l.lwz r4,0xffffffe0(r2) + 1003f98: 9c 84 00 30 l.addi r4,r4,0x30 + 1003f9c: d7 e2 27 ac l.sw 0xffffffac(r2),r4 + 1003fa0: 84 62 ff ac l.lwz r3,0xffffffac(r2) + 1003fa4: a4 63 00 ff l.andi r3,r3,0xff + 1003fa8: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + 1003fac: 84 82 ff e4 l.lwz r4,0xffffffe4(r2) + 1003fb0: db e2 27 ab l.sb 0xffffffab(r2),r4 + 1003fb4: 8c 62 ff ab l.lbz r3,0xffffffab(r2) + 1003fb8: db e2 1f ff l.sb 0xffffffff(r2),r3 +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ + + 1003fbc: 00 00 00 0e l.j 1003ff4 <_uart_print_long+0x144> + 1003fc0: 15 00 00 00 l.nop 0x0 +struct sd_card_csr { +unsigned int PAD:18; +unsigned int CMDI:6; + 1003fc4: 8c 82 ff ff l.lbz r4,0xffffffff(r2) + 1003fc8: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + 1003fcc: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1003fd0: 9c 63 00 57 l.addi r3,r3,0x57 + 1003fd4: d7 e2 1f a4 l.sw 0xffffffa4(r2),r3 + 1003fd8: 84 82 ff a4 l.lwz r4,0xffffffa4(r2) + 1003fdc: a4 84 00 ff l.andi r4,r4,0xff + 1003fe0: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + 1003fe4: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1003fe8: db e2 1f a3 l.sb 0xffffffa3(r2),r3 + 1003fec: 8c 82 ff a3 l.lbz r4,0xffffffa3(r2) + 1003ff0: db e2 27 ff l.sb 0xffffffff(r2),r4 +unsigned int CMDT:2; + 1003ff4: 90 62 ff ff l.lbs r3,0xffffffff(r2) + 1003ff8: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 1003ffc: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004000: 07 ff ff 2b l.jal 1003cac <_uart_putc> + 1004004: 15 00 00 00 l.nop 0x0 + +/*$$MAIN*/ +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ + 1004008: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 100400c: d7 e2 27 9c l.sw 0xffffff9c(r2),r4 + 1004010: 84 62 ff 9c l.lwz r3,0xffffff9c(r2) + 1004014: 9c 63 00 01 l.addi r3,r3,0x1 + 1004018: d7 e2 1f 98 l.sw 0xffffff98(r2),r3 + 100401c: 84 82 ff 98 l.lwz r4,0xffffff98(r2) + 1004020: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 + 1004024: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004028: d7 e2 1f 94 l.sw 0xffffff94(r2),r3 + 100402c: 84 82 ff 94 l.lwz r4,0xffffff94(r2) + 1004030: bd a4 00 07 l.sflesi r4,0x7 + 1004034: 13 ff ff ac l.bf 1003ee4 <_uart_print_long+0x34> + 1004038: 15 00 00 00 l.nop 0x0 + 100403c: 85 21 00 00 l.lwz r9,0x0(r1) + 1004040: 84 41 00 04 l.lwz r2,0x4(r1) + 1004044: 44 00 48 00 l.jr r9 + 1004048: 9c 21 00 74 l.addi r1,r1,0x74 + +0100404c <_uart_print_short>: +unsigned int DPS:1; +unsigned int CICE_s:1; +unsigned int CRCE_s:1; +unsigned int RSVD:1; +unsigned int RTS:2; +} ; + 100404c: 9c 21 ff 70 l.addi r1,r1,0xffffff70 + 1004050: d4 01 10 04 l.sw 0x4(r1),r2 + 1004054: 9c 41 00 90 l.addi r2,r1,0x90 + 1004058: d4 01 48 00 l.sw 0x0(r1),r9 + 100405c: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + + + + 1004060: 9c 60 00 00 l.addi r3,r0,0x0 + 1004064: d7 e2 1f cc l.sw 0xffffffcc(r2),r3 + 1004068: 84 82 ff cc l.lwz r4,0xffffffcc(r2) + 100406c: db e2 27 cb l.sb 0xffffffcb(r2),r4 + 1004070: 8c 62 ff cb l.lbz r3,0xffffffcb(r2) + 1004074: db e2 1f ff l.sb 0xffffffff(r2),r3 + + + 1004078: 18 60 01 00 l.movhi r3,0x100 + 100407c: a8 63 4f 28 l.ori r3,r3,0x4f28 + 1004080: 07 ff ff 67 l.jal 1003e1c <_uart_print_str> + 1004084: 15 00 00 00 l.nop 0x0 +//TO do +// Always check if error in repose (CRC, CICE) etc + 1004088: 9c 80 00 00 l.addi r4,r0,0x0 + 100408c: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 + 1004090: 00 00 00 6a l.j 1004238 <_uart_print_short+0x1ec> + 1004094: 15 00 00 00 l.nop 0x0 +// Always check for CICM (Command inhibit before senindg) + 1004098: 9c 60 00 07 l.addi r3,r0,0x7 + 100409c: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 10040a0: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 10040a4: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 10040a8: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) + 10040ac: 84 82 ff c0 l.lwz r4,0xffffffc0(r2) + 10040b0: e0 63 20 02 l.sub r3,r3,r4 + 10040b4: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 + 10040b8: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 10040bc: b8 63 00 02 l.slli r3,r3,0x2 + 10040c0: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3 + 10040c4: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 10040c8: d7 e2 27 bc l.sw 0xffffffbc(r2),r4 + 10040cc: 84 62 ff bc l.lwz r3,0xffffffbc(r2) + 10040d0: 84 82 ff d4 l.lwz r4,0xffffffd4(r2) + 10040d4: e0 63 20 48 l.srl r3,r3,r4 + 10040d8: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 10040dc: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) + 10040e0: b8 63 00 18 l.slli r3,r3,0x18 + 10040e4: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 + 10040e8: 84 82 ff b8 l.lwz r4,0xffffffb8(r2) + 10040ec: b8 84 00 98 l.srai r4,r4,0x18 + 10040f0: d7 e2 27 dc l.sw 0xffffffdc(r2),r4 + 10040f4: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 10040f8: a4 63 00 0f l.andi r3,r3,0xf + 10040fc: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 1004100: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 1004104: db e2 27 b3 l.sb 0xffffffb3(r2),r4 + 1004108: 8c 62 ff b3 l.lbz r3,0xffffffb3(r2) + 100410c: db e2 1f fe l.sb 0xfffffffe(r2),r3 +// Timeout when polling +// Divied into dividing Functions + 1004110: 90 82 ff fe l.lbs r4,0xfffffffe(r2) + 1004114: d7 e2 27 ac l.sw 0xffffffac(r2),r4 + 1004118: 84 62 ff ac l.lwz r3,0xffffffac(r2) + 100411c: bd 83 00 00 l.sfltsi r3,0x0 + 1004120: 10 00 00 16 l.bf 1004178 <_uart_print_short+0x12c> + 1004124: 15 00 00 00 l.nop 0x0 + 1004128: 90 82 ff fe l.lbs r4,0xfffffffe(r2) + 100412c: d7 e2 27 a8 l.sw 0xffffffa8(r2),r4 + 1004130: 84 62 ff a8 l.lwz r3,0xffffffa8(r2) + 1004134: bd 43 00 09 l.sfgtsi r3,0x9 + 1004138: 10 00 00 10 l.bf 1004178 <_uart_print_short+0x12c> + 100413c: 15 00 00 00 l.nop 0x0 +// Clean up + 1004140: 8c 82 ff fe l.lbz r4,0xfffffffe(r2) + 1004144: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 1004148: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 100414c: 9c 63 00 30 l.addi r3,r3,0x30 + 1004150: d7 e2 1f a4 l.sw 0xffffffa4(r2),r3 + 1004154: 84 82 ff a4 l.lwz r4,0xffffffa4(r2) + 1004158: a4 84 00 ff l.andi r4,r4,0xff + 100415c: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + 1004160: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1004164: db e2 1f a3 l.sb 0xffffffa3(r2),r3 + 1004168: 8c 82 ff a3 l.lbz r4,0xffffffa3(r2) + 100416c: db e2 27 fe l.sb 0xfffffffe(r2),r4 + +//TO do +// Always check if error in repose (CRC, CICE) etc +// Always check for CICM (Command inhibit before senindg) +// Timeout when polling +// Divied into dividing Functions + 1004170: 00 00 00 0e l.j 10041a8 <_uart_print_short+0x15c> + 1004174: 15 00 00 00 l.nop 0x0 +// Clean up + +//#define TX + 1004178: 8c 62 ff fe l.lbz r3,0xfffffffe(r2) + 100417c: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + 1004180: 84 82 ff e8 l.lwz r4,0xffffffe8(r2) + 1004184: 9c 84 00 57 l.addi r4,r4,0x57 + 1004188: d7 e2 27 9c l.sw 0xffffff9c(r2),r4 + 100418c: 84 62 ff 9c l.lwz r3,0xffffff9c(r2) + 1004190: a4 63 00 ff l.andi r3,r3,0xff + 1004194: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 1004198: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 100419c: db e2 27 9b l.sb 0xffffff9b(r2),r4 + 10041a0: 8c 62 ff 9b l.lbz r3,0xffffff9b(r2) + 10041a4: db e2 1f fe l.sb 0xfffffffe(r2),r3 +#define RX +//#define BOTH + 10041a8: 90 82 ff fe l.lbs r4,0xfffffffe(r2) + 10041ac: d7 e2 27 94 l.sw 0xffffff94(r2),r4 + 10041b0: 84 62 ff 94 l.lwz r3,0xffffff94(r2) + 10041b4: bc 23 00 30 l.sfnei r3,0x30 + 10041b8: 10 00 00 08 l.bf 10041d8 <_uart_print_short+0x18c> + 10041bc: 15 00 00 00 l.nop 0x0 + 10041c0: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 10041c4: d7 e2 27 90 l.sw 0xffffff90(r2),r4 + 10041c8: 84 62 ff 90 l.lwz r3,0xffffff90(r2) + 10041cc: bc 23 00 07 l.sfnei r3,0x7 + 10041d0: 10 00 00 08 l.bf 10041f0 <_uart_print_short+0x1a4> + 10041d4: 15 00 00 00 l.nop 0x0 +//#define DB_BOTH + 10041d8: 9c 80 00 01 l.addi r4,r0,0x1 + 10041dc: d7 e2 27 8c l.sw 0xffffff8c(r2),r4 + 10041e0: 84 62 ff 8c l.lwz r3,0xffffff8c(r2) + 10041e4: db e2 1f 8b l.sb 0xffffff8b(r2),r3 + 10041e8: 8c 82 ff 8b l.lbz r4,0xffffff8b(r2) + 10041ec: db e2 27 ff l.sb 0xffffffff(r2),r4 + +void Start() + 10041f0: 90 62 ff ff l.lbs r3,0xffffffff(r2) + 10041f4: d7 e2 1f 84 l.sw 0xffffff84(r2),r3 + 10041f8: 84 82 ff 84 l.lwz r4,0xffffff84(r2) + 10041fc: bc 04 00 00 l.sfeqi r4,0x0 + 1004200: 10 00 00 07 l.bf 100421c <_uart_print_short+0x1d0> + 1004204: 15 00 00 00 l.nop 0x0 +{ + 1004208: 90 62 ff fe l.lbs r3,0xfffffffe(r2) + 100420c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 1004210: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004214: 07 ff fe a6 l.jal 1003cac <_uart_putc> + 1004218: 15 00 00 00 l.nop 0x0 + + + + +//TO do +// Always check if error in repose (CRC, CICE) etc + 100421c: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 1004220: d7 e2 27 80 l.sw 0xffffff80(r2),r4 + 1004224: 84 62 ff 80 l.lwz r3,0xffffff80(r2) + 1004228: 9c 63 00 01 l.addi r3,r3,0x1 + 100422c: d7 e2 1f 7c l.sw 0xffffff7c(r2),r3 + 1004230: 84 82 ff 7c l.lwz r4,0xffffff7c(r2) + 1004234: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 + 1004238: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 100423c: d7 e2 1f 78 l.sw 0xffffff78(r2),r3 + 1004240: 84 82 ff 78 l.lwz r4,0xffffff78(r2) + 1004244: bd a4 00 07 l.sflesi r4,0x7 + 1004248: 13 ff ff 94 l.bf 1004098 <_uart_print_short+0x4c> + 100424c: 15 00 00 00 l.nop 0x0 + 1004250: 85 21 00 00 l.lwz r9,0x0(r1) + 1004254: 84 41 00 04 l.lwz r2,0x4(r1) + 1004258: 44 00 48 00 l.jr r9 + 100425c: 9c 21 00 90 l.addi r1,r1,0x90 + +01004260 <_uart_getc>: + + volatile unsigned long rtn_reg=0; + volatile unsigned long rtn_reg1=0; + + int i; + unsigned char block[512]; + 1004260: 9c 21 ff d4 l.addi r1,r1,0xffffffd4 + 1004264: d4 01 10 00 l.sw 0x0(r1),r2 + 1004268: 9c 41 00 2c l.addi r2,r1,0x2c + unsigned char blocka[512]; + unsigned char blockb[512]; + + unsigned char rec_block[512]; + 100426c: 18 60 90 00 l.movhi r3,0x9000 + 1004270: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 1004274: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 1004278: a8 63 00 05 l.ori r3,r3,0x5 + 100427c: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + 1004280: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1004284: 8c 63 00 00 l.lbz r3,0x0(r3) + 1004288: db e2 1f db l.sb 0xffffffdb(r2),r3 + 100428c: 8c 62 ff db l.lbz r3,0xffffffdb(r2) + 1004290: db e2 1f fe l.sb 0xfffffffe(r2),r3 + 1004294: 8c 62 ff fe l.lbz r3,0xfffffffe(r2) + 1004298: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + 100429c: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 10042a0: a4 63 00 01 l.andi r3,r3,0x1 + 10042a4: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 10042a8: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 10042ac: bc 03 00 00 l.sfeqi r3,0x0 + 10042b0: 13 ff ff ef l.bf 100426c <_uart_getc+0xc> + 10042b4: 15 00 00 00 l.nop 0x0 + unsigned char rec_blocka[512]; + unsigned char rec_blockb[512]; + 10042b8: 18 60 90 00 l.movhi r3,0x9000 + 10042bc: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 10042c0: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 10042c4: 8c 63 00 00 l.lbz r3,0x0(r3) + 10042c8: db e2 1f da l.sb 0xffffffda(r2),r3 + 10042cc: 8c 62 ff da l.lbz r3,0xffffffda(r2) + 10042d0: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + 10042d4: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 10042d8: db e2 1f d9 l.sb 0xffffffd9(r2),r3 + 10042dc: 8c 62 ff d9 l.lbz r3,0xffffffd9(r2) + 10042e0: db e2 1f ff l.sb 0xffffffff(r2),r3 + + #ifdef RX + 10042e4: 90 62 ff ff l.lbs r3,0xffffffff(r2) + 10042e8: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + 10042ec: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 10042f0: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + for (i =0; i<512;i++) + 10042f4: 85 62 ff e0 l.lwz r11,0xffffffe0(r2) + 10042f8: 84 41 00 00 l.lwz r2,0x0(r1) + 10042fc: 44 00 48 00 l.jr r9 + 1004300: 9c 21 00 2c l.addi r1,r1,0x2c + +01004304 <_sd_get_rca>: + } + return 1; + } +*/ +int sd_get_rca(sd_card *d) +{ + 1004304: 9c 21 ff a0 l.addi r1,r1,0xffffffa0 + 1004308: d4 01 10 04 l.sw 0x4(r1),r2 + 100430c: 9c 41 00 60 l.addi r2,r1,0x60 + 1004310: d4 01 48 00 l.sw 0x0(r1),r9 + 1004314: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + uint32 rtn_reg=0; + 1004318: 9c 60 00 00 l.addi r3,r0,0x0 + 100431c: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 + SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48; + 1004320: 18 80 a0 00 l.movhi r4,0xa000 + 1004324: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 + 1004328: 84 62 ff cc l.lwz r3,0xffffffcc(r2) + 100432c: a8 63 00 04 l.ori r3,r3,0x4 + 1004330: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3 + 1004334: 9c 80 03 1a l.addi r4,r0,0x31a + 1004338: d7 e2 27 c8 l.sw 0xffffffc8(r2),r4 + 100433c: 84 82 ff c8 l.lwz r4,0xffffffc8(r2) + 1004340: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) + 1004344: d4 03 20 00 l.sw 0x0(r3),r4 + SD_REG(SD_ARG)=0; + 1004348: 18 60 a0 00 l.movhi r3,0xa000 + 100434c: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 1004350: 9c 60 00 00 l.addi r3,r0,0x0 + 1004354: 84 82 ff d8 l.lwz r4,0xffffffd8(r2) + 1004358: d4 04 18 00 l.sw 0x0(r4),r3 + + if (sd_wait_rsp() == 0) + 100435c: 04 00 00 49 l.jal 1004480 <_sd_wait_rsp> + 1004360: 15 00 00 00 l.nop 0x0 + 1004364: d7 e2 5f c4 l.sw 0xffffffc4(r2),r11 + 1004368: 84 82 ff c4 l.lwz r4,0xffffffc4(r2) + 100436c: d7 e2 27 dc l.sw 0xffffffdc(r2),r4 + 1004370: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 1004374: bc 23 00 00 l.sfnei r3,0x0 + 1004378: 10 00 00 06 l.bf 1004390 <_sd_get_rca+0x8c> + 100437c: 15 00 00 00 l.nop 0x0 + return 0; + 1004380: 9c 80 00 00 l.addi r4,r0,0x0 + 1004384: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 1004388: 00 00 00 37 l.j 1004464 <_sd_get_rca+0x160> + 100438c: 15 00 00 00 l.nop 0x0 + else{ + rtn_reg = SD_REG(SD_NORMAL_INT_STATUS); + 1004390: 18 60 a0 00 l.movhi r3,0xa000 + 1004394: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3 + 1004398: 84 82 ff c0 l.lwz r4,0xffffffc0(r2) + 100439c: a8 84 00 30 l.ori r4,r4,0x30 + 10043a0: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + 10043a4: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 10043a8: 84 63 00 00 l.lwz r3,0x0(r3) + 10043ac: d7 e2 1f bc l.sw 0xffffffbc(r2),r3 + 10043b0: 84 82 ff bc l.lwz r4,0xffffffbc(r2) + 10043b4: d7 e2 27 fc l.sw 0xfffffffc(r2),r4 + if ( (rtn_reg & EI) == EI) //Error in response, init failed return. + 10043b8: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 10043bc: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 + 10043c0: 84 82 ff b8 l.lwz r4,0xffffffb8(r2) + 10043c4: a4 84 80 00 l.andi r4,r4,0x8000 + 10043c8: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + 10043cc: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 10043d0: bc 03 00 00 l.sfeqi r3,0x0 + 10043d4: 10 00 00 06 l.bf 10043ec <_sd_get_rca+0xe8> + 10043d8: 15 00 00 00 l.nop 0x0 + return 0; + 10043dc: 9c 80 00 00 l.addi r4,r0,0x0 + 10043e0: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 10043e4: 00 00 00 20 l.j 1004464 <_sd_get_rca+0x160> + 10043e8: 15 00 00 00 l.nop 0x0 + rtn_reg = SD_REG(SD_RESP1); + 10043ec: 18 60 a0 00 l.movhi r3,0xa000 + 10043f0: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 10043f4: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 10043f8: a8 84 00 0c l.ori r4,r4,0xc + 10043fc: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + 1004400: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1004404: 84 63 00 00 l.lwz r3,0x0(r3) + 1004408: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 + 100440c: 84 82 ff b0 l.lwz r4,0xffffffb0(r2) + 1004410: d7 e2 27 fc l.sw 0xfffffffc(r2),r4 + d->rca=((rtn_reg&RCA_RCA_MASK)>>16); + 1004414: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1004418: d7 e2 1f ac l.sw 0xffffffac(r2),r3 + 100441c: 18 60 ff ff l.movhi r3,0xffff + 1004420: 84 82 ff ac l.lwz r4,0xffffffac(r2) + 1004424: e0 64 18 03 l.and r3,r4,r3 + 1004428: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 100442c: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 1004430: b8 84 00 50 l.srli r4,r4,0x10 + 1004434: d7 e2 27 f4 l.sw 0xfffffff4(r2),r4 + 1004438: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 100443c: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 1004440: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1004444: 84 82 ff a8 l.lwz r4,0xffffffa8(r2) + 1004448: d4 04 18 00 l.sw 0x0(r4),r3 + uart_print_str("rca fine"); + 100444c: 18 60 01 00 l.movhi r3,0x100 + 1004450: a8 63 4f 29 l.ori r3,r3,0x4f29 + 1004454: 07 ff fe 72 l.jal 1003e1c <_uart_print_str> + 1004458: 15 00 00 00 l.nop 0x0 + + } + return 1; + 100445c: 9c 80 00 01 l.addi r4,r0,0x1 + 1004460: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 1004464: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 1004468: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 + +} + 100446c: 85 62 ff d0 l.lwz r11,0xffffffd0(r2) + 1004470: 85 21 00 00 l.lwz r9,0x0(r1) + 1004474: 84 41 00 04 l.lwz r2,0x4(r1) + 1004478: 44 00 48 00 l.jr r9 + 100447c: 9c 21 00 60 l.addi r1,r1,0x60 + +01004480 <_sd_wait_rsp>: + + +//return 0 if no response else return 1. +uint8 sd_wait_rsp() +{ + 1004480: 9c 21 ff b4 l.addi r1,r1,0xffffffb4 + 1004484: d4 01 10 00 l.sw 0x0(r1),r2 + 1004488: 9c 41 00 4c l.addi r2,r1,0x4c + volatile unsigned long r1, r2; + + //Polling for timeout and command complete + while (1 ) + { + r1= SD_REG(SD_ERROR_INT_STATUS); + 100448c: 18 60 a0 00 l.movhi r3,0xa000 + 1004490: d7 e2 1f bc l.sw 0xffffffbc(r2),r3 + 1004494: 84 62 ff bc l.lwz r3,0xffffffbc(r2) + 1004498: a8 63 00 34 l.ori r3,r3,0x34 + 100449c: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 10044a0: 84 62 ff c4 l.lwz r3,0xffffffc4(r2) + 10044a4: 84 63 00 00 l.lwz r3,0x0(r3) + 10044a8: d7 e2 1f c8 l.sw 0xffffffc8(r2),r3 + 10044ac: 84 62 ff c8 l.lwz r3,0xffffffc8(r2) + 10044b0: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 + r2= SD_REG(SD_NORMAL_INT_STATUS) ; + 10044b4: 18 60 a0 00 l.movhi r3,0xa000 + 10044b8: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 + 10044bc: 84 62 ff b8 l.lwz r3,0xffffffb8(r2) + 10044c0: a8 63 00 30 l.ori r3,r3,0x30 + 10044c4: d7 e2 1f cc l.sw 0xffffffcc(r2),r3 + 10044c8: 84 62 ff cc l.lwz r3,0xffffffcc(r2) + 10044cc: 84 63 00 00 l.lwz r3,0x0(r3) + 10044d0: d7 e2 1f d0 l.sw 0xffffffd0(r2),r3 + 10044d4: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 10044d8: d7 e2 1f f8 l.sw 0xfffffff8(r2),r3 + + if (( r1 & CMD_TIMEOUT ) == CMD_TIMEOUT) + 10044dc: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 10044e0: d7 e2 1f d4 l.sw 0xffffffd4(r2),r3 + 10044e4: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) + 10044e8: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 10044ec: 84 62 ff d8 l.lwz r3,0xffffffd8(r2) + 10044f0: a4 63 00 01 l.andi r3,r3,0x1 + 10044f4: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 10044f8: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 10044fc: a4 63 00 ff l.andi r3,r3,0xff + 1004500: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + 1004504: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 1004508: bc 03 00 00 l.sfeqi r3,0x0 + 100450c: 10 00 00 06 l.bf 1004524 <_sd_wait_rsp+0xa4> + 1004510: 15 00 00 00 l.nop 0x0 + return 0; + 1004514: 9c 60 00 00 l.addi r3,r0,0x0 + 1004518: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + 100451c: 00 00 00 12 l.j 1004564 <_sd_wait_rsp+0xe4> + 1004520: 15 00 00 00 l.nop 0x0 + else if ((r2 & CMD_COMPLETE ) == CMD_COMPLETE) + 1004524: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004528: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + 100452c: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1004530: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 1004534: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1004538: a4 63 00 01 l.andi r3,r3,0x1 + 100453c: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + 1004540: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004544: a4 63 00 ff l.andi r3,r3,0xff + 1004548: d7 e2 1f f4 l.sw 0xfffffff4(r2),r3 + 100454c: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1004550: bc 03 00 00 l.sfeqi r3,0x0 + 1004554: 13 ff ff ce l.bf 100448c <_sd_wait_rsp+0xc> + 1004558: 15 00 00 00 l.nop 0x0 + return 1; + 100455c: 9c 60 00 01 l.addi r3,r0,0x1 + 1004560: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + + } + 1004564: 84 62 ff e4 l.lwz r3,0xffffffe4(r2) + 1004568: d7 e2 1f c0 l.sw 0xffffffc0(r2),r3 + //Later Exception restart module + return 0; + +} + 100456c: 85 62 ff c0 l.lwz r11,0xffffffc0(r2) + 1004570: 84 41 00 00 l.lwz r2,0x0(r1) + 1004574: 44 00 48 00 l.jr r9 + 1004578: 9c 21 00 4c l.addi r1,r1,0x4c + +0100457c <_sd_ocr_set>: + +unsigned long sd_ocr_set (unsigned long cmd1, unsigned long arg1, unsigned long cmd2, unsigned long arg2) +{ + 100457c: 9c 21 ff 78 l.addi r1,r1,0xffffff78 + 1004580: d4 01 10 04 l.sw 0x4(r1),r2 + 1004584: 9c 41 00 88 l.addi r2,r1,0x88 + 1004588: d4 01 48 00 l.sw 0x0(r1),r9 + 100458c: d7 e2 1f fc l.sw 0xfffffffc(r2),r3 + 1004590: d7 e2 27 f8 l.sw 0xfffffff8(r2),r4 + 1004594: d7 e2 2f f4 l.sw 0xfffffff4(r2),r5 + 1004598: d7 e2 37 f0 l.sw 0xfffffff0(r2),r6 + static unsigned long rtn_r =0; + + while ((rtn_r & BUSY) != BUSY) + 100459c: 00 00 00 5c l.j 100470c <_sd_ocr_set+0x190> + 10045a0: 15 00 00 00 l.nop 0x0 + { + SD_REG(SD_NORMAL_INT_STATUS)=0; + 10045a4: 18 60 a0 00 l.movhi r3,0xa000 + 10045a8: d7 e2 1f b4 l.sw 0xffffffb4(r2),r3 + 10045ac: 84 82 ff b4 l.lwz r4,0xffffffb4(r2) + 10045b0: a8 84 00 30 l.ori r4,r4,0x30 + 10045b4: d7 e2 27 bc l.sw 0xffffffbc(r2),r4 + 10045b8: 9c 80 00 00 l.addi r4,r0,0x0 + 10045bc: 84 62 ff bc l.lwz r3,0xffffffbc(r2) + 10045c0: d4 03 20 00 l.sw 0x0(r3),r4 + SD_REG(SD_ERROR_INT_STATUS)=0; + 10045c4: 18 60 a0 00 l.movhi r3,0xa000 + 10045c8: d7 e2 1f b0 l.sw 0xffffffb0(r2),r3 + 10045cc: 84 82 ff b0 l.lwz r4,0xffffffb0(r2) + 10045d0: a8 84 00 34 l.ori r4,r4,0x34 + 10045d4: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 10045d8: 9c 80 00 00 l.addi r4,r0,0x0 + 10045dc: 84 62 ff c0 l.lwz r3,0xffffffc0(r2) + 10045e0: d4 03 20 00 l.sw 0x0(r3),r4 + + SD_REG(SD_COMMAND) = cmd1; + 10045e4: 18 60 a0 00 l.movhi r3,0xa000 + 10045e8: d7 e2 1f ac l.sw 0xffffffac(r2),r3 + 10045ec: 84 82 ff ac l.lwz r4,0xffffffac(r2) + 10045f0: a8 84 00 04 l.ori r4,r4,0x4 + 10045f4: d7 e2 27 c4 l.sw 0xffffffc4(r2),r4 + 10045f8: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 10045fc: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 1004600: 84 62 ff a8 l.lwz r3,0xffffffa8(r2) + 1004604: 84 82 ff c4 l.lwz r4,0xffffffc4(r2) + 1004608: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG(SD_ARG) = arg1; + 100460c: 18 80 a0 00 l.movhi r4,0xa000 + 1004610: d7 e2 27 c8 l.sw 0xffffffc8(r2),r4 + 1004614: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004618: d7 e2 1f a4 l.sw 0xffffffa4(r2),r3 + 100461c: 84 62 ff a4 l.lwz r3,0xffffffa4(r2) + 1004620: 84 82 ff c8 l.lwz r4,0xffffffc8(r2) + 1004624: d4 04 18 00 l.sw 0x0(r4),r3 + if (sd_wait_rsp() == 0) + 1004628: 07 ff ff 96 l.jal 1004480 <_sd_wait_rsp> + 100462c: 15 00 00 00 l.nop 0x0 + 1004630: d7 e2 5f a0 l.sw 0xffffffa0(r2),r11 + 1004634: 84 82 ff a0 l.lwz r4,0xffffffa0(r2) + 1004638: d7 e2 27 cc l.sw 0xffffffcc(r2),r4 + 100463c: 84 62 ff cc l.lwz r3,0xffffffcc(r2) + 1004640: bc 23 00 00 l.sfnei r3,0x0 + 1004644: 10 00 00 06 l.bf 100465c <_sd_ocr_set+0xe0> + 1004648: 15 00 00 00 l.nop 0x0 + return 0; + 100464c: 9c 80 00 00 l.addi r4,r0,0x0 + 1004650: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1004654: 00 00 00 40 l.j 1004754 <_sd_ocr_set+0x1d8> + 1004658: 15 00 00 00 l.nop 0x0 + else{ + SD_REG (SD_COMMAND) =cmd2; + 100465c: 18 60 a0 00 l.movhi r3,0xa000 + 1004660: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 + 1004664: 84 82 ff 9c l.lwz r4,0xffffff9c(r2) + 1004668: a8 84 00 04 l.ori r4,r4,0x4 + 100466c: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4 + 1004670: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1004674: d7 e2 1f 98 l.sw 0xffffff98(r2),r3 + 1004678: 84 62 ff 98 l.lwz r3,0xffffff98(r2) + 100467c: 84 82 ff d4 l.lwz r4,0xffffffd4(r2) + 1004680: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG (SD_ARG) =arg2; + 1004684: 18 80 a0 00 l.movhi r4,0xa000 + 1004688: d7 e2 27 d8 l.sw 0xffffffd8(r2),r4 + 100468c: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004690: d7 e2 1f 94 l.sw 0xffffff94(r2),r3 + 1004694: 84 62 ff 94 l.lwz r3,0xffffff94(r2) + 1004698: 84 82 ff d8 l.lwz r4,0xffffffd8(r2) + 100469c: d4 04 18 00 l.sw 0x0(r4),r3 + } + if (sd_wait_rsp() == 0) + 10046a0: 07 ff ff 78 l.jal 1004480 <_sd_wait_rsp> + 10046a4: 15 00 00 00 l.nop 0x0 + 10046a8: d7 e2 5f 90 l.sw 0xffffff90(r2),r11 + 10046ac: 84 82 ff 90 l.lwz r4,0xffffff90(r2) + 10046b0: d7 e2 27 dc l.sw 0xffffffdc(r2),r4 + 10046b4: 84 62 ff dc l.lwz r3,0xffffffdc(r2) + 10046b8: bc 23 00 00 l.sfnei r3,0x0 + 10046bc: 10 00 00 06 l.bf 10046d4 <_sd_ocr_set+0x158> + 10046c0: 15 00 00 00 l.nop 0x0 + return 0; + 10046c4: 9c 80 00 00 l.addi r4,r0,0x0 + 10046c8: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 10046cc: 00 00 00 22 l.j 1004754 <_sd_ocr_set+0x1d8> + 10046d0: 15 00 00 00 l.nop 0x0 + else + rtn_r= SD_REG(SD_RESP1); + 10046d4: 18 60 a0 00 l.movhi r3,0xa000 + 10046d8: d7 e2 1f 8c l.sw 0xffffff8c(r2),r3 + 10046dc: 84 82 ff 8c l.lwz r4,0xffffff8c(r2) + 10046e0: a8 84 00 0c l.ori r4,r4,0xc + 10046e4: d7 e2 27 e0 l.sw 0xffffffe0(r2),r4 + 10046e8: 84 62 ff e0 l.lwz r3,0xffffffe0(r2) + 10046ec: 84 63 00 00 l.lwz r3,0x0(r3) + 10046f0: d7 e2 1f e4 l.sw 0xffffffe4(r2),r3 + 10046f4: 18 80 01 00 l.movhi r4,0x100 + 10046f8: a8 84 4f 40 l.ori r4,r4,0x4f40 + 10046fc: d7 e2 27 88 l.sw 0xffffff88(r2),r4 + 1004700: 84 82 ff e4 l.lwz r4,0xffffffe4(r2) + 1004704: 84 62 ff 88 l.lwz r3,0xffffff88(r2) + 1004708: d4 03 20 00 l.sw 0x0(r3),r4 + +unsigned long sd_ocr_set (unsigned long cmd1, unsigned long arg1, unsigned long cmd2, unsigned long arg2) +{ + static unsigned long rtn_r =0; + + while ((rtn_r & BUSY) != BUSY) + 100470c: 18 60 01 00 l.movhi r3,0x100 + 1004710: a8 63 4f 40 l.ori r3,r3,0x4f40 + 1004714: d7 e2 1f 84 l.sw 0xffffff84(r2),r3 + 1004718: 84 82 ff 84 l.lwz r4,0xffffff84(r2) + 100471c: 84 84 00 00 l.lwz r4,0x0(r4) + 1004720: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + 1004724: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1004728: d7 e2 1f ec l.sw 0xffffffec(r2),r3 + 100472c: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1004730: bd 64 00 00 l.sfgesi r4,0x0 + 1004734: 13 ff ff 9c l.bf 10045a4 <_sd_ocr_set+0x28> + 1004738: 15 00 00 00 l.nop 0x0 + rtn_r= SD_REG(SD_RESP1); + + + } + + return rtn_r; + 100473c: 18 60 01 00 l.movhi r3,0x100 + 1004740: a8 63 4f 40 l.ori r3,r3,0x4f40 + 1004744: d7 e2 1f 80 l.sw 0xffffff80(r2),r3 + 1004748: 84 82 ff 80 l.lwz r4,0xffffff80(r2) + 100474c: 84 84 00 00 l.lwz r4,0x0(r4) + 1004750: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1004754: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 1004758: d7 e2 1f b8 l.sw 0xffffffb8(r2),r3 +} + 100475c: 85 62 ff b8 l.lwz r11,0xffffffb8(r2) + 1004760: 85 21 00 00 l.lwz r9,0x0(r1) + 1004764: 84 41 00 04 l.lwz r2,0x4(r1) + 1004768: 44 00 48 00 l.jr r9 + 100476c: 9c 21 00 88 l.addi r1,r1,0x88 + +01004770 <_sd_controller_init>: + // unsigned int a= SD_REG(SD_STATUS); + //return (a & 1); +// + + sd_card sd_controller_init () +{ + 1004770: 9c 21 fe 68 l.addi r1,r1,0xfffffe68 + 1004774: d4 01 10 04 l.sw 0x4(r1),r2 + 1004778: 9c 41 01 98 l.addi r2,r1,0x198 + 100477c: d4 01 48 00 l.sw 0x0(r1),r9 + 1004780: d7 e2 1f 48 l.sw 0xffffff48(r2),r3 + sd_card dev; + + volatile unsigned long rtn_reg=0; + 1004784: 9c 60 00 00 l.addi r3,r0,0x0 + 1004788: d7 e2 1f e8 l.sw 0xffffffe8(r2),r3 + volatile unsigned long rtn_reg1=0; + 100478c: 9c 80 00 00 l.addi r4,r0,0x0 + 1004790: d7 e2 27 e4 l.sw 0xffffffe4(r2),r4 + + REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x000077F; + 1004794: 18 60 a0 00 l.movhi r3,0xa000 + 1004798: d7 e2 1f 44 l.sw 0xffffff44(r2),r3 + 100479c: 84 82 ff 44 l.lwz r4,0xffffff44(r2) + 10047a0: a8 84 00 2c l.ori r4,r4,0x2c + 10047a4: d7 e2 27 4c l.sw 0xffffff4c(r2),r4 + 10047a8: 9c 60 07 7f l.addi r3,r0,0x77f + 10047ac: d7 e2 1f 40 l.sw 0xffffff40(r2),r3 + 10047b0: 84 62 ff 40 l.lwz r3,0xffffff40(r2) + 10047b4: 84 82 ff 4c l.lwz r4,0xffffff4c(r2) + 10047b8: d4 04 18 00 l.sw 0x0(r4),r3 + + + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + 10047bc: 18 80 a0 00 l.movhi r4,0xa000 + 10047c0: d7 e2 27 50 l.sw 0xffffff50(r2),r4 + 10047c4: 9c 80 00 00 l.addi r4,r0,0x0 + 10047c8: 84 62 ff 50 l.lwz r3,0xffffff50(r2) + 10047cc: d4 03 20 00 l.sw 0x0(r3),r4 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + 10047d0: 18 60 a0 00 l.movhi r3,0xa000 + 10047d4: d7 e2 1f 3c l.sw 0xffffff3c(r2),r3 + 10047d8: 84 82 ff 3c l.lwz r4,0xffffff3c(r2) + 10047dc: a8 84 00 04 l.ori r4,r4,0x4 + 10047e0: d7 e2 27 54 l.sw 0xffffff54(r2),r4 + 10047e4: 9c 80 00 00 l.addi r4,r0,0x0 + 10047e8: 84 62 ff 54 l.lwz r3,0xffffff54(r2) + 10047ec: d4 03 20 00 l.sw 0x0(r3),r4 + + SD_REG(SD_COMMAND) = ( CMD8 | CICE | CRCE | RSP_48); + 10047f0: 18 60 a0 00 l.movhi r3,0xa000 + 10047f4: d7 e2 1f 38 l.sw 0xffffff38(r2),r3 + 10047f8: 84 82 ff 38 l.lwz r4,0xffffff38(r2) + 10047fc: a8 84 00 04 l.ori r4,r4,0x4 + 1004800: d7 e2 27 58 l.sw 0xffffff58(r2),r4 + 1004804: 9c 60 08 1a l.addi r3,r0,0x81a + 1004808: d7 e2 1f 34 l.sw 0xffffff34(r2),r3 + 100480c: 84 62 ff 34 l.lwz r3,0xffffff34(r2) + 1004810: 84 82 ff 58 l.lwz r4,0xffffff58(r2) + 1004814: d4 04 18 00 l.sw 0x0(r4),r3 + SD_REG(SD_ARG) = VHS|CHECK_PATTERN; + 1004818: 18 80 a0 00 l.movhi r4,0xa000 + 100481c: d7 e2 27 5c l.sw 0xffffff5c(r2),r4 + 1004820: 9c 60 01 aa l.addi r3,r0,0x1aa + 1004824: d7 e2 1f 30 l.sw 0xffffff30(r2),r3 + 1004828: 84 62 ff 30 l.lwz r3,0xffffff30(r2) + 100482c: 84 82 ff 5c l.lwz r4,0xffffff5c(r2) + 1004830: d4 04 18 00 l.sw 0x0(r4),r3 + + dev.phys_spec_2_0 = sd_wait_rsp(); + 1004834: 07 ff ff 13 l.jal 1004480 <_sd_wait_rsp> + 1004838: 15 00 00 00 l.nop 0x0 + 100483c: d7 e2 5f 2c l.sw 0xffffff2c(r2),r11 + 1004840: 84 82 ff 2c l.lwz r4,0xffffff2c(r2) + 1004844: d7 e2 27 60 l.sw 0xffffff60(r2),r4 + 1004848: 84 62 ff 60 l.lwz r3,0xffffff60(r2) + 100484c: db e2 1f 2b l.sb 0xffffff2b(r2),r3 + 1004850: 8c 82 ff 2b l.lbz r4,0xffffff2b(r2) + 1004854: db e2 27 f6 l.sb 0xfffffff6(r2),r4 + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + 1004858: 18 60 a0 00 l.movhi r3,0xa000 + 100485c: d7 e2 1f 64 l.sw 0xffffff64(r2),r3 + 1004860: 9c 60 00 00 l.addi r3,r0,0x0 + 1004864: 84 82 ff 64 l.lwz r4,0xffffff64(r2) + 1004868: d4 04 18 00 l.sw 0x0(r4),r3 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + 100486c: 18 80 a0 00 l.movhi r4,0xa000 + 1004870: d7 e2 27 24 l.sw 0xffffff24(r2),r4 + 1004874: 84 62 ff 24 l.lwz r3,0xffffff24(r2) + 1004878: a8 63 00 04 l.ori r3,r3,0x4 + 100487c: d7 e2 1f 68 l.sw 0xffffff68(r2),r3 + 1004880: 9c 60 00 00 l.addi r3,r0,0x0 + 1004884: 84 82 ff 68 l.lwz r4,0xffffff68(r2) + 1004888: d4 04 18 00 l.sw 0x0(r4),r3 + if (dev.phys_spec_2_0) + 100488c: 8c 82 ff f6 l.lbz r4,0xfffffff6(r2) + 1004890: d7 e2 27 6c l.sw 0xffffff6c(r2),r4 + 1004894: 84 62 ff 6c l.lwz r3,0xffffff6c(r2) + 1004898: bc 03 00 00 l.sfeqi r3,0x0 + 100489c: 10 00 00 08 l.bf 10048bc <_sd_controller_init+0x14c> + 10048a0: 15 00 00 00 l.nop 0x0 + { + uart_print_str("2_0 CARD /n"); + 10048a4: 18 60 01 00 l.movhi r3,0x100 + 10048a8: a8 63 4f 32 l.ori r3,r3,0x4f32 + 10048ac: 07 ff fd 5c l.jal 1003e1c <_uart_print_str> + 10048b0: 15 00 00 00 l.nop 0x0 + 10048b4: 00 00 00 ae l.j 1004b6c <_sd_controller_init+0x3fc> + 10048b8: 15 00 00 00 l.nop 0x0 + + } + else + { + + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000; + 10048bc: 18 80 a0 00 l.movhi r4,0xa000 + 10048c0: d7 e2 27 70 l.sw 0xffffff70(r2),r4 + 10048c4: 9c 80 00 00 l.addi r4,r0,0x0 + 10048c8: 84 62 ff 70 l.lwz r3,0xffffff70(r2) + 10048cc: d4 03 20 00 l.sw 0x0(r3),r4 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + 10048d0: 18 60 a0 00 l.movhi r3,0xa000 + 10048d4: d7 e2 1f 20 l.sw 0xffffff20(r2),r3 + 10048d8: 84 82 ff 20 l.lwz r4,0xffffff20(r2) + 10048dc: a8 84 00 04 l.ori r4,r4,0x4 + 10048e0: d7 e2 27 74 l.sw 0xffffff74(r2),r4 + 10048e4: 9c 80 00 00 l.addi r4,r0,0x0 + 10048e8: 84 62 ff 74 l.lwz r3,0xffffff74(r2) + 10048ec: d4 03 20 00 l.sw 0x0(r3),r4 + while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {} + 10048f0: 18 60 a0 00 l.movhi r3,0xa000 + 10048f4: d7 e2 1f 1c l.sw 0xffffff1c(r2),r3 + 10048f8: 84 82 ff 1c l.lwz r4,0xffffff1c(r2) + 10048fc: a8 84 00 08 l.ori r4,r4,0x8 + 1004900: d7 e2 27 78 l.sw 0xffffff78(r2),r4 + 1004904: 84 62 ff 78 l.lwz r3,0xffffff78(r2) + 1004908: 84 63 00 00 l.lwz r3,0x0(r3) + 100490c: d7 e2 1f 7c l.sw 0xffffff7c(r2),r3 + 1004910: 84 82 ff 7c l.lwz r4,0xffffff7c(r2) + 1004914: d7 e2 27 80 l.sw 0xffffff80(r2),r4 + 1004918: 84 62 ff 80 l.lwz r3,0xffffff80(r2) + 100491c: a4 63 00 01 l.andi r3,r3,0x1 + 1004920: d7 e2 1f 84 l.sw 0xffffff84(r2),r3 + 1004924: 84 82 ff 84 l.lwz r4,0xffffff84(r2) + 1004928: a4 84 00 ff l.andi r4,r4,0xff + 100492c: d7 e2 27 88 l.sw 0xffffff88(r2),r4 + 1004930: 84 62 ff 88 l.lwz r3,0xffffff88(r2) + 1004934: bc 23 00 00 l.sfnei r3,0x0 + 1004938: 13 ff ff ee l.bf 10048f0 <_sd_controller_init+0x180> + 100493c: 15 00 00 00 l.nop 0x0 + + + rtn_reg=0; + 1004940: 9c 80 00 00 l.addi r4,r0,0x0 + 1004944: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + while ((rtn_reg & BUSY) != BUSY) + 1004948: 00 00 00 72 l.j 1004b10 <_sd_controller_init+0x3a0> + 100494c: 15 00 00 00 l.nop 0x0 + { + REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48; + 1004950: 18 60 a0 00 l.movhi r3,0xa000 + 1004954: d7 e2 1f 18 l.sw 0xffffff18(r2),r3 + 1004958: 84 82 ff 18 l.lwz r4,0xffffff18(r2) + 100495c: a8 84 00 04 l.ori r4,r4,0x4 + 1004960: d7 e2 27 8c l.sw 0xffffff8c(r2),r4 + 1004964: 9c 60 37 02 l.addi r3,r0,0x3702 + 1004968: d7 e2 1f 14 l.sw 0xffffff14(r2),r3 + 100496c: 84 62 ff 14 l.lwz r3,0xffffff14(r2) + 1004970: 84 82 ff 8c l.lwz r4,0xffffff8c(r2) + 1004974: d4 04 18 00 l.sw 0x0(r4),r3 + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + 1004978: 18 80 a0 00 l.movhi r4,0xa000 + 100497c: d7 e2 27 90 l.sw 0xffffff90(r2),r4 + 1004980: 9c 80 00 00 l.addi r4,r0,0x0 + 1004984: 84 62 ff 90 l.lwz r3,0xffffff90(r2) + 1004988: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 100498c: 07 ff fe bd l.jal 1004480 <_sd_wait_rsp> + 1004990: 15 00 00 00 l.nop 0x0 + 1004994: d7 e2 5f 10 l.sw 0xffffff10(r2),r11 + 1004998: 84 62 ff 10 l.lwz r3,0xffffff10(r2) + 100499c: d7 e2 1f 94 l.sw 0xffffff94(r2),r3 + 10049a0: 84 82 ff 94 l.lwz r4,0xffffff94(r2) + 10049a4: bc 24 00 00 l.sfnei r4,0x0 + 10049a8: 10 00 00 1d l.bf 1004a1c <_sd_controller_init+0x2ac> + 10049ac: 15 00 00 00 l.nop 0x0 + return dev; + 10049b0: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 10049b4: d7 e2 1f 0c l.sw 0xffffff0c(r2),r3 + 10049b8: 84 62 ff 0c l.lwz r3,0xffffff0c(r2) + 10049bc: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 10049c0: d4 04 18 00 l.sw 0x0(r4),r3 + 10049c4: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 10049c8: d7 e2 27 08 l.sw 0xffffff08(r2),r4 + 10049cc: 84 82 ff 08 l.lwz r4,0xffffff08(r2) + 10049d0: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 10049d4: d4 03 20 04 l.sw 0x4(r3),r4 + 10049d8: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 10049dc: d7 e2 1f 04 l.sw 0xffffff04(r2),r3 + 10049e0: 84 62 ff 04 l.lwz r3,0xffffff04(r2) + 10049e4: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 10049e8: d4 04 18 08 l.sw 0x8(r4),r3 + 10049ec: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 10049f0: d7 e2 27 00 l.sw 0xffffff00(r2),r4 + 10049f4: 84 82 ff 00 l.lwz r4,0xffffff00(r2) + 10049f8: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 10049fc: d4 03 20 0c l.sw 0xc(r3),r4 + 1004a00: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1004a04: d7 e2 1e fc l.sw 0xfffffefc(r2),r3 + 1004a08: 84 62 fe fc l.lwz r3,0xfffffefc(r2) + 1004a0c: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004a10: d4 04 18 10 l.sw 0x10(r4),r3 + 1004a14: 00 00 00 ed l.j 1004dc8 <_sd_controller_init+0x658> + 1004a18: 15 00 00 00 l.nop 0x0 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =ACMD41 | RSP_48; + 1004a1c: 18 80 a0 00 l.movhi r4,0xa000 + 1004a20: d7 e2 26 f8 l.sw 0xfffffef8(r2),r4 + 1004a24: 84 62 fe f8 l.lwz r3,0xfffffef8(r2) + 1004a28: a8 63 00 04 l.ori r3,r3,0x4 + 1004a2c: d7 e2 1f 98 l.sw 0xffffff98(r2),r3 + 1004a30: 9c 80 29 02 l.addi r4,r0,0x2902 + 1004a34: d7 e2 26 f4 l.sw 0xfffffef4(r2),r4 + 1004a38: 84 82 fe f4 l.lwz r4,0xfffffef4(r2) + 1004a3c: 84 62 ff 98 l.lwz r3,0xffffff98(r2) + 1004a40: d4 03 20 00 l.sw 0x0(r3),r4 + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + 1004a44: 18 60 a0 00 l.movhi r3,0xa000 + 1004a48: d7 e2 1f 9c l.sw 0xffffff9c(r2),r3 + 1004a4c: 9c 60 00 00 l.addi r3,r0,0x0 + 1004a50: 84 82 ff 9c l.lwz r4,0xffffff9c(r2) + 1004a54: d4 04 18 00 l.sw 0x0(r4),r3 + if (!sd_wait_rsp()) + 1004a58: 07 ff fe 8a l.jal 1004480 <_sd_wait_rsp> + 1004a5c: 15 00 00 00 l.nop 0x0 + 1004a60: d7 e2 5e f0 l.sw 0xfffffef0(r2),r11 + 1004a64: 84 82 fe f0 l.lwz r4,0xfffffef0(r2) + 1004a68: d7 e2 27 a0 l.sw 0xffffffa0(r2),r4 + 1004a6c: 84 62 ff a0 l.lwz r3,0xffffffa0(r2) + 1004a70: bc 23 00 00 l.sfnei r3,0x0 + 1004a74: 10 00 00 1d l.bf 1004ae8 <_sd_controller_init+0x378> + 1004a78: 15 00 00 00 l.nop 0x0 + return dev; + 1004a7c: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1004a80: d7 e2 26 ec l.sw 0xfffffeec(r2),r4 + 1004a84: 84 82 fe ec l.lwz r4,0xfffffeec(r2) + 1004a88: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004a8c: d4 03 20 00 l.sw 0x0(r3),r4 + 1004a90: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004a94: d7 e2 1e e8 l.sw 0xfffffee8(r2),r3 + 1004a98: 84 62 fe e8 l.lwz r3,0xfffffee8(r2) + 1004a9c: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004aa0: d4 04 18 04 l.sw 0x4(r4),r3 + 1004aa4: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1004aa8: d7 e2 26 e4 l.sw 0xfffffee4(r2),r4 + 1004aac: 84 82 fe e4 l.lwz r4,0xfffffee4(r2) + 1004ab0: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004ab4: d4 03 20 08 l.sw 0x8(r3),r4 + 1004ab8: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004abc: d7 e2 1e e0 l.sw 0xfffffee0(r2),r3 + 1004ac0: 84 62 fe e0 l.lwz r3,0xfffffee0(r2) + 1004ac4: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004ac8: d4 04 18 0c l.sw 0xc(r4),r3 + 1004acc: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 1004ad0: d7 e2 26 dc l.sw 0xfffffedc(r2),r4 + 1004ad4: 84 82 fe dc l.lwz r4,0xfffffedc(r2) + 1004ad8: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004adc: d4 03 20 10 l.sw 0x10(r3),r4 + 1004ae0: 00 00 00 ba l.j 1004dc8 <_sd_controller_init+0x658> + 1004ae4: 15 00 00 00 l.nop 0x0 + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + 1004ae8: 18 60 a0 00 l.movhi r3,0xa000 + 1004aec: d7 e2 1e d8 l.sw 0xfffffed8(r2),r3 + 1004af0: 84 82 fe d8 l.lwz r4,0xfffffed8(r2) + 1004af4: a8 84 00 0c l.ori r4,r4,0xc + 1004af8: d7 e2 27 a4 l.sw 0xffffffa4(r2),r4 + 1004afc: 84 62 ff a4 l.lwz r3,0xffffffa4(r2) + 1004b00: 84 63 00 00 l.lwz r3,0x0(r3) + 1004b04: d7 e2 1f a8 l.sw 0xffffffa8(r2),r3 + 1004b08: 84 82 ff a8 l.lwz r4,0xffffffa8(r2) + 1004b0c: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + while (REG32(SD_CONTROLLER_BASE+SD_STATUS)& 1) {} + + + rtn_reg=0; + while ((rtn_reg & BUSY) != BUSY) + 1004b10: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1004b14: d7 e2 1f ac l.sw 0xffffffac(r2),r3 + 1004b18: 84 82 ff ac l.lwz r4,0xffffffac(r2) + 1004b1c: d7 e2 27 b0 l.sw 0xffffffb0(r2),r4 + 1004b20: 84 62 ff b0 l.lwz r3,0xffffffb0(r2) + 1004b24: bd 63 00 00 l.sfgesi r3,0x0 + 1004b28: 13 ff ff 8a l.bf 1004950 <_sd_controller_init+0x1e0> + 1004b2c: 15 00 00 00 l.nop 0x0 + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + if (!sd_wait_rsp()) + return dev; + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + } + dev.Voltage_window=rtn_reg&VOLTAGE_MASK; + 1004b30: 84 82 ff e8 l.lwz r4,0xffffffe8(r2) + 1004b34: d7 e2 27 b4 l.sw 0xffffffb4(r2),r4 + 1004b38: 18 80 00 ff l.movhi r4,0xff + 1004b3c: a8 84 ff ff l.ori r4,r4,0xffff + 1004b40: 84 62 ff b4 l.lwz r3,0xffffffb4(r2) + 1004b44: e0 83 20 03 l.and r4,r3,r4 + 1004b48: d7 e2 27 b8 l.sw 0xffffffb8(r2),r4 + 1004b4c: 84 62 ff b8 l.lwz r3,0xffffffb8(r2) + 1004b50: d7 e2 1f f0 l.sw 0xfffffff0(r2),r3 + dev.HCS_s = 0; + 1004b54: 9c 80 00 00 l.addi r4,r0,0x0 + 1004b58: d7 e2 26 d4 l.sw 0xfffffed4(r2),r4 + 1004b5c: 84 62 fe d4 l.lwz r3,0xfffffed4(r2) + 1004b60: db e2 1e d3 l.sb 0xfffffed3(r2),r3 + 1004b64: 8c 82 fe d3 l.lbz r4,0xfffffed3(r2) + 1004b68: db e2 27 f4 l.sb 0xfffffff4(r2),r4 + + } + + + //GET CID + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =CMD2 | RSP_146; + 1004b6c: 18 60 a0 00 l.movhi r3,0xa000 + 1004b70: d7 e2 1e cc l.sw 0xfffffecc(r2),r3 + 1004b74: 84 82 fe cc l.lwz r4,0xfffffecc(r2) + 1004b78: a8 84 00 04 l.ori r4,r4,0x4 + 1004b7c: d7 e2 27 bc l.sw 0xffffffbc(r2),r4 + 1004b80: 9c 60 02 01 l.addi r3,r0,0x201 + 1004b84: d7 e2 1e c8 l.sw 0xfffffec8(r2),r3 + 1004b88: 84 62 fe c8 l.lwz r3,0xfffffec8(r2) + 1004b8c: 84 82 ff bc l.lwz r4,0xffffffbc(r2) + 1004b90: d4 04 18 00 l.sw 0x0(r4),r3 + REG32(SD_CONTROLLER_BASE+SD_ARG) =0; + 1004b94: 18 80 a0 00 l.movhi r4,0xa000 + 1004b98: d7 e2 27 c0 l.sw 0xffffffc0(r2),r4 + 1004b9c: 9c 80 00 00 l.addi r4,r0,0x0 + 1004ba0: 84 62 ff c0 l.lwz r3,0xffffffc0(r2) + 1004ba4: d4 03 20 00 l.sw 0x0(r3),r4 + if (!sd_wait_rsp()) + 1004ba8: 07 ff fe 36 l.jal 1004480 <_sd_wait_rsp> + 1004bac: 15 00 00 00 l.nop 0x0 + 1004bb0: d7 e2 5e c4 l.sw 0xfffffec4(r2),r11 + 1004bb4: 84 62 fe c4 l.lwz r3,0xfffffec4(r2) + 1004bb8: d7 e2 1f c4 l.sw 0xffffffc4(r2),r3 + 1004bbc: 84 82 ff c4 l.lwz r4,0xffffffc4(r2) + 1004bc0: bc 24 00 00 l.sfnei r4,0x0 + 1004bc4: 10 00 00 1d l.bf 1004c38 <_sd_controller_init+0x4c8> + 1004bc8: 15 00 00 00 l.nop 0x0 + return dev; + 1004bcc: 84 62 ff ec l.lwz r3,0xffffffec(r2) + 1004bd0: d7 e2 1e c0 l.sw 0xfffffec0(r2),r3 + 1004bd4: 84 62 fe c0 l.lwz r3,0xfffffec0(r2) + 1004bd8: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004bdc: d4 04 18 00 l.sw 0x0(r4),r3 + 1004be0: 84 82 ff f0 l.lwz r4,0xfffffff0(r2) + 1004be4: d7 e2 26 bc l.sw 0xfffffebc(r2),r4 + 1004be8: 84 82 fe bc l.lwz r4,0xfffffebc(r2) + 1004bec: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004bf0: d4 03 20 04 l.sw 0x4(r3),r4 + 1004bf4: 84 62 ff f4 l.lwz r3,0xfffffff4(r2) + 1004bf8: d7 e2 1e b8 l.sw 0xfffffeb8(r2),r3 + 1004bfc: 84 62 fe b8 l.lwz r3,0xfffffeb8(r2) + 1004c00: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004c04: d4 04 18 08 l.sw 0x8(r4),r3 + 1004c08: 84 82 ff f8 l.lwz r4,0xfffffff8(r2) + 1004c0c: d7 e2 26 b4 l.sw 0xfffffeb4(r2),r4 + 1004c10: 84 82 fe b4 l.lwz r4,0xfffffeb4(r2) + 1004c14: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004c18: d4 03 20 0c l.sw 0xc(r3),r4 + 1004c1c: 84 62 ff fc l.lwz r3,0xfffffffc(r2) + 1004c20: d7 e2 1e b0 l.sw 0xfffffeb0(r2),r3 + 1004c24: 84 62 fe b0 l.lwz r3,0xfffffeb0(r2) + 1004c28: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004c2c: d4 04 18 10 l.sw 0x10(r4),r3 + 1004c30: 00 00 00 66 l.j 1004dc8 <_sd_controller_init+0x658> + 1004c34: 15 00 00 00 l.nop 0x0 + //Get RCA + SD_REG(SD_COMMAND) = CMD3 | CICE | CRCE | RSP_48; + 1004c38: 18 80 a0 00 l.movhi r4,0xa000 + 1004c3c: d7 e2 26 ac l.sw 0xfffffeac(r2),r4 + 1004c40: 84 62 fe ac l.lwz r3,0xfffffeac(r2) + 1004c44: a8 63 00 04 l.ori r3,r3,0x4 + 1004c48: d7 e2 1f c8 l.sw 0xffffffc8(r2),r3 + 1004c4c: 9c 80 03 1a l.addi r4,r0,0x31a + 1004c50: d7 e2 26 a8 l.sw 0xfffffea8(r2),r4 + 1004c54: 84 82 fe a8 l.lwz r4,0xfffffea8(r2) + 1004c58: 84 62 ff c8 l.lwz r3,0xffffffc8(r2) + 1004c5c: d4 03 20 00 l.sw 0x0(r3),r4 + SD_REG(SD_ARG)=0; + 1004c60: 18 60 a0 00 l.movhi r3,0xa000 + 1004c64: d7 e2 1f cc l.sw 0xffffffcc(r2),r3 + 1004c68: 9c 60 00 00 l.addi r3,r0,0x0 + 1004c6c: 84 82 ff cc l.lwz r4,0xffffffcc(r2) + 1004c70: d4 04 18 00 l.sw 0x0(r4),r3 + if (!sd_wait_rsp()) + 1004c74: 07 ff fe 03 l.jal 1004480 <_sd_wait_rsp> + 1004c78: 15 00 00 00 l.nop 0x0 + 1004c7c: d7 e2 5e a4 l.sw 0xfffffea4(r2),r11 + 1004c80: 84 82 fe a4 l.lwz r4,0xfffffea4(r2) + 1004c84: d7 e2 27 d0 l.sw 0xffffffd0(r2),r4 + 1004c88: 84 62 ff d0 l.lwz r3,0xffffffd0(r2) + 1004c8c: bc 23 00 00 l.sfnei r3,0x0 + 1004c90: 10 00 00 1d l.bf 1004d04 <_sd_controller_init+0x594> + 1004c94: 15 00 00 00 l.nop 0x0 + return dev; + 1004c98: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1004c9c: d7 e2 26 a0 l.sw 0xfffffea0(r2),r4 + 1004ca0: 84 82 fe a0 l.lwz r4,0xfffffea0(r2) + 1004ca4: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004ca8: d4 03 20 00 l.sw 0x0(r3),r4 + 1004cac: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004cb0: d7 e2 1e 9c l.sw 0xfffffe9c(r2),r3 + 1004cb4: 84 62 fe 9c l.lwz r3,0xfffffe9c(r2) + 1004cb8: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004cbc: d4 04 18 04 l.sw 0x4(r4),r3 + 1004cc0: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1004cc4: d7 e2 26 98 l.sw 0xfffffe98(r2),r4 + 1004cc8: 84 82 fe 98 l.lwz r4,0xfffffe98(r2) + 1004ccc: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004cd0: d4 03 20 08 l.sw 0x8(r3),r4 + 1004cd4: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004cd8: d7 e2 1e 94 l.sw 0xfffffe94(r2),r3 + 1004cdc: 84 62 fe 94 l.lwz r3,0xfffffe94(r2) + 1004ce0: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004ce4: d4 04 18 0c l.sw 0xc(r4),r3 + 1004ce8: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 1004cec: d7 e2 26 90 l.sw 0xfffffe90(r2),r4 + 1004cf0: 84 82 fe 90 l.lwz r4,0xfffffe90(r2) + 1004cf4: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004cf8: d4 03 20 10 l.sw 0x10(r3),r4 + 1004cfc: 00 00 00 33 l.j 1004dc8 <_sd_controller_init+0x658> + 1004d00: 15 00 00 00 l.nop 0x0 + rtn_reg = SD_REG(SD_RESP1); + 1004d04: 18 60 a0 00 l.movhi r3,0xa000 + 1004d08: d7 e2 1e 8c l.sw 0xfffffe8c(r2),r3 + 1004d0c: 84 82 fe 8c l.lwz r4,0xfffffe8c(r2) + 1004d10: a8 84 00 0c l.ori r4,r4,0xc + 1004d14: d7 e2 27 d4 l.sw 0xffffffd4(r2),r4 + 1004d18: 84 62 ff d4 l.lwz r3,0xffffffd4(r2) + 1004d1c: 84 63 00 00 l.lwz r3,0x0(r3) + 1004d20: d7 e2 1f d8 l.sw 0xffffffd8(r2),r3 + 1004d24: 84 82 ff d8 l.lwz r4,0xffffffd8(r2) + 1004d28: d7 e2 27 e8 l.sw 0xffffffe8(r2),r4 + dev.rca = ((rtn_reg&RCA_RCA_MASK)); + 1004d2c: 84 62 ff e8 l.lwz r3,0xffffffe8(r2) + 1004d30: d7 e2 1f dc l.sw 0xffffffdc(r2),r3 + 1004d34: 18 60 ff ff l.movhi r3,0xffff + 1004d38: 84 82 ff dc l.lwz r4,0xffffffdc(r2) + 1004d3c: e0 64 18 03 l.and r3,r4,r3 + 1004d40: d7 e2 1f e0 l.sw 0xffffffe0(r2),r3 + 1004d44: 84 82 ff e0 l.lwz r4,0xffffffe0(r2) + 1004d48: d7 e2 27 ec l.sw 0xffffffec(r2),r4 + + dev.Active=1; + 1004d4c: 9c 60 00 01 l.addi r3,r0,0x1 + 1004d50: d7 e2 1e 88 l.sw 0xfffffe88(r2),r3 + 1004d54: 84 82 fe 88 l.lwz r4,0xfffffe88(r2) + 1004d58: db e2 26 87 l.sb 0xfffffe87(r2),r4 + 1004d5c: 8c 62 fe 87 l.lbz r3,0xfffffe87(r2) + 1004d60: db e2 1f f5 l.sb 0xfffffff5(r2),r3 + return dev; + 1004d64: 84 82 ff ec l.lwz r4,0xffffffec(r2) + 1004d68: d7 e2 26 80 l.sw 0xfffffe80(r2),r4 + 1004d6c: 84 82 fe 80 l.lwz r4,0xfffffe80(r2) + 1004d70: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004d74: d4 03 20 00 l.sw 0x0(r3),r4 + 1004d78: 84 62 ff f0 l.lwz r3,0xfffffff0(r2) + 1004d7c: d7 e2 1e 7c l.sw 0xfffffe7c(r2),r3 + 1004d80: 84 62 fe 7c l.lwz r3,0xfffffe7c(r2) + 1004d84: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004d88: d4 04 18 04 l.sw 0x4(r4),r3 + 1004d8c: 84 82 ff f4 l.lwz r4,0xfffffff4(r2) + 1004d90: d7 e2 26 78 l.sw 0xfffffe78(r2),r4 + 1004d94: 84 82 fe 78 l.lwz r4,0xfffffe78(r2) + 1004d98: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004d9c: d4 03 20 08 l.sw 0x8(r3),r4 + 1004da0: 84 62 ff f8 l.lwz r3,0xfffffff8(r2) + 1004da4: d7 e2 1e 74 l.sw 0xfffffe74(r2),r3 + 1004da8: 84 62 fe 74 l.lwz r3,0xfffffe74(r2) + 1004dac: 84 82 ff 48 l.lwz r4,0xffffff48(r2) + 1004db0: d4 04 18 0c l.sw 0xc(r4),r3 + 1004db4: 84 82 ff fc l.lwz r4,0xfffffffc(r2) + 1004db8: d7 e2 26 70 l.sw 0xfffffe70(r2),r4 + 1004dbc: 84 82 fe 70 l.lwz r4,0xfffffe70(r2) + 1004dc0: 84 62 ff 48 l.lwz r3,0xffffff48(r2) + 1004dc4: d4 03 20 10 l.sw 0x10(r3),r4 + +} + 1004dc8: 85 62 ff 48 l.lwz r11,0xffffff48(r2) + 1004dcc: 85 21 00 00 l.lwz r9,0x0(r1) + 1004dd0: 84 41 00 04 l.lwz r2,0x4(r1) + 1004dd4: 44 00 48 00 l.jr r9 + 1004dd8: 9c 21 01 98 l.addi r1,r1,0x198 Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/uart.h (revision 11) @@ -0,0 +1,190 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : uart.h +// Prepared By : jb +// Project Start : 2009-01-01 +// Sourced from OpenCores : http://opencores.org/cvsweb.shtml/or1k/orp/orp_soc/sw/uart/uart.h + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// UART register definitions, function prototypes + +/*$$PROTOTYPES*/ +/******************************************************************************/ +/* */ +/* P R O T O T Y P E S */ +/* */ +/******************************************************************************/ + +extern void uart_init(void); +extern void uart_putc(char); +extern char uart_getc(void); +extern void uart_print_str(char *); +extern void uart_print_long(unsigned long); + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +#if 1 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 1 /* Out: Interrupt Enable Register */ +#define UART_IIR 2 /* In: Interrupt ID Register */ +#define UART_FCR 2 /* Out: FIFO Control Register */ +#define UART_EFR 2 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ +#define UART_LCR 3 /* Out: Line Control Register */ +#define UART_MCR 4 /* Out: Modem Control Register */ +#define UART_LSR 5 /* In: Line Status Register */ +#define UART_MSR 6 /* In: Modem Status Register */ +#define UART_SCR 7 /* I/O: Scratch Register */ + +#else + +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ +#define UART_DLM 4 /* Out: Divisor Latch High (DLAB=1) */ +#define UART_IER 4 /* Out: Interrupt Enable Register */ +#define UART_IIR 8 /* In: Interrupt ID Register */ +#define UART_FCR 8 /* Out: FIFO Control Register */ +#define UART_EFR 8 /* I/O: Extended Features Register */ + /* (DLAB=1, 16C660 only) */ +#define UART_LCR 12 /* Out: Line Control Register */ +#define UART_MCR 12 /* Out: Modem Control Register */ +#define UART_LSR 20 /* In: Line Status Register */ +#define UART_MSR 24 /* In: Modem Status Register */ +#define UART_SCR 28 /* I/O: Scratch Register */ + +#endif + +/* + * These are the definitions for the FIFO Control Register + * (16650 only) + */ +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ +/* 16650 redefinitions */ +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ + +/* + * These are the definitions for the Line Control Register + * + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. + */ +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ +#define UART_LCR_SBC 0x40 /* Set break control */ +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ +#define UART_LCR_EPAR 0x10 /* Even parity select */ +#define UART_LCR_PARITY 0x08 /* Parity Enable */ +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ + +/* + * These are the definitions for the Line Status Register + */ +#define UART_LSR_TEMT 0x40 /* Transmitter empty */ +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ +#define UART_LSR_BI 0x10 /* Break interrupt indicator */ +#define UART_LSR_FE 0x08 /* Frame error indicator */ +#define UART_LSR_PE 0x04 /* Parity error indicator */ +#define UART_LSR_OE 0x02 /* Overrun error indicator */ +#define UART_LSR_DR 0x01 /* Receiver data ready */ + +/* + * These are the definitions for the Interrupt Identification Register + */ +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ + +#define UART_IIR_MSI 0x00 /* Modem status interrupt */ +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ +#define UART_IIR_TOI 0x0c /* Receive time out interrupt */ +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ + +/* + * These are the definitions for the Interrupt Enable Register + */ +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ + +/* + * These are the definitions for the Modem Control Register + */ +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_OUT2 0x08 /* Out2 complement */ +#define UART_MCR_OUT1 0x04 /* Out1 complement */ +#define UART_MCR_RTS 0x02 /* RTS complement */ +#define UART_MCR_DTR 0x01 /* DTR complement */ + +/* + * These are the definitions for the Modem Status Register + */ +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ +#define UART_MSR_RI 0x40 /* Ring Indicator */ +#define UART_MSR_DSR 0x20 /* Data Set Ready */ +#define UART_MSR_CTS 0x10 /* Clear to Send */ +#define UART_MSR_DDCD 0x08 /* Delta DCD */ +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ +#define UART_MSR_DDSR 0x02 /* Delta DSR */ +#define UART_MSR_DCTS 0x01 /* Delta CTS */ +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ + +/* + * These are the definitions for the Extended Features Register + * (StarTech 16C660 only, when DLAB=1) + */ +#define UART_EFR_CTS 0x80 /* CTS flow control */ +#define UART_EFR_RTS 0x40 /* RTS flow control */ +#define UART_EFR_SCD 0x20 /* Special character detect */ +#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */ + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ny fil.c (revision 11) @@ -0,0 +1,327 @@ +******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : main.c +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Perform some simple functions, used as an example when first using the +// debug cable and proxy with GDB. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#define INCLUDED_FROM_C_FILE + +#include "orsocdef.h" +#include "board.h" +#include "uart.h" +#include "sd_controller.h" +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +/*$$GLOBAL VARIABLES*/ +/******************************************************************************/ +/* */ +/* G L O B A L V A R I A B L E S */ +/* */ +/******************************************************************************/ + +/*$$PRIVATE VARIABLES*/ +/******************************************************************************/ +/* */ +/* P R I V A T E V A R I A B L E S */ +/* */ +/******************************************************************************/ + + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + uint32 i; + uint32 read; + uint32 range; + uint32 adr_offset; + + range = 0x7ff; // Max range: 0x7fffff + adr_offset = 0x00000000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + if (read != (adr_offset + i)) { + while(TRUE){ //ERROR=HALT PROCESSOR + } + } + } +} + + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + + +void external_exeption() +{ + REG uint8 i; + REG uint32 PicSr,sr; + +} + +/*$$MAIN*/ +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ +typdef struct { +unsigned int RCA; +unsigned long Voltage_window; +bool HCS; +bool Active; +bool phys_spec_2_0; +sd_card_cid * cid_reg; +sd_card_csd * csd_reg; + +} sd_card; + + +typdef struct { +unsigned short int MID; +unsigned char OID[2]; +unsigned char PNM[5]; +unsigned short int BCD; +unsigned short int MDT; +unsigned long PSN; +} sd_card_cid; + +typdef struct { + + +} sd_card_csd; + + +typdef struct { +unsigned int CMDI:6; +unsigned int CMDT:2; +unsigned int DPS:1; +unsigned int CICE:1; +unsigned int CRCE:1; +unsigned int RSVD:1; +unsigned int RTS:2; +} sd_controller_csr; + + +sd_card* sd_controller_init () +{ +sd_card dev; + +return dev; + +} + + +send_cmd (unsigned long *arg, sd_controller_csr *set) +{ + + +} + +void Start() +{ + sd_card *sd_card_0; + *sd_card_0 = sd_controller_init(); + + + volatile unsigned long rtn_reg=0; + volatile unsigned long rtn_reg1=0; + + unsigned long a=0x80000000; + unsigned long b=0x0001; + + unsigned long test=0x0000F0FF; + // Send out something over UART + uart_init(); + if ( (a & b) == 0x80000000) + uart_print_str("Hello mask\n"); + + + uart_print_str("Hello World5!\n"); + uart_print_str("Echoing received chars...\n\r"); + uart_print_str("Print long \n"); + + uart_print_str("Status Reg \n"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_STATUS) ; + uart_print_long(rtn_reg); + uart_print_str("\n"); + + uart_print_str("Normal status Reg \n"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS ); + uart_print_long(rtn_reg); + uart_print_str("\n"); + + REG32(SD_CONTROLLER_BASE+SD_TIMEOUT)=0x0000007F; + + /* CMD08 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000081A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x000001AA; + + + + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + + + uart_print_str("1Response inc"); + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + uart_print_long(rtn_reg); + uart_print_str("\n"); + + */ + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x000; + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000; + + + rtn_reg=0; + while ((rtn_reg & 0x80000000) != 0x80000000) + { + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000371A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x0000FFFF; + REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS) =0; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + //Put some CRC, timeout and indexcheck here + + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x0000291A; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x00000000; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + + rtn_reg= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + + } + + + rtn_reg=0; + + REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS)=0; + + REG32(SD_CONTROLLER_BASE+SD_COMMAND) =0x00000209; + REG32(SD_CONTROLLER_BASE+SD_ARG) =0x00000000; + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + while ( (rtn_reg1 & b) !=1){ + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_NORMAL_INT_STATUS) ; + } + + uart_print_str("cid crc"); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_ERROR_INT_STATUS) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r1 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP1) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r2 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP2) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r3 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP3) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + uart_print_str("r4 "); + rtn_reg1= REG32(SD_CONTROLLER_BASE+SD_RESP4) ; + uart_print_long(rtn_reg1); + uart_print_str("\n"); + + + + + while(1){ + + } + + +} + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/main.c =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/main.c (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/main.c (revision 11) @@ -0,0 +1,396 @@ + + +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : main.c +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Perform some simple functions, used as an example when first using the +// debug cable and proxy with GDB. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#define INCLUDED_FROM_C_FILE + +#include "orsocdef.h" +#include "board.h" +#include "uart.h" +#include "sd_controller.h" +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +/*$$GLOBAL VARIABLES*/ +/******************************************************************************/ +/* */ +/* G L O B A L V A R I A B L E S */ +/* */ +/******************************************************************************/ + +/*$$PRIVATE VARIABLES*/ +/******************************************************************************/ +/* */ +/* P R I V A T E V A R I A B L E S */ +/* */ +/******************************************************************************/ + + +/*$$FUNCTIONS*/ +/******************************************************************************/ +/* */ +/* F U N C T I O N S */ +/* */ +/******************************************************************************/ + + +/******************************************************************************/ +/* W R I T E T O EXTERNAL SDRAM 1 */ +/******************************************************************************/ + +// Write to External SDRAM +void Write_External_SDRAM_1(void) +{ + uint32 i; + uint32 read; + uint32 range; + uint32 adr_offset; + + range = 0x7ff; // Max range: 0x7fffff + adr_offset = 0x00000000; // External memory offset + + for (i=0x0; i < range; i=i+4) { + REG32(adr_offset + i) = (adr_offset + i); + } + + for (i=0x0; i < range; i=i+4) { + read = REG32(adr_offset + i); + if (read != (adr_offset + i)) { + while(TRUE){ //ERROR=HALT PROCESSOR + } + } + } +} + + +/*$$EXTERNAL EXEPTIONS*/ +/******************************************************************************/ +/* E X T E R N A L E X E P T I O N S */ +/******************************************************************************/ + + +void external_exeption() +{ + REG uint8 i; + REG uint32 PicSr,sr; + +} + +/*$$MAIN*/ +/******************************************************************************/ +/* */ +/* M A I N P R O G R A M */ +/* */ +/******************************************************************************/ + +struct sd_card_csr { +unsigned int PAD:18; +unsigned int CMDI:6; +unsigned int CMDT:2; +unsigned int DPS:1; +unsigned int CICE_s:1; +unsigned int CRCE_s:1; +unsigned int RSVD:1; +unsigned int RTS:2; +} ; + + + + + +//TO do +// Always check if error in repose (CRC, CICE) etc +// Always check for CICM (Command inhibit before senindg) +// Timeout when polling +// Divied into dividing Functions +// Clean up + + +#define BOTH + + +void Start() +{ + struct sd_card_csr *sd_set_reg = (struct sd_card_csr *) (SD_CONTROLLER_BASE+SD_COMMAND); + + volatile unsigned long rtn_reg=0; + volatile unsigned long rtn_reg1=0; + int i; + unsigned char block[512]; + unsigned char blockb[512]; + unsigned long b=0x0001; + sd_card sd_card_0; + for (i =0; i<512;i++) + blockb[i]=i; + + uart_init(); + sd_card_0 = sd_controller_init(); //Initiate card + // Send out something over UART + + + if (sd_card_0.Active==1) + { + uart_print_str("Init 2 succes!\n"); + uart_print_str("\nvoltage_windows:\n"); + uart_print_long(sd_card_0.Voltage_window); + uart_print_str("\nRCA_Nr:\n"); + uart_print_long(sd_card_0.rca); + uart_print_str("\nphys_spec_2_0 Y/N 1/0? :\n"); + uart_print_long(sd_card_0.phys_spec_2_0); + uart_print_str("\nHCS? :\n"); + uart_print_long(sd_card_0.phys_spec_2_0); + uart_print_str(":\n"); + } + else + uart_print_str("Init2 failed :/!\n"); + + + + //Put in transfer state, select card + set block size + + + SD_REG(SD_COMMAND) = CMD7 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=sd_card_0.rca | 0xf0f0; + if (!sd_wait_rsp()) + uart_print_str("Go send failed :/!\n"); + else if ( SD_REG(SD_RESP1) == (CARD_STATUS_STB | READY_FOR_DATA ) ) + uart_print_str("Ready to transfer data!\n"); + + //Set block size to 512 + + SD_REG(SD_COMMAND) = CMD16 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=512; + if (!sd_wait_rsp()) + uart_print_str("Go send failed :/!\n"); + + //Set Bus width to 4, CMD55 followed by ACMD 6 + REG32(SD_CONTROLLER_BASE+SD_COMMAND) = CMD55|RSP_48; + REG32(SD_CONTROLLER_BASE+SD_ARG) =sd_card_0.rca | 0xf0f0; + if (!sd_wait_rsp()) + uart_print_str("CMD55 send failed :/!\n"); + + SD_REG(SD_COMMAND) = ACMD6 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=0x2; + if (!sd_wait_rsp()) + uart_print_str("ACMD6 send failed :/!\n"); + + + + //Transfer data to addr 0 + SD_REG(BD_TX) = &blockb; + SD_REG(BD_TX) = 0; + + //Wait for send to complete + while ( ((rtn_reg &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + + SD_REG(BD_ISR) =0; + //Read from addr 0 to another array + + SD_REG(BD_RX) = █ + SD_REG(BD_RX) =0; + + + + while ( ((rtn_reg &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + + uart_print_long( SD_REG(BD_ISR) ) ; + uart_print_str("Card Status reg: \n"); + uart_print_long( SD_REG(SD_RESP1) ) ; + uart_print_str("\n"); + uart_print_long( SD_REG(BD_ISR) ) ; + uart_print_str("\n"); + + for (i =0; i<512;i++) { + uart_print_short (block[i]); + uart_print_str("."); + + } + + + + #endif + #ifdef DB_BOTH + + + + SD_REG(BD_TX) = █ + SD_REG(BD_TX) = 512; + SD_REG(BD_TX) = &blocka; + SD_REG(BD_TX) = 1024; + SD_REG(BD_TX) = &blockb; + SD_REG(BD_TX) = 2048; + + SD_REG(BD_RX) = &rec_block; + SD_REG(BD_RX) = 512; + SD_REG(BD_RX) = &rec_blocka; + SD_REG(BD_RX) = 1024; + SD_REG(BD_RX) = &rec_blockb; + SD_REG(BD_RX) = 2048; + + uart_print_str("FREE BD: \n"); + uart_print_long( SD_REG(BD_STATUS) ) ; + uart_print_str("\n"); + + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + while ( (( SD_REG(BD_ISR) &1) !=1 ) ){ + rtn_reg= SD_REG(BD_ISR) ; + } + SD_REG(BD_ISR) =0; + + + + uart_print_str("FREE BD: \n"); + uart_print_long( SD_REG(BD_STATUS) ) ; + uart_print_str("\n"); + SD_REG(BD_ISR) =0; + uart_print_long( SD_REG(BD_ISR) ) ; + uart_print_str("Card Status reg: \n"); + uart_print_long( SD_REG(SD_RESP1) ) ; + uart_print_str("\n"); + uart_print_long( SD_REG(BD_ISR) ) ; + uart_print_str("\n"); + for (i =0; i<512;i++) { + uart_print_short (rec_block[i]); + uart_print_str("."); + } + uart_print_str("\n"); + for (i =0; i<512;i++) { + uart_print_short (rec_blocka[i]); + uart_print_str("."); + } + uart_print_str("\n"); + for (i =0; i<512;i++) { + uart_print_short (rec_blockb[i]); + uart_print_str("."); + } + + + + + + + + #endif + + + + + + /* + SD_REG(SD_COMMAND) = CMD17 | CICE | CRCE | RSP_48; + SD_REG(SD_ARG)=0; + if (!sd_wait_rsp()) + uart_print_str("Go send failed :/!\n"); + + uart_print_str("Block resp:/!\n"); + uart_print_long( SD_REG(SD_RESP1) ) ; */ + + +/* + uart_print_str("\n"); + rtn_reg= SD_REG(BD_STATUS) ; + uart_print_long(rtn_reg); + + SD_REG(BD_RX) = █ + SD_REG(BD_RX) = 0; + uart_print_str("\n"); + + rtn_reg= SD_REG(BD_STATUS) ; + rtn_reg1=rtn_reg; + uart_print_long(rtn_reg); */ + + + + //while(1){ + + + + //} + + +} + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S.lowram =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S.lowram (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S.lowram (revision 11) @@ -0,0 +1,320 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : BootReset.S +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Define the contents of the reset vector (from 0x100), an IC enable routine +// as well as en external IRQ service routine. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#include "board.h" +#include "spr_defs.h" + +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */ +/******************************************************************************/ + +.macro load32i reg const + l.movhi \reg,hi(\const) + l.ori \reg,\reg,lo(\const) +.endm + +/******************************************************************************/ +/* S E T U P E X C E P T I O N V E C T O R */ +/******************************************************************************/ + +.macro exception_vector name org + .org \org + .p2align 8 + .global __exception_\name +__exception_\name: + + l.j __exception_\name + l.nop +.endm + +/******************************************************************************/ +/* B R A N C H T O N A M E */ +/******************************************************************************/ + +.macro BSR name + l.j \name + l.nop +ret_\name: +.endm + + +/*$$RESET START*/ +/******************************************************************************/ +/* */ +/* R E S E T S T A R T */ +/* */ +/******************************************************************************/ + +.section .vectors, "ax" + +.org 0x100 - 0x100 // Sector .vectors start at 0x100 + + +_reset: + +// Set stack pointer (r1) to 00003560 +// Clear all other registers + + .equ sp,0x00003560 ; + l.movhi r0,0x0000 ; #r0 = 0 + l.ori r0,r0,0x0000 ; + l.movhi r1,hi(sp) ; #r1 = sp + l.ori r1,r1,lo(sp) ; + l.or r2,r0,r0 ; #clear r2 + l.or r3,r0,r0 ; #clear r3 + l.or r4,r0,r0 ; #clear r4 + l.or r5,r0,r0 ; #clear r5 + l.or r6,r0,r0 ; #clear r6 + l.or r7,r0,r0 ; #clear r7 + l.or r8,r0,r0 ; #clear r8 + l.or r9,r0,r0 ; #clear r9 + l.or r10,r0,r0 ; #clear r10 + l.or r11,r0,r0 ; #clear r11 + l.or r12,r0,r0 ; #clear r12 + l.or r13,r0,r0 ; #clear r13 + l.or r14,r0,r0 ; #clear r14 + l.or r15,r0,r0 ; #clear r15 + l.or r16,r0,r0 ; #clear r16 + l.or r17,r0,r0 ; #clear r17 + l.or r18,r0,r0 ; #clear r18 + l.or r19,r0,r0 ; #clear r19 + l.or r20,r0,r0 ; #clear r20 + l.or r21,r0,r0 ; #clear r21 + l.or r22,r0,r0 ; #clear r22 + l.or r23,r0,r0 ; #clear r23 + l.or r24,r0,r0 ; #clear r24 + l.or r25,r0,r0 ; #clear r25 + l.or r26,r0,r0 ; #clear r26 + l.or r27,r0,r0 ; #clear r27 + l.or r28,r0,r0 ; #clear r28 + l.or r29,r0,r0 ; #clear r29 + l.or r30,r0,r0 ; #clear r30 + l.or r31,r0,r0 ; #clear r31 + + +#if IC_ENABLE == 1 /* INSTRUCTION CACHE */ + BSR ic_enable +#endif + +// Jump to start of program + + load32i r2, (_Start) + l.jr r2 + l.nop + + exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100 + exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100 + exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100 + exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100 + exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100 + exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100 + + +// Defines what will happen when an external interrupt occurs + +.org 0x800 - 0x100 + + .global __external_IRQ + +__external_IRQ: + l.addi r1,r1,-30*4 //move SP 30*4 adresses lower + + l.sw 0x1c(r1),r9 + + l.jal (save_state) + l.nop + + // we mess with r3, r4 and r9 + // + l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt + l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled + l.sfeqi r4,0 + l.bnf JUMP // external irq enabled, all ok. + l.nop + +JUMP: l.jal (_external_exeption) + l.nop + + l.jal (restore_state) + l.nop + + l.lwz r9 ,0x1c(r1) + l.addi r1,r1,30*4 //move SP 30*4 adresses lower + + //Return from exception + l.rfe + + +// Save current state (all general purpose registers) + +save_state: + l.sw 0x0(r1),r2 + l.sw 0x4(r1),r3 + l.sw 0x8(r1),r4 + l.sw 0xc(r1),r5 + l.sw 0x10(r1),r6 + l.sw 0x14(r1),r7 + l.sw 0x18(r1),r8 + l.sw 0x20(r1),r10 + l.sw 0x24(r1),r11 + l.sw 0x28(r1),r12 + l.sw 0x2c(r1),r13 + l.sw 0x30(r1),r14 + l.sw 0x34(r1),r15 + l.sw 0x38(r1),r16 + l.sw 0x3c(r1),r17 + l.sw 0x40(r1),r18 + l.sw 0x44(r1),r19 + l.sw 0x48(r1),r20 + l.sw 0x4c(r1),r21 + l.sw 0x50(r1),r22 + l.sw 0x54(r1),r23 + l.sw 0x58(r1),r24 + l.sw 0x5c(r1),r25 + l.sw 0x60(r1),r26 + l.sw 0x64(r1),r27 + l.sw 0x68(r1),r28 + l.sw 0x6c(r1),r29 + l.sw 0x70(r1),r30 + l.jr r9 + l.nop + +// Restore current state + +restore_state: + // disable interrupts (if needed) + l.lwz r2,0x0(r1) + l.lwz r3 ,0x4(r1) + l.lwz r4 ,0x8(r1) + l.lwz r5 ,0xc(r1) + l.lwz r6 ,0x10(r1) + l.lwz r7 ,0x14(r1) + l.lwz r8 ,0x18(r1) + l.lwz r10,0x20(r1) + l.lwz r11,0x24(r1) + l.lwz r12,0x28(r1) + l.lwz r13,0x2c(r1) + l.lwz r14,0x30(r1) + l.lwz r15,0x34(r1) + l.lwz r16,0x38(r1) + l.lwz r17,0x3c(r1) + l.lwz r18,0x40(r1) + l.lwz r19,0x44(r1) + l.lwz r20,0x48(r1) + l.lwz r21,0x4c(r1) + l.lwz r22,0x50(r1) + l.lwz r23,0x54(r1) + l.lwz r24,0x58(r1) + l.lwz r25,0x5c(r1) + l.lwz r26,0x60(r1) + l.lwz r27,0x64(r1) + l.lwz r28,0x68(r1) + l.lwz r29,0x6c(r1) + l.lwz r30,0x70(r1) + l.jr r9 + l.nop + + + +/*************************** + * Instruction cache enable + */ +#if IC_ENABLE == 1 +ic_enable: + + /* Disable IC */ + l.mfspr r6,r0,SPR_SR + l.addi r5,r0,-1 + l.xori r5,r5,SPR_SR_ICE + l.and r5,r6,r5 + l.mtspr r0,r5,SPR_SR + + /* Invalidate IC */ + l.addi r6,r0,0 + l.addi r5,r0,IC_SIZE +1: + l.mtspr r0,r6,SPR_ICBIR + l.sfne r6,r5 + l.bf 1b + l.addi r6,r6,IC_LINE + + /* Enable IC */ + l.mfspr r6,r0,SPR_SR + l.ori r6,r6,SPR_SR_ICE + l.mtspr r0,r6,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.j ret_ic_enable + l.nop +#endif \ No newline at end of file Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/BootReset.S (revision 11) @@ -0,0 +1,320 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : BootReset.S +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// Define the contents of the reset vector (from 0x100), an IC enable routine +// as well as en external IRQ service routine. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + + +/*$$INCLUDE FILES*/ +/******************************************************************************/ +/* */ +/* I N C L U D E F I L E S */ +/* */ +/******************************************************************************/ + +#include "board.h" +#include "spr_defs.h" + +/*$$PRIVATE MACROS*/ +/******************************************************************************/ +/* */ +/* P R I V A T E M A C R O S */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* L O A D 3 2 B I T C O N S T A N T I N T O R E G I S T E R */ +/******************************************************************************/ + +.macro load32i reg const + l.movhi \reg,hi(\const) + l.ori \reg,\reg,lo(\const) +.endm + +/******************************************************************************/ +/* S E T U P E X C E P T I O N V E C T O R */ +/******************************************************************************/ + +.macro exception_vector name org + .org \org + .p2align 8 + .global __exception_\name +__exception_\name: + + l.j __exception_\name + l.nop +.endm + +/******************************************************************************/ +/* B R A N C H T O N A M E */ +/******************************************************************************/ + +.macro BSR name + l.j \name + l.nop +ret_\name: +.endm + + +/*$$RESET START*/ +/******************************************************************************/ +/* */ +/* R E S E T S T A R T */ +/* */ +/******************************************************************************/ + +.section .vectors, "ax" + +.org 0x100 - 0x100 // Sector .vectors start at 0x100 + + +_reset: + +// Set stack pointer (r1) to 00003560 +// Clear all other registers + + .equ sp,0x00003560 ; + l.movhi r0,0x0000 ; #r0 = 0 + l.ori r0,r0,0x0000 ; + l.movhi r1,hi(sp) ; #r1 = sp + l.ori r1,r1,lo(sp) ; + l.or r2,r0,r0 ; #clear r2 + l.or r3,r0,r0 ; #clear r3 + l.or r4,r0,r0 ; #clear r4 + l.or r5,r0,r0 ; #clear r5 + l.or r6,r0,r0 ; #clear r6 + l.or r7,r0,r0 ; #clear r7 + l.or r8,r0,r0 ; #clear r8 + l.or r9,r0,r0 ; #clear r9 + l.or r10,r0,r0 ; #clear r10 + l.or r11,r0,r0 ; #clear r11 + l.or r12,r0,r0 ; #clear r12 + l.or r13,r0,r0 ; #clear r13 + l.or r14,r0,r0 ; #clear r14 + l.or r15,r0,r0 ; #clear r15 + l.or r16,r0,r0 ; #clear r16 + l.or r17,r0,r0 ; #clear r17 + l.or r18,r0,r0 ; #clear r18 + l.or r19,r0,r0 ; #clear r19 + l.or r20,r0,r0 ; #clear r20 + l.or r21,r0,r0 ; #clear r21 + l.or r22,r0,r0 ; #clear r22 + l.or r23,r0,r0 ; #clear r23 + l.or r24,r0,r0 ; #clear r24 + l.or r25,r0,r0 ; #clear r25 + l.or r26,r0,r0 ; #clear r26 + l.or r27,r0,r0 ; #clear r27 + l.or r28,r0,r0 ; #clear r28 + l.or r29,r0,r0 ; #clear r29 + l.or r30,r0,r0 ; #clear r30 + l.or r31,r0,r0 ; #clear r31 + + +#if IC_ENABLE == 1 /* INSTRUCTION CACHE */ + BSR ic_enable +#endif + +// Jump to start of program + + load32i r2, (_Start) + l.jr r2 + l.nop + + exception_vector bus_error 0x200 - 0x100 // Sector .vectors start at 0x100 + exception_vector data_page_fault 0x300 - 0x100 // Sector .vectors start at 0x100 + exception_vector instruction_page_fault 0x400 - 0x100 // Sector .vectors start at 0x100 + exception_vector tick_timer 0x500 - 0x100 // Sector .vectors start at 0x100 + exception_vector unaligned_access 0x600 - 0x100 // Sector .vectors start at 0x100 + exception_vector illegal_instruction 0x700 - 0x100 // Sector .vectors start at 0x100 + + +// Defines what will happen when an external interrupt occurs + +.org 0x800 - 0x100 + + .global __external_IRQ + +__external_IRQ: + l.addi r1,r1,-30*4 //move SP 30*4 adresses lower + + l.sw 0x1c(r1),r9 + + l.jal (save_state) + l.nop + + // we mess with r3, r4 and r9 + // + l.mfspr r3,r0,SPR_ESR_BASE // get SR before interrupt + l.andi r4,r3,SPR_SR_IEE // check if it had SPR_SR_IEE bit enabled + l.sfeqi r4,0 + l.bnf JUMP // external irq enabled, all ok. + l.nop + +JUMP: l.jal (_external_exeption) + l.nop + + l.jal (restore_state) + l.nop + + l.lwz r9 ,0x1c(r1) + l.addi r1,r1,30*4 //move SP 30*4 adresses lower + + //Return from exception + l.rfe + + +// Save current state (all general purpose registers) + +save_state: + l.sw 0x0(r1),r2 + l.sw 0x4(r1),r3 + l.sw 0x8(r1),r4 + l.sw 0xc(r1),r5 + l.sw 0x10(r1),r6 + l.sw 0x14(r1),r7 + l.sw 0x18(r1),r8 + l.sw 0x20(r1),r10 + l.sw 0x24(r1),r11 + l.sw 0x28(r1),r12 + l.sw 0x2c(r1),r13 + l.sw 0x30(r1),r14 + l.sw 0x34(r1),r15 + l.sw 0x38(r1),r16 + l.sw 0x3c(r1),r17 + l.sw 0x40(r1),r18 + l.sw 0x44(r1),r19 + l.sw 0x48(r1),r20 + l.sw 0x4c(r1),r21 + l.sw 0x50(r1),r22 + l.sw 0x54(r1),r23 + l.sw 0x58(r1),r24 + l.sw 0x5c(r1),r25 + l.sw 0x60(r1),r26 + l.sw 0x64(r1),r27 + l.sw 0x68(r1),r28 + l.sw 0x6c(r1),r29 + l.sw 0x70(r1),r30 + l.jr r9 + l.nop + +// Restore current state + +restore_state: + // disable interrupts (if needed) + l.lwz r2,0x0(r1) + l.lwz r3 ,0x4(r1) + l.lwz r4 ,0x8(r1) + l.lwz r5 ,0xc(r1) + l.lwz r6 ,0x10(r1) + l.lwz r7 ,0x14(r1) + l.lwz r8 ,0x18(r1) + l.lwz r10,0x20(r1) + l.lwz r11,0x24(r1) + l.lwz r12,0x28(r1) + l.lwz r13,0x2c(r1) + l.lwz r14,0x30(r1) + l.lwz r15,0x34(r1) + l.lwz r16,0x38(r1) + l.lwz r17,0x3c(r1) + l.lwz r18,0x40(r1) + l.lwz r19,0x44(r1) + l.lwz r20,0x48(r1) + l.lwz r21,0x4c(r1) + l.lwz r22,0x50(r1) + l.lwz r23,0x54(r1) + l.lwz r24,0x58(r1) + l.lwz r25,0x5c(r1) + l.lwz r26,0x60(r1) + l.lwz r27,0x64(r1) + l.lwz r28,0x68(r1) + l.lwz r29,0x6c(r1) + l.lwz r30,0x70(r1) + l.jr r9 + l.nop + + + +/*************************** + * Instruction cache enable + */ +#if IC_ENABLE == 1 +ic_enable: + + /* Disable IC */ + l.mfspr r6,r0,SPR_SR + l.addi r5,r0,-1 + l.xori r5,r5,SPR_SR_ICE + l.and r5,r6,r5 + l.mtspr r0,r5,SPR_SR + + /* Invalidate IC */ + l.addi r6,r0,0 + l.addi r5,r0,IC_SIZE +1: + l.mtspr r0,r6,SPR_ICBIR + l.sfne r6,r5 + l.bf 1b + l.addi r6,r6,IC_LINE + + /* Enable IC */ + l.mfspr r6,r0,SPR_SR + l.ori r6,r6,SPR_SR_ICE + l.mtspr r0,r6,SPR_SR + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.nop + l.j ret_ic_enable + l.nop +#endif \ No newline at end of file Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ram.ld =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ram.ld (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/ram.ld (revision 11) @@ -0,0 +1,68 @@ +/* Linker script for OR1200 program */ + +/* Linking for loading into high SDRAM */ + +MEMORY +{ + ld_info : ORIGIN = 0x01000000, LENGTH = 0x000000F0 + vectors : ORIGIN = 0x01000100, LENGTH = 0x00000D00 - 0x100 + flash : ORIGIN = 0x01000D00, LENGTH = 0x00002000 - 0x0A00 + ram : ORIGIN = 0x01003000, LENGTH = 0x00fffff0 +} + + +/* Linking for loading into external SDRAM */ + +/* +MEMORY +{ + ld_info : ORIGIN = 0x00000000, LENGTH = 0x000000F0 + vectors : ORIGIN = 0x00000100, LENGTH = 0x00000D00 - 0x100 + flash : ORIGIN = 0x00000D00, LENGTH = 0x00002000 - 0x0A00 + ram : ORIGIN = 0x00003000, LENGTH = 0x00001000 +} +*/ +/* + The following section defines where to put the different input sections. + .text contains the code. + .data contains the initialized data. + .bss contains uninitialized data. + .sdata contains small constant data. +*/ + +SECTIONS +{ + +/* + .ld_info : + { + revision.o(.data) + } > ld_info +*/ + .vectors : { *(.vectors) } > vectors + + .text : { *(.text) } > ram + .rodata : { *(.rodata)} > ram + .data : { *(.data) } > ram + .bss : { *(.bss) } > ram + + .stack : + { + __STACK_TOP = . ; + . = . + 0x00000500; + __STACK_BOTTOM = . ; + } > ram +} + +/* + Definitions of identifiers that control initialization and memory allocation: + These two symbols must be present. + __BSS_START : Start of uninitialized data + __BSS_END : End of data to be cleared +*/ + +__CODE_START = ADDR( .text ); +__CODE_END = ADDR( .text ) + SIZEOF( .text ); + +__DATA_START = ADDR( .bss ); +__DATA_END = ADDR( .bss ) + SIZEOF( .bss ); Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/Makefile =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/Makefile (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/Makefile (revision 11) @@ -0,0 +1,57 @@ +ifndef CROSS_COMPILE +#CROSS_COMPILE = or32-elf- +#Changed 2007-11-17 svenand +CROSS_COMPILE = or32-uclinux- +CC = $(CROSS_COMPILE)gcc +LD = $(CROSS_COMPILE)ld +NM = $(CROSS_COMPILE)nm +OBJ = $(CROSS_COMPILE)objdump +OBJC = $(CROSS_COMPILE)objcopy +endif + +#entry point for program +#0 for sdram, 0x93... for internal SRAM +#LD_ENTRY_POINT=0x00000100 +LD_ENTRY_POINT=0x01000100 + +CFLAGS = -g -c -Wunknown-pragmas -mhard-mul -msoft-div -msoft-float +LD_FLAGS= --stats -Tram.ld -e ${LD_ENTRY_POINT} +INCL = board.h spr_defs.h +OBJECTS = BootReset.o main.o uart.o sd_controller.o +LIBS = + +export CROSS_COMPILE + +all: boot.or32 System.map + +boot.or32: $(OBJECTS) Makefile + @printf "\r\n\t--- Linking ---\r\n" + $(LD) -Map System.map -Bstatic $(OBJECTS) $(LIBS) $(LD_FLAGS) -o $@ + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort >> System.map + $(OBJ) -x -d -S boot.or32 >> System.map + +%.o:%.S $(INCL) Makefile + @printf "\r\n\t--- Assembling $(<) ---\r\n" + $(CC) $(CFLAGS) -o $@ $(<) + +%.o:%.c $(INCL) Makefile + @printf "\r\n\t--- Compiling $(<) ---\r\n" + $(CC) $(CFLAGS) -o $@ $(<) + + +######################################################################### + +clean: + @rm -f *.o *.ihex *.BIN boot.* System.map *.vmem *.bin *.asm *~ + +distclean: clean + find . -type f \ + \( -name .depend -o -name '*.srec' -o -name '*.bin' \ + -o -name '*.pdf' \) \ + -print | xargs rm -f + rm -f $(OBJS) *.bak tags TAGS + rm -fr *.*~ + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/board.h =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/board.h (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/sw/board.h (revision 11) @@ -0,0 +1,139 @@ +/*$$HEADER*/ +/******************************************************************************/ +/* */ +/* H E A D E R I N F O R M A T I O N */ +/* */ +/******************************************************************************/ + +// Project Name : Development Board Debugger Example +// File Name : board.h +// Prepared By : jb +// Project Start : 2009-01-01 + + +/*$$COPYRIGHT NOTICE*/ +/******************************************************************************/ +/* */ +/* C O P Y R I G H T N O T I C E */ +/* */ +/******************************************************************************/ + +// Copyright (c) ORSoC 2009 All rights reserved. + +// The information in this document is the property of ORSoC. +// Except as specifically authorized in writing by ORSoC, the receiver of +// this document shall keep the information contained herein confidential and +// shall protect the same in whole or in part thereof from disclosure and +// dissemination to third parties. Disclosure and disseminations to the receiver's +// employees shall only be made on a strict need to know basis. + + +/*$$DESCRIPTION*/ +/******************************************************************************/ +/* */ +/* D E S C R I P T I O N */ +/* */ +/******************************************************************************/ + +// This file contains definitions for the FPGA board used. + +/*$$CHANGE HISTORY*/ +/******************************************************************************/ +/* */ +/* C H A N G E H I S T O R Y */ +/* */ +/******************************************************************************/ + +// Date Version Description +//------------------------------------------------------------------------ +// 090101 1.0 First version jb + +/*$$DEFINES*/ +/******************************************************************************/ +/* */ +/* D E F I N E S */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* S Y S T E M C L O C K F R E Q . */ +/******************************************************************************/ +#define IN_CLK 25000000 // 25MHz + +/******************************************************************************/ +/* S D R A M */ +/******************************************************************************/ + +//#define SDRAM_BASE 0x00000000 +//#define SDRAM_SIZE 0x02000000 // 32-MByte +//#define SDRAM_END SDRAM_BASE + SDRAM_SIZE - 1 + +/******************************************************************************/ +/* G P I O */ +/******************************************************************************/ +// Not present in the current design +/* +#define GPIO_BASE 0x9A000000 // General purpose IO base address +#define RGPIO_IN 0x0 // GPIO input data +#define RGPIO_OUT 0x4 // GPIO output data +#define RGPIO_OE 0x8 // GPIO output enable +#define RGPIO_INTE 0xC // GPIO interrupt enable +#define RGPIO_PTRIG 0x10 // Type of event that triggers an IRQ +#define RGPIO_AUX 0x14 // +#define RGPIO_CTRL 0x18 // GPIO control register +#define RGPIO_INTS 0x1C // Interupt status +#define RGPIO_ECLK 0x20 // Enable gpio_eclk to latch RGPIO_IN +#define RGPIO_NEC 0x24 // Select active edge of gpio_eclk +*/ +/******************************************************************************/ +/* U A R T */ +/******************************************************************************/ +//#define UART_BAUD_RATE 19200 +#define UART_BAUD_RATE 115200 +#define UART_BASE 0x90000000 +#define UART_IRQ 19 + +/******************************************************************************/ +/* SD_CONTROLLER */ +/******************************************************************************/ +#define SD_CONTROLLER_BASE 0xa0000000 + + + +/*$$TYPEDEFS*/ +/******************************************************************************/ +/* */ +/* T Y P E D E F S */ +/* */ +/******************************************************************************/ + +#ifdef INCLUDED_FROM_C_FILE + + #define LOAD_INFO_STR + + typedef struct load_info + { + unsigned long boardtype; // + unsigned long decompressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long compressed_crc; // Filled in by ext. program for generating SRecord file + unsigned long decompressed_size; // Filled in by ext. program for generating SRecord file + unsigned long compressed_size; // Filled in by ext. program for generating SRecord file + unsigned long extra_pad[23]; // Extra padding + unsigned char boardName[12]; // + unsigned char caaName[20]; // + unsigned char caaRev[8]; // + unsigned char addInfo[16]; // + + } LOAD_INFO; + + + typedef unsigned char BYTE; /* 8 bits */ + typedef unsigned short WORD; /* 16 bits */ + typedef unsigned long LONG_WORD; /* 32 bits */ + +#endif + +#ifndef REG + #define REG register +#endif + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.sdc =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.sdc (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.sdc (revision 11) @@ -0,0 +1,91 @@ +################################################################################ +# SDC WRITER VERSION "3.1"; +# DESIGN "ref_design_top"; +# Timing constraints scenario: "Primary"; +# DATE "Sun Mar 01 09:53:11 2009"; +# VENDOR "Actel"; +# PROGRAM "Actel Designer Software Release v8.5"; +# VERSION "8.5.0.34" Copyright (C) 1989-2008 Actel Corp. +################################################################################ + + +set sdc_version 1.7 + + +######## Clock Constraints ######## + +create_clock -name { clk_i } -period 40.000 -waveform { 0.000 20.000 } { clk_pad_i } + +create_clock -name { tck } -period 83.333 -waveform { 0.000 41.667 } { dbg_tck_pad_i } + + + + +######## Generated Clock Constraints ######## + +create_generated_clock -name { iclk_gen/Core:GLA } -divide_by 25 -multiply_by 25 -source { iclk_gen/Core:CLKA } { iclk_gen/Core:GLA } +# +# *** Note *** SmartTime supports extensions to the create_generated_clock constraint supported by SDC, +# Extensions to this constraint may not be accepted by tools other than Actel's + +create_generated_clock -name { iclk_gen/Core:GLB } -divide_by 25 -multiply_by 48 -source { iclk_gen/Core:CLKA } { iclk_gen/Core:GLB } +# +# *** Note *** SmartTime supports extensions to the create_generated_clock constraint supported by SDC, +# Extensions to this constraint may not be accepted by tools other than Actel's + + + +######## Clock Source Latency Constraints ######### + + + +######## Input Delay Constraints ######## + + + + + +######## Output Delay Constraints ######## + +set_output_delay -max 33.000 -clock { iclk_gen/Core:GLA } [get_ports { mem_adr_pad_o mem_adr_pad_o[0] mem_adr_pad_o[10] mem_adr_pad_o[11] mem_adr_pad_o[12] mem_adr_pad_o[1] mem_adr_pad_o[2] mem_adr_pad_o[3] mem_adr_pad_o[4] mem_adr_pad_o[5] mem_adr_pad_o[6] mem_adr_pad_o[7] mem_adr_pad_o[8] mem_adr_pad_o[9] mem_ba_pad_o mem_ba_pad_o[0] mem_ba_pad_o[1] mem_cas_pad_o mem_cke_pad_o mem_cs_pad_o mem_dat_pad_io mem_dat_pad_io[0] mem_dat_pad_io[10] mem_dat_pad_io[11] mem_dat_pad_io[12] mem_dat_pad_io[13] mem_dat_pad_io[14] mem_dat_pad_io[15] mem_dat_pad_io[1] mem_dat_pad_io[2] mem_dat_pad_io[3] mem_dat_pad_io[4] mem_dat_pad_io[5] mem_dat_pad_io[6] mem_dat_pad_io[7] mem_dat_pad_io[8] mem_dat_pad_io[9] mem_dqm_pad_o mem_dqm_pad_o[0] mem_dqm_pad_o[1] mem_ras_pad_o mem_we_pad_o }] + +set_output_delay -min -1.000 -clock { iclk_gen/Core:GLA } [get_ports { mem_adr_pad_o mem_adr_pad_o[0] mem_adr_pad_o[10] mem_adr_pad_o[11] mem_adr_pad_o[12] mem_adr_pad_o[1] mem_adr_pad_o[2] mem_adr_pad_o[3] mem_adr_pad_o[4] mem_adr_pad_o[5] mem_adr_pad_o[6] mem_adr_pad_o[7] mem_adr_pad_o[8] mem_adr_pad_o[9] mem_ba_pad_o mem_ba_pad_o[0] mem_ba_pad_o[1] mem_cas_pad_o mem_cke_pad_o mem_cs_pad_o mem_dat_pad_io mem_dat_pad_io[0] mem_dat_pad_io[10] mem_dat_pad_io[11] mem_dat_pad_io[12] mem_dat_pad_io[13] mem_dat_pad_io[14] mem_dat_pad_io[15] mem_dat_pad_io[1] mem_dat_pad_io[2] mem_dat_pad_io[3] mem_dat_pad_io[4] mem_dat_pad_io[5] mem_dat_pad_io[6] mem_dat_pad_io[7] mem_dat_pad_io[8] mem_dat_pad_io[9] mem_dqm_pad_o mem_dqm_pad_o[0] mem_dqm_pad_o[1] mem_ras_pad_o mem_we_pad_o }] + + + + + +######## Delay Constraints ######## + + + +######## Delay Constraints ######## + + + +######## Multicycle Constraints ######## + + + +######## False Path Constraints ######## + + + +######## Output load Constraints ######## + + + +######## Disable Timing Constraints ######### + + + +######## Clock Uncertainty Constraints ######### + +set_clock_uncertainty 0.4 -from { clk_i } -to { iclk_gen/Core:GLA iclk_gen/Core:GLB } +# PLL tracking jitter + +set_clock_uncertainty 0.4 -from { iclk_gen/Core:GLA iclk_gen/Core:GLB } -to { clk_i } +# PLL tracking jitter + + + Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/data/ref_design_top.pdc.ce =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/data/ref_design_top.pdc.ce =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/data/ref_design_top.pdc.ce (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/data/ref_design_top.pdc.ce (revision 11)
sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/data/ref_design_top.pdc.ce Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.pdc =================================================================== --- sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.pdc (nonexistent) +++ sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk/syn/ref_design_top.pdc (revision 11) @@ -0,0 +1,99 @@ +# Actel Physical design constraints file + +# Version: 8.5 8.5.0.34 + +# Design Name: ref_design_top + +# Input Netlist Format: edif + +# Family: ProASIC3 , Die: A3P1000 , Package: 208 PQFP , Speed grade: STD + +# Date generated: Sun Mar 01 10:03:16 2009 + + +# +# IO banks setting +# + +set_iobank Bank3 -vcci 3.30 -fixed no +set_iobank Bank2 -vcci 3.30 -fixed no +set_iobank Bank1 -vcci 3.30 -fixed no +set_iobank Bank0 -vcci 3.30 -fixed no + +# +# Local clock constraints +# + +assign_quadrant_clock -net dbg_tck -quadrant LR -fixed yes -color 16744448 + +# +# Region constraints +# + + +# +# I/O constraints +# + +set_io clk_pad_i -pinname 30 -fixed yes +set_io dbg_tck_pad_i -pinname 98 -fixed yes +set_io dbg_tdi_pad_i -pinname 95 -fixed yes +set_io dbg_tdo_pad_o -pinname 94 -fixed yes +set_io dbg_tms_pad_i -pinname 93 -fixed yes +set_io gpio_a_pad_io\[0\] -pinname 74 -fixed yes +set_io gpio_a_pad_io\[1\] -pinname 75 -fixed yes +set_io gpio_a_pad_io\[2\] -pinname 76 -fixed yes +set_io gpio_a_pad_io\[3\] -pinname 77 -fixed yes +set_io gpio_a_pad_io\[4\] -pinname 78 -fixed yes +set_io gpio_a_pad_io\[5\] -pinname 79 -fixed yes +set_io gpio_a_pad_io\[6\] -pinname 80 -fixed yes +set_io gpio_a_pad_io\[7\] -pinname 82 -fixed yes +set_io mem_adr_pad_o\[0\] -REGISTER Yes -pinname 194 -fixed yes +set_io mem_adr_pad_o\[1\] -REGISTER Yes -pinname 197 -fixed yes +set_io mem_adr_pad_o\[2\] -REGISTER Yes -pinname 199 -fixed yes +set_io mem_adr_pad_o\[3\] -REGISTER Yes -pinname 202 -fixed yes +set_io mem_adr_pad_o\[4\] -REGISTER Yes -pinname 203 -fixed yes +set_io mem_adr_pad_o\[5\] -REGISTER Yes -pinname 201 -fixed yes +set_io mem_adr_pad_o\[6\] -REGISTER Yes -pinname 198 -fixed yes +set_io mem_adr_pad_o\[7\] -REGISTER Yes -pinname 196 -fixed yes +set_io mem_adr_pad_o\[8\] -REGISTER Yes -pinname 193 -fixed yes +set_io mem_adr_pad_o\[9\] -REGISTER Yes -pinname 191 -fixed yes +set_io mem_adr_pad_o\[10\] -REGISTER Yes -pinname 192 -fixed yes +set_io mem_adr_pad_o\[11\] -REGISTER Yes -pinname 189 -fixed yes +set_io mem_adr_pad_o\[12\] -REGISTER Yes -pinname 185 -fixed yes +set_io mem_ba_pad_o\[0\] -REGISTER Yes -pinname 188 -fixed yes +set_io mem_ba_pad_o\[1\] -REGISTER Yes -pinname 190 -fixed yes +set_io mem_cas_pad_o -REGISTER Yes -pinname 181 -fixed yes +set_io mem_cke_pad_o -pinname 183 -fixed yes +set_io mem_cs_pad_o -REGISTER Yes -pinname 184 -fixed yes +set_io mem_dat_pad_io\[0\] -REGISTER Yes -pinname 152 -fixed yes +set_io mem_dat_pad_io\[1\] -REGISTER Yes -pinname 160 -fixed yes +set_io mem_dat_pad_io\[2\] -REGISTER Yes -pinname 163 -fixed yes +set_io mem_dat_pad_io\[3\] -REGISTER Yes -pinname 165 -fixed yes +set_io mem_dat_pad_io\[4\] -REGISTER Yes -pinname 167 -fixed yes +set_io mem_dat_pad_io\[5\] -REGISTER Yes -pinname 169 -fixed yes +set_io mem_dat_pad_io\[6\] -REGISTER Yes -pinname 173 -fixed yes +set_io mem_dat_pad_io\[7\] -REGISTER Yes -pinname 175 -fixed yes +set_io mem_dat_pad_io\[8\] -REGISTER Yes -pinname 176 -fixed yes +set_io mem_dat_pad_io\[9\] -REGISTER Yes -pinname 174 -fixed yes +set_io mem_dat_pad_io\[10\] -REGISTER Yes -pinname 172 -fixed yes +set_io mem_dat_pad_io\[11\] -REGISTER Yes -pinname 168 -fixed yes +set_io mem_dat_pad_io\[12\] -REGISTER Yes -pinname 166 -fixed yes +set_io mem_dat_pad_io\[13\] -REGISTER Yes -pinname 164 -fixed yes +set_io mem_dat_pad_io\[14\] -REGISTER Yes -pinname 161 -fixed yes +set_io mem_dat_pad_io\[15\] -REGISTER Yes -pinname 159 -fixed yes +set_io mem_dqm_pad_o\[0\] -REGISTER Yes -pinname 177 -fixed yes +set_io mem_dqm_pad_o\[1\] -REGISTER Yes -pinname 180 -fixed yes +set_io mem_ras_pad_o -REGISTER Yes -pinname 182 -fixed yes +set_io mem_we_pad_o -REGISTER Yes -pinname 179 -fixed yes +set_io rst_pad_i -RES_PULL Up -pinname 49 -fixed yes +set_io rst_pad_o -RES_PULL Down -pinname 31 -fixed yes +set_io spi_flash_hold_n_pad_o -pinname 86 -fixed yes +set_io spi_flash_miso_pad_i -pinname 85 -fixed yes +set_io spi_flash_mosi_pad_o -REGISTER Yes -pinname 87 -fixed yes +set_io spi_flash_sclk_pad_o -pinname 90 -fixed yes +set_io spi_flash_ss_pad_o -pinname 84 -fixed yes +set_io spi_flash_w_n_pad_o -pinname 83 -fixed yes +set_io uart0_srx_pad_i -REGISTER Yes -pinname 91 -fixed yes +set_io uart0_stx_pad_o -pinname 92 -fixed yes + Index: sdcard_mass_storage_controller/locks/db.lock =================================================================== --- sdcard_mass_storage_controller/locks/db.lock (nonexistent) +++ sdcard_mass_storage_controller/locks/db.lock (revision 11) @@ -0,0 +1,3 @@ +This file is not used by Subversion 1.3.x or later. +However, its existence is required for compatibility with +Subversion 1.2.x or earlier. Index: sdcard_mass_storage_controller/locks/db-logs.lock =================================================================== --- sdcard_mass_storage_controller/locks/db-logs.lock (nonexistent) +++ sdcard_mass_storage_controller/locks/db-logs.lock (revision 11) @@ -0,0 +1,3 @@ +This file is not used by Subversion 1.3.x or later. +However, its existence is required for compatibility with +Subversion 1.2.x or earlier. Index: sdcard_mass_storage_controller/README.txt =================================================================== --- sdcard_mass_storage_controller/README.txt (nonexistent) +++ sdcard_mass_storage_controller/README.txt (revision 11) @@ -0,0 +1,5 @@ +This is a Subversion repository; use the 'svnadmin' tool to examine +it. Do not add, delete, or modify files here unless you know how +to avoid corrupting the repository. + +Visit http://subversion.tigris.org/ for more information.

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