Subversion Repositories sdcard_mass_storage_controller

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw.cxf

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_usedLocations.pdc

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/compile_report.log

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/header_report.log

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

/sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw.cdb

sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_pre.v =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_pre.v (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_pre.v (revision 15) @@ -0,0 +1,88 @@ +`timescale 1 ns/100 ps +// Version: 8.5 8.5.0.34 + + +module versatile_fifo_dptam_dw( + d_a, + q_a, + adr_a, + we_a, + clk_a, + q_b, + adr_b, + d_b, + we_b, + clk_b + ); +/* synthesis syn_black_box + +pragma attribute versatile_fifo_dptam_dw ment_tsu0 adr_a[0]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu1 adr_a[10]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu2 adr_a[1]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu3 adr_a[2]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu4 adr_a[3]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu5 adr_a[4]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu6 adr_a[5]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu7 adr_a[6]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu8 adr_a[7]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu9 adr_a[8]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu10 adr_a[9]->clk_a+0.280 +pragma attribute versatile_fifo_dptam_dw ment_tsu11 adr_b[0]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu12 adr_b[10]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu13 adr_b[1]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu14 adr_b[2]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu15 adr_b[3]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu16 adr_b[4]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu17 adr_b[5]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu18 adr_b[6]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu19 adr_b[7]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu20 adr_b[8]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu21 adr_b[9]->clk_b+0.282 +pragma attribute versatile_fifo_dptam_dw ment_tsu22 d_a[0]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu23 d_a[1]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu24 d_a[2]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu25 d_a[3]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu26 d_a[4]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu27 d_a[5]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu28 d_a[6]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu29 d_a[7]->clk_a+0.193 +pragma attribute versatile_fifo_dptam_dw ment_tsu30 d_b[0]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu31 d_b[1]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu32 d_b[2]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu33 d_b[3]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu34 d_b[4]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu35 d_b[5]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu36 d_b[6]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu37 d_b[7]->clk_b+0.176 +pragma attribute versatile_fifo_dptam_dw ment_tsu38 we_a->clk_a+2.731 +pragma attribute versatile_fifo_dptam_dw ment_tsu39 we_b->clk_b+3.346 +pragma attribute versatile_fifo_dptam_dwment_tco0 clk_a->q_a[0]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco1 clk_a->q_a[1]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco2 clk_a->q_a[2]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco3 clk_a->q_a[3]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco4 clk_a->q_a[4]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco5 clk_a->q_a[5]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco6 clk_a->q_a[6]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco7 clk_a->q_a[7]+3.154 +pragma attribute versatile_fifo_dptam_dwment_tco8 clk_b->q_b[0]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco9 clk_b->q_b[1]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco10 clk_b->q_b[2]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco11 clk_b->q_b[3]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco12 clk_b->q_b[4]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco13 clk_b->q_b[5]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco14 clk_b->q_b[6]+3.139 +pragma attribute versatile_fifo_dptam_dwment_tco15 clk_b->q_b[7]+3.139 +*/ +/* synthesis black_box_pad_pin ="" */ +input [7:0] d_a; +output [7:0] q_a; +input [10:0] adr_a; +input we_a; +input clk_a; +output [7:0] q_b; +input [10:0] adr_b; +input [7:0] d_b; +input we_b; +input clk_b; + +endmodule Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/global_report.log =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/global_report.log (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/global_report.log (revision 15) @@ -0,0 +1,18 @@ + +Global Usage Report: +==================== + +Product : Designer +Release : v8.5 +Version : 8.5.0.34 +Date : Tue Apr 21 10:24:26 2009 +Design Name : versatile_fifo_dptam_dw +Family : ProASIC3 +Die : A3P1000 +Package : 208 PQFP +Design State : Post-Layout + + + + + Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/interface_report.log =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/interface_report.log (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/interface_report.log (revision 15) @@ -0,0 +1,187 @@ + +Interface Report: +================= + +Block Name : versatile_fifo_dptam_dw +Date : Tue Apr 21 10:24:26 2009 + + +Ports that are candidates for global sharing: +--------------------------------------------- + + + Fanout Type Direction Name + ------------------------------------------------------------------- + + + +Port Interface: +--------------- + + + Fanout Type Direction Name + ------------------------------------------------------------------- + + 4 INT_NET INPUT Port : adr_a[0] + + 4 INT_NET INPUT Port : adr_a[1] + + 4 INT_NET INPUT Port : adr_a[2] + + 4 INT_NET INPUT Port : adr_a[3] + + 4 INT_NET INPUT Port : adr_a[4] + + 4 INT_NET INPUT Port : adr_a[5] + + 4 INT_NET INPUT Port : adr_a[6] + + 4 INT_NET INPUT Port : adr_a[7] + + 4 INT_NET INPUT Port : adr_a[8] + + 4 INT_NET INPUT Port : adr_a[9] + + 4 INT_NET INPUT Port : adr_a[10] + + 4 INT_NET INPUT Port : adr_b[0] + + 4 INT_NET INPUT Port : adr_b[1] + + 4 INT_NET INPUT Port : adr_b[2] + + 4 INT_NET INPUT Port : adr_b[3] + + 4 INT_NET INPUT Port : adr_b[4] + + 4 INT_NET INPUT Port : adr_b[5] + + 4 INT_NET INPUT Port : adr_b[6] + + 4 INT_NET INPUT Port : adr_b[7] + + 4 INT_NET INPUT Port : adr_b[8] + + 4 INT_NET INPUT Port : adr_b[9] + + 4 INT_NET INPUT Port : adr_b[10] + + 4 INT_NET INPUT Port : clk_a + + 4 INT_NET INPUT Port : clk_b + + 1 INT_NET INPUT Port : d_a[0] + Instance : ram_tile_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_a[1] + Instance : ram_tile_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_a[2] + Instance : ram_tile_0_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_a[3] + Instance : ram_tile_0_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_a[4] + Instance : ram_tile_1_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_a[5] + Instance : ram_tile_1_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_a[6] + Instance : ram_tile_2_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_a[7] + Instance : ram_tile_2_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_b[0] + Instance : ram_tile_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_b[1] + Instance : ram_tile_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_b[2] + Instance : ram_tile_0_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_b[3] + Instance : ram_tile_0_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_b[4] + Instance : ram_tile_1_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_b[5] + Instance : ram_tile_1_I_1/U_8_0 + + 1 INT_NET INPUT Port : d_b[6] + Instance : ram_tile_2_I_1/U_7_0 + + 1 INT_NET INPUT Port : d_b[7] + Instance : ram_tile_2_I_1/U_8_0 + + 1 INT_NET OUTPUT Port : q_a[0] + Instance : ram_tile_I_1/U_1_0 + + 1 INT_NET OUTPUT Port : q_a[1] + Instance : ram_tile_I_1/U_3_0 + + 1 INT_NET OUTPUT Port : q_a[2] + Instance : ram_tile_0_I_1/U_1_0 + + 1 INT_NET OUTPUT Port : q_a[3] + Instance : ram_tile_0_I_1/U_3_0 + + 1 INT_NET OUTPUT Port : q_a[4] + Instance : ram_tile_1_I_1/U_1_0 + + 1 INT_NET OUTPUT Port : q_a[5] + Instance : ram_tile_1_I_1/U_3_0 + + 1 INT_NET OUTPUT Port : q_a[6] + Instance : ram_tile_2_I_1/U_1_0 + + 1 INT_NET OUTPUT Port : q_a[7] + Instance : ram_tile_2_I_1/U_3_0 + + 1 INT_NET OUTPUT Port : q_b[0] + Instance : ram_tile_I_1/U_0_0 + + 1 INT_NET OUTPUT Port : q_b[1] + Instance : ram_tile_I_1/U_2_0 + + 1 INT_NET OUTPUT Port : q_b[2] + Instance : ram_tile_0_I_1/U_0_0 + + 1 INT_NET OUTPUT Port : q_b[3] + Instance : ram_tile_0_I_1/U_2_0 + + 1 INT_NET OUTPUT Port : q_b[4] + Instance : ram_tile_1_I_1/U_0_0 + + 1 INT_NET OUTPUT Port : q_b[5] + Instance : ram_tile_1_I_1/U_2_0 + + 1 INT_NET OUTPUT Port : q_b[6] + Instance : ram_tile_2_I_1/U_0_0 + + 1 INT_NET OUTPUT Port : q_b[7] + Instance : ram_tile_2_I_1/U_2_0 + + 1 INT_NET INPUT Port : we_a + Instance : we_a_RNIA08 + + 1 INT_NET INPUT Port : we_b + Instance : we_b_RNIB08 + +----------------------------------------------------------------------------------------------------------- + + Types: + ------ + PAD_NET : The port is driving a PAD pin. + CLK_NET : The port is driving only clock pins of instances. + INT_NET : The port is driving other type of pins. + NC_NET : The port is floating. + + Globals: + -------- + Int Globals : + Global net : YES if a port is driven by a global net Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_sim.v (revision 15) @@ -0,0 +1,173 @@ +`timescale 1 ns/100 ps +// Version: 8.5 8.5.0.34 + + +module versatile_fifo_dptam_dw( + d_a, + q_a, + adr_a, + we_a, + clk_a, + q_b, + adr_b, + d_b, + we_b, + clk_b + ); +input [7:0] d_a; +output [7:0] q_a; +input [10:0] adr_a; +input we_a; +input clk_a; +output [7:0] q_b; +input [10:0] adr_b; +input [7:0] d_b; +input we_b; +input clk_b; + + wire VCC, GND, \ram_tile_2.DOUT0_SIG[2] , + \ram_tile_2.DOUT0_SIG[3] , \ram_tile_2.DOUT0_SIG[4] , + \ram_tile_2.DOUT0_SIG[5] , \ram_tile_2.DOUT0_SIG[6] , + \ram_tile_2.DOUT0_SIG[7] , \ram_tile_2.DOUT0_SIG[8] , + \ram_tile_2.DOUT1_SIG[2] , \ram_tile_2.DOUT1_SIG[3] , + \ram_tile_2.DOUT1_SIG[4] , \ram_tile_2.DOUT1_SIG[5] , + \ram_tile_2.DOUT1_SIG[6] , \ram_tile_2.DOUT1_SIG[7] , + \ram_tile_2.DOUT1_SIG[8] , \ram_tile_1.DOUT0_SIG[2] , + \ram_tile_1.DOUT0_SIG[3] , \ram_tile_1.DOUT0_SIG[4] , + \ram_tile_1.DOUT0_SIG[5] , \ram_tile_1.DOUT0_SIG[6] , + \ram_tile_1.DOUT0_SIG[7] , \ram_tile_1.DOUT0_SIG[8] , + \ram_tile_1.DOUT1_SIG[2] , \ram_tile_1.DOUT1_SIG[3] , + \ram_tile_1.DOUT1_SIG[4] , \ram_tile_1.DOUT1_SIG[5] , + \ram_tile_1.DOUT1_SIG[6] , \ram_tile_1.DOUT1_SIG[7] , + \ram_tile_1.DOUT1_SIG[8] , \ram_tile_0.DOUT0_SIG[2] , + \ram_tile_0.DOUT0_SIG[3] , \ram_tile_0.DOUT0_SIG[4] , + \ram_tile_0.DOUT0_SIG[5] , \ram_tile_0.DOUT0_SIG[6] , + \ram_tile_0.DOUT0_SIG[7] , \ram_tile_0.DOUT0_SIG[8] , + \ram_tile_0.DOUT1_SIG[2] , \ram_tile_0.DOUT1_SIG[3] , + \ram_tile_0.DOUT1_SIG[4] , \ram_tile_0.DOUT1_SIG[5] , + \ram_tile_0.DOUT1_SIG[6] , \ram_tile_0.DOUT1_SIG[7] , + \ram_tile_0.DOUT1_SIG[8] , \ram_tile.DOUT0_SIG[2] , + \ram_tile.DOUT0_SIG[3] , \ram_tile.DOUT0_SIG[4] , + \ram_tile.DOUT0_SIG[5] , \ram_tile.DOUT0_SIG[6] , + \ram_tile.DOUT0_SIG[7] , \ram_tile.DOUT0_SIG[8] , + \ram_tile.DOUT1_SIG[2] , \ram_tile.DOUT1_SIG[3] , + \ram_tile.DOUT1_SIG[4] , \ram_tile.DOUT1_SIG[5] , + \ram_tile.DOUT1_SIG[6] , \ram_tile.DOUT1_SIG[7] , + \ram_tile.DOUT1_SIG[8] , we_b_i, we_a_i, GND_net_1, VCC_net_1; + + INV we_b_RNIB08 (.A(we_b), .Y(we_b_i)); + VCC VCC_i_0 (.Y(VCC_net_1)); + RAM4K9 ram_tile_0_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9( + adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6( + adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3( + adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0( + adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9( + adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6( + adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3( + adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0( + adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), + .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[3]), .DINA0( + d_b[2]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), + .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[3]), .DINB0( + d_a[2]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1( + GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), + .BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA( + clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8( + \ram_tile_0.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_0.DOUT0_SIG[7] ), + .DOUTA6(\ram_tile_0.DOUT0_SIG[6] ), .DOUTA5( + \ram_tile_0.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_0.DOUT0_SIG[4] ), + .DOUTA3(\ram_tile_0.DOUT0_SIG[3] ), .DOUTA2( + \ram_tile_0.DOUT0_SIG[2] ), .DOUTA1(q_b[3]), .DOUTA0(q_b[2]), + .DOUTB8(\ram_tile_0.DOUT1_SIG[8] ), .DOUTB7( + \ram_tile_0.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_0.DOUT1_SIG[6] ), + .DOUTB5(\ram_tile_0.DOUT1_SIG[5] ), .DOUTB4( + \ram_tile_0.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_0.DOUT1_SIG[3] ), + .DOUTB2(\ram_tile_0.DOUT1_SIG[2] ), .DOUTB1(q_a[3]), .DOUTB0( + q_a[2])); + INV we_a_RNIA08 (.A(we_a), .Y(we_a_i)); + GND GND_i_0 (.Y(GND_net_1)); + RAM4K9 ram_tile_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9( + adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6( + adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3( + adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0( + adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9( + adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6( + adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3( + adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0( + adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), + .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[1]), .DINA0( + d_b[0]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), + .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[1]), .DINB0( + d_a[0]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1( + GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), + .BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA( + clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8( + \ram_tile.DOUT0_SIG[8] ), .DOUTA7(\ram_tile.DOUT0_SIG[7] ), + .DOUTA6(\ram_tile.DOUT0_SIG[6] ), .DOUTA5( + \ram_tile.DOUT0_SIG[5] ), .DOUTA4(\ram_tile.DOUT0_SIG[4] ), + .DOUTA3(\ram_tile.DOUT0_SIG[3] ), .DOUTA2( + \ram_tile.DOUT0_SIG[2] ), .DOUTA1(q_b[1]), .DOUTA0(q_b[0]), + .DOUTB8(\ram_tile.DOUT1_SIG[8] ), .DOUTB7( + \ram_tile.DOUT1_SIG[7] ), .DOUTB6(\ram_tile.DOUT1_SIG[6] ), + .DOUTB5(\ram_tile.DOUT1_SIG[5] ), .DOUTB4( + \ram_tile.DOUT1_SIG[4] ), .DOUTB3(\ram_tile.DOUT1_SIG[3] ), + .DOUTB2(\ram_tile.DOUT1_SIG[2] ), .DOUTB1(q_a[1]), .DOUTB0( + q_a[0])); + VCC VCC_i (.Y(VCC)); + RAM4K9 ram_tile_2_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9( + adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6( + adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3( + adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0( + adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9( + adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6( + adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3( + adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0( + adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), + .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[7]), .DINA0( + d_b[6]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), + .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[7]), .DINB0( + d_a[6]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1( + GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), + .BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA( + clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8( + \ram_tile_2.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_2.DOUT0_SIG[7] ), + .DOUTA6(\ram_tile_2.DOUT0_SIG[6] ), .DOUTA5( + \ram_tile_2.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_2.DOUT0_SIG[4] ), + .DOUTA3(\ram_tile_2.DOUT0_SIG[3] ), .DOUTA2( + \ram_tile_2.DOUT0_SIG[2] ), .DOUTA1(q_b[7]), .DOUTA0(q_b[6]), + .DOUTB8(\ram_tile_2.DOUT1_SIG[8] ), .DOUTB7( + \ram_tile_2.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_2.DOUT1_SIG[6] ), + .DOUTB5(\ram_tile_2.DOUT1_SIG[5] ), .DOUTB4( + \ram_tile_2.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_2.DOUT1_SIG[3] ), + .DOUTB2(\ram_tile_2.DOUT1_SIG[2] ), .DOUTB1(q_a[7]), .DOUTB0( + q_a[6])); + RAM4K9 ram_tile_1_I_1 (.ADDRA11(GND), .ADDRA10(adr_b[10]), .ADDRA9( + adr_b[9]), .ADDRA8(adr_b[8]), .ADDRA7(adr_b[7]), .ADDRA6( + adr_b[6]), .ADDRA5(adr_b[5]), .ADDRA4(adr_b[4]), .ADDRA3( + adr_b[3]), .ADDRA2(adr_b[2]), .ADDRA1(adr_b[1]), .ADDRA0( + adr_b[0]), .ADDRB11(GND), .ADDRB10(adr_a[10]), .ADDRB9( + adr_a[9]), .ADDRB8(adr_a[8]), .ADDRB7(adr_a[7]), .ADDRB6( + adr_a[6]), .ADDRB5(adr_a[5]), .ADDRB4(adr_a[4]), .ADDRB3( + adr_a[3]), .ADDRB2(adr_a[2]), .ADDRB1(adr_a[1]), .ADDRB0( + adr_a[0]), .DINA8(GND), .DINA7(GND), .DINA6(GND), .DINA5(GND), + .DINA4(GND), .DINA3(GND), .DINA2(GND), .DINA1(d_b[5]), .DINA0( + d_b[4]), .DINB8(GND), .DINB7(GND), .DINB6(GND), .DINB5(GND), + .DINB4(GND), .DINB3(GND), .DINB2(GND), .DINB1(d_a[5]), .DINB0( + d_a[4]), .WIDTHA0(VCC), .WIDTHA1(GND), .WIDTHB0(VCC), .WIDTHB1( + GND), .PIPEA(GND), .PIPEB(GND), .WMODEA(GND), .WMODEB(GND), + .BLKA(GND), .BLKB(GND), .WENA(we_b_i), .WENB(we_a_i), .CLKA( + clk_b), .CLKB(clk_a), .RESET(VCC), .DOUTA8( + \ram_tile_1.DOUT0_SIG[8] ), .DOUTA7(\ram_tile_1.DOUT0_SIG[7] ), + .DOUTA6(\ram_tile_1.DOUT0_SIG[6] ), .DOUTA5( + \ram_tile_1.DOUT0_SIG[5] ), .DOUTA4(\ram_tile_1.DOUT0_SIG[4] ), + .DOUTA3(\ram_tile_1.DOUT0_SIG[3] ), .DOUTA2( + \ram_tile_1.DOUT0_SIG[2] ), .DOUTA1(q_b[5]), .DOUTA0(q_b[4]), + .DOUTB8(\ram_tile_1.DOUT1_SIG[8] ), .DOUTB7( + \ram_tile_1.DOUT1_SIG[7] ), .DOUTB6(\ram_tile_1.DOUT1_SIG[6] ), + .DOUTB5(\ram_tile_1.DOUT1_SIG[5] ), .DOUTB4( + \ram_tile_1.DOUT1_SIG[4] ), .DOUTB3(\ram_tile_1.DOUT1_SIG[3] ), + .DOUTB2(\ram_tile_1.DOUT1_SIG[2] ), .DOUTB1(q_a[5]), .DOUTB0( + q_a[4])); + GND GND_i (.Y(GND)); + +endmodule Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/datasheet_report.log =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/datasheet_report.log (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/datasheet_report.log (revision 15) @@ -0,0 +1,193 @@ +SmartTime Version 3.0 +Actel Corporation - Actel Designer Software Release v8.5 (Version 8.5.0.34) + + Design versatile_fifo_dptam_dw + Family ProASIC3 + Die A3P1000 + Package 208 PQFP + Temperature COM + Voltage COM + Speed Grade STD + Design State Post-Layout + Data source Silicon verified + Analysis Min Case BEST + Analysis Max Case WORST + Scenario for Timing Analysis Primary + + Using Enhanced Min Delay Analysis +Pin Description ++-----------+----------+--------+----------------+ +| Name | Location | Type | I/O Technology | ++-----------+----------+--------+----------------+ +| d_a[7] | | Input | | +| d_a[6] | | Input | | +| d_a[5] | | Input | | +| d_a[4] | | Input | | +| d_a[3] | | Input | | +| d_a[2] | | Input | | +| d_a[1] | | Input | | +| d_a[0] | | Input | | +| q_a[7] | | Output | | +| q_a[6] | | Output | | +| q_a[5] | | Output | | +| q_a[4] | | Output | | +| q_a[3] | | Output | | +| q_a[2] | | Output | | +| q_a[1] | | Output | | +| q_a[0] | | Output | | +| adr_a[10] | | Input | | +| adr_a[9] | | Input | | +| adr_a[8] | | Input | | +| adr_a[7] | | Input | | +| adr_a[6] | | Input | | +| adr_a[5] | | Input | | +| adr_a[4] | | Input | | +| adr_a[3] | | Input | | +| adr_a[2] | | Input | | +| adr_a[1] | | Input | | +| adr_a[0] | | Input | | +| we_a | | Input | | +| clk_a | | Clock | | +| q_b[7] | | Output | | +| q_b[6] | | Output | | +| q_b[5] | | Output | | +| q_b[4] | | Output | | +| q_b[3] | | Output | | +| q_b[2] | | Output | | +| q_b[1] | | Output | | +| q_b[0] | | Output | | +| adr_b[10] | | Input | | +| adr_b[9] | | Input | | +| adr_b[8] | | Input | | +| adr_b[7] | | Input | | +| adr_b[6] | | Input | | +| adr_b[5] | | Input | | +| adr_b[4] | | Input | | +| adr_b[3] | | Input | | +| adr_b[2] | | Input | | +| adr_b[1] | | Input | | +| adr_b[0] | | Input | | +| d_b[7] | | Input | | +| d_b[6] | | Input | | +| d_b[5] | | Input | | +| d_b[4] | | Input | | +| d_b[3] | | Input | | +| d_b[2] | | Input | | +| d_b[1] | | Input | | +| d_b[0] | | Input | | +| we_b | | Input | | +| clk_b | | Clock | | ++-----------+----------+--------+----------------+ + + +DC Electrical Characteristics +Not Applicable + + +AC Electrical Characteristics ++-------------------+--------------+--------+--------------+--------+---------+------+ +| Description | | | | Min | Max | Unit | ++-------------------+--------------+--------+--------------+--------+---------+------+ +| Clock frequency | clk_a | | | | 231.267 | MHz | +| Clock period | clk_a | | | 4.324 | | ns | +| Clock frequency | clk_b | | | | 231.267 | MHz | +| Clock period | clk_b | | | 4.324 | | ns | +| Setup time | adr_a[0] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[10] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[1] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[2] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[3] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[4] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[5] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[6] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[7] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[8] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_a[9] | before | clk_a (rise) | 0.280 | | ns | +| Setup time | adr_b[0] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[10] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[1] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[2] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[3] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[4] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[5] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[6] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[7] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[8] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | adr_b[9] | before | clk_b (rise) | 0.282 | | ns | +| Setup time | d_a[0] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[1] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[2] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[3] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[4] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[5] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[6] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_a[7] | before | clk_a (rise) | 0.193 | | ns | +| Setup time | d_b[0] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[1] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[2] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[3] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[4] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[5] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[6] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | d_b[7] | before | clk_b (rise) | 0.176 | | ns | +| Setup time | we_a | before | clk_a (rise) | 2.731 | | ns | +| Setup time | we_b | before | clk_b (rise) | 3.346 | | ns | +| Hold time | adr_a[0] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[10] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[1] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[2] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[3] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[4] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[5] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[6] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[7] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[8] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_a[9] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | adr_b[0] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[10] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[1] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[2] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[3] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[4] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[5] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[6] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[7] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[8] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | adr_b[9] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_a[0] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[1] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[2] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[3] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[4] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[5] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[6] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_a[7] | after | clk_a (rise) | 0.000 | | ns | +| Hold time | d_b[0] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[1] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[2] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[3] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[4] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[5] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[6] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | d_b[7] | after | clk_b (rise) | 0.000 | | ns | +| Hold time | we_a | after | clk_a (rise) | -0.353 | | ns | +| Hold time | we_b | after | clk_b (rise) | -0.317 | | ns | +| Propagation delay | clk_a (rise) | to | q_a[0] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[1] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[2] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[3] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[4] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[5] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[6] | 1.063 | 3.154 | ns | +| Propagation delay | clk_a (rise) | to | q_a[7] | 1.063 | 3.154 | ns | +| Propagation delay | clk_b (rise) | to | q_b[0] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[1] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[2] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[3] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[4] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[5] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[6] | 1.057 | 3.139 | ns | +| Propagation delay | clk_b (rise) | to | q_b[7] | 1.057 | 3.139 | ns | ++-------------------+--------------+--------+--------------+--------+---------+------+ + + Index: sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_syn.v =================================================================== --- sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_syn.v (nonexistent) +++ sdcard_mass_storage_controller/trunk/backend/Actel/Block/versatile_fifo_dptam_dw/versatile_fifo_dptam_dw_syn.v (revision 15) @@ -0,0 +1,88 @@ +`timescale 1 ns/100 ps +// Version: 8.5 8.5.0.34 + + +module versatile_fifo_dptam_dw( + d_a, + q_a, + adr_a, + we_a, + clk_a, + q_b, + adr_b, + d_b, + we_b, + clk_b + ); +/* synthesis syn_black_box + +syn_tsu0 = " adr_a[0]->clk_a = 0.28" +syn_tsu1 = " adr_a[10]->clk_a = 0.28" +syn_tsu2 = " adr_a[1]->clk_a = 0.28" +syn_tsu3 = " adr_a[2]->clk_a = 0.28" +syn_tsu4 = " adr_a[3]->clk_a = 0.28" +syn_tsu5 = " adr_a[4]->clk_a = 0.28" +syn_tsu6 = " adr_a[5]->clk_a = 0.28" +syn_tsu7 = " adr_a[6]->clk_a = 0.28" +syn_tsu8 = " adr_a[7]->clk_a = 0.28" +syn_tsu9 = " adr_a[8]->clk_a = 0.28" +syn_tsu10 = " adr_a[9]->clk_a = 0.28" +syn_tsu11 = " adr_b[0]->clk_b = 0.282" +syn_tsu12 = " adr_b[10]->clk_b = 0.282" +syn_tsu13 = " adr_b[1]->clk_b = 0.282" +syn_tsu14 = " adr_b[2]->clk_b = 0.282" +syn_tsu15 = " adr_b[3]->clk_b = 0.282" +syn_tsu16 = " adr_b[4]->clk_b = 0.282" +syn_tsu17 = " adr_b[5]->clk_b = 0.282" +syn_tsu18 = " adr_b[6]->clk_b = 0.282" +syn_tsu19 = " adr_b[7]->clk_b = 0.282" +syn_tsu20 = " adr_b[8]->clk_b = 0.282" +syn_tsu21 = " adr_b[9]->clk_b = 0.282" +syn_tsu22 = " d_a[0]->clk_a = 0.193" +syn_tsu23 = " d_a[1]->clk_a = 0.193" +syn_tsu24 = " d_a[2]->clk_a = 0.193" +syn_tsu25 = " d_a[3]->clk_a = 0.193" +syn_tsu26 = " d_a[4]->clk_a = 0.193" +syn_tsu27 = " d_a[5]->clk_a = 0.193" +syn_tsu28 = " d_a[6]->clk_a = 0.193" +syn_tsu29 = " d_a[7]->clk_a = 0.193" +syn_tsu30 = " d_b[0]->clk_b = 0.176" +syn_tsu31 = " d_b[1]->clk_b = 0.176" +syn_tsu32 = " d_b[2]->clk_b = 0.176" +syn_tsu33 = " d_b[3]->clk_b = 0.176" +syn_tsu34 = " d_b[4]->clk_b = 0.176" +syn_tsu35 = " d_b[5]->clk_b = 0.176" +syn_tsu36 = " d_b[6]->clk_b = 0.176" +syn_tsu37 = " d_b[7]->clk_b = 0.176" +syn_tsu38 = " we_a->clk_a = 2.731" +syn_tsu39 = " we_b->clk_b = 3.346" +syn_tco0 = " clk_a->q_a[0] = 3.154" +syn_tco1 = " clk_a->q_a[1] = 3.154" +syn_tco2 = " clk_a->q_a[2] = 3.154" +syn_tco3 = " clk_a->q_a[3] = 3.154" +syn_tco4 = " clk_a->q_a[4] = 3.154" +syn_tco5 = " clk_a->q_a[5] = 3.154" +syn_tco6 = " clk_a->q_a[6] = 3.154" +syn_tco7 = " clk_a->q_a[7] = 3.154" +syn_tco8 = " clk_b->q_b[0] = 3.139" +syn_tco9 = " clk_b->q_b[1] = 3.139" +syn_tco10 = " clk_b->q_b[2] = 3.139" +syn_tco11 = " clk_b->q_b[3] = 3.139" +syn_tco12 = " clk_b->q_b[4] = 3.139" +syn_tco13 = " clk_b->q_b[5] = 3.139" +syn_tco14 = " clk_b->q_b[6] = 3.139" +syn_tco15 = " clk_b->q_b[7] = 3.139" +*/ +/* synthesis black_box_pad_pin ="" */ +input [7:0] d_a; +output [7:0] q_a; +input [10:0] adr_a; +input we_a; +input clk_a; +output [7:0] q_b; +input [10:0] adr_b; +input [7:0] d_b; +input we_b; +input clk_b; + +endmodule