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/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_crc_7.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_defines.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_crc_16.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_cmd_master.v File deleted \ No newline at end of file
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_cmd_serial_host.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_clock_divider.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_data_master.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_controller_top.v File deleted \ No newline at end of file
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_Bd.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_data_host.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_FIFO_RX_Filler.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/smii_rx_fifo.v.bak File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/smii_rx_fifo.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/smii_tx_fifo.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/smii_rx_fifo_tb.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/SD_defines.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/fifo/smii_tx_fifo_tb.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_controller_top_tb.v File deleted \ No newline at end of file
/sdcard_mass_storage_controller/trunk/rtl/verilog/SD_FIFO_TX_Filler.v File deleted
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_Bd.v
0,0 → 1,211
 
`include "SD_defines.v"
 
 
 
module SD_Bd (
input clk,
input rst,
//input stb_m,
input we_m,
input re_m,
input [`RAM_MEM_WIDTH-1:0] dat_in_m,
output reg [`RAM_MEM_WIDTH-1:0] dat_out_m,
output reg [`BD_WIDTH-1 :0] free_bd,
output reg new_bw,
input re_s,
output reg ack_o_s,
input a_cmp,
output reg[`RAM_MEM_WIDTH-1:0] dat_out_s
);
reg last_a_cmp;
`ifdef RAM_MEM_WIDTH_32
`ifdef ACTEL
reg [RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0]; /* synthesis syn_ramstyle = "no_rw_check"*/
`else
reg [RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
`endif
 
reg write_cnt;
reg read_cnt;
reg [`BD_WIDTH -1 :0] m_wr_pnt;
reg [`BD_WIDTH -1 :0] m_rd_pnt;
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
//Main side read/write
always @(posedge clk or posedge rst )
begin
new_bw =0;
if (rst) begin
m_wr_pnt<=0;
m_rd_pnt<=1;
write_cnt<=0;
new_bw =0;
 
end
else if (we_m) begin
if (free_bd >0) begin
write_cnt <=~ write_cnt;
m_wr_pnt<=m_wr_pnt+1;
if (!write_cnt) begin //First write indicate source buffer addr
bd_mem[m_wr_pnt]<=dat_in_m;
end
else begin //Second write indicate SD card block addr
bd_mem[m_wr_pnt]<=dat_in_m;
new_bw =1;
end
end
end
else if (re_m) begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+2;
end
 
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
free_bd <=(`BD_SIZE /2);
end
else if (new_bw ) begin
free_bd <= free_bd-1;
end
else if (a_cmp) begin
free_bd <= free_bd+1;
end
end
 
 
//Second side read
always @(posedge clk or posedge rst)
begin
if (rst) begin
s_rd_pnt<=0;
end
else if (re_s) begin
s_rd_pnt<=s_rd_pnt+1;
dat_out_s<= bd_mem[s_rd_pnt];
end
end
 
`else `ifdef RAM_MEM_WIDTH_16
`ifdef ACTEL
reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0]; //synthesis syn_ramstyle = "no_rw_check"
`else
reg [ `RAM_MEM_WIDTH -1:0] bd_mem [ `BD_SIZE -1 :0];
`endif
 
reg [1:0]write_cnt;
reg [1:0]read_s_cnt;
reg read_cnt;
 
reg [`BD_WIDTH -1 :0] m_wr_pnt;
reg [`BD_WIDTH -1 :0] m_rd_pnt;
reg [`BD_WIDTH -1 :0] s_rd_pnt ;
//Main side read/write
always @(posedge clk or posedge rst )
begin
new_bw =0;
if (rst) begin
m_wr_pnt<=0;
m_rd_pnt<=2 ;
write_cnt<=0;
new_bw =0;
read_cnt<=0;
end
else if (we_m) begin
if (free_bd >0) begin
write_cnt <=write_cnt+1;
m_wr_pnt<=m_wr_pnt+1;
if (!write_cnt[1]) begin //First write indicate source buffer addr (2x16)
bd_mem[m_wr_pnt]<=dat_in_m;
end
else begin //Second write indicate SD card block addr (2x16)
bd_mem[m_wr_pnt]<=dat_in_m;
new_bw =write_cnt[0]; //Second 16 bytes writen, complete BD
end
end
end
else if (re_m) begin //2 Reads to get a 32 bit Word
read_cnt <=~ read_cnt;
if (!read_cnt) begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+1;
end
else begin
dat_out_m <=bd_mem[m_rd_pnt];
m_rd_pnt <=m_rd_pnt+3;
end
end
 
end
 
always @(posedge clk or posedge rst)
begin
if (rst) begin
free_bd <=(`BD_SIZE /4);
last_a_cmp<=0;
end
else if (new_bw ) begin
free_bd <= free_bd-1;
end
else if (a_cmp) begin
last_a_cmp <=a_cmp;
if (!last_a_cmp)
free_bd <= free_bd+1;
end
else
last_a_cmp <=a_cmp;
end
 
 
//Second side read
always @(posedge clk or posedge rst)
begin
if (rst) begin
s_rd_pnt<=0;
read_s_cnt<=0;
ack_o_s<=0;
end
else if (re_s) begin
read_s_cnt <=read_s_cnt+1;
s_rd_pnt<=s_rd_pnt+1;
ack_o_s<=1;
if (!read_s_cnt[1]) //First read indicate source buffer addr (2x16)
dat_out_s<= bd_mem[s_rd_pnt];
else //Second read indicate SD card block addr (2x16)
dat_out_s<= bd_mem[s_rd_pnt];
end
else
ack_o_s<=0;
end
 
`endif
 
`endif
 
 
endmodule
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_controller_top.v
0,0 → 1,579
`include "SD_defines.v"
module SD_CONTROLLER_TOP(
// WISHBONE common
wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
 
// WISHBONE slave
wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o,
 
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i,
m_wb_cti_o, m_wb_bte_o,
//SD BUS
sd_cmd_dat_i,sd_cmd_out_o, sd_cmd_oe_o,
sd_dat_dat_i, sd_dat_out_o , sd_dat_oe_o, sd_clk_o_pad
);
 
 
 
// WISHBONE common
input wb_clk_i; // WISHBONE clock
input wb_rst_i; // WISHBONE reset
input [31:0] wb_dat_i; // WISHBONE data input
output reg [31:0] wb_dat_o; // WISHBONE data output
// WISHBONE error output
 
// WISHBONE slave
input [7:0] wb_adr_i; // WISHBONE address input
input [3:0] wb_sel_i; // WISHBONE byte select input
input wb_we_i; // WISHBONE write enable input
input wb_cyc_i; // WISHBONE cycle input
input wb_stb_i; // WISHBONE strobe input
 
output wb_ack_o; // WISHBONE acknowledge output
 
// WISHBONE master
output [31:0] m_wb_adr_o;
output [3:0] m_wb_sel_o;
output m_wb_we_o;
 
input [31:0] m_wb_dat_i;
output [31:0] m_wb_dat_o;
output m_wb_cyc_o;
output m_wb_stb_o;
input m_wb_ack_i;
output [2:0] m_wb_cti_o;
output [1:0] m_wb_bte_o;
//SD port
 
input wire [3:0] sd_dat_dat_i;
output wire [3:0] sd_dat_out_o;
output wire sd_dat_oe_o;
 
input wire sd_cmd_dat_i;
output wire sd_cmd_out_o;
output wire sd_cmd_oe_o;
 
output wire sd_clk_o_pad;
 
reg wb_ack_o;
reg wb_inta_o;
reg new_cmd;
 
 
 
 
 
`define SUPPLY_VOLTAGE_3_3
`define SD_CARD_2_0
`define SD_BUS_WIDTH_
//Register addres
`define argument 8'h00
`define command 8'h04
`define status 8'h08
`define resp1 8'h0c
 
`define controller 8'h1c
`define block 8'h20
`define power 8'h24
`define software 8'h28
`define timeout 8'h2c
`define normal_isr 8'h30
`define error_isr 8'h34
`define normal_iser 8'h38
`define error_iser 8'h3c
//`define normal_isiger 8'h40
//`define error_isiger 8'h44
`define capa 8'h48
`define clock_d 8'h4c
`define bd_status 8'h50
`define bd_isr 8'h54
`define bd_iser 8'h58
 
 
//bd_isiger 8'h5c
`define bd_rx 8'h60
`define bd_tx 8'h80
 
 
assign m_wb_sel_o = 4'b1111;
`ifdef SUPPLY_VOLTAGE_3_3
parameter power_controll_reg = 8'b0000_111_1;
`elsif SUPPLY_VOLTAGE_3_0
parameter power_controll_reg = 8'b0000_110_1;
`elsif SUPPLY_VOLTAGE_1_8
parameter power_controll_reg = 8'b0000_101_1;
`endif
 
parameter block_size_reg = `BLOCK_SIZE ; //512-Bytes
 
 
`ifdef SD_BUS_WIDTH_4
parameter controll_setting_reg =16'b0000_0000_0000_0010;
`else
parameter controll_setting_reg =16'b0000_0000_0000_0000;
`endif
parameter capabilies_reg =16'b0000_0000_0000_0000;
//Registers
reg [31:0] argument_reg;
reg [15:0] cmd_setting_reg;
reg [15:0] status_reg;
reg [31:0] cmd_resp_1;
 
reg [7:0] software_reset_reg; //Merge ?
reg [15:0] time_out_reg; //Merge ?
reg [15:0]normal_int_status_reg;
reg [15:0]error_int_status_reg;
reg [15:0]normal_int_status_enable_reg;
reg [15:0]error_int_status_enable_reg;
//reg [15:0]normal_int_signal_enable_reg;
//reg [15:0]error_int_signal_enable_reg;
 
reg [7:0]clock_divider;
reg [15:0] Bd_Status_reg;
reg [7:0] Bd_isr_reg;
reg [7:0] Bd_isr_enable_reg;
 
 
reg Bd_isr_reset;
//Add blockram for bigger BD defines.
wire [15:0] status_reg_w;
wire [31:0] cmd_resp_1_w;
 
wire [15:0]normal_int_status_reg_w;
wire [15:0]error_int_status_reg_w;
wire sd_clk_i;
wire bd_rx_stb;
reg rx_in;
reg int_ack;
reg we_m_rx_bd;
reg re_m_rx_bd;
reg [`RAM_MEM_WIDTH-1:0] dat_in_m_rx_bd;
wire [`RAM_MEM_WIDTH-1:0] dat_out_m_rx_bd;
wire [`BD_WIDTH-1 :0] free_bd_rx_bd;
wire new_rx_bd;
reg re_s_rx_bd;
 
reg a_cmp_rx_bd;
wire [`RAM_MEM_WIDTH-1:0] dat_out_s_rx_bd;
 
reg we_m_tx_bd;
reg re_m_tx_bd;
reg [`RAM_MEM_WIDTH-1:0] dat_in_m_tx_bd;
wire [`RAM_MEM_WIDTH-1:0] dat_out_m_tx_bd;
wire [`BD_WIDTH-1 :0] free_bd_tx_bd;
wire new_tx_bd;
reg re_s_tx_bd;
reg a_cmp_tx_bd;
 
wire [`RAM_MEM_WIDTH-1:0] dat_out_s_tx_bd;
reg [1:0] we;
wire re_s_tx_bd_w;
wire a_cmp_tx_bd_w;
wire re_s_rx_bd_w;
wire a_cmp_rx_bd_w;
wire we_req_t;
wire [31:0] cmd_arg_m;
wire [31:0] cmd_set_m;
wire [31:0] sys_adr;
wire cmd_busy;
wire [3:0]data_out;
reg we_ack;
reg int_busy;
assign cmd_busy = int_busy | status_reg[0];
wire sd_clk_o;
 
 
wire [7:0] bd_int_st_w;
`ifdef SD_CLK_BUS_CLK
assign sd_clk_i = wb_clk_i;
`endif
 
 
`ifdef SD_CLK_STATIC
assign sd_clk_o = sd_clk_i;
`endif
`ifdef SD_CLK_DYNAMIC
CLOCK_DIVIDER CLOCK_DIVIDER_1 (
.CLK (sd_clk_i),
.DIVIDER (clock_divider),
.RST (wb_rst_i),
.SD_CLK (sd_clk_o)
);
`endif
assign sd_clk_o_pad = sd_clk_o ;
wire [1:0]st_dat_t;
 
SD_CMD_MASTER cmd_master_1
(
.CLK_PAD_IO (wb_clk_i),
.SD_CLK_I (sd_clk_o),
.RST_PAD_I (wb_rst_i | software_reset_reg[0]),
.New_CMD (new_cmd),
.data_write (d_write),
.data_read (d_read),
.cmd_dat_i (sd_cmd_dat_i),
.cmd_out_o (sd_cmd_out_o),
.cmd_oe_o ( sd_cmd_oe_o),
.ARG_REG (argument_reg),
.CMD_SET_REG (cmd_setting_reg),
.STATUS_REG (status_reg_w),
.TIMEOUT_REG (time_out_reg),
.RESP_1_REG (cmd_resp_1_w),
 
.ERR_INT_REG (error_int_status_reg_w),
.NORMAL_INT_REG (normal_int_status_reg_w),
.CLK_DIVIDER (clock_divider),
.st_dat_t (st_dat_t)
);
 
 
 
SD_DATA_MASTER data_master_1
(
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.new_tx_bd (new_tx_bd),
.dat_in_tx (dat_out_s_tx_bd),
.free_tx_bd (free_bd_tx_bd),
.ack_i_s_tx ( ack_o_s_tx ),
.re_s_tx (re_s_tx_bd_w),
.a_cmp_tx (a_cmp_tx_bd_w),
.new_rx_bd (new_rx_bd),
.dat_in_rx (dat_out_s_rx_bd),
.free_rx_bd (free_bd_rx_bd),
.ack_i_s_rx ( ack_o_s_rx ),
.re_s_rx (re_s_rx_bd_w),
.a_cmp_rx (a_cmp_rx_bd_w),
.cmd_busy (cmd_busy),
.we_req (we_req_t),
.we_ack (we_ack),
.d_write ( d_write ),
.d_read ( d_read ),
.cmd_arg ( cmd_arg_m),
.cmd_set ( cmd_set_m),
.cmd_tsf_err (normal_int_status_reg[15]) ,
.card_status (cmd_resp_1[12:8]) ,
.start_tx_fifo (start_w),
.start_rx_fifo (start_r),
.sys_adr (sys_adr),
.tx_empt (tx_e ),
.rx_full(full_rx ),
.busy_n (busy_n),
.transm_complete (trans_complete ),
.crc_ok (crc_ok),
.ack_transfer (ack_transfer),
.bd_int_st (bd_int_st_w),
.bd_int_st_rst (Bd_isr_reset),
.CIDAT (cidat_w)
);
//Placeholder to rx fifo
wire [`SD_BUS_W -1 : 0 ]data_in_rx_fifo;
 
wire stop_transf;
wire [`SD_BUS_W -1 : 0 ] data_out_tx_fifo;
SD_DATA_SERIAL_HOST SD_DATA_SERIAL_HOST_1(
.sd_clk (sd_clk_o),
.rst (wb_rst_i | software_reset_reg[0]),
.data_in (data_out_tx_fifo),
.rd (rd),
.data_out (data_in_rx_fifo),
.we (we_rx),
.DAT_oe_o (sd_dat_oe_o),
.DAT_dat_o (sd_dat_out_o),
.DAT_dat_i (sd_dat_dat_i),
.start_dat (st_dat_t),
.ack_transfer (ack_transfer),
.busy_n (busy_n),
.transm_complete (trans_complete ),
.crc_ok (crc_ok)
);
 
 
 
 
SD_Bd rx_bd
(
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.we_m (we_m_rx_bd),
.re_m (re_m_rx_bd),
.dat_in_m (dat_in_m_rx_bd),
.dat_out_m (dat_out_m_rx_bd),
.free_bd (free_bd_rx_bd),
.new_bw (new_rx_bd),
.re_s (re_s_rx_bd),
.ack_o_s (ack_o_s_rx),
.a_cmp (a_cmp_rx_bd),
.dat_out_s (dat_out_s_rx_bd)
 
);
 
SD_Bd tx_bd
(
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.we_m (we_m_tx_bd),
.re_m (re_m_tx_bd),
.dat_in_m (dat_in_m_tx_bd),
.dat_out_m (dat_out_m_tx_bd),
.free_bd (free_bd_tx_bd),
.new_bw (new_tx_bd),
.ack_o_s (ack_o_s_tx),
.re_s (re_s_tx_bd),
.a_cmp (a_cmp_tx_bd),
.dat_out_s (dat_out_s_tx_bd)
 
);
//SD_Bd tx_bd
//(
 
 
 
 
wire [31:0] m_wb_dat_o_rx;
wire [3:0] m_wb_sel_o_tx;
wire [31:0] m_wb_adr_o_tx;
wire [31:0] m_wb_adr_o_rx;
 
SD_FIFO_TX_FILLER FIFO_filer_tx (
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.m_wb_adr_o (m_wb_adr_o_tx),
 
.m_wb_we_o (m_wb_we_o_tx),
 
.m_wb_dat_i (m_wb_dat_i),
.m_wb_cyc_o (m_wb_cyc_o_tx),
.m_wb_stb_o (m_wb_stb_o_tx),
.m_wb_ack_i ( m_wb_ack_i),
.en (start_w),
.adr (sys_adr),
.sd_clk (sd_clk_o),
.dat_o (data_out_tx_fifo ),
.rd ( rd ),
.empty (tx_e)
);
 
SD_FIFO_RX_FILLER FIFO_filer_rx (
.clk (wb_clk_i),
.rst (wb_rst_i | software_reset_reg[0]),
.m_wb_adr_o (m_wb_adr_o_rx),
 
.m_wb_we_o (m_wb_we_o_rx),
.m_wb_dat_o (m_wb_dat_o_rx),
.m_wb_cyc_o (m_wb_cyc_o_rx),
.m_wb_stb_o (m_wb_stb_o_rx),
.m_wb_ack_i ( m_wb_ack_i),
.en (start_r),
.adr (sys_adr),
.sd_clk (sd_clk_o),
.dat_i (data_in_rx_fifo ),
.wr ( we_rx ),
.full (full_rx)
);
 
assign m_wb_cyc_o = start_w ? m_wb_cyc_o_tx :start_r ?m_wb_cyc_o_rx: 0;
assign m_wb_stb_o = start_w ? m_wb_stb_o_tx :start_r ?m_wb_stb_o_rx: 0;
assign m_wb_dat_o = m_wb_dat_o_rx;
assign m_wb_we_o = start_w ? m_wb_we_o_tx :start_r ?m_wb_we_o_rx: 0;
assign m_wb_adr_o = start_w ? m_wb_adr_o_tx :start_r ?m_wb_adr_o_rx: 0;
 
 
 
always @ (re_s_tx_bd_w or a_cmp_tx_bd_w or re_s_rx_bd_w or a_cmp_rx_bd_w or we_req_t) begin
re_s_tx_bd<=re_s_tx_bd_w;
a_cmp_tx_bd <=a_cmp_tx_bd_w;
re_s_rx_bd <=re_s_rx_bd_w;
a_cmp_rx_bd<=a_cmp_rx_bd_w;
end
 
always @ ( free_bd_tx_bd or free_bd_rx_bd ) begin
Bd_Status_reg[15:8]=free_bd_rx_bd;
Bd_Status_reg[7:0]=free_bd_tx_bd;
end
 
wire status_reg_busy;
reg cmd_int_busy;
always @( cmd_resp_1_w or error_int_status_reg_w or normal_int_status_reg_w ) begin
 
 
cmd_resp_1<= cmd_resp_1_w;
 
normal_int_status_reg<= normal_int_status_reg_w ;
error_int_status_reg<= error_int_status_reg_w ;
end
 
 
always @ ( cidat_w or cmd_int_busy or status_reg_w or status_reg_busy or bd_int_st_w) begin
status_reg[0]<= status_reg_busy;
status_reg[15:1]<= status_reg_w[15:1];
 
status_reg[1] <= cidat_w;
Bd_isr_reg<=bd_int_st_w;
end
assign status_reg_busy = cmd_int_busy ? 1'b1: status_reg_w[0];
// generate acknowledge output signal
//always @(posedge wb_clk_i) begin
// wb_ack_o <= wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;
//end
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
we_m_rx_bd <= 0;
we_m_tx_bd <= 0;
new_cmd<= 1'b0 ;
we_ack <= 0;
int_ack = 1;
cmd_int_busy<=0;
if ( wb_rst_i )begin
argument_reg <=0;
cmd_setting_reg <= 0;
software_reset_reg <= 0;
time_out_reg <= 0;
normal_int_status_enable_reg <= 0;
error_int_status_enable_reg <= 0;
//normal_int_signal_enable_reg <= 0;
//error_int_signal_enable_reg <= 0;
clock_divider <=`RESET_CLK_DIV;
int_ack=1 ;
we<=0;
int_busy <=0;
we_ack <=0;
wb_ack_o=0;
cmd_int_busy<=0;
Bd_isr_reset<=0;
dat_in_m_tx_bd<=0;
dat_in_m_rx_bd<=0;
Bd_isr_enable_reg<=0;
end
else if ((wb_stb_i & wb_cyc_i) || wb_ack_o )begin //CS
Bd_isr_reset<=0;
if (wb_we_i) begin
case (wb_adr_i)
`argument: begin
argument_reg <= wb_dat_i;
new_cmd <= 1'b1 ;
end
`command : begin
cmd_setting_reg <= wb_dat_i;
int_busy <= 1;
end
`software : software_reset_reg <= wb_dat_i;
`timeout : time_out_reg <= wb_dat_i;
`normal_iser : normal_int_status_enable_reg <= wb_dat_i;
`error_iser : error_int_status_enable_reg <= wb_dat_i;
// `normal_isiger : normal_int_signal_enable_reg <= wb_dat_i;
// `error_isiger : error_int_signal_enable_reg <= wb_dat_i;
`clock_d: clock_divider <= wb_dat_i;
`bd_isr: Bd_isr_reset<= 1;
`bd_iser : Bd_isr_enable_reg <= wb_dat_i ;
`ifdef RAM_MEM_WIDTH_32
`endif
`ifdef RAM_MEM_WIDTH_16
`bd_rx: begin
we <= we+1;
we_m_rx_bd <= 1;
int_ack = 0;
if (we[1:0]==2'b00)
we_m_rx_bd <= 0;
else if (we[1:0]==2'b01)
dat_in_m_rx_bd <= wb_dat_i[15:0];
else if ( we[1:0]==2'b10)
dat_in_m_rx_bd <= wb_dat_i[31:16];
else begin
int_ack = 1;
we<= 0;
we_m_rx_bd <= 0;
end
end
`bd_tx: begin
we <= we+1;
we_m_tx_bd <= 1;
int_ack = 0;
if (we[1:0]==2'b00)
we_m_tx_bd <= 0;
else if (we[1:0]==2'b01)
dat_in_m_tx_bd <= wb_dat_i[15:0];
else if ( we[1:0]==2'b10)
dat_in_m_tx_bd <= wb_dat_i[31:16];
else begin
int_ack = 1;
we<= 0;
we_m_tx_bd <= 0;
end
end
`endif
endcase
end
wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;
end
else if (we_req_t) begin
new_cmd <= 1'b1 ;
cmd_setting_reg <= cmd_set_m;
argument_reg <= cmd_arg_m ;
cmd_int_busy<= 1;
we_ack <= 1;
end
if (status_reg[0])
int_busy <= 0;
//wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_ack_o & int_ack;
end
 
always @(posedge wb_clk_i )begin
if (wb_stb_i & wb_cyc_i) begin //CS
case (wb_adr_i)
`argument: wb_dat_o <= argument_reg ;
`command : wb_dat_o <= cmd_setting_reg ;
`status : wb_dat_o <= status_reg ;
`resp1 : wb_dat_o <= cmd_resp_1 ;
`controller : wb_dat_o <= controll_setting_reg ;
`block : wb_dat_o <= block_size_reg ;
`power : wb_dat_o <= power_controll_reg ;
`software : wb_dat_o <= software_reset_reg ;
`timeout : wb_dat_o <= time_out_reg ;
`normal_isr : wb_dat_o <= normal_int_status_reg ;
`error_isr : wb_dat_o <= error_int_status_reg ;
`normal_iser : wb_dat_o <= normal_int_status_enable_reg ;
`error_iser : wb_dat_o <= error_int_status_enable_reg ;
//`normal_isiger : wb_dat_o <= normal_int_signal_enable_reg ;
// `error_isiger : wb_dat_o <= error_int_signal_enable_reg ;
`capa : wb_dat_o <= capabilies_reg ;
`bd_status : wb_dat_o <= Bd_Status_reg;
`bd_isr : wb_dat_o <= Bd_isr_reg ;
`bd_iser : wb_dat_o <= Bd_isr_enable_reg ;
endcase
end
end
 
 
 
 
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_data_host.v
0,0 → 1,348
//-------------------------
//-------------------------
 
 
 
 
`include "SD_defines.v"
 
 
module SD_DATA_SERIAL_HOST(
input sd_clk,
input rst,
//Tx Fifo
input [`SD_BUS_W-1:0] data_in ,
 
output reg rd,
//Rx Fifo
output reg [`SD_BUS_W-1:0] data_out ,
output reg we,
//tristate data
output reg DAT_oe_o,
output reg[`SD_BUS_W-1:0] DAT_dat_o,
input [`SD_BUS_W-1:0] DAT_dat_i,
//Controll signals
input [1:0] start_dat,
input ack_transfer,
 
output reg busy_n,
output reg transm_complete,
output reg crc_ok
);
 
//CRC16
reg [`SD_BUS_W-1:0] crc_in;
reg crc_en;
reg crc_rst;
wire [15:0] crc_out [`SD_BUS_W-1:0];
reg [`SD_BUS_W-1:0] temp_in;
reg [10:0] transf_cnt;
parameter SIZE = 6;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 6'b000001;
parameter WRITE_DAT = 6'b000010;
parameter WRITE_CRC = 6'b000100;
parameter WRITE_BUSY = 6'b001000;
parameter READ_WAIT = 6'b010000;
parameter READ_DAT = 6'b100000;
reg [2:0] crc_status;
reg busy_int;
genvar i;
generate
for(i=0; i<`SD_BUS_W; i=i+1) begin:CRC_16_gen
CRC_16 CRC_16_i (crc_in[i],crc_en, sd_clk, crc_rst, crc_out[i]);
end
endgenerate
 
reg ack_transfer_int;
always @ (posedge sd_clk or posedge rst )
begin
if (rst)
ack_transfer_int <=0;
else
ack_transfer_int<=ack_transfer;
end
reg q_start_bit;
always @ (state or start_dat or q_start_bit or transf_cnt or crc_status or busy_int or DAT_dat_i or ack_transfer_int)
begin : FSM_COMBO
next_state = 0;
case(state)
IDLE: begin
if (start_dat == 2'b01)
next_state=WRITE_DAT;
else if (start_dat == 2'b10)
next_state=READ_WAIT;
else
next_state=IDLE;
end
WRITE_DAT: begin
if (transf_cnt >= `BIT_BLOCK)
next_state= WRITE_CRC;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=WRITE_DAT;
end
 
WRITE_CRC: begin
if (crc_status ==0)
next_state= WRITE_BUSY;
else
next_state=WRITE_CRC;
end
WRITE_BUSY: begin
if ( (busy_int ==1) & ack_transfer_int)
next_state= IDLE;
else
next_state = WRITE_BUSY;
end
READ_WAIT: begin
if (q_start_bit== 0 )
next_state= READ_DAT;
else
next_state=READ_WAIT;
end
READ_DAT: begin
if ( ack_transfer_int) //Startbit consumed...
next_state= IDLE;
else if (start_dat == 2'b11)
next_state=IDLE;
else
next_state=READ_DAT;
end
endcase
end
 
always @ (posedge sd_clk or posedge rst )
begin
if (rst ) begin
q_start_bit<=1;
end
else begin
q_start_bit <= DAT_dat_i[0];
end
end
 
 
//----------------Seq logic------------
always @ (posedge sd_clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
 
reg [4:0] crc_c;
reg [3:0] last_din;
reg [2:0] crc_s ;
always @ (negedge sd_clk or posedge rst )
begin
if (rst) begin
DAT_oe_o<=0;
crc_en<=0;
crc_rst<=1;
transf_cnt<=0;
crc_c<=15;
rd<=0;
last_din<=0;
crc_c<=0;
crc_in<=0;
DAT_dat_o<=0;
crc_status<=7;
crc_s<=0;
transm_complete<=0;
busy_n<=1;
we<=0;
data_out<=0;
crc_ok<=0;
busy_int<=0;
end
else begin
case(state)
IDLE: begin
DAT_oe_o<=0;
DAT_dat_o<=4'b1111;
crc_en<=0;
crc_rst<=1;
transf_cnt<=0;
crc_c<=16;
crc_status<=7;
crc_s<=0;
we<=0;
rd<=0;
busy_n<=1;
end
WRITE_DAT: begin
transm_complete <=0;
busy_n<=0;
crc_ok<=0;
transf_cnt<=transf_cnt+1;
if (transf_cnt==1) begin
rd<=1;
crc_rst<=0;
crc_en<=1;
last_din <=data_in;
DAT_oe_o<=1;
DAT_dat_o<=0;
crc_in<= data_in;
end
else if ( (transf_cnt>=2) && (transf_cnt<=`BIT_BLOCK-`CRC_OFF )) begin
rd<=1;
DAT_oe_o<=1;
DAT_dat_o<= last_din;
last_din <=data_in;
crc_in<= data_in;
if ( transf_cnt >=`BIT_BLOCK-`CRC_OFF ) begin
crc_en<=0;
end
end
else if (transf_cnt>`BIT_BLOCK-`CRC_OFF & crc_c!=0) begin
rd<=0;
crc_en<=0;
crc_c<=crc_c-1;
DAT_oe_o<=1;
DAT_dat_o[0]<=crc_out[0][crc_c-1];
DAT_dat_o[1]<=crc_out[1][crc_c-1];
DAT_dat_o[2]<=crc_out[2][crc_c-1];
DAT_dat_o[3]<=crc_out[3][crc_c-1];
end
else if (transf_cnt==`BIT_BLOCK-2) begin
DAT_oe_o<=1;
DAT_dat_o<=4'b1111;
rd<=0;
end
else if (transf_cnt !=0) begin
DAT_oe_o<=0;
rd<=0;
end
end
WRITE_CRC : begin
rd<=0;
DAT_oe_o<=0;
crc_status<=crc_status-1;
if (( crc_status<=4) && ( crc_status>=2) )
crc_s[crc_status-2] <=DAT_dat_i[0];
end
WRITE_BUSY : begin
transm_complete <=1;
if (crc_s == 3'b010)
crc_ok<=1;
else
crc_ok<=0;
busy_int<=DAT_dat_i[0];
`ifdef SIM
crc_ok<=1;
`endif
/* `ifdef NO_CRC_CHECK_ON_WRITE_DATA
crc_ok<=1;
`endif
*/
end
READ_WAIT:begin
DAT_oe_o<=0;
crc_rst<=0;
crc_en<=1;
crc_in<=0;
crc_c<=15;// end
busy_n<=0;
transm_complete<=0;
end
READ_DAT: begin
if (transf_cnt<`BIT_BLOCK_REC) begin
we<=1;
data_out<=DAT_dat_i;
crc_in<=DAT_dat_i;
crc_ok<=1;
transf_cnt<=transf_cnt+1;
end
else if ( transf_cnt <= (`BIT_BLOCK_REC +`BIT_CRC_CYCLE)) begin
transf_cnt<=transf_cnt+1;
crc_en<=0;
last_din <=DAT_dat_i;
if (transf_cnt> `BIT_BLOCK_REC) begin
crc_c<=crc_c-1;
we<=0;
`ifdef SD_BUS_WIDTH_1
if (crc_out[0][crc_status] == last_din[0])
crc_ok<=0;
`endif
`ifdef SD_BUS_WIDTH_4
if (crc_out[0][crc_c] != last_din[0])
crc_ok<=0;
if (crc_out[1][crc_c] != last_din[1])
crc_ok<=0;
if (crc_out[2][crc_c] != last_din[2])
crc_ok<=0;
if (crc_out[3][crc_c] != last_din[3])
crc_ok<=0;
`endif
`ifdef SIM
crc_ok<=1;
`endif
if (crc_c==0) begin
transm_complete <=1;
busy_n<=0;
we<=0;
end
end
end
end
endcase
end
 
end
 
 
 
 
 
 
 
 
//Sync
 
 
 
 
 
endmodule
 
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v
0,0 → 1,124
`include "SD_defines.v"
 
 
module sd_rx_fifo
(
input [4-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [1:0] mem_empt,
input rclk,
input rst
);
reg [32-1:0] ram [0:`FIFO_RX_MEM_DEPTH-1];
reg [`FIFO_RX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
reg [8-1:0] we;
reg [4*(8)-1:0] tmp;
reg ft;
always @ (posedge wclk or posedge rst)
if (rst)
we <= 8'h1;
else
if (wr)
we <= {we[8-2:0],we[8-1]};
always @ (posedge wclk or posedge rst)
if (rst) begin
tmp <= {4*(8-1){1'b0}};
ft<=0;
end
else
begin
`ifdef LITTLE_ENDIAN
if (wr & we[7]) begin
tmp[4*1-1:4*0] <= d;
ft<=1; end
if (wr & we[6])
tmp[4*2-1:4*1] <= d;
if (wr & we[5])
tmp[4*3-1:4*2] <= d;
if (wr & we[4])
tmp[4*4-1:4*3] <= d;
if (wr & we[3])
tmp[4*5-1:4*4] <= d;
if (wr & we[2])
tmp[4*6-1:4*5] <= d;
if (wr & we[1])
tmp[4*7-1:4*6] <= d;
if (wr & we[0])
tmp[4*8-1:4*7] <= d;
`endif
`ifdef BIG_ENDIAN
if (wr & we[0])
tmp[4*2-1:4*1] <= d;
if (wr & we[1])
tmp[4*1-1:4*0] <= d;
if (wr & we[2])
tmp[4*4-1:4*3] <= d;
if (wr & we[3])
tmp[4*3-1:4*2] <= d;
if (wr & we[4])
tmp[4*6-1:4*5] <= d;
if (wr & we[5])
tmp[4*5-1:4*4] <= d;
if (wr & we[6])
tmp[4*8-1:4*7] <= d;
if (wr & we[7]) begin
tmp[4*7-1:4*6] <= d;
ft<=1;
end
`endif
end
assign ram_we = wr & we[0] &ft;
assign ram_din = tmp;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_RX_MEM_DEPTH-1) begin
adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_RX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_RX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_RX_MEM_ADR_SIZE'h0;
else
if (!empty & rd)
if (adr_o == `FIFO_RX_MEM_DEPTH-1) begin
adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_RX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_RX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_RX_MEM_ADR_SIZE'h1;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign full = (adr_i[`FIFO_RX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_RX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_RX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[`FIFO_RX_MEM_ADR_SIZE-2:0]];
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/smii_tx_fifo.v
0,0 → 1,72
`include "SD_defines.v"
 
 
module sd_tx_fifo
(
input [4-1:0] d,
input wr,
input wclk,
output [4-1:0] q,
input rd,
output full,
output empty,
output [5:0] mem_empt,
input rclk,
input rst
);
reg [4-1:0] ram [0:`FIFO_TX_MEM_DEPTH-1];
reg [`FIFO_TX_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [4-1:0] ram_din;
 
assign ram_we = wr & ~full;
assign ram_din = d;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_TX_MEM_DEPTH-1) begin
adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_TX_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_TX_MEM_ADR_SIZE'h1;
always @ (posedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_TX_MEM_ADR_SIZE'h0;
else
if (!empty & rd) begin
if (adr_o == `FIFO_TX_MEM_DEPTH-1) begin
adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_TX_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_TX_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_TX_MEM_ADR_SIZE'h1;
end
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign full= ( adr_i[`FIFO_TX_MEM_ADR_SIZE-2:0] == adr_o[`FIFO_TX_MEM_ADR_SIZE-2:0] ) & (adr_i[`FIFO_TX_MEM_ADR_SIZE-1] ^ adr_o[`FIFO_TX_MEM_ADR_SIZE-1]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[5:0]];
endmodule
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/smii_rx_fifo_tb.v
0,0 → 1,128
// module name
`define MODULE_NAME sd_rx_fifo
 
 
module sd_rx_fifo_tb ( );
reg [4-1:0] d;
reg wr;
reg wclk;
wire [32-1:0] q;
reg rd;
wire fe;
reg rclk;
reg rst;
wire empty;
reg [31:0] slask;
wire [1:0] mem_empt;
sd_rx_fifo sd_rx_fifo_1(
.d (d),
.wr (wr),
.wclk (wclk),
.q (q),
.rd (rd),
.full (fe),
.empty (empty),
.mem_empt (mem_empt),
.rclk (rclk),
.rst (rst)
);
 
 
event reset_trigger;
event reset_done_trigger;
event start_trigger;
event start_done_trigger;
 
reg [3:0] send [16:0];
reg [3:0] send_c;
reg start;
reg sw;
initial
begin
wclk=0;
rst=0;
rclk=0;
d =0;
rst=0;
wr=0;
#5 ->reset_trigger;
send [0] = 4'ha;
send [1] = 4'hb;
send [2] = 4'hc;
send [3] = 4'hd;
send [4] = 4'he;
send [5] = 4'hf;
send [6] = 4'hd;
send [7] = 4'hc;
send [8] = 4'hf;
send [9] = 4'he;
send [10] = 4'hd;
send [11] = 4'hc;
send [12] = 4'hb;
send [13] = 4'ha;
send [14] = 4'ha;
send [15] = 4'hb;
send_c =0;
sw=0;
start=0;
end
 
 
always begin
#5 rclk = !rclk;
end
 
always begin
#10 wclk = !wclk;
end
 
 
 
initial begin
forever begin
@ (reset_trigger);
@ (posedge wclk);
rst =1 ;
@ (posedge wclk);
rst = 0;
#20
start=1;
-> reset_done_trigger;
end
end
 
always @ (posedge rclk)
if (!empty) begin
rd=1;
slask =q;
end
else
rd=0;
always @ (posedge wclk)
begin
if(start)
sw=~sw;
if (sw) begin
d=send[send_c];
wr=1;
send_c=send_c+1; end
else begin
wr=0;
end
// if (!rd) begin
// @ (posedge rclk);
// slask =q;
// rd=1;
// @ (posedge rclk);
// rd=0;
// end
end
endmodule
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/SD_defines.v
0,0 → 1,77
//Read the documentation before changing values
 
`define BIG_ENDIAN
//`define LITLE_ENDIAN
 
//`define SIM
`define SYN
 
`define ACTEL
 
//`define CUSTOM
//`define ALTERA
//`define XLINX
//`define SIMULATOR
 
//MAX 255 BD
//BD size/4
 
`ifdef ACTEL
`define NR_O_BD_4
`define BD_WIDTH 4
`define BD_SIZE 16
`define RAM_MEM_WIDTH_16
`define RAM_MEM_WIDTH 16
`endif
 
`define RESEND_MAX_CNT 3
 
`ifdef SYN
`define RESET_CLK_DIV 2
`define MEM_OFFSET 4
`endif
 
`ifdef SIM
`define RESET_CLK_DIV 0
`define MEM_OFFSET 1
`endif
 
//SD-Clock Defines ---------
//Use bus clock or a seperate clock
`define SD_CLK_BUS_CLK
//`define SD_CLK_SEP
 
// Use of internal clock divider
//`define SD_CLK_STATIC
`define SD_CLK_DYNAMIC
 
 
//SD DATA-transfer defines---
`define BLOCK_SIZE 512
`define SD_BUS_WIDTH_4
`define SD_BUS_W 4
 
//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.
//Add 18 for crc, endbit and z.
`define BIT_BLOCK 1044
`define CRC_OFF 19
`define BIT_BLOCK_REC 1024
 
`define BIT_CRC_CYCLE 16
 
 
//FIFO defines---------------
`define FIFO_RX_MEM_DEPTH 4
`define FIFO_RX_MEM_ADR_SIZE 3
 
`define FIFO_TX_MEM_DEPTH 64
`define FIFO_TX_MEM_ADR_SIZE 7
//---------------------------
 
 
 
 
 
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/smii_tx_fifo_tb.v
0,0 → 1,130
// module name
`define MODULE_NAME sd_rx_fifo
 
 
module sd_tx_fifo_tb ( );
reg [4-1:0] d;
reg wr;
reg wclk;
wire [4-1:0] q;
reg rd;
wire fe;
reg rclk;
reg rst;
wire empty;
reg [31:0] slask;
wire [1:0] mem_empt;
sd_tx_fifo sd_tx_fifo_1(
.d (d),
.wr (wr),
.wclk (wclk),
.q (q),
.rd (rd),
.full (fe),
.empty (empty),
.mem_empt (mem_empt),
.rclk (rclk),
.rst (rst)
);
 
 
event reset_trigger;
event reset_done_trigger;
event start_trigger;
event start_done_trigger;
 
reg [3:0] send [16:0];
reg [3:0] send_c;
reg start;
reg sw;
initial
begin
wclk=0;
rst=0;
rclk=0;
d =0;
rst=0;
wr=0;
#5 ->reset_trigger;
send [0] = 4'ha;
send [1] = 4'hb;
send [2] = 4'hc;
send [3] = 4'hd;
send [4] = 4'he;
send [5] = 4'hf;
send [6] = 4'hd;
send [7] = 4'hc;
send [8] = 4'hf;
send [9] = 4'he;
send [10] = 4'hd;
send [11] = 4'hc;
send [12] = 4'hb;
send [13] = 4'ha;
send [14] = 4'ha;
send [15] = 4'hb;
send_c =0;
sw=0;
start=0;
end
 
 
always begin
#5 rclk = !rclk;
end
 
always begin
#10 wclk = !wclk;
end
 
 
 
initial begin
forever begin
@ (reset_trigger);
@ (posedge wclk);
rst =1 ;
@ (posedge wclk);
rst = 0;
#20
start=1;
-> reset_done_trigger;
end
end
 
always @ (posedge rclk)
if (!empty) begin
rd=1;
slask =q;
end
else
rd=0;
always @ (posedge wclk)
begin
if(start)
sw=~sw;
if (sw) begin
d=send[send_c];
wr=1;
send_c=send_c+1; end
else begin
wr=0;
end
// if (!rd) begin
// @ (posedge rclk);
// slask =q;
// rd=1;
// @ (posedge rclk);
// rd=0;
// end
end
endmodule
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v.bak
0,0 → 1,124
`include "SD_defines.v"
`define FIFO_MEM_DEPTH 4
`define FIFO_MEM_ADR_SIZE 3
 
module sd_rx_fifo
(
input [4-1:0] d,
input wr,
input wclk,
output [32-1:0] q,
input rd,
output full,
output empty,
output [1:0] mem_empt,
input rclk,
input rst
);
reg [32-1:0] ram [0:`FIFO_MEM_DEPTH-1];
reg [`FIFO_MEM_ADR_SIZE-1:0] adr_i, adr_o;
wire ram_we;
wire [32-1:0] ram_din;
reg [8-1:0] we;
reg [4*(8)-1:0] tmp;
reg ft;
always @ (posedge wclk or posedge rst)
if (rst)
we <= 8'h1;
else
if (wr)
we <= {we[8-2:0],we[8-1]};
always @ (posedge wclk or posedge rst)
if (rst) begin
tmp <= {4*(8-1){1'b0}};
ft<=0;
end
else
begin
`ifdef LITTLE_ENDIAN
if (wr & we[7]) begin
tmp[4*1-1:4*0] <= d;
ft<=1; end
if (wr & we[6])
tmp[4*2-1:4*1] <= d;
if (wr & we[5])
tmp[4*3-1:4*2] <= d;
if (wr & we[4])
tmp[4*4-1:4*3] <= d;
if (wr & we[3])
tmp[4*5-1:4*4] <= d;
if (wr & we[2])
tmp[4*6-1:4*5] <= d;
if (wr & we[1])
tmp[4*7-1:4*6] <= d;
if (wr & we[0])
tmp[4*8-1:4*7] <= d;
`endif
`ifdef BIG_ENDIAN
if (wr & we[0])
tmp[4*1-1:4*0] <= d;
if (wr & we[1])
tmp[4*2-1:4*1] <= d;
if (wr & we[2])
tmp[4*3-1:4*2] <= d;
if (wr & we[3])
tmp[4*4-1:4*3] <= d;
if (wr & we[4])
tmp[4*5-1:4*4] <= d;
if (wr & we[5])
tmp[4*6-1:4*5] <= d;
if (wr & we[6])
tmp[4*7-1:4*6] <= d;
if (wr & we[7]) begin
tmp[4*8-1:4*7] <= d;
ft<=1;
end
`endif
end
assign ram_we = wr & we[0] &ft;
assign ram_din = tmp;
always @ (posedge wclk)
if (ram_we)
ram[adr_i[`FIFO_MEM_ADR_SIZE-2:0]] <= ram_din;
always @ (posedge wclk or posedge rst)
if (rst)
adr_i <= `FIFO_MEM_ADR_SIZE'h0;
else
if (ram_we)
if (adr_i == `FIFO_MEM_DEPTH-1) begin
adr_i[`FIFO_MEM_ADR_SIZE-2:0] <=0;
adr_i[`FIFO_MEM_ADR_SIZE-1]<=~adr_i[`FIFO_MEM_ADR_SIZE-1];
end
else
adr_i <= adr_i + `FIFO_MEM_ADR_SIZE'h1;
always @ (negedge rclk or posedge rst)
if (rst)
adr_o <= `FIFO_MEM_ADR_SIZE'h0;
else
if (!empty & rd)
if (adr_o == `FIFO_MEM_DEPTH-1) begin
adr_o[`FIFO_MEM_ADR_SIZE-2:0] <=0;
adr_o[`FIFO_MEM_ADR_SIZE-1] <=~adr_o[`FIFO_MEM_ADR_SIZE-1];
end
else
adr_o <= adr_o + `FIFO_MEM_ADR_SIZE'h1;
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign full = (adr_i[1:0] == adr_o[1:0] ) & (adr_i[2] ^ adr_o[2]) ;
assign empty = (adr_i == adr_o) ;
assign mem_empt = ( adr_i-adr_o);
assign q = ram[adr_o[1:0]];
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
0,0 → 1,97
`include "SD_defines.v"
module SD_FIFO_RX_FILLER
(
input clk,
input rst,
//WB Signals
output [31:0] m_wb_adr_o,
 
output reg m_wb_we_o,
 
output reg [31:0] m_wb_dat_o,
output reg m_wb_cyc_o,
output reg m_wb_stb_o,
input m_wb_ack_i,
//output [2:0] m_wb_cti_o,
//output [1:0] m_wb_bte_o,
 
//Data Master Control signals
input en,
input [31:0] adr,
 
//Data Serial signals
input sd_clk,
input [`SD_BUS_W-1:0] dat_i,
input wr,
output full
//
 
);
wire [31:0] dat_o;
reg rd;
reg reset_rx_fifo;
sd_rx_fifo Rx_Fifo (
.d ( dat_i ),
.wr ( wr ),
.wclk (sd_clk),
.q ( dat_o),
.rd (rd),
.full (full),
.empty (empty),
.mem_empt (),
.rclk (clk),
.rst (rst | reset_rx_fifo)
);
 
//reg [31:0] tmp_dat;
reg [8:0] offset;
assign m_wb_adr_o = adr+offset;
//assign m_wb_dat_o = dat_o;
reg ackd;
always @(posedge clk or posedge rst )begin
 
if (rst) begin
offset<=0;
m_wb_we_o <=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
ackd<=1;
m_wb_dat_o<=0;
rd<=0;
reset_rx_fifo<=1;
end
else if (en) begin//Start filling the TX buffer
rd<=0;
reset_rx_fifo<=0;
if (!empty & ackd) begin
rd<=1;
m_wb_dat_o<=dat_o;
m_wb_we_o <=1;
m_wb_cyc_o <= 1;
m_wb_stb_o <= 1;
ackd<=0;
end
if( !ackd & m_wb_ack_i) begin
m_wb_we_o <=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
offset<=offset+`MEM_OFFSET;
ackd<=1;
end
end
else begin
reset_rx_fifo<=1;
rd<=0;
offset<=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
m_wb_we_o <=0;
ackd<=1;
end
 
end
endmodule
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_controller_top_tb.v
0,0 → 1,354
//`define TX_ERROR_TEST
 
module SD_CONTROLLER_TOP_TB(
 
);
 
// WISHBONE common
 
reg wb_clk_i; // WISHBONE clock
reg wb_rst; // WISHBONE reset
reg [31:0] wbs_sds_dat_i; // WISHBONE data input
wire [31:0] wbs_sds_dat_o; // WISHBONE data output
// WISHBONE error output
// WISHBONE slave
reg [9:0] wbs_sds_adr_i; // WISHBONE address input
reg [3:0] wbs_sds_sel_i; // WISHBONE byte select input
reg wbs_sds_we_i; // WISHBONE write enable input
reg wbs_sds_cyc_i; // WISHBONE cycle input
reg wbs_sds_stb_i; // WISHBONE strobe input
wire wbs_sds_ack_o; // WISHBONE acknowledge output
// WISHBONE master
wire [31:0] wbm_sdm_adr_o;
wire [3:0] wbm_sdm_sel_o;
wire wbm_sdm_we_o;
 
wire [31:0] wbm_sdm_dat_i;
wire [31:0] wbm_sdm_dat_o;
wire wbm_sdm_cyc_o;
wire wbm_sdm_stb_o;
reg wbm_sdm_ack_i;
wire [2:0] wbm_sdm_cti_o;
wire [1:0] wbm_sdm_bte_o;
//SD port
 
 
 
 
reg [3:0] sd_dat_pad_i;
wire [3:0] sd_dat_out;
wire sd_dat_oe_o;
reg sd_cmd_dat_i;
wire sd_cmd_out_o;
wire sd_cmd_oe_o;
wire sd_clk;
 
wire sd_cmd_oe;
wire sd_cmd_out;
wire sd_dat_oe;
wire [3:0] sd_dat_pad_io;
reg bluff_in;
reg [3:0] data_bluff_in;
assign sd_cmd_pad_io = sd_cmd_oe ? sd_cmd_out : 1'bZ ;
assign sd_dat_pad_io = sd_dat_oe ? sd_dat_out : 4'bzzzz ;
 
SD_CONTROLLER_TOP sd_controller_top_0
(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst),
.wb_dat_i(wbs_sds_dat_i),
.wb_dat_o(wbs_sds_dat_o),
.wb_adr_i(wbs_sds_adr_i[7:0]),
.wb_sel_i(wbs_sds_sel_i),
.wb_we_i(wbs_sds_we_i),
.wb_stb_i(wbs_sds_stb_i),
.wb_cyc_i(wbs_sds_cyc_i),
.wb_ack_o(wbs_sds_ack_o),
.m_wb_adr_o(wbm_sdm_adr_o),
.m_wb_sel_o(wbm_sdm_sel_o),
.m_wb_we_o(wbm_sdm_we_o),
.m_wb_dat_o(wbm_sdm_dat_o),
.m_wb_dat_i(wbm_sdm_dat_i),
.m_wb_cyc_o(wbm_sdm_cyc_o),
.m_wb_stb_o(wbm_sdm_stb_o),
.m_wb_ack_i(wbm_sdm_ack_i),
.m_wb_cti_o(wbm_sdm_cti_o),
.m_wb_bte_o(wbm_sdm_bte_o),
.sd_cmd_dat_i(bluff_in),
.sd_cmd_out_o (sd_cmd_out ),
.sd_cmd_oe_o (sd_cmd_oe),
.sd_dat_dat_i (data_bluff_in), //sd_dat_pad_io),
.sd_dat_out_o ( sd_dat_out ) ,
.sd_dat_oe_o ( sd_dat_oe ),
.sd_clk_o (sd_clk_pad_o)
);
 
reg [31:0] sd_mem [0:256];
reg [3:0] dat_mem [0:1040];
reg [31:0]in_mem [0:512];
 
// Fill the memory with values taken from a data file
initial $readmemh("data2.txt",sd_mem);
initial $readmemh("data_dat.txt",dat_mem);
// Display the contents of memory
integer k;
initial begin
$display("Contents of Mem after reading data file:");
for (k=0; k<256; k=k+1) $display("%d:%h",k,sd_mem[k]);
end
 
initial begin
$display("Contents of Mem after reading data file:");
for (k=1000; k<1040; k=k+1) $display("%d:%h",k,dat_mem[k]);
end
 
 
reg [13:0] dat_mem_cnt;
 
reg [3:0] i2;
reg [24:0] out_cnt;
reg [24:0] out_cnt3;
reg [31:0] reg_out [0:7];
reg [31:0] adr_out [0:7];
reg asd[3:0];
reg [2:0] i;
event reset_trigger;
event reset_done_trigger;
event start_trigger;
event start_done_trigger;
reg [3:0] cnta;
reg [12:0] in_mem_cnt;
initial
begin
wb_clk_i =0; // WISHBONE clock
wb_rst =0; // WISHBONE reset
wbs_sds_dat_i =0; // WISHBONE data input
wbs_sds_adr_i =0; // WISHBONE address input
wbs_sds_sel_i =0; // WISHBONE byte select input
wbs_sds_we_i =0; // WISHBONE write enable input
wbs_sds_cyc_i =0; // WISHBONE cycle input
wbs_sds_stb_i =0; // WISHBONE strobe input
cnta = 5'b01010;
wbm_sdm_ack_i =0 ;
sd_dat_pad_i = 0;
sd_cmd_dat_i = 0;
out_cnt =0;
dat_mem_cnt=0;
i=0;
out_cnt3=0;
i2=0;
in_mem_cnt=0;
asd[0]=1'h1;
asd[1]=1'h1;
asd[2]=1'h0;
asd[3]=1'h1;
asd[4]=1'h0;
asd[5]=1'h0;
asd[6]=1'h0;
asd[7]=1'h1;
sd_cmd_dat_i = 0 ;
reg_out[0] <= 32'h777F; //Timeout
reg_out[1] <= 32'b0000_0000_0000_0000_0000_0000_0000_0001; //Clock div
//reg_out[2] <= 32'h211; //cmd_setting_reg
//reg_ou1t3] <= 32'b0000_0000_0000_0000_0000_0000_0000_0001; //argument_reg
 
reg_out[2] <= 32'h0; //System
reg_out[3] <= 32'h0; //card
reg_out[4] <= 128;
reg_out[5] <= 135248;
 
adr_out[0] <= 32'b0000_0000_0000_0000_0000_0000_0010_1100;
adr_out[1] <= 32'b0000_0000_0000_0000_0000_0000_0100_1100;
//adr_out[2] <= 32'b0000_0000_0000_0000_0000_0000_0000_0100;
//adr_out[3] <= 32'b0000_0000_0000_0000_0000_0000_0000_0000;
 
adr_out[2] <= 32'h60;
adr_out[3] <= 32'h60;
adr_out[4] <= 32'h80;
adr_out[5] <= 32'h80;
 
 
//adr_out[2] <= 32'h80;
//adr_out[3] <= 32'h80;
//adr_out[4] <= 32'h80;
//adr_out[5] <= 32'h80;
 
#5 ->reset_trigger;
end
 
reg [31:0]tempo;
 
initial begin
forever begin
@ (reset_trigger);
@ (posedge wb_clk_i);
wb_rst =1 ;
@ (posedge wb_clk_i);
wb_rst = 0;
wbs_sds_dat_i <= reg_out[out_cnt][31:0];
wbs_sds_we_i <=1;
wbs_sds_stb_i <=1;
wbs_sds_cyc_i <=1;
wbs_sds_adr_i <= adr_out[out_cnt];
out_cnt = out_cnt +1;
-> reset_done_trigger;
end
end
 
always begin
#5 wb_clk_i = !wb_clk_i;
end
always @ (posedge wb_clk_i) begin
if (out_cnt <=6) begin
if (wbs_sds_ack_o == 1) begin
wbs_sds_dat_i <= reg_out[out_cnt][31:0];
wbs_sds_we_i <= 1;
wbs_sds_stb_i <= 1;
wbs_sds_cyc_i <= 1;
wbs_sds_adr_i <=adr_out[out_cnt];
out_cnt = out_cnt +1;
end
end
else begin
wbs_sds_we_i <=0;
wbs_sds_stb_i <=0;
wbs_sds_cyc_i <=0;
out_cnt = out_cnt +1;
end
// if (out_cnt==76)
// out_cnt=2;
if (out_cnt==100) begin
data_bluff_in<=4'b1011;
bluff_in<=1;
end
if (out_cnt==110) begin
bluff_in<=0;
end
 
if ((out_cnt>750) && (out_cnt<758)) begin
tempo <=wbs_sds_dat_i;
wbs_sds_we_i <= 1;
wbs_sds_stb_i <= 1;
wbs_sds_cyc_i <= 1;
wbs_sds_adr_i <=8'h54;
out_cnt = out_cnt +1;
end
if (out_cnt==758) begin
wbs_sds_dat_i <= 0;
wbs_sds_we_i <= 0;
wbs_sds_stb_i <= 0;
wbs_sds_cyc_i <= 0;
wbs_sds_adr_i <=0;
end
if (out_cnt==4620) begin
wbs_sds_dat_i <= 32'b0;
wbs_sds_we_i <= 1;
wbs_sds_stb_i <= 1;
wbs_sds_cyc_i <= 1;
wbs_sds_adr_i <=32'h54;
out_cnt = out_cnt +1;
end
if (out_cnt==4622) begin
wbs_sds_dat_i <= 32'b0;
wbs_sds_we_i <= 0;
wbs_sds_stb_i <= 0;
wbs_sds_cyc_i <= 0;
wbs_sds_adr_i <=32'h54;
out_cnt = out_cnt +1;
end
 
end
always @ (posedge sd_clk_pad_o) begin
out_cnt3<=out_cnt3+1;
if (out_cnt>115) begin
i=i+1;
if (i>3)
i=0;
bluff_in<=asd[i];
end
if (out_cnt3>=104) begin
data_bluff_in<=4'b0000;
end
if (out_cnt3>=105) begin
data_bluff_in <= dat_mem[dat_mem_cnt];
dat_mem_cnt=dat_mem_cnt+1;
end
if (out_cnt3==1151)
data_bluff_in <=4'b1111;
if (out_cnt3==1152)
data_bluff_in <=4'b1111;
if (out_cnt3==1153)
data_bluff_in <=4'b1110;
if (out_cnt3==1154)
data_bluff_in <=4'b1110;
if (out_cnt3==1155)
data_bluff_in <=4'b1111;
if (out_cnt3==1156)
data_bluff_in <=4'b1110;
if (out_cnt3==1157)
data_bluff_in <=4'b1111;
if (out_cnt3>=1158)
data_bluff_in <=4'b1110;
 
if (out_cnt3>=1185) begin
data_bluff_in <=4'b1111;
out_cnt3<=0;
dat_mem_cnt<=0;
end
end
 
assign wbm_sdm_dat_i = sd_mem[wbm_sdm_adr_o];
 
 
 
always @ (posedge wb_clk_i) begin
i2<=i2+1;
if (wbm_sdm_cyc_o & wbm_sdm_stb_o &!wbm_sdm_we_o) begin
if (cnta[i2]==1)
wbm_sdm_ack_i<=1;
 
end
 
else if (wbm_sdm_cyc_o & wbm_sdm_stb_o &wbm_sdm_we_o) begin
if (cnta[i2]==1) begin
wbm_sdm_ack_i<=1;
in_mem[in_mem_cnt]<= wbm_sdm_dat_o;
in_mem_cnt<=in_mem_cnt+1;
end
end
else begin
wbm_sdm_ack_i <=0;
end
`ifdef TX_ERROR_TEST
if ((out_cnt >3000 ) && (out_cnt <3300 )) begin
wbm_sdm_ack_i <=0;
end
`endif
end
 
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
0,0 → 1,187
`include "SD_defines.v"
module SD_FIFO_TX_FILLER
(
input clk,
input rst,
//WB Signals
output [31:0] m_wb_adr_o,
 
output reg m_wb_we_o,
input [31:0] m_wb_dat_i,
 
output reg m_wb_cyc_o,
output reg m_wb_stb_o,
input m_wb_ack_i,
//output [2:0] m_wb_cti_o,
//output [1:0] m_wb_bte_o,
 
//Data Master Control signals
input en,
input [31:0] adr,
 
 
//Data Serial signals
input sd_clk,
output [`SD_BUS_W-1:0] dat_o,
input rd,
output empty
//
 
);
reg reset_tx_fifo;
 
reg [3:0] din;
reg wr_tx;
reg [8:0] we;
reg [8:0] offset;
wire [5:0]mem_empt;
sd_tx_fifo Tx_Fifo (
.d ( din ),
.wr ( wr_tx ),
.wclk (clk),
.q ( dat_o),
.rd (rd),
.full (fe),
.empty (empty),
.mem_empt (mem_empt),
.rclk (sd_clk),
.rst (rst | reset_tx_fifo)
);
 
reg [3:0] t_c_buffer_0;
reg [3:0] t_c_buffer_1;
assign m_wb_adr_o = adr+offset;
 
reg write_ptr;
reg read_ptr;
reg first;
reg [31:0] tmp_dat_buffer_0;
reg [31:0] tmp_dat_buffer_1;
 
 
always @(posedge clk or posedge rst )begin
if (rst) begin
offset <=0;
we <= 8'h1;
m_wb_we_o <=0;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
wr_tx<=0;
tmp_dat_buffer_0<=0;
tmp_dat_buffer_1<=0;
t_c_buffer_0<=0;
t_c_buffer_1<=0;
reset_tx_fifo<=1;
write_ptr<=0;
read_ptr<=0;
first<=1;
din<=0;
end
else if (en) begin //Start filling the TX buffer
reset_tx_fifo<=0;
if (m_wb_ack_i) begin
write_ptr<=write_ptr+1;
offset<=offset+`MEM_OFFSET;
if (!write_ptr) begin
tmp_dat_buffer_0 <= m_wb_dat_i;
t_c_buffer_0<=9;
end
else begin
tmp_dat_buffer_1 <= m_wb_dat_i;
t_c_buffer_1<=9;
end
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
end
if ((t_c_buffer_0>0 ) && (read_ptr==0)) begin
if (!fe) begin
we <= {we[9-1:0],we[9-1]};
wr_tx <=1;
t_c_buffer_0<=t_c_buffer_0-1;
if (we[0])
din <= tmp_dat_buffer_0 [3:0];
else if (we[1])
din <= tmp_dat_buffer_0 [7:4];
else if (we[2])
din <= tmp_dat_buffer_0 [11:8] ;
else if (we[3])
din <= tmp_dat_buffer_0 [15:12];
else if (we[4])
din <= tmp_dat_buffer_0 [19:16] ;
else if (we[5])
din <= tmp_dat_buffer_0 [23:20] ;
else if (we[6])
din <= tmp_dat_buffer_0 [27:24];
else if (we[7])
din <= tmp_dat_buffer_0 [31:28] ;
else if (we[8]) begin
wr_tx <=0;
read_ptr<=read_ptr+1;
end
end
end
else if ((t_c_buffer_1>0 ) && (read_ptr==1)) begin
if (!fe) begin
we <= {we[9-1:0],we[9-1]};
wr_tx <=1;
t_c_buffer_1<=t_c_buffer_1-1;
if (we[0])
din <= tmp_dat_buffer_1 [3:0];
else if (we[1])
din <= tmp_dat_buffer_1 [7:4];
else if (we[2])
din <= tmp_dat_buffer_1 [11:8] ;
else if (we[3])
din <= tmp_dat_buffer_1 [15:12];
else if (we[4])
din <= tmp_dat_buffer_1 [19:16] ;
else if (we[5])
din <= tmp_dat_buffer_1 [23:20] ;
else if (we[6])
din <= tmp_dat_buffer_1 [27:24];
else if (we[7])
din <= tmp_dat_buffer_1 [31:28] ;
else if (we[8]) begin
wr_tx <=0;
read_ptr<=read_ptr+1;
end
end
end
else begin
wr_tx <=0;
we <=1;
end
if ((!m_wb_ack_i) & ( first || (write_ptr != read_ptr) ) ) begin //If not full And no Ack
m_wb_we_o <=0;
m_wb_cyc_o <= 1;
m_wb_stb_o <= 1;
first<=0;
end
 
end
else begin
offset <=0;
reset_tx_fifo<=1;
m_wb_cyc_o <= 0;
m_wb_stb_o <= 0;
m_wb_we_o <=0;
first<=1;
t_c_buffer_0<=0;
t_c_buffer_1<=0;
write_ptr<=0;
read_ptr<=0;
first<=1;
din<=0;
end
end
endmodule
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_defines.v
0,0 → 1,77
//Read the documentation before changing values
 
`define BIG_ENDIAN
//`define LITLE_ENDIAN
 
//`define SIM
`define SYN
 
`define ACTEL
 
//`define CUSTOM
//`define ALTERA
//`define XLINX
//`define SIMULATOR
 
//MAX 255 BD
//BD size/4
 
`ifdef ACTEL
`define NR_O_BD_4
`define BD_WIDTH 4
`define BD_SIZE 16
`define RAM_MEM_WIDTH_16
`define RAM_MEM_WIDTH 16
`endif
 
`define RESEND_MAX_CNT 3
 
`ifdef SYN
`define RESET_CLK_DIV 2
`define MEM_OFFSET 4
`endif
 
`ifdef SIM
`define RESET_CLK_DIV 0
`define MEM_OFFSET 1
`endif
 
//SD-Clock Defines ---------
//Use bus clock or a seperate clock
`define SD_CLK_BUS_CLK
//`define SD_CLK_SEP
 
// Use of internal clock divider
//`define SD_CLK_STATIC
`define SD_CLK_DYNAMIC
 
 
//SD DATA-transfer defines---
`define BLOCK_SIZE 512
`define SD_BUS_WIDTH_4
`define SD_BUS_W 4
 
//at 512 bytes per block, equal 1024 4 bytes writings with a bus width of 4, add 2 for startbit and Z bit.
//Add 18 for crc, endbit and z.
`define BIT_BLOCK 1044
`define CRC_OFF 19
`define BIT_BLOCK_REC 1024
 
`define BIT_CRC_CYCLE 16
 
 
//FIFO defines---------------
`define FIFO_RX_MEM_DEPTH 4
`define FIFO_RX_MEM_ADR_SIZE 3
 
`define FIFO_TX_MEM_DEPTH 64
`define FIFO_TX_MEM_ADR_SIZE 7
//---------------------------
 
 
 
 
 
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_crc_16.v
0,0 → 1,46
// ==========================================================================
// CRC Generation Unit - Linear Feedback Shift Register implementation
// (c) Kay Gorontzi, GHSi.de, distributed under the terms of LGPL
// https://www.ghsi.de/CRC/index.php?
// =========================================================================
module CRC_16(BITVAL, Enable, CLK, RST, CRC);
input BITVAL;// Next input bit
input Enable;
input CLK; // Current bit valid (Clock)
input RST; // Init CRC value
output reg [15:0] CRC; // Current output CRC value
 
// We need output registers
wire inv;
assign inv = BITVAL ^ CRC[15]; // XOR required?
always @(posedge CLK or posedge RST) begin
if (RST) begin
CRC = 0;
end
else begin
if (Enable==1) begin
CRC[15] = CRC[14];
CRC[14] = CRC[13];
CRC[13] = CRC[12];
CRC[12] = CRC[11] ^ inv;
CRC[11] = CRC[10];
CRC[10] = CRC[9];
CRC[9] = CRC[8];
CRC[8] = CRC[7];
CRC[7] = CRC[6];
CRC[6] = CRC[5];
CRC[5] = CRC[4] ^ inv;
CRC[4] = CRC[3];
CRC[3] = CRC[2];
CRC[2] = CRC[1];
CRC[1] = CRC[0];
CRC[0] = inv;
end
end
end
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_crc_7.v
0,0 → 1,34
module CRC_7(BITVAL, Enable, CLK, RST, CRC);
input BITVAL;// Next input bit
input Enable;
input CLK; // Current bit valid (Clock)
input RST; // Init CRC value
output [6:0] CRC; // Current output CRC value
 
reg [6:0] CRC;
// We need output registers
wire inv;
assign inv = BITVAL ^ CRC[6]; // XOR required?
always @(posedge CLK or posedge RST) begin
if (RST) begin
CRC = 0;
end
else begin
if (Enable==1) begin
CRC[6] = CRC[5];
CRC[5] = CRC[4];
CRC[4] = CRC[3];
CRC[3] = CRC[2] ^ inv;
CRC[2] = CRC[1];
CRC[1] = CRC[0];
CRC[0] = inv;
end
end
end
endmodule
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_cmd_master.v
0,0 → 1,284
`include "SD_defines.v"
 
module SD_CMD_MASTER(
input CLK_PAD_IO,
input SD_CLK_I,
input RST_PAD_I,
input New_CMD,
input data_write,
input data_read,
 
input cmd_dat_i,
output cmd_out_o,
output cmd_oe_o,
 
input [31:0]ARG_REG,
input [15:0]CMD_SET_REG,
input [15:0] TIMEOUT_REG,
output reg [15:0] STATUS_REG,
output reg [31:0] RESP_1_REG,
 
output reg [15:0] ERR_INT_REG,
output reg [15:0] NORMAL_INT_REG,
input [7:0] CLK_DIVIDER,
output [1:0] st_dat_t
);
//
 
`define dat_ava status[6]
`define crc_valid status[5]
`define small_rsp 7'b0101000
`define big_rsp 7'b1111111
 
`define CMDI CMD_SET_REG[13:8]
`define WORD_SELECT CMD_SET_REG[7:6]
`define CICE CMD_SET_REG[4]
`define CRCE CMD_SET_REG[3]
`define RTS CMD_SET_REG[1:0]
`define CTE ERR_INT_REG[0]
`define CCRCE ERR_INT_REG[1]
`define CIE ERR_INT_REG[3]
`define EI NORMAL_INT_REG[15]
`define CC NORMAL_INT_REG[0]
`define CICMD STATUS_REG[0]
 
//-----------Types--------------------------------------------------------
 
reg CRC_check_enable;
reg index_check_enable;
reg [6:0]response_size;
reg go_idle_o;
reg [15:0] settings;
reg [39:0] cmd_out;
reg req_out;
reg ack_out;
wire req_in;
wire ack_in;
wire [39:0] cmd_in;
wire [15:0]serial_status;
reg [15:0]status;
reg [15:0] Watchdog_Cnt;
reg complete;
 
 
parameter SIZE = 3;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
 
parameter IDLE = 3'b001;
parameter SETUP = 3'b010;
parameter EXECUTE = 3'b100;
 
//---------------Input ports---------------
CMD_SERIAL_HOST CMD_SERIAL_HOST_1(
.SD_CLK_IN (SD_CLK_I),
.RST_IN (RST_PAD_I),
.SETTING_IN (settings),
.GO_IDLE (go_idle_o),
.CMD_IN (cmd_out),
.REQ_IN (req_out),
.ACK_IN (ack_out),
.REQ_OUT (req_in),
.ACK_OUT (ack_in),
.CMD_OUT (cmd_in),
.STATUS (serial_status),
.cmd_dat_i (cmd_dat_i),
.cmd_out_o (cmd_out_o),
.cmd_oe_o ( cmd_oe_o),
.st_dat_t (st_dat_t)
);
 
reg ack_in_int;
 
 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I )
begin
if (RST_PAD_I) begin
ack_in_int<=0;
end
else begin
ack_in_int<=ack_in;
end
end
 
 
 
always @ ( state or New_CMD or complete or ack_in_int )
begin : FSM_COMBO
next_state = 0;
 
case(state)
IDLE: begin
if (New_CMD) begin
next_state = SETUP;
end
else begin
next_state = IDLE;
end
end
SETUP:begin
if (ack_in_int)
next_state = EXECUTE;
else
next_state = SETUP;
end
EXECUTE: begin
if (complete) begin
next_state = IDLE;
end
else begin
next_state = EXECUTE;
end
end
default : next_state = IDLE;
endcase
end
 
 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I )
begin : FSM_SEQ
if (RST_PAD_I ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
 
 
 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I )
begin
if (RST_PAD_I ) begin
CRC_check_enable=0;
complete =0;
RESP_1_REG = 0;
ERR_INT_REG =0;
NORMAL_INT_REG=0;
STATUS_REG=0;
status=0;
cmd_out =0 ;
settings=0;
response_size=0;
req_out=0;
index_check_enable=0;
ack_out=0;
Watchdog_Cnt=0;
`CCRCE=0;
`EI = 0;
`CC = 0;
go_idle_o=0;
end
else begin
complete=0;
case(state)
IDLE: begin
go_idle_o=0;
req_out=0;
ack_out =0;
`CICMD =0;
if ( req_in == 1) begin //Status change
status=serial_status;
ack_out = 1;
STATUS_REG[15:12] =serial_status[3:0];
end
end
SETUP: begin
NORMAL_INT_REG=0;
ERR_INT_REG =0;
STATUS_REG =0;
index_check_enable = `CICE;
CRC_check_enable = `CRCE;
if ( (`RTS == 2'b10 ) || ( `RTS == 2'b11)) begin
response_size = 7'b0101000;
end
else if (`RTS == 2'b01) begin
response_size = 7'b1111111;
end
else begin
response_size=0;
end
cmd_out[39:38]=2'b01;
cmd_out[37:32]=`CMDI; //CMD_INDEX
cmd_out[31:0]= ARG_REG; //CMD_Argument
settings[14:13]=`WORD_SELECT; //Reserved
settings[12] = data_read; //Type of command
settings[11] = data_write;
settings[10:8]=3'b111; //Delay
settings[7]=`CRCE; //CRC-check
settings[6:0]=response_size; //response size
Watchdog_Cnt = 0;
`CICMD =1;
end
EXECUTE: begin
Watchdog_Cnt = Watchdog_Cnt +1;
if (Watchdog_Cnt>TIMEOUT_REG) begin
`CTE=1;
`EI = 1;
if (ack_in == 1) begin
complete=1;
end
go_idle_o=1;
end
//Default
req_out=0;
ack_out =0;
//Start sending when serial module is ready
if (ack_in == 1) begin
req_out =1;
end
//Incoming New Status
else if ( req_in == 1) begin
status=serial_status;
STATUS_REG[15:12] =serial_status[3:0];
ack_out = 1;
if ( `dat_ava ) begin //Data avaible
complete=1;
`EI = 0;
if (CRC_check_enable & ~`crc_valid) begin
`CCRCE=1;
`EI = 1;
end
else if (index_check_enable & (cmd_out[37:32] != cmd_in [37:32]) ) begin
`CIE=1;
`EI = 1;
end
// else begin
`EI = 0;
`CC = 1;
RESP_1_REG=cmd_in[31:0];
// end
end ////Data avaible
end //Status change
end //EXECUTE state
endcase
end
end
 
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_cmd_serial_host.v
0,0 → 1,581
`include "SD_defines.v"
//-------------------------
//-------------------------
module CMD_SERIAL_HOST ( SD_CLK_IN, RST_IN, SETTING_IN,GO_IDLE ,CMD_IN, REQ_IN, ACK_OUT, REQ_OUT,ACK_IN, CMD_OUT, STATUS, cmd_dat_i, cmd_out_o, cmd_oe_o, st_dat_t);
//---------------Input ports---------------
input SD_CLK_IN;
input RST_IN;
input [15:0] SETTING_IN;
input GO_IDLE;
input [39:0] CMD_IN;
input REQ_IN;
input ACK_IN;
input cmd_dat_i;
 
//---------------Output ports---------------
output [39:0] CMD_OUT;
output ACK_OUT;
output REQ_OUT;
output [15:0] STATUS;
output reg cmd_oe_o;
output reg cmd_out_o;
output reg [1:0] st_dat_t;
//---------------Input ports Data Type------
wire SD_CLK_IN;
wire RST_IN;
wire [15:0] SETTING_IN;
wire [39:0] CMD_IN;
wire REQ_IN;
wire ACK_IN;
wire GO_IDLE;
//---------------Output ports Data Type------
reg [39:0] CMD_OUT;
wire ACK_OUT ;
reg [15:0] STATUS;
reg REQ_OUT;
 
//-------------Internal Constant-------------
 
`ifdef SIM
`define INIT_DELAY 2
`else
`define INIT_DELAY 64
`endif
`define NCR 2
parameter SEND_SIZE = 48;
parameter SIZE = 10;
parameter CONTENT_SIZE = 40;
parameter
INIT = 10'b0000_0000_01,
IDLE = 10'b0000_0000_10,
WRITE_WR = 10'b0000_0001_00,
DLY_WR = 10'b0000_0010_00,
READ_WR = 10'b0000_0100_00,
DLY_READ = 10'b0000_1000_00,
ACK_WR = 10'b0001_0000_00,
WRITE_WO = 10'b0010_0000_00,
DLY_WO = 10'b0100_0000_00,
ACK_WO = 10'b1000_0000_00;
parameter Read_Delay = 7;
parameter EIGHT_PAD = 8;
//---------------Internal variable-----------
//-Internal settings/buffers
reg [6:0] Response_Size;
reg [2:0] Delay_Cycler;
reg [CONTENT_SIZE-1:0] In_Buff;
reg [39:0] Out_Buff;
//-Internal State input
reg Write_Read;
reg Write_Only;
 
//-CRC
reg [4:0] word_select_counter;
reg CRC_RST;
reg [6:0]CRC_IN;
wire [6:0] CRC_VAL;
reg CRC_Enable;
reg CRC_OUT;
reg CRC_Check_On;
reg Crc_Buffering;
reg CRC_Valid;
//-Internal Counterns
//6 bit sent counter
reg [7:0]Cmd_Cnt; //8 bit recive counter
reg [2:0]Delay_Cnt; //3 bit Delay counter
//-State Variable
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
//Misc
`define Vector_Index (CONTENT_SIZE-1-Cmd_Cnt)
`define Bit_Nr (SEND_SIZE-Cmd_Cnt)
//TRI-STATE
reg block_write;
reg block_read;
 
 
//
reg [1:0]word_select;
reg FSM_ACK;
reg DECODER_ACK;
 
reg q;
reg Req_internal_in;
reg q1;
reg Ack_internal_in;
//------------------------------------------
CRC_7 CRC_7(
CRC_OUT,
CRC_Enable,
SD_CLK_IN,
CRC_RST,
CRC_VAL);
//------------------------------------------
always @ (state or Delay_Cnt or Write_Read or Cmd_Cnt or Write_Only or Ack_internal_in or cmd_dat_i or Response_Size or Delay_Cycler)
begin : FSM_COMBO
next_state = 0;
case(state)
INIT: begin
if (Cmd_Cnt >= `INIT_DELAY )begin
next_state = IDLE;
end
else begin
next_state = INIT;
end
end
 
IDLE: begin
if (Write_Read ) begin
next_state = WRITE_WR;
end
else if (Write_Only ) begin
next_state = WRITE_WO;
end
else begin
next_state = IDLE;
end
end
WRITE_WR:
if (Cmd_Cnt >=SEND_SIZE-1) begin
next_state = DLY_WR;
end
else begin
next_state = WRITE_WR;
end
WRITE_WO:
if (Cmd_Cnt >= SEND_SIZE-1) begin
next_state = DLY_WO;
end
else begin
next_state = WRITE_WO;
end
DLY_WR :
if ( (Delay_Cnt >= `NCR) && ( !cmd_dat_i)) begin
next_state = READ_WR;
end
else begin
next_state = DLY_WR;
end
DLY_WO :
if (Delay_Cnt >= Delay_Cycler) begin
next_state = ACK_WO;
end
else begin
next_state = DLY_WO;
end
READ_WR :
if (Cmd_Cnt >= (Response_Size+EIGHT_PAD)) begin
next_state = DLY_READ;
end
else begin
next_state = READ_WR;
end
ACK_WO :
next_state = IDLE;
DLY_READ :
if (Ack_internal_in ) begin
next_state = ACK_WR;
end
else begin
next_state = DLY_READ;
end
ACK_WR :
next_state = IDLE;
 
 
default : next_state = INIT;
endcase
end
//----
always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE)
begin
if (RST_IN || GO_IDLE) begin
Req_internal_in <=1'b0;
q <=1'b0;
end
else begin
q<=REQ_IN;
Req_internal_in<=q;
end
 
 
end
 
always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE)
begin
if (RST_IN || GO_IDLE) begin
Ack_internal_in <=1'b0;
q1 <=1'b0;
end
else begin
q1<=ACK_IN;
Ack_internal_in<=q1;
end
 
 
end
 
 
 
 
 
always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
begin:COMMAND_DECODER
if (RST_IN || GO_IDLE ) begin
Delay_Cycler <=3'b0;
Response_Size <=7'b0;
DECODER_ACK <= 1;
Write_Read<=1'b0;
Write_Only<=1'b0;
CRC_Check_On <=0;
In_Buff <=0;
block_write<=0;
block_read <=0;
word_select<=0;
end
else begin
if (Req_internal_in == 1) begin
Response_Size[6:0] <= SETTING_IN [6:0];
CRC_Check_On <= SETTING_IN [7];
Delay_Cycler[2:0] <= SETTING_IN [10:8];
block_write <= SETTING_IN [11];
block_read <= SETTING_IN [12];
word_select <=SETTING_IN [14:13];
In_Buff <= CMD_IN;
DECODER_ACK<=0;
if (SETTING_IN [6:0]>0) begin
Write_Read<=1'b1;
Write_Only<=1'b0;
end
else begin
Write_Read<=1'b0;
Write_Only<=1'b1;
end
end
else begin
Write_Read<=1'b0;
Write_Only<=1'b0;
DECODER_ACK <= 1;
end
end
end
//End block COMMAND_DECODER
 
//-------Function for Combo logic-----------------
 
 
 
assign ACK_OUT = FSM_ACK & DECODER_ACK;
 
//----------------Seq logic------------
always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
begin : FSM_SEQ
if (RST_IN ) begin
state <= #1 INIT;
end
else if (GO_IDLE) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
 
//-------------OUTPUT_LOGIC-------
always @ (posedge SD_CLK_IN or posedge RST_IN or posedge GO_IDLE )
begin : OUTPUT_LOGIC
if (RST_IN || GO_IDLE ) begin
CRC_Enable=0;
word_select_counter<=0;
Delay_Cnt =0;
cmd_oe_o=1;
cmd_out_o = 1;
Out_Buff =0;
FSM_ACK=1;
REQ_OUT =0;
CRC_RST =1;
CRC_OUT =0;
CRC_IN =0;
CMD_OUT =0;
Crc_Buffering =0;
STATUS = 0;
CRC_Valid=0;
Cmd_Cnt=0;
st_dat_t<=0;
if(GO_IDLE) begin
cmd_oe_o=0;
cmd_out_o = 0;
end
end
else begin
case(state)
INIT : begin
Cmd_Cnt=Cmd_Cnt+1;
cmd_oe_o=1;
cmd_out_o = 1;
end
IDLE : begin
cmd_oe_o=0; //Put CMD to Z
Delay_Cnt =0;
Cmd_Cnt =0;
CRC_RST =1;
CRC_Enable=0;
CMD_OUT=0;
st_dat_t<=0;
word_select_counter<=0;
end
WRITE_WR: begin
FSM_ACK=0;
CRC_RST =0;
CRC_Enable=1;
if (Cmd_Cnt==0) begin
STATUS = 16'b0000_0000_0000_0001;
REQ_OUT=1;
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
//Wait one cycle before sending, for setting up the CRC unit.
if (Crc_Buffering==1) begin
cmd_oe_o =1;
if (`Bit_Nr > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
cmd_out_o = In_Buff[`Vector_Index];
if (`Bit_Nr > 9 ) begin //1 step ahead
CRC_OUT = In_Buff[`Vector_Index-1];
end else begin
CRC_Enable=0;
end
end
else if ( (`Bit_Nr <=8) && (`Bit_Nr >=2) ) begin
CRC_Enable=0;
cmd_out_o = CRC_VAL[(`Bit_Nr)-2];
if (block_read & block_write)
st_dat_t<=2'b11;
else if (block_read)
st_dat_t<=2'b10;
end
else begin
cmd_out_o =1'b1;
end
Cmd_Cnt = Cmd_Cnt+1 ;
end
else begin //Pre load CRC
Crc_Buffering=1;
CRC_OUT = In_Buff[`Vector_Index];
end
end
 
WRITE_WO: begin
FSM_ACK=0;
CRC_RST =0;
CRC_Enable=1;
if (Cmd_Cnt==0) begin
STATUS[3:0] = 16'b0000_0000_0000_0010;
REQ_OUT=1;
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
//Wait one cycle before sending, for setting up the CRC unit.
if (Crc_Buffering==1) begin
cmd_oe_o =1;
if (`Bit_Nr > 8 ) begin // 1->40 CMD, (41 >= CNT && CNT <=47) CRC, 48 stop_bit
cmd_out_o = In_Buff[`Vector_Index];
if (`Bit_Nr > 9 ) begin //1 step ahead
CRC_OUT = In_Buff[`Vector_Index-1];
end
else begin
CRC_Enable=0;
end
end
else if( (`Bit_Nr <=8) && (`Bit_Nr >=2) ) begin
CRC_Enable=0;
cmd_out_o = CRC_VAL[(`Bit_Nr)-2];
if (block_read)
st_dat_t<=2'b10;
end
else begin
cmd_out_o =1'b1;
end
Cmd_Cnt = Cmd_Cnt+1;
end
else begin //Pre load CRC
Crc_Buffering=1;
CRC_OUT = In_Buff[`Vector_Index];
end
end
DLY_WR : begin
if (Delay_Cnt==0) begin
STATUS[3:0] = 4'b0011;
REQ_OUT=1;
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
CRC_Enable=0;
CRC_RST =1;
Cmd_Cnt = 1;
cmd_oe_o=0;
if (Delay_Cnt<3'b111)
Delay_Cnt =Delay_Cnt+1;
Crc_Buffering=0;
end
DLY_WO : begin
if (Delay_Cnt==0) begin
STATUS[3:0] = 4'b0100;
STATUS[5] = 0;
STATUS[6] = 1;
REQ_OUT=1;
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
CRC_Enable=0;
CRC_RST =1;
Cmd_Cnt = 0;
cmd_oe_o=0;
Delay_Cnt =Delay_Cnt+1;
Crc_Buffering=0;
end
READ_WR : begin
Delay_Cnt =0;
CRC_RST =0;
CRC_Enable=1;
cmd_oe_o =0;
if (Cmd_Cnt==1) begin
STATUS[3:0] = 16'b0000_0000_0000_0101;
REQ_OUT=1;
Out_Buff[39]=0; //startbit (0)
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
if (Cmd_Cnt < (Response_Size))begin
if (Cmd_Cnt<8 ) //1+1+6 (S,T,Index)
Out_Buff[39-Cmd_Cnt] = cmd_dat_i;
else begin
if (word_select == 2'b00) begin
if(Cmd_Cnt<40) begin
word_select_counter<= word_select_counter+1;
Out_Buff[31-word_select_counter] = cmd_dat_i;
end
end
else if (word_select == 2'b01) begin
if ( (Cmd_Cnt>=40) && (Cmd_Cnt<72) )begin
word_select_counter<= word_select_counter+1;
Out_Buff[31-word_select_counter] = cmd_dat_i;
end
end
else if (word_select == 2'b10) begin
if ( (Cmd_Cnt>72) && (Cmd_Cnt<104) )begin
word_select_counter<= word_select_counter+1;
Out_Buff[31-word_select_counter] = cmd_dat_i;
end
end
else if (word_select == 2'b11) begin
if ( (Cmd_Cnt>104) && (Cmd_Cnt<126) )begin
word_select_counter<= word_select_counter+1;
Out_Buff[31-word_select_counter] = cmd_dat_i;
end
end
end
CRC_OUT = cmd_dat_i;
end
else if ( Cmd_Cnt - Response_Size <=6 ) begin
CRC_IN [(Response_Size+6)-(Cmd_Cnt)] = cmd_dat_i;
CRC_Enable=0;
end
else begin
if ((CRC_IN != CRC_VAL) && ( CRC_Check_On == 1)) begin
CRC_Valid=0;
CRC_Enable=0;
end
else begin
CRC_Valid=1;
CRC_Enable=0;
end
if (block_read & block_write)
st_dat_t<=2'b11;
else if (block_write)
st_dat_t<=2'b01;
end
Cmd_Cnt = Cmd_Cnt+1;
end
DLY_READ: begin
if (Delay_Cnt==0) begin
STATUS[3:0] = 4'b0110;
STATUS[5] = CRC_Valid;
STATUS[6] = 1;
REQ_OUT=1;
end
else if (Ack_internal_in) begin
REQ_OUT=0;
end
CRC_Enable=0;
CRC_RST =1;
Cmd_Cnt = 0;
cmd_oe_o=0;
CMD_OUT[39:0]=Out_Buff;
Delay_Cnt =Delay_Cnt+1;
end
ACK_WO: begin
FSM_ACK=1;
end
ACK_WR: begin
FSM_ACK=1;
REQ_OUT =0;
end
endcase
end
end
endmodule
 
 
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_clock_divider.v
0,0 → 1,39
`include "SD_defines.v"
module CLOCK_DIVIDER (
input wire CLK,
input [7:0] DIVIDER,
input wire RST,
output SD_CLK
);
reg [7:0] ClockDiv;
reg SD_CLK_O;
`ifdef SYN
CLKINT CLKINT0
(.A (SD_CLK_O),
.Y (SD_CLK)
);
`endif
//`ifdef SIM
// assign SD_CLK = SD_CLK_O;
//endif
always @ (posedge CLK or posedge RST)
begin
if (RST) begin
ClockDiv <=8'b0000_0000;
SD_CLK_O <= 0;
end
else if (ClockDiv == DIVIDER )begin
ClockDiv <= 0;
SD_CLK_O <= ~SD_CLK_O;
end else begin
ClockDiv <= ClockDiv + 1;
SD_CLK_O <= SD_CLK_O;
end
end
endmodule
/sdcard_mass_storage_controller/trunk/rtl/sdc_dma/verilog/SD_data_master.v
0,0 → 1,453
`include "SD_defines.v"
 
module SD_DATA_MASTER (
input clk,
input rst,
//Tx Bd
input new_tx_bd,
input [`RAM_MEM_WIDTH-1:0] dat_in_tx,
input [`BD_WIDTH-1:0] free_tx_bd,
input ack_i_s_tx,
output reg re_s_tx,
output reg a_cmp_tx,
//Rx Bd
input new_rx_bd,
input [`RAM_MEM_WIDTH-1:0] dat_in_rx,
input [`BD_WIDTH-1:0] free_rx_bd,
input ack_i_s_rx,
output reg re_s_rx,
output reg a_cmp_rx,
//Input from SD-Host Reg
input cmd_busy, //STATUS_REG[0] and mux
//Output to SD-Host Reg
output reg we_req,
input we_ack,
output reg d_write,
output reg d_read,
output reg [31:0] cmd_arg,
output reg [15:0] cmd_set,
input cmd_tsf_err,
input [4:0] card_status,
//To fifo filler
output reg start_tx_fifo,
output reg start_rx_fifo,
output reg [31:0] sys_adr,
input tx_empt,
input rx_full,
//SD-DATA_Host
input busy_n ,
input transm_complete ,
input crc_ok,
output reg ack_transfer,
//status output
output reg [7:0] bd_int_st ,
input bd_int_st_rst,
output reg CIDAT
);
`define BD_EMPTY (`BD_SIZE /4)
`ifdef RAM_MEM_WIDTH_32
`define READ_CYCLE 2
reg bd_cnt ;
`else `ifdef RAM_MEM_WIDTH_16
`define READ_CYCLE 4
reg [1:0] bd_cnt;
`endif
`endif
 
reg send_done;
reg rec_done;
reg rec_failed;
reg tx_cycle;
reg rx_cycle;
reg [2:0] resend_try_cnt;
`ifdef SIM
parameter CMD24 = 16'h181A ; //11000 0001 1010
parameter CMD17 = 16'h111A; //10001 0001 1010
parameter CMD12 = 16'hC1A ; //01100 0001 1010
`else
parameter CMD24 = 16'h181A;
parameter CMD17 = 16'h111A;
parameter CMD12 = 16'hC1A ;
`endif
parameter SIZE = 9;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
parameter IDLE = 9'b000000001;
parameter GET_TX_BD = 9'b000000010;
parameter GET_RX_BD = 9'b000000100;
parameter SEND_CMD = 9'b000001000;
parameter RECIVE_CMD = 9'b000010000;
parameter DATA_TRANSFER = 9'b000100000;
parameter STOP = 9'b001000000;
parameter STOP_SEND = 9'b010000000;
parameter STOP_RECIVE_CMD = 9'b100000000;
 
reg trans_done;
reg trans_failed;
 
 
always @ (state or free_tx_bd or free_rx_bd or bd_cnt or send_done or rec_done or rec_failed or trans_done or trans_failed)
begin : FSM_COMBO
next_state = 0;
case(state)
IDLE: begin
if (free_tx_bd !=`BD_EMPTY)begin
next_state = GET_TX_BD;
end
else if (free_rx_bd !=`BD_EMPTY) begin
next_state = GET_RX_BD;
end
else begin
next_state = IDLE;
end
end
GET_TX_BD: begin
if (bd_cnt>= (`READ_CYCLE-1))begin
next_state = SEND_CMD;
end
else begin
next_state = GET_TX_BD;
end
end
GET_RX_BD: begin
if (bd_cnt >= (`READ_CYCLE-1))begin
next_state = SEND_CMD;
end
else begin
next_state = GET_RX_BD;
end
end
SEND_CMD: begin
if (send_done)begin
next_state = RECIVE_CMD;
end
else begin
next_state = SEND_CMD;
end
end
RECIVE_CMD: begin
if (rec_done)
next_state = DATA_TRANSFER;
else if (rec_failed)
next_state = SEND_CMD;
else
next_state = RECIVE_CMD;
end
 
DATA_TRANSFER: begin
if (trans_done)
next_state = IDLE;
else if (trans_failed)
next_state = STOP;
else
next_state = DATA_TRANSFER;
end
STOP: begin
next_state = STOP_SEND;
end
STOP_SEND: begin
if (send_done)begin
next_state = STOP_RECIVE_CMD;
end
else begin
next_state = STOP_SEND;
end
end
STOP_RECIVE_CMD : begin
if (rec_done)
next_state = SEND_CMD;
else if (rec_failed)
next_state = STOP;
else if (resend_try_cnt>=`RESEND_MAX_CNT)
next_state = IDLE;
else
next_state = STOP_RECIVE_CMD;
end
default : next_state = IDLE;
endcase
 
end
 
//----------------Seq logic------------
always @ (posedge clk or posedge rst )
begin : FSM_SEQ
if (rst ) begin
state <= #1 IDLE;
end
else begin
state <= #1 next_state;
end
end
 
 
 
//Output logic-----------------
 
 
always @ (posedge clk or posedge rst )
begin
if (rst) begin
send_done<=0;
bd_cnt<=0;
sys_adr<=0;
cmd_arg<=0;
rec_done<=0;
start_tx_fifo<=0;
start_rx_fifo<=0;
send_done<=0;
rec_failed<=0;
d_write <=0;
d_read <=0;
trans_failed<=0;
trans_done<=0;
tx_cycle <=0;
rx_cycle <=0;
ack_transfer<=0;
a_cmp_tx<=0;
a_cmp_rx<=0;
CIDAT<=0;
bd_int_st<=0;
we_req<=0;
re_s_tx<=0;
re_s_rx<=0;
cmd_set<=0;
resend_try_cnt=0;
end
else begin
case(state)
IDLE: begin
send_done<=0;
bd_cnt<=0;
sys_adr<=0;
cmd_arg<=0;
rec_done<=0;
rec_failed<=0;
start_tx_fifo<=0;
start_rx_fifo<=0;
send_done<=0;
d_write <=0;
d_read <=0;
trans_failed<=0;
trans_done<=0;
tx_cycle <=0;
rx_cycle <=0;
ack_transfer<=0;
a_cmp_tx<=0;
a_cmp_rx<=0;
resend_try_cnt=0;
end
GET_RX_BD: begin
//0,1,2,3...
re_s_rx <= 1;
`ifdef RAM_MEM_WIDTH_16
if (ack_i_s_rx) begin
if( bd_cnt == 2'b00) begin
sys_adr [15:0] <= dat_in_rx; end
else if ( bd_cnt == 2'b01) begin
sys_adr [31:16] <= dat_in_rx; end
else if ( bd_cnt == 2) begin
cmd_arg [15:0] <= dat_in_rx;
re_s_rx <= 0; end
else if ( bd_cnt == 3) begin
cmd_arg [31:16] <= dat_in_rx;
re_s_rx <= 0;
end
bd_cnt <= bd_cnt+1;
end
`endif
//Add Later Save last block addres for comparison with current (For multiple block cmd)
//Add support for Pre-erased
cmd_set <= CMD17;
rx_cycle<=1;
end
GET_TX_BD: begin
//0,1,2,3...
re_s_tx <= 1;
`ifdef RAM_MEM_WIDTH_16
if (ack_i_s_tx) begin
if( bd_cnt == 2'b00) begin
sys_adr [15:0] <= dat_in_tx; end
else if ( bd_cnt == 2'b01) begin
sys_adr [31:16] <= dat_in_tx; end
else if ( bd_cnt == 2) begin
cmd_arg [15:0] <= dat_in_tx;
re_s_tx <= 0; end
else if ( bd_cnt == 3) begin
cmd_arg [31:16] <= dat_in_tx;
re_s_tx <= 0;
end
bd_cnt <= bd_cnt+1;
end
`endif
//Add Later Save last block addres for comparison with current (For multiple block cmd)
//Add support for Pre-erased
cmd_set <= CMD24;
tx_cycle <=1;
end
SEND_CMD : begin
rec_done<=0;
if (rx_cycle) begin
re_s_rx <=0;
d_read<=1;
end
else begin
re_s_tx <=0;
d_write<=1;
end
start_rx_fifo<=0; //Reset FIFO
start_tx_fifo<=0; //Reset FIFO
if (!cmd_busy) begin
we_req <= 1;
end //When send complete change state and wait for reply
if (we_ack) begin
send_done<=1;
we_req <= 1;
end
end
RECIVE_CMD : begin
//When waiting for reply fill TX fifo
if (tx_cycle)
start_tx_fifo<=1; //start_fifo prebuffering
else
start_rx_fifo <=1;
we_req <= 0;
send_done<=0;
if (!cmd_busy) begin //Means the sending is completed,
d_read<=0;
d_write<=0;
if (!cmd_tsf_err) begin
if (card_status[0]) begin
`ifdef SYN
if ( (card_status[4:1] == 4'b0100) || (card_status[4:1] == 4'b0110) || (card_status[4:1] == 4'b0101) )
rec_done<=1;
else begin
rec_failed<=1;
bd_int_st[4] <=1;
end
`endif
`ifdef SIM
rec_done<=1;
`endif
//Check card_status[5:1] for state 4 or 6...
//If wrong state change interupt status reg,so software can put card in
// transfer state and restart/cancel Data transfer
end
end
else
rec_failed<=1; //CRC-Error, CIC-Error or timeout
end
end
DATA_TRANSFER: begin
CIDAT<=1;
if (tx_cycle) begin
if (tx_empt) begin
bd_int_st[2] <=1;
trans_failed<=1;
end
end
else begin
if (rx_full) begin
bd_int_st[2] <=1;
trans_failed<=1;
end
end
//Check for fifo underflow,
//2 DO: if deteced stop transfer, reset data host
if (transm_complete) begin //Transfer complete
ack_transfer<=1;
if ((!crc_ok) && (busy_n)) begin //Wrong CRC and Data line free.
bd_int_st[5] <=1;
trans_failed<=1;
end
else if ((crc_ok) && (busy_n)) begin //Data Line free
trans_done <=1;
bd_int_st[0]<=1;
if (tx_cycle)
a_cmp_tx<=1;
else
a_cmp_rx<=1;
end
end
end
STOP: begin
cmd_set <= CMD12;
rec_done<=0;
rec_failed<=0;
send_done<=0;
trans_failed<=0;
trans_done<=0;
d_read<=1;
d_write<=1;
start_rx_fifo <=0;
start_tx_fifo <=0;
end
STOP_SEND: begin
resend_try_cnt=resend_try_cnt+1;
if (resend_try_cnt==`RESEND_MAX_CNT)
bd_int_st[1]<=1;
if (!cmd_busy)
we_req <= 1;
if (we_ack)
send_done<=1;
end
STOP_RECIVE_CMD: begin
we_req <= 0;
if (!cmd_busy) begin //Means the sending is completed,
if (!cmd_tsf_err) begin
rec_done<=1;
send_done<=0;
d_read<=0;
d_write<=0;
if (tx_cycle)
cmd_set<= CMD24;
else
cmd_set <= CMD17;
end
else
rec_failed<=1;
end
end
endcase
if (bd_int_st_rst)
bd_int_st<=0;
end
end
endmodule

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