URL
https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk
Subversion Repositories sdcard_mass_storage_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdcard_mass_storage_controller/trunk
- from Rev 127 to Rev 128
- ↔ Reverse comparison
Rev 127 → Rev 128
/sim/rtl_sim/log/eth_tb_host.log
0,0 → 1,2
================ HOST Module Testbench access log ================ |
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/sim/rtl_sim/log/eth_tb_wb_m_mon.log
0,0 → 1,4
============= WISHBONE Master Bus Monitor error log ============= |
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Only ERRONEOUS conditions are logged ! |
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/sim/rtl_sim/log/sd_tb_memory.log
0,0 → 1,2
=============== MEMORY Module Testbench access log =============== |
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/sim/rtl_sim/log/eth_tb_phy.log
0,0 → 1,2
================ PHY Module Testbench access log ================ |
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/sim/rtl_sim/log/sd_model.log
--- sim/rtl_sim/log/eth_tb_wb_s_mon.log (nonexistent)
+++ sim/rtl_sim/log/eth_tb_wb_s_mon.log (revision 128)
@@ -0,0 +1,4 @@
+============== WISHBONE Slave Bus Monitor error log ==============
+
+ Only ERRONEOUS conditions are logged !
+
/sim/rtl_sim/log/sdc_tb.log
0,0 → 1,77
========================== SD IP Core Testbench results =========================== |
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*************************************************************************************** |
*************************************************************************************** |
Heading: access_to_reg |
*************************************************************************************** |
*************************************************************************************** |
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************************************************************************************* |
At time: 2903 |
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS ) |
*FAILED* because |
Register %h defaultvalue is not RSP ; 72 |
************************************************************************************* |
|
************************************************************************************* |
At time: 3215 |
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS ) |
*FAILED* because |
Register %h defaultvalue is not RSP ; 28 |
************************************************************************************* |
|
************************************************************************************* |
At time: 3423 |
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS ) |
*FAILED* because |
Register %h defaultvalue is not RSP ; 36 |
************************************************************************************* |
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*************************************************************************************** |
*************************************************************************************** |
Heading: Send CMD |
*************************************************************************************** |
*************************************************************************************** |
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************************************************************************************* |
At time: 8077 |
Test: 0: Send CMD, No Response |
reported *SUCCESSFULL*! |
************************************************************************************* |
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*************************************************************************************** |
*************************************************************************************** |
Heading: access_to_reg |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 61507 |
Test: 3.0: Init Seq, No Response |
reported *SUCCESSFULL*! |
************************************************************************************* |
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*************************************************************************************** |
*************************************************************************************** |
Heading: access_to_reg |
*************************************************************************************** |
*************************************************************************************** |
|
************************************************************************************* |
At time: 208147 |
Test: 4.0: Send data |
reported *SUCCESSFULL*! |
************************************************************************************* |
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************************************************************************************* |
At time: 415419 |
Test: 4.0: Send data |
reported *SUCCESSFULL*! |
************************************************************************************* |
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*************************************************************************************** |
*************************************************************************************** |
Heading: Send CMD, with simulated bus error on SD_CMD line |
*************************************************************************************** |
*************************************************************************************** |
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