URL
https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk
Subversion Repositories sdcard_mass_storage_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdcard_mass_storage_controller/trunk
- from Rev 129 to Rev 130
- ↔ Reverse comparison
Rev 129 → Rev 130
/bench/sdc_dma/verilog/SD_controller_top_tb.v
88,7 → 88,7
`define CICE 16'h10 |
`define CRCE 16'h08 |
|
module SD_CONTROLLER_TOP_TB( |
module SD_controller_top_tb( |
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); |
|
388,7 → 388,7
|
initial |
begin |
tb_log_file = $fopen("../../log/sdc_tb.log"); |
tb_log_file = $fopen("../log/sdc_tb.log"); |
if (tb_log_file < 2) |
begin |
$display("*E Could not open/create testbench log file in ../log/ directory!"); |
397,7 → 397,7
$fdisplay(tb_log_file, "========================== SD IP Core Testbench results ==========================="); |
$fdisplay(tb_log_file, " "); |
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phy_log_file_desc = $fopen("../../log/eth_tb_phy.log"); |
phy_log_file_desc = $fopen("../log/eth_tb_phy.log"); |
if (phy_log_file_desc < 2) |
begin |
$fdisplay(tb_log_file, "*E Could not open/create sd_tb_phy.log file in ../log/ directory!"); |
406,7 → 406,7
$fdisplay(phy_log_file_desc, "================ PHY Module Testbench access log ================"); |
$fdisplay(phy_log_file_desc, " "); |
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memory_log_file_desc = $fopen("../../log/sd_tb_memory.log"); |
memory_log_file_desc = $fopen("../log/sd_tb_memory.log"); |
if (memory_log_file_desc < 2) |
begin |
$fdisplay(tb_log_file, "*E Could not open/create sd_tb_memory.log file in ../log/ directory!"); |
415,7 → 415,7
$fdisplay(memory_log_file_desc, "=============== MEMORY Module Testbench access log ==============="); |
$fdisplay(memory_log_file_desc, " "); |
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host_log_file_desc = $fopen("../../log/eth_tb_host.log"); |
host_log_file_desc = $fopen("../log/eth_tb_host.log"); |
if (host_log_file_desc < 2) |
begin |
$fdisplay(tb_log_file, "*E Could not open/create eth_tb_host.log file in ../log/ directory!"); |
424,7 → 424,7
$fdisplay(host_log_file_desc, "================ HOST Module Testbench access log ================"); |
$fdisplay(host_log_file_desc, " "); |
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wb_s_mon_log_file_desc = $fopen("../../log/eth_tb_wb_s_mon.log"); |
wb_s_mon_log_file_desc = $fopen("../log/eth_tb_wb_s_mon.log"); |
if (wb_s_mon_log_file_desc < 2) |
begin |
$fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_s_mon.log file in ../log/ directory!"); |
435,7 → 435,7
$fdisplay(wb_s_mon_log_file_desc, " Only ERRONEOUS conditions are logged !"); |
$fdisplay(wb_s_mon_log_file_desc, " "); |
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wb_m_mon_log_file_desc = $fopen("../../log/eth_tb_wb_m_mon.log"); |
wb_m_mon_log_file_desc = $fopen("../log/eth_tb_wb_m_mon.log"); |
if (wb_m_mon_log_file_desc < 2) |
begin |
$fdisplay(tb_log_file, "*E Could not open/create eth_tb_wb_m_mon.log file in ../log/ directory!"); |
/sim/rtl_sim/log/sd_model.log
0,0 → 1,2
**Error in sequnce, CMD 2 should precede 3 in Startup state |
**Error in sequnce, CMD 2 should precede 3 in Startup state |
/sim/rtl_sim/run/comp.do
126,7 → 126,7
} |
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# Run the simulation |
# run -all |
run -all |
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# If waves are required |
if [llength $wave_patterns] { |