URL
https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk
Subversion Repositories sdcard_mass_storage_controller
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdcard_mass_storage_controller/trunk
- from Rev 130 to Rev 131
- ↔ Reverse comparison
Rev 130 → Rev 131
/bench/sdc_dma/verilog/SD_controller_top_tb.v
2308,7 → 2308,6
data = 0; |
rand_sel = 0; |
sel = 4'hF; |
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//Reset Core |
addr = `SD_BASE + `software ; |
data = 1; |
2325,7 → 2324,7
addr = `SD_BASE + `software ; |
data = 0; |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); |
sdModelTB0.add_wrong_cmd_crc<=1; |
sdModelTB0.add_wrong_cmd_crc<=1; |
//Setup settings |
addr = `SD_BASE + `command ; |
data = 0; //CMD index 0, Erro check =0, rsp = 0; |
2334,13 → 2333,12
addr = `SD_BASE + `argument ; |
data = 0; //CMD index 0, Erro check =0, rsp = 0; |
wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits); |
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//wait for send finnish |
addr = `SD_BASE + `normal_isr ; |
data = 0; //CMD index 0, Erro check =0, rsp = 0; |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
while (tmp_data != 1) |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
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if (tmp_data[15]) begin |
2461,11 → 2459,22
//wait for response or timeout |
addr = `SD_BASE + `normal_isr ; |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
while (tmp_data != 1) begin |
while (tmp_data == 0) begin |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
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end |
if (tmp_data[15]== 1) begin |
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addr = `SD_BASE + `error_isr ; |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
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`TIME; |
$display("Bus error catched, Error status reg: %h", tmp_data); |
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end |
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end |
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addr = `SD_BASE + `normal_isr ; |
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits); |
if (tmp_data[15]) begin |
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`TIME; |
2472,9 → 2481,9
$display("Normal status register is 0x1: %h, bus error succesfully captured", tmp_data); |
end |
else begin |
test_fail_num("Bus error wasent captured, Normal status register is 0x1: %h",tmp_data); |
test_fail_num("Bus error wasent captured, Normal status register is: %h",tmp_data); |
`TIME; |
$display("Bus error wasent captured, Normal status register is 0x1: %h",tmp_data); |
$display("Bus error wasent captured, Normal status register is : %h",tmp_data); |
fail = fail + 1; |
end |
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/sim/rtl_sim/log/sd_model.log
1,2 → 1,3
**Error in sequnce, CMD 2 should precede 3 in Startup state |
**Error in sequnce, CMD 2 should precede 3 in Startup state |
**Error in sequnce, ACMD 41 should precede 2 in Startup state |
/sim/rtl_sim/log/sdc_tb.log
75,3 → 75,9
*************************************************************************************** |
*************************************************************************************** |
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************************************************************************************* |
At time: 443473 |
Test: Test 5 part 4: Send CMD2, 136-Bit |
reported *SUCCESSFULL*! |
************************************************************************************* |
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