OpenCores
URL https://opencores.org/ocsvn/sdcard_mass_storage_controller/sdcard_mass_storage_controller/trunk

Subversion Repositories sdcard_mass_storage_controller

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdcard_mass_storage_controller/trunk
    from Rev 135 to Rev 136
    ↔ Reverse comparison
  •

Rev 135 → Rev 136

/bench/sdc_dma/verilog/sd_controller_top_tb.v
137,12 → 137,13
wire sd_dat_oe;
wire cmdIn;
wire [3:0] datIn;
 
wire card_detect;
trireg sd_cmd;
tri [3:0] sd_dat;
 
assign sd_cmd = sd_cmd_oe ? cmdIn: 1'bz;
assign sd_dat = sd_dat_oe ? datIn : 4'bz;
assign card_detect = 1'b1;
reg succes;
sdModel sdModelTB0
(
183,7 → 184,8
.sd_dat_dat_i ( sd_dat ), //sd_dat_pad_io),
.sd_dat_out_o (datIn ) ,
.sd_dat_oe_o ( sd_dat_oe ),
.sd_clk_o_pad (sd_clk_pad_o)
.sd_clk_o_pad (sd_clk_pad_o),
.card_detect (card_detect)
`ifdef SD_CLK_SEP
,sd_clk_i_pad
`endif
367,12 → 369,12
$display("===========================================================================");
// test_send_rec_data_error_rsp
//test_send_rec_data_error_rsp(0, 1);
test_send_rec_data_error_rsp(0, 1);
// $display("");
// $display("===========================================================================");
// $display("T6 test_send_cmd_error_rsp Complete");
$display("T6 test_send_cmd_error_rsp Complete");
// $display("===========================================================================");
$display("All Tests past");
$display("All Test finnished. Nr Failed: %d, Nr Succes: %d", tests_failed,tests_successfull);
succes = 1'b1;
end
 
575,7 → 577,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0] != 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
711,7 → 713,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0] != 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
fail = fail + 1;
733,7 → 735,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 8, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0] != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
754,7 → 756,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0] != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
777,7 → 779,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0] != 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
805,7 → 807,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
834,7 → 836,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
864,7 → 866,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
890,7 → 892,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
913,7 → 915,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1114,7 → 1116,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0]!= 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
fail = fail + 1;
1136,7 → 1138,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 8, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
1157,7 → 1159,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1180,7 → 1182,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1208,7 → 1210,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1237,7 → 1239,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1267,7 → 1269,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1293,7 → 1295,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1316,7 → 1318,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1526,7 → 1528,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0]!= 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
fail = fail + 1;
1548,7 → 1550,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 8, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
$display("V 1.0 Card, Timeout In TEST 4.0 %h", tmp_data);
1569,7 → 1571,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1592,7 → 1594,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1620,7 → 1622,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1649,7 → 1651,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1679,7 → 1681,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1705,7 → 1707,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1728,7 → 1730,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1887,7 → 1889,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0]!= 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
fail = fail + 1;
1909,7 → 1911,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 8, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
$display("V 1.0 Card, Timeout In TEST 3.0 %h", tmp_data);
1930,7 → 1932,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1953,7 → 1955,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
1981,7 → 1983,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2010,7 → 2012,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2183,7 → 2185,7
15: begin
i_addr = `normal_isr;
rsp = 16'h000;
rsp = 16'h0004;
end
 
2269,7 → 2271,7
reg [31:0] rsp;
begin
// test_send_cmd
test_heading("Send CMD, with simulated bus error on SD_CMD line");
test_heading("Send CMD, With simulated bus error on SD_CMD line");
$display(" ");
$display("test_send_cmd_error_rsp");
fail = 0;
2337,7 → 2339,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0]!= 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
2361,7 → 2363,7
if (test_num == 1) //
begin
test_name = " TEST 5, part 1: Send CMD, 48-Bit Response, No error check ";
`TIME; $display(" TEST 5, part 1: Send CMD, 48-Bit Response, No error check ");
`TIME; $display(" TEST 5, part 1: Send CMD, 48-Bit Response, No error check ");
wbm_init_waits = 0;
wbm_subseq_waits = {$random} % 5;
data = 0;
2396,7 → 2398,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2459,7 → 2461,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data == 0) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
2467,25 → 2469,13
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
`TIME;
$display("Bus error catched, Error status reg: %h", tmp_data);
$display("Bus error succesfully catched, Error status register: %h", tmp_data);
tmp_data[0]=1;
end
end
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]) begin
`TIME;
$display("Normal status register is 0x1: %h, bus error succesfully captured", tmp_data);
end
else begin
test_fail_num("Bus error wasent captured, Normal status register is: %h",tmp_data);
`TIME;
$display("Bus error wasent captured, Normal status register is : %h",tmp_data);
fail = fail + 1;
end
 
2492,6 → 2482,8
end
 
 
if (test_num == 3) //
begin
test_name = " Test 5 part 4: Send CMD2, 136-Bit ";
2530,7 → 2522,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2666,7 → 2658,7
addr = `SD_BASE + `normal_isr ;
data = 0; //CMD index 0, Erro check =0, rsp = 0;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1)
while (tmp_data[0]!= 1)
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
//When send finnish check if any error
2729,7 → 2721,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2792,7 → 2784,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
2855,7 → 2847,7
//wait for response or timeout
addr = `SD_BASE + `normal_isr ;
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
while (tmp_data != 1) begin
while (tmp_data[0]!= 1) begin
wbm_read(addr, tmp_data, sel, 1, wbm_init_waits, wbm_subseq_waits);
if (tmp_data[15]== 1) begin
fail = fail + 1;
/bench/sdc_dma/verilog/sdModel.v
330,7 → 330,7
CardStatus[8]<=1;
startUppCnt<=startUppCnt+1;
OCR[31]<=Busy;
OCR[31]<=~Busy;
if (startUppCnt == `TIME_BUSY)
Busy <=1;
end
898,7 → 898,7
 
initial
begin
sdModel_file_desc = $fopen("../out/sd_model.log");
sdModel_file_desc = $fopen("../log/sd_model.log");
if (sdModel_file_desc < 2)
begin
$display("*E Could not open/create testbench log file in /log/ directory!");
/rtl/sdc_dma/verilog/sd_defines.v
3,8 → 3,8
`define BIG_ENDIAN
//`define LITLE_ENDIAN
 
//`define SIM
`define SYN
`define SIM
//`define SYN
 
`define SDC_IRQ_ENABLE
 
/rtl/sdc_dma/verilog/sd_cmd_master.v
28,7 → 28,7
input req_in,
input ack_in,
input [39:0] cmd_in,
input [15:0] serial_status,
input [7:0] serial_status,
input card_detect
);
102,7 → 102,7
 
//---------------Input ports---------------
 
/*
 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I )
begin
if (RST_PAD_I) begin
123,9 → 123,9
card_present<=1'b0;
end
end
*/
 
 
 
always @ (posedge CLK_PAD_IO or posedge RST_PAD_I )
begin
if (RST_PAD_I) begin
/sim/rtl_sim/log/eth_tb_host.log
1,2 → 1,2
================ HOST Module Testbench access log ================
================ HOST Module Testbench access log ================
/sim/rtl_sim/log/eth_tb_wb_m_mon.log
1,4 → 1,4
============= WISHBONE Master Bus Monitor error log =============
Only ERRONEOUS conditions are logged !
============= WISHBONE Master Bus Monitor error log =============
Only ERRONEOUS conditions are logged !
/sim/rtl_sim/log/sd_tb_memory.log
1,2 → 1,2
=============== MEMORY Module Testbench access log ===============
=============== MEMORY Module Testbench access log ===============
/sim/rtl_sim/log/eth_tb_phy.log
1,2 → 1,2
================ PHY Module Testbench access log ================
================ PHY Module Testbench access log ================
/sim/rtl_sim/log/sd_model.log
1,3 → 1,3
**Error in sequnce, CMD 2 should precede 3 in Startup state
**Error in sequnce, CMD 2 should precede 3 in Startup state
**Error in sequnce, ACMD 41 should precede 2 in Startup state
**Error in sequnce, CMD 2 should precede 3 in Startup state
**Error in sequnce, CMD 2 should precede 3 in Startup state
**Error in sequnce, ACMD 41 should precede 2 in Startup state
/sim/rtl_sim/log/eth_tb_wb_s_mon.log
1,4 → 1,4
============== WISHBONE Slave Bus Monitor error log ==============
Only ERRONEOUS conditions are logged !
============== WISHBONE Slave Bus Monitor error log ==============
Only ERRONEOUS conditions are logged !
/sim/rtl_sim/log/sdc_tb.log
1,83 → 1,80
========================== SD IP Core Testbench results ===========================
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 2903
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
*FAILED* because
Register %h defaultvalue is not RSP ; 72
*************************************************************************************
*************************************************************************************
At time: 3215
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
*FAILED* because
Register %h defaultvalue is not RSP ; 28
*************************************************************************************
*************************************************************************************
At time: 3423
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
*FAILED* because
Register %h defaultvalue is not RSP ; 36
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: Send CMD
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 8077
Test: 0: Send CMD, No Response
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 61507
Test: 3.0: Init Seq, No Response
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 208147
Test: 4.0: Send data
reported *SUCCESSFULL*!
*************************************************************************************
*************************************************************************************
At time: 415419
Test: 4.0: Send data
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: Send CMD, with simulated bus error on SD_CMD line
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 443473
Test: Test 5 part 4: Send CMD2, 136-Bit
reported *SUCCESSFULL*!
*************************************************************************************
========================== SD IP Core Testbench results ===========================
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 4359
Test: TEST 0: 32-BIT READ-WRITE REGISTERS ( VARIOUS BUS DELAYS )
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: Send CMD
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 8077
Test: 0: Send CMD, No Response
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 61507
Test: 3.0: Init Seq, No Response
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 208563
Test: 4.0: Send data
reported *SUCCESSFULL*!
*************************************************************************************
*************************************************************************************
At time: 416251
Test: 4.0: Send data
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: Send CMD, With simulated bus error on SD_CMD line
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 444201
Test: Test 5 part 4: Send CMD2, 136-Bit
reported *SUCCESSFULL*!
*************************************************************************************
***************************************************************************************
***************************************************************************************
Heading: access_to_reg
***************************************************************************************
***************************************************************************************
*************************************************************************************
At time: 651889
Test: 4.0: Send data
reported *SUCCESSFULL*!
*************************************************************************************
/sim/rtl_sim/run/comp.do
2,7 → 2,8
--Tested on Modelsim 6.5b Revison 2009.05
puts {
ModelSimSE SD_HOST_CONTROLLER compile script version 1.1
Copyright (c) Doulos June 2004, SD
Copyright (c) Doulos June 2004,
Modifed 2010, Adam Edvardsson, ORSoC
}
 
# Simply change the project settings in this section
11,48 → 12,48
 
set library_file_list {
design_library {
../../../rtl/sdc_dma/verilog/SD_defines.v
../../../rtl/sdc_dma/verilog/SD_Bd.v
../../../rtl/sdc_dma/verilog/SD_clock_divider.v
../../../rtl/sdc_dma/verilog/SD_cmd_master.v
../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
../../../rtl/sdc_dma/verilog/SD_controller_top.v
../../../rtl/sdc_dma/verilog/SD_controller_wb.v
../../../rtl/sdc_dma/verilog/SD_crc_7.v
../../../rtl/sdc_dma/verilog/SD_crc_16.v
../../../rtl/sdc_dma/verilog/SD_data_host.v
../../../rtl/sdc_dma/verilog/SD_data_master.v
../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
../../../rtl/sdc_dma/verilog/sd_defines.v
../../../rtl/sdc_dma/verilog/sd_bd.v
../../../rtl/sdc_dma/verilog/sd_clock_divider.v
../../../rtl/sdc_dma/verilog/sd_cmd_master.v
../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
../../../rtl/sdc_dma/verilog/sdc_controller.v
../../../rtl/sdc_dma/verilog/sd_controller_wb.v
../../../rtl/sdc_dma/verilog/sd_crc_7.v
../../../rtl/sdc_dma/verilog/sd_crc_16.v
../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
../../../rtl/sdc_dma/verilog/sd_data_master.v
../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
}
test_library { ../../../bench/sdc_dma/verilog/wb_model_defines.v
../../../bench/sdc_dma/verilog/SD_controller_top_tb.v
../../../bench/sdc_dma/verilog/sdModel.v
../../../bench/sdc_dma/verilog/sd_controller_top_tb.v
../../../bench/sdc_dma/verilog/sdModel.v
../../../bench/sdc_dma/verilog/timescale.v
../../../bench/sdc_dma/verilog/wb_bus_mon.v
../../../bench/sdc_dma/verilog/wb_master32.v
../../../bench/sdc_dma/verilog/wb_master_behavioral.v
../../../bench/sdc_dma/verilog/wb_slave_behavioral.v
../../../rtl/sdc_dma/verilog/SD_defines.v
../../../rtl/sdc_dma/verilog/SD_Bd.v
../../../rtl/sdc_dma/verilog/SD_clock_divider.v
../../../rtl/sdc_dma/verilog/SD_cmd_master.v
../../../rtl/sdc_dma/verilog/SD_cmd_serial_host.v
../../../rtl/sdc_dma/verilog/SD_controller_top.v
../../../rtl/sdc_dma/verilog/SD_controller_wb.v
../../../rtl/sdc_dma/verilog/SD_crc_7.v
../../../rtl/sdc_dma/verilog/SD_crc_16.v
../../../rtl/sdc_dma/verilog/SD_data_host.v
../../../rtl/sdc_dma/verilog/SD_data_master.v
../../../rtl/sdc_dma/verilog/SD_FIFO_RX_Filler.v
../../../rtl/sdc_dma/verilog/SD_FIFO_TX_Filler.v
../../../rtl/sdc_dma/verilog/fifo/smii_rx_fifo.v
../../../rtl/sdc_dma/verilog/fifo/smii_tx_fifo.v
../../../rtl/sdc_dma/verilog/sd_defines.v
../../../rtl/sdc_dma/verilog/sd_bd.v
../../../rtl/sdc_dma/verilog/sd_clock_divider.v
../../../rtl/sdc_dma/verilog/sd_cmd_master.v
../../../rtl/sdc_dma/verilog/sd_cmd_serial_host.v
../../../rtl/sdc_dma/verilog/sdc_controller.v
../../../rtl/sdc_dma/verilog/sd_controller_wb.v
../../../rtl/sdc_dma/verilog/sd_crc_7.v
../../../rtl/sdc_dma/verilog/sd_crc_16.v
../../../rtl/sdc_dma/verilog/sd_data_serial_host.v
../../../rtl/sdc_dma/verilog/sd_data_master.v
../../../rtl/sdc_dma/verilog/sd_fifo_rx_filler.v
../../../rtl/sdc_dma/verilog/sd_fifo_tx_filler.v
../../../rtl/sdc_dma/verilog/sd_rx_fifo.v
../../../rtl/sdc_dma/verilog/sd_tx_fifo.v
}
}
set top_level test_library.SD_controller_top_tb
set top_level test_library.sd_controller_top_tb
 
 
 
122,11 → 123,11
catch {property wave -radix $radix $signal}
}
}
if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
# if $tk_ok {wm geometry .wave [winfo screenwidth .]x330+0-20}
}
 
# Run the simulation
when {/SD_controller_top_tb/succes = 1} {stop}
when {/sd_controller_top_tb/succes = 1} {stop}
run -all
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.