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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

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  • This comparison shows the changes necessary to convert path
    /sdr_ctrl/trunk
    from Rev 28 to Rev 27
    Reverse comparison

Rev 28 → Rev 27

/verif/log/core_sdr16_sim.log
292,7 → 292,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 53060 ns Iteration: 0 Instance: /tb_core
### test 1: basic_test1 --> PASSED
###########################################
/verif/log/core_sdr8_sim.log
292,7 → 292,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 57460 ns Iteration: 0 Instance: /tb_core
### test 1: basic_test1 --> PASSED
###########################################
/verif/log/core_SDR_32BIT_basic_test1.log
22,7 → 22,7
# Loading work.sdrc_xfr_ctl
# Loading work.sdrc_bs_convert
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) ../tb/tb_core.sv(195): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# ** Warning: (vsim-3015) ../tb/tb_core.sv(193): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# Region: /tb_core/u_sdram32
# do run.do
# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
576,5 → 576,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 50860 ns Iteration: 0 Instance: /tb_core
/verif/log/core_SDR_16BIT_basic_test1.log
268,5 → 268,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 53060 ns Iteration: 0 Instance: /tb_core
/verif/log/core_SDR_8BIT_basic_test1.log
268,5 → 268,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 57460 ns Iteration: 0 Instance: /tb_core
/verif/log/core_sdr32_sim.log
46,7 → 46,7
# Loading work.sdrc_xfr_ctl
# Loading work.sdrc_bs_convert
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) ../tb/tb_core.sv(195): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# ** Warning: (vsim-3015) ../tb/tb_core.sv(193): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# Region: /tb_core/u_sdram32
# do run.do
# tb_core.u_sdram32 : at time 10157.0 ns AREF : Auto Refresh
600,7 → 600,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_core.sv(300)
# ** Note: $finish : ../tb/tb_core.sv(298)
# Time: 50860 ns Iteration: 0 Instance: /tb_core
### test 1: basic_test1 --> PASSED
###########################################

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