URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl
- from Rev 15 to Rev 14
- ↔ Reverse comparison
Rev 15 → Rev 14
/trunk/rtl/core/sdrc_req_gen.v
81,6 → 81,7
req_wr_n, // 0 => Write request, 1 => read req |
req_ack, // Request has been accepted |
sdr_core_busy_n, // SDRAM Core Busy Indication |
sdr_dev_config, // sdram configuration |
cfg_colbits, |
|
/* Req to bank_ctl */ |
131,6 → 132,7
input b2r_ack, b2r_arb_ok, sdr_init_done; |
// |
input sdr_width; |
input [1:0] sdr_dev_config; |
|
/****************************************************************************/ |
// Internal Nets |
/trunk/rtl/core/sdrc_core.v
107,6 → 107,7
|
/* Parameters */ |
cfg_sdr_en, |
cfg_sdr_dev_config, // using 64M/4bank SDRAMs |
cfg_sdr_mode_reg, |
cfg_sdr_tras_d, |
cfg_sdr_trp_d, |
176,6 → 177,7
input [3:0] cfg_sdr_trp_d ; // Precharge to active delay |
input [3:0] cfg_sdr_trcd_d ; // Active to R/W delay |
input cfg_sdr_en ; // Enable SDRAM controller |
input [1:0] cfg_sdr_dev_config ; // 2'b00 - 8 MB, 01 - 16 MB, 10 - 32 MB , 11 - 64 MB |
input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller |
input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit |
input [11:0] cfg_sdr_mode_reg ; |
216,6 → 218,7
wire xfr_rdstart, xfr_rdlast; |
wire xfr_wrstart, xfr_wrlast; |
wire [`SDR_REQ_ID_W-1:0]xfr_id; |
wire [13:0] xfr_addr_msb; |
wire [APP_DW-1:0] app_rd_data; |
wire app_wr_next_req, app_rd_valid; |
wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n; |
228,6 → 231,7
wire [SDR_BW-1:0] sdr_den_n_int; |
|
wire [1:0] xfr_bank_sel; |
wire [1:0] cfg_sdr_dev_config; |
|
wire [APP_AW:0] app_req_addr_int; |
wire [APP_AW-1:0] app_req_addr; |
267,6 → 271,7
sdrc_req_gen #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_req_gen ( |
.clk (clk ), |
.reset_n (reset_n ), |
.sdr_dev_config (cfg_sdr_dev_config ), |
.cfg_colbits (cfg_colbits ), |
|
/* Request from app */ |
345,8 → 350,10
.x2b_wrok (x2b_wrok ), |
|
/* for generate cuurent xfr address msb */ |
.sdr_dev_config (cfg_sdr_dev_config ), |
.sdr_req_norm_dma_last(app_req_dma_last_int), |
.xfr_bank_sel (xfr_bank_sel ), |
.xfr_addr_msb (xfr_addr_msb ), |
|
/* SDRAM Timing */ |
.tras_delay (cfg_sdr_tras_d ), |
/trunk/rtl/core/sdrc.def
23,5 → 23,10
`define SDR_REFRESH 4'b0001 |
`define SDR_MODE 4'b0000 |
|
// sdr configuration |
`define SDR_CONFIG_IS_8M 2'b00 |
`define SDR_CONFIG_IS_16M 2'b01 |
`define SDR_CONFIG_IS_32M 2'b10 |
`define SDR_CONFIG_IS_64M 2'b11 |
|
|
/trunk/rtl/core/sdrc_bank_ctl.v
86,7 → 86,9
x2b_wrok, // OK to do a write |
|
/* xfr msb address */ |
sdr_dev_config, |
xfr_bank_sel, |
xfr_addr_msb, |
sdr_req_norm_dma_last, |
|
/* SDRAM Timing */ |
133,7 → 135,9
|
input [3:0] tras_delay, trp_delay, trcd_delay; |
|
input [1:0] sdr_dev_config; |
input [1:0] xfr_bank_sel; |
output [13:0] xfr_addr_msb; |
|
/****************************************************************************/ |
// Internal Nets |
559,6 → 563,8
(xfr_bank_sel==2) ? bank2_row: |
(xfr_bank_sel==1) ? bank1_row: bank0_row; |
|
assign xfr_addr_msb = (sdr_dev_config == 2'b11) ? {cur_row, xfr_bank_sel[1:0]}: |
{cur_row, xfr_bank_sel[0]}; |
|
|
endmodule // sdr_bank_ctl |