URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl
- from Rev 28 to Rev 29
- ↔ Reverse comparison
Rev 28 → Rev 29
/trunk/verif/run/compile.modelsim
6,5 → 6,8
\rm -rf work |
vlib work |
endif |
|
vlog -work work +define+$1 -f filelist.f |
if($1 == "core") then # run SDRAM Core level test case |
vlog -work work +define+$2 -f filelist_core.f |
else # Run SDRAM Top Level test cases |
vlog -work work +define+$2 -f filelist_top.f |
endif |
/trunk/verif/run/filelist_rtl.f
0,0 → 1,10
+incdir+../../rtl/core \ |
../../rtl/top/sdrc_top.v \ |
../../rtl/wb2sdrc/wb2sdrc.v \ |
../../rtl/lib/async_fifo.v \ |
../../rtl/core/sdrc_core.v \ |
../../rtl/core/sdrc_bank_ctl.v \ |
../../rtl/core/sdrc_bank_fsm.v \ |
../../rtl/core/sdrc_bs_convert.v \ |
../../rtl/core/sdrc_req_gen.v \ |
../../rtl/core/sdrc_xfr_ctl.v |
trunk/verif/run/filelist_rtl.f
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/verif/run/filelist_top.f
===================================================================
--- trunk/verif/run/filelist_top.f (nonexistent)
+++ trunk/verif/run/filelist_top.f (revision 29)
@@ -0,0 +1,16 @@
++define+S50 \
++define+VERBOSE \
++incdir+../../rtl/core \
+../tb/tb_top.sv \
+../model/IS42VM16400K.V
+../model/mt48lc2m32b2.v \
+../model/mt48lc8m8a2.v \
+../../rtl/top/sdrc_top.v \
+../../rtl/wb2sdrc/wb2sdrc.v \
+../../rtl/lib/async_fifo.v \
+../../rtl/core/sdrc_core.v \
+../../rtl/core/sdrc_bank_ctl.v \
+../../rtl/core/sdrc_bank_fsm.v \
+../../rtl/core/sdrc_bs_convert.v \
+../../rtl/core/sdrc_req_gen.v \
+../../rtl/core/sdrc_xfr_ctl.v
trunk/verif/run/filelist_top.f
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/verif/run/filelist_core.f
===================================================================
--- trunk/verif/run/filelist_core.f (nonexistent)
+++ trunk/verif/run/filelist_core.f (revision 29)
@@ -0,0 +1,12 @@
++define+S50 \
++incdir+../../rtl/core \
+../tb/tb_core.sv \
+../model/IS42VM16400K.V
+../model/mt48lc2m32b2.v \
+../model/mt48lc8m8a2.v \
+../../rtl/core/sdrc_core.v \
+../../rtl/core/sdrc_bank_ctl.v \
+../../rtl/core/sdrc_bank_fsm.v \
+../../rtl/core/sdrc_bs_convert.v \
+../../rtl/core/sdrc_req_gen.v \
+../../rtl/core/sdrc_xfr_ctl.v
trunk/verif/run/filelist_core.f
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/verif/run/run_all
===================================================================
--- trunk/verif/run/run_all (revision 28)
+++ trunk/verif/run/run_all (revision 29)
@@ -1,16 +1,48 @@
#!/bin/csh -f
+#format
+# run_modesim
+# Example ./run_modelsim core SDR_16BIT
+#
+# Option-1:
+# core - Run the SDRAM core level test case
+# top - Run the SDRAM Top level test case
+# Option-2:
+# SDR-16BIT - Run 16 Bit SDRAM Test case
+# SDR-32BIT - Run 32 Bit SDRAM Test case
+# SDR-8BIT - Run 8 Bit SDRAM Test case
+#
+#
+echo "######### SDRAM CORE STAND ALONG TEST CASE ########"
echo "#############################"
echo " INITIATING SDR 16 BIT Tests"
echo ##############################
-./run_modelsim SDR_16BIT | tee ../log/sdr16_sim.log
+./run_modelsim core SDR_16BIT | tee ../log/core_sdr16_sim.log
echo "#############################"
echo " INITIATING SDR 32 BIT Tests"
echo ##############################
-./run_modelsim SDR_32BIT | tee ../log/sdr32_sim.log
+./run_modelsim core SDR_32BIT | tee ../log/core_sdr32_sim.log
echo "#############################"
echo " INITIATING SDR 8 BIT Tests"
echo ##############################
-./run_modelsim SDR_8BIT | tee ../log/sdr8_sim.log
+./run_modelsim core SDR_8BIT | tee ../log/core_sdr8_sim.log
+
+
+echo "######### SDRAM TOP TEST CASE ########"
+
+echo "#############################"
+echo " INITIATING SDR 16 BIT Tests"
+echo ##############################
+./run_modelsim top SDR_16BIT | tee ../log/top_sdr16_sim.log
+
+echo "#############################"
+echo " INITIATING SDR 32 BIT Tests"
+echo ##############################
+./run_modelsim top SDR_32BIT | tee ../log/top_sdr32_sim.log
+
+echo "#############################"
+echo " INITIATING SDR 8 BIT Tests"
+echo ##############################
+./run_modelsim top SDR_8BIT | tee ../log/top_sdr8_sim.log
/trunk/verif/run/run_modelsim
10,9 → 10,9
#set misc_tests=( ) |
|
|
echo " Compiling with MODELSIM in $1 Mode " |
echo " Compiling with MODELSIM in $1 $2 Mode " |
|
./compile.modelsim $1 | tee ../log/$1_complie.log |
./compile.modelsim $1 $2 | tee ../log/$1_$2_complie.log |
|
|
if ($status != 0) then |
37,7 → 37,7
#echo "" |
echo "### Running test ${i}: ${run_test}" |
|
vsim -do run.do -c tb_top +${run_test} | tee ../log/run.log |
vsim -do run.do -c tb_$1 +${run_test} | tee ../log/run.log |
if ($status != 0) then |
cat ../log/run.log |
exit |
50,7 → 50,7
@ all_testsm += 1; |
endif |
|
mv ../log/run.log ../log/$1_${run_test}.log |
mv ../log/run.log ../log/$1_$2_${run_test}.log |
|
|
end |
63,7 → 63,7
echo "### Test Logs " |
foreach run_test ($sdr_tests) |
@ i += 1; |
echo " test ${i}: ../log/$1_${run_test}.log" |
echo " test ${i}: ../log/$1_$2_${run_test}.log" |
|
end |
echo "###########################################" |
73,6 → 73,6
echo "###########################################" |
echo "### Test Summary " |
echo "### " |
echo "### Failed $failedm of $all_testsm $1 tests" |
echo "### Failed $failedm of $all_testsm $2 tests" |
echo "###########################################" |
|