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  • This comparison shows the changes necessary to convert path 
    /sdr_ctrl/trunk/rtl/core
    from Rev 37 to Rev 44
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Rev 37 → Rev 44

/sdrc_bs_convert.v
15,7 → 15,9
Author(s):
- Dinesh Annayya, dinesha@opencores.org
Version : 1.0 - 8th Jan 2012
Version : 0.0 - 8th Jan 2012 - Initial structure
0.2 - 2nd Feb 2012
Improved the command pipe structure to accept up-to 4 command of different bank.
 
50,28 → 52,37
reset_n,
sdr_width,
 
/* Control Signal from xfr ctrl */
x2a_rdstart,
x2a_wrstart,
x2a_rdlast,
x2a_wrlast,
app_rd_data_int,
app_rd_valid_int,
app_wr_data_int,
app_wr_en_n_int,
app_wr_next_int,
 
/* Control Signal from request ctrl */
app_req_addr_int,
app_req_len_int,
app_req_ack_int,
app_sdr_req_int,
 
/* Control Signal from Bank Ctrl */
app_req_dma_last_int,
 
/* Control Signal from/to to application i/f */
app_req_addr,
app_req_addr_int,
app_req_len,
app_req_len_int,
app_sdr_req,
app_sdr_req_int,
app_req_dma_last,
app_req_dma_last_int,
app_req_wr_n,
app_req_ack,
app_req_ack_int,
 
app_wr_data,
app_wr_data_int,
app_wr_en_n,
app_wr_en_n_int,
app_wr_next_int,
app_wr_next,
 
app_rd_data_int,
app_rd_data,
app_rd_valid_int,
app_rd_valid
);
parameter APP_AW = 30; // Application Address Width
86,28 → 97,41
input reset_n ;
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 
/* Control Signal from xfr ctrl */
input x2a_rdstart; // read start indication
input x2a_wrstart; // writ start indication
input x2a_rdlast; // read last burst access
input x2a_wrlast; // write last transfer
input [SDR_DW-1:0] app_rd_data_int;
input app_rd_valid_int;
output [SDR_DW-1:0] app_wr_data_int;
output [SDR_BW-1:0] app_wr_en_n_int;
input app_wr_next_int;
 
/* Control Signal from request ctrl */
output [APP_AW:0] app_req_addr_int;
output [APP_RW-1:0] app_req_len_int;
input app_req_ack_int;
output app_sdr_req_int;
 
/* Control Signal from Bank Ctrl */
output app_req_dma_last_int;
 
 
/* Control Signal from/to to application i/f */
input [APP_AW-1:0] app_req_addr;
output [APP_AW:0] app_req_addr_int;
input [APP_RW-1:0] app_req_len ;
output [APP_RW-1:0] app_req_len_int;
input app_req_wr_n;
input app_sdr_req;
output app_sdr_req_int;
input app_req_dma_last;
output app_req_dma_last_int;
input app_req_ack_int;
output app_req_ack;
 
input [APP_DW-1:0] app_wr_data;
output [SDR_DW-1:0] app_wr_data_int;
input [APP_BW-1:0] app_wr_en_n;
output [SDR_BW-1:0] app_wr_en_n_int;
input app_wr_next_int;
output app_wr_next;
 
input [SDR_DW-1:0] app_rd_data_int;
output [APP_DW-1:0] app_rd_data;
input app_rd_valid_int;
output app_rd_valid;
 
reg [APP_AW:0] app_req_addr_int;
124,8 → 148,8
reg app_wr_next;
 
reg [23:0] saved_rd_data;
reg [7:0] rd_xfr_count;
reg [7:0] wr_xfr_count;
reg [1:0] rd_xfr_count;
reg [1:0] wr_xfr_count;
 
 
wire ok_to_req;
152,7 → 176,8
app_req_addr_int = {app_req_addr,1'b0};
app_req_len_int = {app_req_len,1'b0};
app_req_dma_last_int = app_req_dma_last;
app_sdr_req_int = app_sdr_req && ok_to_req;
//app_sdr_req_int = app_sdr_req && ok_to_req;
app_sdr_req_int = app_sdr_req ;
app_req_ack = app_req_ack_int;
app_wr_next = (app_wr_next_int & wr_xfr_count[0]);
app_rd_valid = (rd_xfr_count & rd_xfr_count[0]);
176,10 → 201,9
app_req_dma_last_int = app_req_dma_last;
app_sdr_req_int = app_sdr_req && ok_to_req;
app_req_ack = app_req_ack_int;
app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b01));
app_rd_valid = (rd_xfr_count & (rd_xfr_count[1:0]== 2'b01));
// Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00
if(wr_xfr_count[1:0] == 2'b01)
app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b11));
app_rd_valid = (rd_xfr_count & (rd_xfr_count[1:0]== 2'b11));
if(wr_xfr_count[1:0] == 2'b11)
begin
app_wr_en_n_int = app_wr_en_n[3];
app_wr_data_int = app_wr_data[31:24];
189,7 → 213,7
app_wr_en_n_int = app_wr_en_n[2];
app_wr_data_int = app_wr_data[23:16];
end
else if(wr_xfr_count[1:0] == 2'b11)
else if(wr_xfr_count[1:0] == 2'b01)
begin
app_wr_en_n_int = app_wr_en_n[1];
app_wr_data_int = app_wr_data[15:8];
204,7 → 228,6
end
 
 
reg lcl_mc_req_wr_n;
 
always @(posedge clk)
begin
212,33 → 235,33
begin
rd_xfr_count <= 8'b0;
wr_xfr_count <= 8'b0;
lcl_mc_req_wr_n <= 1'b1;
saved_rd_data <= 24'h0;
end
else begin
if(app_req_ack)
lcl_mc_req_wr_n <= app_req_wr_n;
 
// During Write Phase
if(app_req_ack && (app_req_wr_n == 0)) begin
wr_xfr_count <= app_req_len_int;
if(x2a_wrlast) begin
wr_xfr_count <= 0;
end
else if(app_wr_next_int & !lcl_mc_req_wr_n) begin
wr_xfr_count <= wr_xfr_count - 1'b1;
else if(app_wr_next_int) begin
wr_xfr_count <= wr_xfr_count + 1'b1;
end
 
// During Read Phase
if(app_req_ack && app_req_wr_n) begin
rd_xfr_count <= app_req_len_int;
if(x2a_rdlast) begin
rd_xfr_count <= 0;
end
else if(app_rd_valid_int & lcl_mc_req_wr_n) begin
rd_xfr_count <= rd_xfr_count - 1'b1;
else if(app_rd_valid_int) begin
rd_xfr_count <= rd_xfr_count + 1'b1;
end
 
// Save Previous Data
if(app_rd_valid_int) begin
if(sdr_width == 2'b01) // 16 Bit SDR Mode
saved_rd_data[15:0] <= app_rd_data_int;
else begin// 8 bit SDR Mode -
// Note: counter is down counter from 00 -> 11 -> 10 -> 01 --> 00
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= app_rd_data_int[7:0];
else if(rd_xfr_count[1:0] == 2'b11) saved_rd_data[15:8] <= app_rd_data_int[7:0];
else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= app_rd_data_int[7:0];
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= app_rd_data_int[7:0];
end
end
/sdrc_core.v
34,10 → 34,12
Author(s):
- Dinesh Annayya, dinesha@opencores.org
Version : 1.0 - 8th Jan 2012
Version : 0.0 - 8th Jan 2012
Initial version with 16/32 Bit SDRAM Support
: 1.1 - 24th Jan 2012
: 0.1 - 24th Jan 2012
8 Bit SDRAM Support is added
0.2 - 2nd Feb 2012
Improved the command pipe structure to accept up-to 4 command of different bank.
 
Copyright (C) 2000 Authors and OPENCORES.ORG
253,7 → 255,9
wire b2x_wrap;
wire app_wr_next_int;
wire app_rd_valid_int;
wire x2a_rdlast;
 
 
// synopsys translate_off
wire [3:0] sdr_cmd;
assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
262,6 → 266,7
assign sdr_den_n = sdr_den_n_int ;
assign sdr_dout = sdr_dout_int ;
 
assign app_last_rd = x2a_rdlast;
 
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
416,12 → 421,11
.sdr_din (pad_sdr_din2 ),
.sdr_dout (sdr_dout_int ),
.sdr_den_n (sdr_den_n_int ),
/* Data Flow to the app */
.x2a_rdstart (xfr_rdstart ),
.x2a_wrstart (xfr_wrstart ),
.x2a_id (xfr_id ),
.x2a_rdlast (app_last_rd ),
.x2a_rdlast (x2a_rdlast ),
.x2a_wrlast (xfr_wrlast ),
.app_wrdt (add_wr_data_int ),
.app_wren_n (app_wr_en_n_int ),
459,29 → 463,39
.reset_n (reset_n ),
.sdr_width (sdr_width ),
 
/* Control Signal from xfr ctrl */
.x2a_rdstart (xfr_rdstart ),
.x2a_wrstart (xfr_wrstart ),
.x2a_rdlast (x2a_rdlast ),
.x2a_wrlast (xfr_wrlast ),
.app_rd_data_int (app_rd_data_int ),
.app_rd_valid_int (app_rd_valid_int ),
.app_wr_data_int (add_wr_data_int ),
.app_wr_en_n_int (app_wr_en_n_int ),
.app_wr_next_int (app_wr_next_int ),
 
/* Control Signal from request ctrl */
.app_req_addr_int (app_req_addr_int ),
.app_req_len_int (app_req_len_int ),
.app_req_ack_int (app_req_ack_int ),
.app_sdr_req_int (app_req_int ),
 
/* Control Signal from Bank Ctrl */
.app_req_dma_last_int(app_req_dma_last_int),
 
/* Control Signal from/to to application i/f */
.app_req_addr (app_req_addr ),
.app_req_addr_int (app_req_addr_int ),
.app_req_len (app_req_len ),
.app_req_len_int (app_req_len_int ),
.app_sdr_req (app_req ),
.app_sdr_req_int (app_req_int ),
.app_req_dma_last (app_req_dma_last ),
.app_req_dma_last_int(app_req_dma_last_int),
.app_req_wr_n (app_req_wr_n ),
.app_req_ack_int (app_req_ack_int ),
.app_req_ack (app_req_ack ),
 
.app_wr_data (app_wr_data ),
.app_wr_data_int (add_wr_data_int ),
.app_wr_en_n (app_wr_en_n ),
.app_wr_en_n_int (app_wr_en_n_int ),
.app_wr_next_int (app_wr_next_int ),
.app_wr_next (app_wr_next_req ),
 
.app_rd_data_int (app_rd_data_int ),
.app_rd_data (app_rd_data ),
.app_rd_valid_int (app_rd_valid_int ),
.app_rd_valid (app_rd_valid )
 
);
endmodule // sdrc_core

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