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  • This comparison shows the changes necessary to convert path 
    /sdr_ctrl/trunk/rtl/core
    from Rev 44 to Rev 45
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Rev 44 → Rev 45

/sdrc_req_gen.v
154,6 → 154,27
reg [APP_AW-1:0] curr_sdr_addr, sdr_addrs_mask;
wire [APP_AW-1:0] next_sdr_addr, next_sdr_addr1;
 
 
//--------------------------------------------------------------------
// Generate the internal Adress and Burst length Based on sdram width
//--------------------------------------------------------------------
reg [APP_AW:0] req_addr_int;
reg [APP_RW-1:0] req_len_int;
always @(*) begin
if(sdr_width == 2'b00) begin // 32 Bit SDR Mode
req_addr_int = {1'b0,req_addr};
req_len_int = req_len;
end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode
// Changed the address and length to match the 16 bit SDR Mode
req_addr_int = {req_addr,1'b0};
req_len_int = {req_len,1'b0};
end else begin // 8 Bit SDR Mode
// Changed the address and length to match the 16 bit SDR Mode
req_addr_int = {req_addr,2'b0};
req_len_int = {req_len,2'b0};
end
end
 
//
// The maximum length for no page overflow is 200h/100h - caddr. Split a request
// into 2 or more requests if it crosses a page boundary.
199,10 → 220,10
 
lcl_wrap <= (req_ack) ? req_wrap : lcl_wrap;
lcl_req_len <= (req_ack) ? req_len :
lcl_req_len <= (req_ack) ? req_len_int :
(req_ld) ? next_req_len : lcl_req_len;
 
curr_sdr_addr <= (req_ack) ? req_addr :
curr_sdr_addr <= (req_ack) ? req_addr_int :
(req_ld) ? next_sdr_addr : curr_sdr_addr;
 
sdr_addrs_mask <= (req_ack) ?((sdr_width == 2'b00) ? req_addr_mask :
/sdrc_xfr_ctl.v
107,8 → 107,8
x2a_rdlast,
x2a_wrlast,
x2a_id,
app_wrdt,
app_wren_n,
a2x_wrdt,
a2x_wren_n,
x2a_wrnext,
x2a_rddt,
x2a_rdok,
158,8 → 158,8
output x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast;
output [`SDR_REQ_ID_W-1:0] x2a_id;
 
input [SDR_DW-1:0] app_wrdt;
input [SDR_BW-1:0] app_wren_n;
input [SDR_DW-1:0] a2x_wrdt;
input [SDR_BW-1:0] a2x_wren_n;
output [SDR_DW-1:0] x2a_rddt;
output x2a_wrnext, x2a_rdok, sdr_init_done;
556,7 → 556,7
sdr_we_n <= xfr_cmd[0];
sdr_cke <= (xfr_st != `XFR_IDLE) ? 1'b1 :
~(mgmt_idle & b2x_idle & r2x_idle);
sdr_dqm <= (wr_next) ? app_wren_n : {SDR_BW{1'b0}};
sdr_dqm <= (wr_next) ? a2x_wren_n : {SDR_BW{1'b0}};
sdr_den_n <= (wr_next) ? {SDR_BW{1'b0}} : {SDR_BW{1'b1}};
end // else: !if(~reset_n)
 
567,7 → 567,7
sdr_ba <= xfr_ba;
end // if (~xfr_cmd[3])
sdr_dout <= (wr_next) ? app_wrdt : sdr_dout;
sdr_dout <= (wr_next) ? a2x_wrdt : sdr_dout;
 
end // always @ (posedge clk)
/sdrc_bs_convert.v
48,43 → 48,32
 
`include "sdrc_define.v"
module sdrc_bs_convert (
clk,
reset_n,
sdr_width,
clk ,
reset_n ,
sdr_width ,
 
/* Control Signal from xfr ctrl */
x2a_rdstart,
x2a_wrstart,
x2a_rdlast,
x2a_wrlast,
app_rd_data_int,
app_rd_valid_int,
app_wr_data_int,
app_wr_en_n_int,
app_wr_next_int,
x2a_rdstart ,
x2a_wrstart ,
x2a_rdlast ,
x2a_wrlast ,
x2a_rddt ,
x2a_rdok ,
a2x_wrdt ,
a2x_wren_n ,
x2a_wrnext ,
 
/* Control Signal from request ctrl */
app_req_addr_int,
app_req_len_int,
app_req_ack_int,
app_sdr_req_int,
/* Control Signal from/to to application i/f */
app_wr_data ,
app_wr_en_n ,
app_wr_next ,
app_last_wr ,
app_rd_data ,
app_rd_valid ,
app_last_rd
);
 
/* Control Signal from Bank Ctrl */
app_req_dma_last_int,
 
/* Control Signal from/to to application i/f */
app_req_addr,
app_req_len,
app_sdr_req,
app_req_dma_last,
app_req_wr_n,
app_req_ack,
app_wr_data,
app_wr_en_n,
app_wr_next,
app_rd_data,
app_rd_valid
);
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
93,137 → 82,104
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
input clk;
input reset_n ;
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input clk ;
input reset_n ;
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
 
/* Control Signal from xfr ctrl */
input x2a_rdstart; // read start indication
input x2a_wrstart; // writ start indication
input x2a_rdlast; // read last burst access
input x2a_wrlast; // write last transfer
input [SDR_DW-1:0] app_rd_data_int;
input app_rd_valid_int;
output [SDR_DW-1:0] app_wr_data_int;
output [SDR_BW-1:0] app_wr_en_n_int;
input app_wr_next_int;
/* Control Signal from xfr ctrl Read Transaction*/
input x2a_rdstart ; // read start indication
input x2a_rdlast ; // read last burst access
input [SDR_DW-1:0] x2a_rddt ;
input x2a_rdok ;
 
/* Control Signal from request ctrl */
output [APP_AW:0] app_req_addr_int;
output [APP_RW-1:0] app_req_len_int;
input app_req_ack_int;
output app_sdr_req_int;
/* Control Signal from xfr ctrl Write Transaction*/
input x2a_wrstart ; // writ start indication
input x2a_wrlast ; // write last transfer
input x2a_wrnext ;
output [SDR_DW-1:0] a2x_wrdt ;
output [SDR_BW-1:0] a2x_wren_n ;
 
/* Control Signal from Bank Ctrl */
output app_req_dma_last_int;
// Application Write Transaction
input [APP_DW-1:0] app_wr_data ;
input [APP_BW-1:0] app_wr_en_n ;
output app_wr_next ;
output app_last_wr ; // Indicate last Write Transfer for a given burst size
 
// Application Read Transaction
output [APP_DW-1:0] app_rd_data ;
output app_rd_valid ;
output app_last_rd ; // Indicate last Read Transfer for a given burst size
 
/* Control Signal from/to to application i/f */
input [APP_AW-1:0] app_req_addr;
input [APP_RW-1:0] app_req_len ;
input app_req_wr_n;
input app_sdr_req;
input app_req_dma_last;
output app_req_dma_last_int;
output app_req_ack;
//----------------------------------------------
// Local Decleration
// ----------------------------------------
 
input [APP_DW-1:0] app_wr_data;
input [APP_BW-1:0] app_wr_en_n;
output app_wr_next;
reg [APP_DW-1:0] app_rd_data ;
reg app_rd_valid ;
reg [SDR_DW-1:0] a2x_wrdt ;
reg [SDR_BW-1:0] a2x_wren_n ;
reg app_wr_next ;
 
output [APP_DW-1:0] app_rd_data;
output app_rd_valid;
reg [23:0] saved_rd_data ;
reg [1:0] rd_xfr_count ;
reg [1:0] wr_xfr_count ;
 
reg [APP_AW:0] app_req_addr_int;
reg [APP_RW-1:0] app_req_len_int;
 
reg app_req_dma_last_int;
reg app_sdr_req_int;
reg app_req_ack;
assign app_last_wr = x2a_wrlast;
assign app_last_rd = x2a_rdlast;
 
reg [APP_DW-1:0] app_rd_data;
reg app_rd_valid;
reg [SDR_DW-1:0] app_wr_data_int;
reg [SDR_BW-1:0] app_wr_en_n_int;
reg app_wr_next;
 
reg [23:0] saved_rd_data;
reg [1:0] rd_xfr_count;
reg [1:0] wr_xfr_count;
 
 
wire ok_to_req;
 
assign ok_to_req = ((wr_xfr_count == 0) && (rd_xfr_count == 0));
 
always @(*) begin
if(sdr_width == 2'b00) // 32 Bit SDR Mode
begin
app_req_addr_int = {1'b0,app_req_addr};
app_req_len_int = app_req_len;
app_wr_data_int = app_wr_data;
app_wr_en_n_int = app_wr_en_n;
app_req_dma_last_int = app_req_dma_last;
app_sdr_req_int = app_sdr_req;
app_wr_next = app_wr_next_int;
app_rd_data = app_rd_data_int;
app_rd_valid = app_rd_valid_int;
app_req_ack = app_req_ack_int;
a2x_wrdt = app_wr_data;
a2x_wren_n = app_wr_en_n;
app_wr_next = x2a_wrnext;
app_rd_data = x2a_rddt;
app_rd_valid = x2a_rdok;
end
else if(sdr_width == 2'b01) // 16 Bit SDR Mode
begin
// Changed the address and length to match the 16 bit SDR Mode
app_req_addr_int = {app_req_addr,1'b0};
app_req_len_int = {app_req_len,1'b0};
app_req_dma_last_int = app_req_dma_last;
//app_sdr_req_int = app_sdr_req && ok_to_req;
app_sdr_req_int = app_sdr_req ;
app_req_ack = app_req_ack_int;
app_wr_next = (app_wr_next_int & wr_xfr_count[0]);
app_rd_valid = (rd_xfr_count & rd_xfr_count[0]);
app_wr_next = (x2a_wrnext & wr_xfr_count[0]);
app_rd_valid = (rd_xfr_count & rd_xfr_count[0]);
if(wr_xfr_count[0] == 1'b1)
begin
app_wr_en_n_int = app_wr_en_n[3:2];
app_wr_data_int = app_wr_data[31:16];
a2x_wren_n = app_wr_en_n[3:2];
a2x_wrdt = app_wr_data[31:16];
end
else
begin
app_wr_en_n_int = app_wr_en_n[1:0];
app_wr_data_int = app_wr_data[15:0];
a2x_wren_n = app_wr_en_n[1:0];
a2x_wrdt = app_wr_data[15:0];
end
app_rd_data = {app_rd_data_int,saved_rd_data[15:0]};
app_rd_data = {x2a_rddt,saved_rd_data[15:0]};
end else // 8 Bit SDR Mode
begin
// Changed the address and length to match the 16 bit SDR Mode
app_req_addr_int = {app_req_addr,2'b0};
app_req_len_int = {app_req_len,2'b0};
app_req_dma_last_int = app_req_dma_last;
app_sdr_req_int = app_sdr_req && ok_to_req;
app_req_ack = app_req_ack_int;
app_wr_next = (app_wr_next_int & (wr_xfr_count[1:0]== 2'b11));
app_rd_valid = (rd_xfr_count & (rd_xfr_count[1:0]== 2'b11));
app_wr_next = (x2a_wrnext & (wr_xfr_count[1:0]== 2'b11));
app_rd_valid = (rd_xfr_count & (rd_xfr_count[1:0]== 2'b11));
if(wr_xfr_count[1:0] == 2'b11)
begin
app_wr_en_n_int = app_wr_en_n[3];
app_wr_data_int = app_wr_data[31:24];
a2x_wren_n = app_wr_en_n[3];
a2x_wrdt = app_wr_data[31:24];
end
else if(wr_xfr_count[1:0] == 2'b10)
begin
app_wr_en_n_int = app_wr_en_n[2];
app_wr_data_int = app_wr_data[23:16];
a2x_wren_n = app_wr_en_n[2];
a2x_wrdt = app_wr_data[23:16];
end
else if(wr_xfr_count[1:0] == 2'b01)
begin
app_wr_en_n_int = app_wr_en_n[1];
app_wr_data_int = app_wr_data[15:8];
a2x_wren_n = app_wr_en_n[1];
a2x_wrdt = app_wr_data[15:8];
end
else begin
app_wr_en_n_int = app_wr_en_n[0];
app_wr_data_int = app_wr_data[7:0];
a2x_wren_n = app_wr_en_n[0];
a2x_wrdt = app_wr_data[7:0];
end
app_rd_data = {app_rd_data_int,saved_rd_data[23:0]};
app_rd_data = {x2a_rddt,saved_rd_data[23:0]};
end
end
 
243,7 → 199,7
if(x2a_wrlast) begin
wr_xfr_count <= 0;
end
else if(app_wr_next_int) begin
else if(x2a_wrnext) begin
wr_xfr_count <= wr_xfr_count + 1'b1;
end
 
251,18 → 207,18
if(x2a_rdlast) begin
rd_xfr_count <= 0;
end
else if(app_rd_valid_int) begin
else if(x2a_rdok) begin
rd_xfr_count <= rd_xfr_count + 1'b1;
end
 
// Save Previous Data
if(app_rd_valid_int) begin
if(x2a_rdok) begin
if(sdr_width == 2'b01) // 16 Bit SDR Mode
saved_rd_data[15:0] <= app_rd_data_int;
saved_rd_data[15:0] <= x2a_rddt;
else begin// 8 bit SDR Mode -
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= app_rd_data_int[7:0];
else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= app_rd_data_int[7:0];
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= app_rd_data_int[7:0];
if(rd_xfr_count[1:0] == 2'b00) saved_rd_data[7:0] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b01) saved_rd_data[15:8] <= x2a_rddt[7:0];
else if(rd_xfr_count[1:0] == 2'b10) saved_rd_data[23:16] <= x2a_rddt[7:0];
end
end
end
/sdrc_core.v
90,6 → 90,8
app_wr_data,
app_wr_en_n,
app_last_wr,
 
app_rd_data,
app_rd_valid,
app_last_rd,
155,6 → 157,7
input [APP_DW-1:0] app_wr_data ; // Write Data
output app_wr_next_req ; // Next Write Data Request
input [APP_BW-1:0] app_wr_en_n ; // Byte wise Write Enable
output app_last_wr ; // Last Write trannsfer of a given Burst
output [APP_DW-1:0] app_rd_data ; // Read Data
output app_rd_valid ; // Read Valid
output app_last_rd ; // Last Read Transfer of a given Burst
196,9 → 199,6
// Internal Nets
// SDR_REQ_GEN
wire r2x_idle, app_req_ack,app_req_ack_int;
wire app_req_dma_last_int;
wire r2b_req, r2b_start, r2b_last, r2b_write;
wire [`SDR_REQ_ID_W-1:0]r2b_req_id;
wire [1:0] r2b_ba;
wire [11:0] r2b_raddr;
206,24 → 206,16
wire [APP_RW-1:0] r2b_len;
 
// SDR BANK CTL
wire b2r_ack, b2x_idle;
wire b2x_req, b2x_start, b2x_last, b2x_tras_ok;
wire [`SDR_REQ_ID_W-1:0]b2x_id;
wire [1:0] b2x_ba;
wire b2x_ba_last;
wire [11:0] b2x_addr;
wire [APP_RW-1:0] b2x_len;
wire [1:0] b2x_cmd;
 
// SDR_XFR_CTL
wire x2b_ack;
wire [3:0] x2b_pre_ok;
wire x2b_refresh, x2b_act_ok, x2b_rdok, x2b_wrok;
wire xfr_rdstart, app_last_rd;
wire xfr_wrstart, xfr_wrlast;
wire [`SDR_REQ_ID_W-1:0]xfr_id;
wire [APP_DW-1:0] app_rd_data;
wire app_wr_next_req, app_rd_valid;
wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n;
wire [SDR_BW-1:0] sdr_dqm;
wire [1:0] sdr_ba;
235,38 → 227,26
 
wire [1:0] xfr_bank_sel;
 
wire [APP_AW:0] app_req_addr_int;
wire [APP_AW-1:0] app_req_addr;
wire [APP_RW-1:0] app_req_len_int;
wire [APP_RW-1:0] app_req_len;
 
wire [APP_DW-1:0] app_wr_data;
wire [SDR_DW-1:0] add_wr_data_int;
wire [SDR_DW-1:0] a2x_wrdt ;
wire [APP_BW-1:0] app_wr_en_n;
wire [SDR_BW-1:0] app_wr_en_n_int;
wire [SDR_BW-1:0] a2x_wren_n;
 
//wire [31:0] app_rd_data;
wire [SDR_DW-1:0] app_rd_data_int;
wire [SDR_DW-1:0] x2a_rddt;
 
//
wire app_req_int;
wire r2b_wrap;
wire b2r_arb_ok;
wire b2x_wrap;
wire app_wr_next_int;
wire app_rd_valid_int;
wire x2a_rdlast;
 
 
// synopsys translate_off
wire [3:0] sdr_cmd;
assign sdr_cmd = {sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n};
// synopsys translate_on
 
assign sdr_den_n = sdr_den_n_int ;
assign sdr_dout = sdr_dout_int ;
assign sdr_den_n = sdr_den_n_int ;
assign sdr_dout = sdr_dout_int ;
 
assign app_last_rd = x2a_rdlast;
 
// To meet the timing at read path, read data is registered w.r.t pad_sdram_clock and register back to sdram_clk
// assumption, pad_sdram_clk is synhronous and delayed clock of sdram_clk.
281,6 → 261,7
pad_sdr_din2 <= pad_sdr_din1;
end
 
 
/****************************************************************************/
// Instantiate sdr_req_gen
// This module takes requests from the app, chops them to burst booundaries
293,14 → 274,14
 
/* Request from app */
.r2x_idle (r2x_idle ),
.req (app_req_int ),
.req (app_req ),
.req_id (4'b0 ),
.req_addr (app_req_addr_int ),
.req_addr (app_req_addr ),
.req_addr_mask (app_req_addr_mask ),
.req_len (app_req_len_int ),
.req_len (app_req_len ),
.req_wrap (app_req_wrap ),
.req_wr_n (app_req_wr_n ),
.req_ack (app_req_ack_int ),
.req_ack (app_req_ack ),
.sdr_core_busy_n (sdr_core_busy_n ),
/* Req to bank_ctl */
367,7 → 348,7
.x2b_wrok (x2b_wrok ),
 
/* for generate cuurent xfr address msb */
.sdr_req_norm_dma_last(app_req_dma_last_int),
.sdr_req_norm_dma_last(app_req_dma_last),
.xfr_bank_sel (xfr_bank_sel ),
 
/* SDRAM Timing */
422,16 → 403,16
.sdr_dout (sdr_dout_int ),
.sdr_den_n (sdr_den_n_int ),
/* Data Flow to the app */
.x2a_rdstart (xfr_rdstart ),
.x2a_wrstart (xfr_wrstart ),
.x2a_rdstart (x2a_rdstart ),
.x2a_wrstart (x2a_wrstart ),
.x2a_id (xfr_id ),
.x2a_rdlast (x2a_rdlast ),
.x2a_wrlast (xfr_wrlast ),
.app_wrdt (add_wr_data_int ),
.app_wren_n (app_wr_en_n_int ),
.x2a_wrnext (app_wr_next_int ),
.x2a_rddt (app_rd_data_int ),
.x2a_rdok (app_rd_valid_int ),
.x2a_wrlast (x2a_wrlast ),
.a2x_wrdt (a2x_wrdt ),
.a2x_wren_n (a2x_wren_n ),
.x2a_wrnext (x2a_wrnext ),
.x2a_rddt (x2a_rddt ),
.x2a_rdok (x2a_rdok ),
.sdr_init_done (sdr_init_done ),
/* SDRAM Parameters */
464,37 → 445,32
.sdr_width (sdr_width ),
 
/* Control Signal from xfr ctrl */
.x2a_rdstart (xfr_rdstart ),
.x2a_wrstart (xfr_wrstart ),
// Read Interface Inputs
.x2a_rdstart (x2a_rdstart ),
.x2a_rdlast (x2a_rdlast ),
.x2a_wrlast (xfr_wrlast ),
.app_rd_data_int (app_rd_data_int ),
.app_rd_valid_int (app_rd_valid_int ),
.app_wr_data_int (add_wr_data_int ),
.app_wr_en_n_int (app_wr_en_n_int ),
.app_wr_next_int (app_wr_next_int ),
.x2a_rdok (x2a_rdok ),
// Read Interface outputs
.x2a_rddt (x2a_rddt ),
 
/* Control Signal from request ctrl */
.app_req_addr_int (app_req_addr_int ),
.app_req_len_int (app_req_len_int ),
.app_req_ack_int (app_req_ack_int ),
.app_sdr_req_int (app_req_int ),
// Write Interface, Inputs
.x2a_wrstart (x2a_wrstart ),
.x2a_wrlast (x2a_wrlast ),
.x2a_wrnext (x2a_wrnext ),
 
/* Control Signal from Bank Ctrl */
.app_req_dma_last_int(app_req_dma_last_int),
// Write Interface, Outputs
.a2x_wrdt (a2x_wrdt ),
.a2x_wren_n (a2x_wren_n ),
 
/* Control Signal from sdrc_bank_ctl */
 
/* Control Signal from/to to application i/f */
.app_req_addr (app_req_addr ),
.app_req_len (app_req_len ),
.app_sdr_req (app_req ),
.app_req_dma_last (app_req_dma_last ),
.app_req_wr_n (app_req_wr_n ),
.app_req_ack (app_req_ack ),
.app_wr_data (app_wr_data ),
.app_wr_en_n (app_wr_en_n ),
.app_wr_next (app_wr_next_req ),
.app_last_wr (app_last_wr ),
.app_rd_data (app_rd_data ),
.app_rd_valid (app_rd_valid )
.app_rd_valid (app_rd_valid ),
.app_last_rd (app_last_rd )
 
);

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