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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
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- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/rtl/core
- from Rev 64 to Rev 69
- ↔ Reverse comparison
Rev 64 → Rev 69
/sdrc_bank_fsm.v
100,8 → 100,8
input r2b_req, r2b_start, r2b_last, |
r2b_write, r2b_wrap; |
input [`SDR_REQ_ID_W-1:0] r2b_req_id; |
input [11:0] r2b_raddr; |
input [11:0] r2b_caddr; |
input [12:0] r2b_raddr; |
input [12:0] r2b_caddr; |
input [`REQ_BW-1:0] r2b_len; |
output b2r_ack; |
input sdr_dma_last; |
110,7 → 110,7
output b2x_req, b2x_start, b2x_last, |
tras_ok, b2x_wrap; |
output [`SDR_REQ_ID_W-1:0] b2x_id; |
output [11:0] b2x_addr; |
output [12:0] b2x_addr; |
output [`REQ_BW-1:0] b2x_len; |
output [1:0] b2x_cmd; |
input x2b_ack; |
121,7 → 121,7
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input [3:0] tras_delay, trp_delay, trcd_delay; |
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output [11:0] bank_row; |
output [12:0] bank_row; |
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/****************************************************************************/ |
// Internal Nets |
138,17 → 138,17
reg b2x_req, b2r_ack; |
wire [`SDR_REQ_ID_W-1:0] b2x_id; |
reg [`SDR_REQ_ID_W-1:0] l_id; |
reg [11:0] b2x_addr; |
reg [12:0] b2x_addr; |
reg [`REQ_BW-1:0] l_len; |
wire [`REQ_BW-1:0] b2x_len; |
reg [1:0] b2x_cmd_t; |
reg bank_valid; |
reg [11:0] bank_row; |
reg [12:0] bank_row; |
reg [3:0] tras_cntr, timer0; |
reg l_wrap, l_write; |
wire b2x_wrap; |
reg [11:0] l_raddr; |
reg [11:0] l_caddr; |
reg [12:0] l_raddr; |
reg [12:0] l_caddr; |
reg l_sdr_dma_last; |
reg bank_prech_page_closed; |
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268,7 → 268,7
b2x_req = 1'b0; |
b2x_cmd_t = 2'bx; |
b2r_ack = 1'b0; |
b2x_addr = 12'bx; |
b2x_addr = 13'bx; |
next_bank_st = bank_st; |
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case (bank_st) |
294,7 → 294,7
b2x_req = 1'b0; |
b2x_cmd_t = 2'bx; |
b2r_ack = 1'b0; |
b2x_addr = 12'bx; |
b2x_addr = 13'bx; |
next_bank_st = `BANK_IDLE; |
end // if (~r2b_req) |
else if (page_hit) begin |
309,7 → 309,7
b2x_req = tras_ok & x2b_pre_ok_t; |
b2x_cmd_t = `OP_PRE; |
b2r_ack = 1'b1; |
b2x_addr = r2b_raddr & 12'hBFF; // Dont want to pre all banks! |
b2x_addr = r2b_raddr & 13'hBFF; // Dont want to pre all banks! |
next_bank_st = (l_sdr_dma_last) ? `BANK_PRE : (x2b_ack) ? `BANK_ACT : `BANK_PRE; // bank was precharged on l_sdr_dma_last |
end // else: !if(page_hit) |
end |
319,7 → 319,7
b2x_req = tras_ok & x2b_pre_ok_t; |
b2x_cmd_t = `OP_PRE; |
b2r_ack = 1'b0; |
b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks! |
b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks! |
bank_prech_page_closed = 1'b0; |
next_bank_st = (x2b_ack) ? `BANK_ACT : `BANK_PRE; |
end // case: `BANK_PRE |
349,7 → 349,7
b2x_req = tras_ok & x2b_pre_ok_t; |
b2x_cmd_t = `OP_PRE; |
b2r_ack = 1'b0; |
b2x_addr = l_raddr & 12'hBFF; // Dont want to pre all banks! |
b2x_addr = l_raddr & 13'hBFF; // Dont want to pre all banks! |
bank_prech_page_closed = 1'b1; |
next_bank_st = (x2b_ack) ? `BANK_IDLE : `BANK_DMA_LAST_PRE; |
end // case: `BANK_DMA_LAST_PRE |
/sdrc_req_gen.v
11,19 → 11,19
cfg_colbits= 2'b00 |
Address[7:0] - Column Address |
Address[9:8] - Bank Address |
Address[21:10] - Row Address |
Address[22:10] - Row Address |
cfg_colbits= 2'b01 |
Address[8:0] - Column Address |
Address[10:9] - Bank Address |
Address[22:11] - Row Address |
Address[23:11] - Row Address |
cfg_colbits= 2'b10 |
Address[9:0] - Column Address |
Address[11:10] - Bank Address |
Address[23:12] - Row Address |
Address[24:12] - Row Address |
cfg_colbits= 2'b11 |
Address[10:0] - Column Address |
Address[12:11] - Bank Address |
Address[24:13] - Row Address |
Address[25:13] - Row Address |
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The SDRAMs are operated in 4 beat burst mode. |
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108,7 → 108,7
b2r_arb_ok |
); |
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parameter APP_AW = 25; // Application Address Width |
parameter APP_AW = 26; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
139,8 → 139,8
output r2b_wrap ; // 1 - Wrap the Address at the page boundary. |
output [`SDR_REQ_ID_W-1:0] r2b_req_id; |
output [1:0] r2b_ba ; // Bank Address |
output [11:0] r2b_raddr ; // Row Address |
output [11:0] r2b_caddr ; // Column Address |
output [12:0] r2b_raddr ; // Row Address |
output [12:0] r2b_caddr ; // Column Address |
output [`REQ_BW-1:0] r2b_len ; // Burst Length |
input b2r_ack ; // Request Ack |
input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command |
168,8 → 168,8
reg [12:0] max_r2b_len_r; |
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reg [1:0] r2b_ba; |
reg [11:0] r2b_raddr; |
reg [11:0] r2b_caddr; |
reg [12:0] r2b_raddr; |
reg [12:0] r2b_caddr; |
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reg [APP_AW-1:0] curr_sdr_addr ; |
wire [APP_AW-1:0] next_sdr_addr ; |
328,13 → 328,13
* 2'b10 - 10 Bit |
* 2'b11 - 11 Bits |
************************/ |
r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} : |
(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} : |
(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]}; |
r2b_caddr <= (cfg_colbits == 2'b00) ? {5'b0, map_address[7:0]} : |
(cfg_colbits == 2'b01) ? {4'b0, map_address[8:0]} : |
(cfg_colbits == 2'b10) ? {3'b0, map_address[9:0]} : {2'b0, map_address[10:0]}; |
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] : |
(cfg_colbits == 2'b01) ? map_address[22:11] : |
(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13]; |
r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[22:10] : |
(cfg_colbits == 2'b01) ? map_address[23:11] : |
(cfg_colbits == 2'b10) ? map_address[24:12] : map_address[25:13]; |
end |
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endmodule // sdr_req_gen |
/sdrc_xfr_ctl.v
140,7 → 140,7
b2x_wrap, r2x_idle, b2x_idle; |
input [`SDR_REQ_ID_W-1:0] b2x_id; |
input [1:0] b2x_ba; |
input [11:0] b2x_addr; |
input [12:0] b2x_addr; |
input [`REQ_BW-1:0] b2x_len; |
input [1:0] b2x_cmd; |
output x2b_ack; |
163,7 → 163,7
sdr_we_n; |
output [SDR_BW-1:0] sdr_dqm; |
output [1:0] sdr_ba; |
output [11:0] sdr_addr; |
output [12:0] sdr_addr; |
input [SDR_DW-1:0] sdr_din; |
output [SDR_DW-1:0] sdr_dout; |
output [SDR_BW-1:0] sdr_den_n; |
187,7 → 187,7
`define XFR_RDWT 2'b11 |
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reg [1:0] xfr_st, next_xfr_st; |
reg [11:0] xfr_caddr; |
reg [12:0] xfr_caddr; |
wire last_burst; |
wire x2a_rdstart, x2a_wrstart, x2a_rdlast, x2a_wrlast; |
reg l_start, l_last, l_wrap; |
195,13 → 195,13
reg [`SDR_REQ_ID_W-1:0] l_id; |
wire [1:0] xfr_ba; |
reg [1:0] l_ba; |
wire [11:0] xfr_addr; |
wire [12:0] xfr_addr; |
wire [`REQ_BW-1:0] xfr_len, next_xfr_len; |
reg [`REQ_BW-1:0] l_len; |
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reg mgmt_idle, mgmt_req; |
reg [3:0] mgmt_cmd; |
reg [11:0] mgmt_addr; |
reg [12:0] mgmt_addr; |
reg [1:0] mgmt_ba; |
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reg sel_mgmt, sel_b2x; |
302,7 → 302,7
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always @ (posedge clk) begin |
if (~reset_n) begin |
xfr_caddr <= 12'b0; |
xfr_caddr <= 13'b0; |
l_start <= 1'b0; |
l_last <= 1'b0; |
l_wrap <= 1'b0; |
545,7 → 545,7
sdr_we_n; |
reg [SDR_BW-1:0] sdr_dqm; |
reg [1:0] sdr_ba; |
reg [11:0] sdr_addr; |
reg [12:0] sdr_addr; |
reg [SDR_DW-1:0] sdr_dout; |
reg [SDR_BW-1:0] sdr_den_n; |
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645,7 → 645,7
mgmt_req = 1'b0; |
mgmt_cmd = `SDR_DESEL; |
mgmt_ba = 2'b0; |
mgmt_addr = 12'h400; // A10 = 1 => all banks |
mgmt_addr = 13'h400; // A10 = 1 => all banks |
ld_tmr0 = 1'b0; |
tmr0_d = 4'b0; |
dec_cntr1 = 1'b0; |
660,7 → 660,7
mgmt_req = 1'b1; |
mgmt_cmd = (precharge_ok) ? `SDR_PRECHARGE : `SDR_DESEL; |
mgmt_ba = 2'b0; |
mgmt_addr = 12'h400; // A10 = 1 => all banks |
mgmt_addr = 13'h400; // A10 = 1 => all banks |
ld_tmr0 = mgmt_ack; |
tmr0_d = trp_delay; |
ld_cntr1 = 1'b0; |
675,7 → 675,7
mgmt_req = 1'b1; |
mgmt_cmd = `SDR_DESEL; |
mgmt_ba = 2'b0; |
mgmt_addr = 12'h400; // A10 = 1 => all banks |
mgmt_addr = 13'h400; // A10 = 1 => all banks |
ld_tmr0 = 1'b0; |
tmr0_d = trp_delay; |
ld_cntr1 = 1'b0; |
690,7 → 690,7
mgmt_req = 1'b1; |
mgmt_cmd = `SDR_REFRESH; |
mgmt_ba = 2'b0; |
mgmt_addr = 12'h400; // A10 = 1 => all banks |
mgmt_addr = 13'h400; // A10 = 1 => all banks |
ld_tmr0 = mgmt_ack; |
tmr0_d = trcar_delay; |
dec_cntr1 = mgmt_ack; |
705,7 → 705,7
mgmt_req = 1'b1; |
mgmt_cmd = `SDR_DESEL; |
mgmt_ba = 2'b0; |
mgmt_addr = 12'h400; // A10 = 1 => all banks |
mgmt_addr = 13'h400; // A10 = 1 => all banks |
ld_tmr0 = 1'b0; |
tmr0_d = trcar_delay; |
dec_cntr1 = 1'b0; |
737,7 → 737,7
mgmt_req = 1'b1; |
mgmt_cmd = `SDR_DESEL; |
mgmt_ba = 2'bx; |
mgmt_addr = 12'bx; |
mgmt_addr = 13'bx; |
ld_tmr0 = 1'b0; |
tmr0_d = 4'h7; |
dec_cntr1 = 1'b0; |
752,7 → 752,7
mgmt_req = 1'b0; |
mgmt_cmd = `SDR_DESEL; |
mgmt_ba = 2'bx; |
mgmt_addr = 12'bx; |
mgmt_addr = 13'bx; |
ld_tmr0 = 1'b0; |
tmr0_d = 4'h7; |
dec_cntr1 = 1'b0; |
/sdrc_core.v
43,6 → 43,8
4 command of different bank. |
0.3 - 7th Feb 2012 |
Bug fix for parameter defination for request length has changed from 9 to 12 |
0.4 - 26th April 2013 |
SDRAM Address Bit is Extended by 12 bit to 13 bit to support higher SDRAM |
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Copyright (C) 2000 Authors and OPENCORES.ORG |
125,7 → 127,7
cfg_sdr_rfsh, |
cfg_sdr_rfmax); |
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parameter APP_AW = 25; // Application Address Width |
parameter APP_AW = 26; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
171,7 → 173,7
output sdr_we_n ; // SDRAM write enable |
output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask |
output [1:0] sdr_ba ; // SDRAM Bank Enable |
output [11:0] sdr_addr ; // SDRAM Address |
output [12:0] sdr_addr ; // SDRAM Address |
input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input |
output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output |
output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable |
186,7 → 188,7
input cfg_sdr_en ; // Enable SDRAM controller |
input [1:0] cfg_req_depth ; // Maximum Request accepted by SDRAM controller |
input [APP_RW-1:0] app_req_len ; // Application Burst Request length in 32 bit |
input [11:0] cfg_sdr_mode_reg ; |
input [12:0] cfg_sdr_mode_reg ; |
input [2:0] cfg_sdr_cas ; // SDRAM CAS Latency |
input [3:0] cfg_sdr_trcar_d ; // Auto-refresh period |
input [3:0] cfg_sdr_twr_d ; // Write recovery delay |
200,14 → 202,14
// SDR_REQ_GEN |
wire [`SDR_REQ_ID_W-1:0]r2b_req_id; |
wire [1:0] r2b_ba; |
wire [11:0] r2b_raddr; |
wire [11:0] r2b_caddr; |
wire [12:0] r2b_raddr; |
wire [12:0] r2b_caddr; |
wire [`REQ_BW-1:0] r2b_len; |
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// SDR BANK CTL |
wire [`SDR_REQ_ID_W-1:0]b2x_id; |
wire [1:0] b2x_ba; |
wire [11:0] b2x_addr; |
wire [12:0] b2x_addr; |
wire [`REQ_BW-1:0] b2x_len; |
wire [1:0] b2x_cmd; |
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218,7 → 220,7
wire sdr_cs_n, sdr_cke, sdr_ras_n, sdr_cas_n, sdr_we_n; |
wire [SDR_BW-1:0] sdr_dqm; |
wire [1:0] sdr_ba; |
wire [11:0] sdr_addr; |
wire [12:0] sdr_addr; |
wire [SDR_DW-1:0] sdr_dout; |
wire [SDR_DW-1:0] sdr_dout_int; |
wire [SDR_BW-1:0] sdr_den_n; |
/sdrc_bank_ctl.v
105,8 → 105,8
r2b_write, r2b_wrap; |
input [`SDR_REQ_ID_W-1:0] r2b_req_id; |
input [1:0] r2b_ba; |
input [11:0] r2b_raddr; |
input [11:0] r2b_caddr; |
input [12:0] r2b_raddr; |
input [12:0] r2b_caddr; |
input [`REQ_BW-1:0] r2b_len; |
output b2r_arb_ok, b2r_ack; |
input sdr_req_norm_dma_last; |
116,7 → 116,7
b2x_tras_ok, b2x_wrap; |
output [`SDR_REQ_ID_W-1:0] b2x_id; |
output [1:0] b2x_ba; |
output [11:0] b2x_addr; |
output [12:0] b2x_addr; |
output [`REQ_BW-1:0] b2x_len; |
output [1:0] b2x_cmd; |
input x2b_ack; |
135,7 → 135,7
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wire [3:0] r2i_req, i2r_ack, i2x_req, |
i2x_start, i2x_last, i2x_wrap, tras_ok; |
wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3; |
wire [12:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3; |
wire [`REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3; |
wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3; |
wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3; |
143,7 → 143,7
reg b2x_req; |
wire b2x_idle, b2x_start, b2x_last, b2x_wrap; |
wire [`SDR_REQ_ID_W-1:0] b2x_id; |
wire [11:0] b2x_addr; |
wire [12:0] b2x_addr; |
wire [`REQ_BW-1:0] b2x_len; |
wire [1:0] b2x_cmd; |
wire [3:0] x2i_ack; |
165,7 → 165,7
wire rank_fifo_wr, rank_fifo_rd; |
wire rank_fifo_full, rank_fifo_mt; |
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wire [11:0] bank0_row, bank1_row, bank2_row, bank3_row; |
wire [12:0] bank0_row, bank1_row, bank2_row, bank3_row; |
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assign b2x_tras_ok = &tras_ok; |
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562,7 → 562,7
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/* address for current xfr, debug only */ |
wire [11:0] cur_row = (xfr_bank_sel==3) ? bank3_row: |
wire [12:0] cur_row = (xfr_bank_sel==3) ? bank3_row: |
(xfr_bank_sel==2) ? bank2_row: |
(xfr_bank_sel==1) ? bank1_row: bank0_row; |
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