URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/rtl/core
- from Rev 71 to Rev 73
- ↔ Reverse comparison
Rev 71 → Rev 73
/sdrc_define.v
25,7 → 25,9
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`define ASIC 1'b1 |
`define FPGA 1'b0 |
`define TARGET_DESIGN `FPGA |
// Don't Enable FPGA mode, there is functional bug in handling Active to |
// Precharge timing |
`define TARGET_DESIGN `ASIC |
// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits |
`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width |
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/sdrc_req_gen.v
46,6 → 46,7
- Dinesh Annayya, dinesha@opencores.org |
Version : 0.0 - 8th Jan 2012 |
0.1 - 5th Feb 2012, column/row/bank address are register to improve the timing issue in FPGA synthesis |
0.2 - 19th Aug 2021, Address Mapping fix |
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187,11 → 188,11
req_len_int = req_len; |
end else if(sdr_width == 2'b01) begin // 16 Bit SDR Mode |
// Changed the address and length to match the 16 bit SDR Mode |
req_addr_int = {req_addr,1'b0}; |
req_addr_int = {1'b0,req_addr}; |
req_len_int = {req_len,1'b0}; |
end else begin // 8 Bit SDR Mode |
// Changed the address and length to match the 16 bit SDR Mode |
req_addr_int = {req_addr,2'b0}; |
req_addr_int = {1'b0,req_addr}; |
req_len_int = {req_len,2'b0}; |
end |
end |