URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/rtl/wb2sdrc
- from Rev 42 to Rev 55
- ↔ Reverse comparison
Rev 42 → Rev 55
/wb2sdrc.v
91,7 → 91,7
|
input wb_stb_i ; |
output wb_ack_o ; |
input [29:0] wb_addr_i ; |
input [24:0] wb_addr_i ; |
input wb_we_i ; // 1 - Write , 0 - Read |
input [dw-1:0] wb_dat_i ; |
input [dw/8-1:0] wb_sel_i ; // Byte enable |
120,7 → 120,7
input sdram_clk ; // sdram clock |
input sdram_resetn ; // sdram reset |
output sdr_req ; // SDRAM request |
output [29:0] sdr_req_addr ; // SDRAM Request Address |
output [24:0] sdr_req_addr ; // SDRAM Request Address |
output [bl-1:0] sdr_req_len ; |
output sdr_req_wr_n ; // 0 - Write, 1 -> Read |
input sdr_req_ack ; // SDRAM request Accepted |
213,7 → 213,7
// Application layer to SDRAM Controller |
// ------------------------------------------------------------------ |
// Address + Burst Length + W/R Request |
async_fifo #(.W(30+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo ( |
async_fifo #(.W(25+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo ( |
// Write Path Sys CLock Domain |
.wr_clk (wb_clk_i ), |
.wr_reset_n (!wb_rst_i ), |