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  • This comparison shows the changes necessary to convert path 
    /sdr_ctrl/trunk/rtl
    from Rev 51 to Rev 54
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Rev 51 → Rev 54

/core/sdrc_bank_fsm.v
96,8 → 96,6
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
 
input clk, reset_n;
 
107,7 → 105,7
input [`SDR_REQ_ID_W-1:0] r2b_req_id;
input [11:0] r2b_raddr;
input [11:0] r2b_caddr;
input [REQ_BW-1:0] r2b_len;
input [`REQ_BW-1:0] r2b_len;
output b2r_ack;
input sdr_dma_last;
 
116,7 → 114,7
tras_ok, b2x_wrap;
output [`SDR_REQ_ID_W-1:0] b2x_id;
output [11:0] b2x_addr;
output [REQ_BW-1:0] b2x_len;
output [`REQ_BW-1:0] b2x_len;
output [1:0] b2x_cmd;
input x2b_ack;
 
144,8 → 142,8
wire [`SDR_REQ_ID_W-1:0] b2x_id;
reg [`SDR_REQ_ID_W-1:0] l_id;
reg [11:0] b2x_addr;
reg [REQ_BW-1:0] l_len;
wire [REQ_BW-1:0] b2x_len;
reg [`REQ_BW-1:0] l_len;
wire [`REQ_BW-1:0] b2x_len;
reg [1:0] b2x_cmd_t;
reg bank_valid;
reg [11:0] bank_row;
/core/sdrc_req_gen.v
116,8 → 116,6
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
 
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
 
input clk ;
input reset_n ;
143,7 → 141,7
output [1:0] r2b_ba ; // Bank Address
output [11:0] r2b_raddr ; // Row Address
output [11:0] r2b_caddr ; // Column Address
output [REQ_BW-1:0] r2b_len ; // Burst Length
output [`REQ_BW-1:0] r2b_len ; // Burst Length
input b2r_ack ; // Request Ack
input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command
//
160,10 → 158,10
reg r2x_idle, req_ack, r2b_req, r2b_start,
r2b_write, req_idle, req_ld, lcl_wrap;
reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
reg [REQ_BW-1:0] lcl_req_len;
reg [`REQ_BW-1:0] lcl_req_len;
 
wire r2b_last, page_ovflw;
wire [REQ_BW-1:0] r2b_len, next_req_len;
wire [`REQ_BW-1:0] r2b_len, next_req_len;
wire [12:0] max_r2b_len;
reg [12:0] max_r2b_len_r;
 
225,9 → 223,9
 
assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
 
assign next_req_len = lcl_req_len - r2b_len;
assign next_req_len = lcl_req_len - max_r2b_len_r;
 
assign next_sdr_addr = curr_sdr_addr + r2b_len;
assign next_sdr_addr = curr_sdr_addr + max_r2b_len_r;
 
 
assign r2b_wrap = lcl_wrap;
/core/sdrc_xfr_ctl.v
135,8 → 135,6
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
 
 
input clk, reset_n;
147,7 → 145,7
input [`SDR_REQ_ID_W-1:0] b2x_id;
input [1:0] b2x_ba;
input [11:0] b2x_addr;
input [REQ_BW-1:0] b2x_len;
input [`REQ_BW-1:0] b2x_len;
input [1:0] b2x_cmd;
output x2b_ack;
 
202,8 → 200,8
wire [1:0] xfr_ba;
reg [1:0] l_ba;
wire [11:0] xfr_addr;
wire [REQ_BW-1:0] xfr_len, next_xfr_len;
reg [REQ_BW-1:0] l_len;
wire [`REQ_BW-1:0] xfr_len, next_xfr_len;
reg [`REQ_BW-1:0] l_len;
 
reg mgmt_idle, mgmt_req;
reg [3:0] mgmt_cmd;
282,11 → 280,11
 
assign wr_start = ld_xfr & b2x_write & b2x_start;
assign rd_last = rd_next & last_burst & ~|xfr_len[REQ_BW-1:1];
assign rd_last = rd_next & last_burst & ~|xfr_len[`REQ_BW-1:1];
 
//assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1];
 
assign wr_last = last_burst & ~|xfr_len[REQ_BW-1:1];
assign wr_last = last_burst & ~|xfr_len[`REQ_BW-1:1];
//assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba;
assign xfr_ba = (sel_mgmt) ? mgmt_ba :
/core/sdrc_core.v
133,8 → 133,6
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
 
//-----------------------------------------------
// Global Variable
204,13 → 202,13
wire [1:0] r2b_ba;
wire [11:0] r2b_raddr;
wire [11:0] r2b_caddr;
wire [REQ_BW-1:0] r2b_len;
wire [`REQ_BW-1:0] r2b_len;
 
// SDR BANK CTL
wire [`SDR_REQ_ID_W-1:0]b2x_id;
wire [1:0] b2x_ba;
wire [11:0] b2x_addr;
wire [REQ_BW-1:0] b2x_len;
wire [`REQ_BW-1:0] b2x_len;
wire [1:0] b2x_cmd;
 
// SDR_XFR_CTL
/core/sdrc_define.v
26,4 → 26,6
`define ASIC 1'b1
`define FPGA 1'b0
`define TARGET_DESIGN `FPGA
// 12 bit subtractor is not feasibile for FPGA, so changed to 6 bits
`define REQ_BW (`TARGET_DESIGN == `FPGA) ? 6 : 12 // Request Width
 
/core/sdrc_bank_ctl.v
100,8 → 100,6
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
// 12 bit subtractor is not feasibile for FPGA, so changed to 8 bits
parameter REQ_BW = (`TARGET_DESIGN == `FPGA) ? 8 : 12; // Request Width
input clk, reset_n;
 
input [1:0] a2b_req_depth;
113,7 → 111,7
input [1:0] r2b_ba;
input [11:0] r2b_raddr;
input [11:0] r2b_caddr;
input [REQ_BW-1:0] r2b_len;
input [`REQ_BW-1:0] r2b_len;
output b2r_arb_ok, b2r_ack;
input sdr_req_norm_dma_last;
 
123,7 → 121,7
output [`SDR_REQ_ID_W-1:0] b2x_id;
output [1:0] b2x_ba;
output [11:0] b2x_addr;
output [REQ_BW-1:0] b2x_len;
output [`REQ_BW-1:0] b2x_len;
output [1:0] b2x_cmd;
input x2b_ack;
 
142,7 → 140,7
wire [3:0] r2i_req, i2r_ack, i2x_req,
i2x_start, i2x_last, i2x_wrap, tras_ok;
wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3;
wire [REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
wire [`REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3;
wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3;
wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3;
 
150,7 → 148,7
wire b2x_idle, b2x_start, b2x_last, b2x_wrap;
wire [`SDR_REQ_ID_W-1:0] b2x_id;
wire [11:0] b2x_addr;
wire [REQ_BW-1:0] b2x_len;
wire [`REQ_BW-1:0] b2x_len;
wire [1:0] b2x_cmd;
wire [3:0] x2i_ack;
reg [1:0] b2x_ba;
231,34 → 229,33
(rank_ba[7:6] == 2'b10) ? i2x_req[2] & ~i2x_cmd2[1] :
i2x_req[3] & ~i2x_cmd3[1];
always @ (rank_req or rank_ba or xfr_ba or xfr_ba_last) begin
always @ (*) begin
b2x_req = 1'b0;
b2x_ba = xfr_ba;
 
if (rank_req[0]) begin
b2x_req = 1'b1;
b2x_ba = xfr_ba;
end // if (rank_req[0])
else if (rank_req[1]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[3:2];
end // if (rank_req[1])
else if (rank_req[2]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[5:4];
end // if (rank_req[2])
else if (rank_req[3]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[7:6];
end // if (rank_req[3])
else begin
b2x_req = 1'b0;
b2x_ba = 2'b00;
end // else: !if(rank_req[3])
end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
if(`TARGET_DESIGN == `ASIC) begin // Support Multiple Rank request only on ASIC
if (rank_req[0]) begin
b2x_req = 1'b1;
b2x_ba = xfr_ba;
end // if (rank_req[0])
else if (rank_req[1]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[3:2];
end // if (rank_req[1])
else if (rank_req[2]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[5:4];
end // if (rank_req[2])
else if (rank_req[3]) begin
b2x_req = 1'b1;
b2x_ba = rank_ba[7:6];
end // if (rank_req[3])
end else begin // If FPGA
if (rank_req[0]) begin
b2x_req = 1'b1;
end
end
end // always @ (rank_req or rank_fifo_mt or r2b_ba or rank_ba)
 
assign b2x_idle = rank_fifo_mt;
assign b2x_start = i2x_start[b2x_ba];

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