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URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

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  • This comparison shows the changes necessary to convert path 
    /sdr_ctrl/trunk/verif/tb
    from Rev 45 to Rev 46
    ↔ Reverse comparison
  •

Rev 45 → Rev 46

/tb_core.sv
76,6 → 76,7
reg [dw/8-1:0] app_wr_en_n ; // Write Enable, Active Low
wire app_rd_valid ; // Read Valid
wire app_last_rd ; // Last Read Valid
wire app_last_wr ; // Last Write Valid
wire [dw-1:0] app_rd_data ; // Read Data
 
//--------------------------------------------
135,7 → 136,6
/* Request from app */
.app_req (app_req ), // Transfer Request
.app_req_addr (app_req_addr ), // SDRAM Address
.app_req_addr_mask (29'h1FFF_FFFF ), // Address mask for queue wrap
.app_req_len (app_req_len ), // Burst Length (in 16 bit words)
.app_req_wrap (1'b0 ), // Wrap mode request (xfr_len = 4)
.app_req_wr_n (app_req_wr_n ), // 0 => Write request, 1 => read req
146,6 → 146,7
.app_wr_en_n (app_wr_en_n ),
.app_rd_data (app_rd_data ),
.app_last_rd (app_last_rd ),
.app_last_wr (app_last_wr ),
.app_rd_valid (app_rd_valid ),
.app_wr_next_req (app_wr_next_req ),
.app_req_dma_last (app_req ),
270,28 → 271,90
 
#1000;
burst_write(32'h4_0000,6'h4);
$display("-------------------------------------- ");
$display(" Case-1: Single Write/Read Case ");
$display("-------------------------------------- ");
 
burst_write(32'h4_0000,8'h4);
#1000;
burst_read();
 
#1000;
burst_write(32'h0040_0000,6'h5);
#1000;
// Repeat one more time to analysis the
// SDRAM state change for same col/row address
$display("-------------------------------------- ");
$display(" Case-2: Repeat same transfer once again ");
$display("----------------------------------------");
burst_write(32'h4_0000,8'h4);
burst_read();
burst_write(32'h0040_0000,8'h5);
burst_read();
 
// 4 Write & 4 Read
burst_write(32'h4_0000,6'h4);
burst_write(32'h5_0000,6'h5);
burst_write(32'h6_0000,6'h6);
burst_write(32'h7_0000,6'h7);
$display("----------------------------------------");
$display(" Case-3 Create a Page Cross Over ");
$display("----------------------------------------");
burst_write(32'h4_0FFC,8'h8);
burst_write(32'h0040_0FF8,8'hF);
burst_read();
burst_read();
 
$display("----------------------------------------");
$display(" Case:4 4 Write & 4 Read ");
$display("----------------------------------------");
burst_write(32'h4_0000,8'h4);
burst_write(32'h5_0000,8'h5);
burst_write(32'h6_0000,8'h6);
burst_write(32'h7_0000,8'h7);
burst_read();
burst_read();
burst_read();
burst_read();
 
$display("---------------------------------------");
$display(" Case:5 16 Write & 16 Read With Different Bank and Row ");
$display("---------------------------------------");
//----------------------------------------
// Address Decodeing:
// with cfg_col bit configured as: 00
// <12 Bit Row> <2 Bit Bank> <8 Bit Column> <2'b00>
//
burst_write({12'h000,2'b00,8'h00,2'b00},8'h4); // Row: 0 Bank : 0
burst_write({12'h000,2'b01,8'h00,2'b00},8'h5); // Row: 0 Bank : 1
burst_write({12'h000,2'b10,8'h00,2'b00},8'h6); // Row: 0 Bank : 2
burst_write({12'h000,2'b11,8'h00,2'b00},8'h7); // Row: 0 Bank : 3
burst_write({12'h001,2'b00,8'h00,2'b00},8'h4); // Row: 1 Bank : 0
burst_write({12'h001,2'b01,8'h00,2'b00},8'h5); // Row: 1 Bank : 1
burst_write({12'h001,2'b10,8'h00,2'b00},8'h6); // Row: 1 Bank : 2
burst_write({12'h001,2'b11,8'h00,2'b00},8'h7); // Row: 1 Bank : 3
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
 
// 2 write and 2 read random
burst_write({12'h002,2'b00,8'h00,2'b00},8'h4); // Row: 2 Bank : 0
burst_write({12'h002,2'b01,8'h00,2'b00},8'h5); // Row: 2 Bank : 1
burst_write({12'h002,2'b10,8'h00,2'b00},8'h6); // Row: 2 Bank : 2
burst_write({12'h002,2'b11,8'h00,2'b00},8'h7); // Row: 2 Bank : 3
burst_write({12'h003,2'b00,8'h00,2'b00},8'h4); // Row: 3 Bank : 0
burst_write({12'h003,2'b01,8'h00,2'b00},8'h5); // Row: 3 Bank : 1
burst_write({12'h003,2'b10,8'h00,2'b00},8'h6); // Row: 3 Bank : 2
burst_write({12'h003,2'b11,8'h00,2'b00},8'h7); // Row: 3 Bank : 3
 
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
 
$display("---------------------------------------------------");
$display(" Case: 6 Random 2 write and 2 read random");
$display("---------------------------------------------------");
for(k=0; k < 20; k++) begin
StartAddr = $random & 32'h003FFFFF;
burst_write(StartAddr,($random & 8'h3f)+1);
/tb_top.sv
253,8 → 253,11
wait(u_dut.sdr_init_done == 1);
 
#1000;
 
$display("-------------------------------------- ");
$display(" Case-1: Single Write/Read Case ");
$display("-------------------------------------- ");
 
burst_write(32'h4_0000,8'h4);
#1000;
burst_read();
261,15 → 264,25
 
// Repeat one more time to analysis the
// SDRAM state change for same col/row address
$display("-------------------------------------- ");
$display(" Case-2: Repeat same transfer once again ");
$display("----------------------------------------");
burst_write(32'h4_0000,8'h4);
#1000;
#1000;
burst_read();
burst_write(32'h0040_0000,8'h5);
burst_read();
 
#1000;
$display("----------------------------------------");
$display(" Case-3 Create a Page Cross Over ");
$display("----------------------------------------");
burst_write(32'h4_0FFC,8'h8);
burst_write(32'h0040_0FF8,8'hF);
burst_read();
burst_read();
 
// 4 Write & 4 Read
$display("----------------------------------------");
$display(" Case:4 4 Write & 4 Read ");
$display("----------------------------------------");
burst_write(32'h4_0000,8'h4);
burst_write(32'h5_0000,8'h5);
burst_write(32'h6_0000,8'h6);
279,9 → 292,52
burst_read();
burst_read();
 
$display("---------------------------------------");
$display(" Case:5 16 Write & 16 Read With Different Bank and Row ");
$display("---------------------------------------");
//----------------------------------------
// Address Decodeing:
// with cfg_col bit configured as: 00
// <12 Bit Row> <2 Bit Bank> <8 Bit Column> <2'b00>
//
burst_write({12'h000,2'b00,8'h00,2'b00},8'h4); // Row: 0 Bank : 0
burst_write({12'h000,2'b01,8'h00,2'b00},8'h5); // Row: 0 Bank : 1
burst_write({12'h000,2'b10,8'h00,2'b00},8'h6); // Row: 0 Bank : 2
burst_write({12'h000,2'b11,8'h00,2'b00},8'h7); // Row: 0 Bank : 3
burst_write({12'h001,2'b00,8'h00,2'b00},8'h4); // Row: 1 Bank : 0
burst_write({12'h001,2'b01,8'h00,2'b00},8'h5); // Row: 1 Bank : 1
burst_write({12'h001,2'b10,8'h00,2'b00},8'h6); // Row: 1 Bank : 2
burst_write({12'h001,2'b11,8'h00,2'b00},8'h7); // Row: 1 Bank : 3
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
 
// 2 write and 2 read random
burst_write({12'h002,2'b00,8'h00,2'b00},8'h4); // Row: 2 Bank : 0
burst_write({12'h002,2'b01,8'h00,2'b00},8'h5); // Row: 2 Bank : 1
burst_write({12'h002,2'b10,8'h00,2'b00},8'h6); // Row: 2 Bank : 2
burst_write({12'h002,2'b11,8'h00,2'b00},8'h7); // Row: 2 Bank : 3
burst_write({12'h003,2'b00,8'h00,2'b00},8'h4); // Row: 3 Bank : 0
burst_write({12'h003,2'b01,8'h00,2'b00},8'h5); // Row: 3 Bank : 1
burst_write({12'h003,2'b10,8'h00,2'b00},8'h6); // Row: 3 Bank : 2
burst_write({12'h003,2'b11,8'h00,2'b00},8'h7); // Row: 3 Bank : 3
 
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
burst_read();
 
$display("---------------------------------------------------");
$display(" Case: 6 Random 2 write and 2 read random");
$display("---------------------------------------------------");
for(k=0; k < 20; k++) begin
StartAddr = $random & 32'h003FFFFF;
burst_write(StartAddr,($random & 8'h3f)+1);

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