URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/verif
- from Rev 33 to Rev 37
- ↔ Reverse comparison
Rev 33 → Rev 37
/log/top_SDR_16BIT_basic_test1.log
1131,5 → 1131,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 73460 ns Iteration: 0 Instance: /tb_top |
/log/top_sdr8_sim.log
1465,7 → 1465,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 77860 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/log/top_SDR_8BIT_basic_test1.log
1438,5 → 1438,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 77860 ns Iteration: 0 Instance: /tb_top |
/log/top_sdr32_sim.log
52,7 → 52,7
# Loading work.sdrc_xfr_ctl |
# Loading work.sdrc_bs_convert |
# Loading work.mt48lc2m32b2 |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# Region: /tb_top/u_sdram32 |
# do run.do |
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh |
760,7 → 760,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 71260 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/log/top_sdr16_sim.log
1158,7 → 1158,7
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 73460 ns Iteration: 0 Instance: /tb_top |
### test 1: basic_test1 --> PASSED |
########################################### |
/log/top_SDR_32BIT_basic_test1.log
25,7 → 25,7
# Loading work.sdrc_xfr_ctl |
# Loading work.sdrc_bs_convert |
# Loading work.mt48lc2m32b2 |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42). |
# Region: /tb_top/u_sdram32 |
# do run.do |
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh |
733,5 → 733,5
############################### |
# STATUS: SDRAM Write/Read TEST PASSED |
############################### |
# ** Note: $finish : ../tb/tb_top.sv(304) |
# ** Note: $finish : ../tb/tb_top.sv(283) |
# Time: 71260 ns Iteration: 0 Instance: /tb_top |
/tb/tb_top.sv
89,21 → 89,12
|
`ifdef SDR_32BIT |
wire [31:0] Dq ; // SDRAM Read/Write Data Bus |
wire [31:0] sdr_dout ; // SDRAM Data Out |
wire [31:0] pad_sdr_din ; // SDRAM Data Input |
wire [3:0] sdr_den_n ; // SDRAM Data Enable |
wire [3:0] sdr_dqm ; // SDRAM DATA Mask |
`elsif SDR_16BIT |
wire [15:0] Dq ; // SDRAM Read/Write Data Bus |
wire [15:0] sdr_dout ; // SDRAM Data Out |
wire [15:0] pad_sdr_din ; // SDRAM Data Input |
wire [1:0] sdr_den_n ; // SDRAM Data Enable |
wire [1:0] sdr_dqm ; // SDRAM DATA Mask |
`else |
wire [7:0] Dq ; // SDRAM Read/Write Data Bus |
wire [7:0] sdr_dout ; // SDRAM Data Out |
wire [7:0] pad_sdr_din ; // SDRAM Data Input |
wire [0:0] sdr_den_n ; // SDRAM Data Enable |
wire [0:0] sdr_dqm ; // SDRAM DATA Mask |
`endif |
|
113,7 → 104,6
|
// to fix the sdram interface timing issue |
wire #(2.0) sdram_clk_d = sdram_clk; |
wire #(1.0) sdram_pad_clk = sdram_clk_d; |
|
`ifdef SDR_32BIT |
|
149,7 → 139,6
|
/* Interface to SDRAMs */ |
.sdram_clk (sdram_clk ), |
.sdram_pad_clk (sdram_pad_clk ), |
.sdram_resetn (RESETN ), |
.sdr_cs_n (sdr_cs_n ), |
.sdr_cke (sdr_cke ), |
159,9 → 148,7
.sdr_dqm (sdr_dqm ), |
.sdr_ba (sdr_ba ), |
.sdr_addr (sdr_addr ), |
.pad_sdr_din (Dq ), |
.sdr_dout (sdr_dout ), |
.sdr_den_n (sdr_den_n ), |
.sdr_dq (Dq ), |
|
/* Parameters */ |
.sdr_init_done (sdr_init_done ), |
181,10 → 168,6
|
|
`ifdef SDR_32BIT |
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ; |
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ; |
assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ; |
assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ; |
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 ( |
.Dq (Dq ) , |
.Addr (sdr_addr ), |
200,9 → 183,6
|
`elsif SDR_16BIT |
|
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ; |
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ; |
|
IS42VM16400K u_sdram16 ( |
.dq (Dq ), |
.addr (sdr_addr ), |
217,7 → 197,6
); |
`else |
|
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ; |
|
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 ( |
.Dq (Dq ) , |