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    /sdr_ctrl/trunk
    from Rev 36 to Rev 37
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Rev 36 → Rev 37

/rtl/top/sdrc_top.v
23,10 → 23,12
nothing
Author(s): Dinesh Annayya, dinesha@opencores.org
Version : 1.0 - 8th Jan 2012
Version : 0.0 - 8th Jan 2012
Initial version with 16/32 Bit SDRAM Support
: 1.1 - 24th Jan 2012
: 0.1 - 24th Jan 2012
8 Bit SDRAM Support is added
0.2 - 31st Jan 2012
sdram_dq and sdram_pad_clk are internally generated
 
Copyright (C) 2000 Authors and OPENCORES.ORG
55,7 → 57,7
*******************************************************************/
 
 
`include "sdrc.def"
`include "sdrc_define.v"
module sdrc_top
(
sdr_width ,
78,7 → 80,6
/* Interface to SDRAMs */
sdram_clk ,
sdram_pad_clk ,
sdram_resetn ,
sdr_cs_n ,
sdr_cke ,
88,9 → 89,7
sdr_dqm ,
sdr_ba ,
sdr_addr ,
pad_sdr_din ,
sdr_dout ,
sdr_den_n ,
sdr_dq ,
/* Parameters */
sdr_init_done ,
123,7 → 122,6
// Global Variable
// ----------------------------------------------
input sdram_clk ; // SDRAM Clock
input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data
input sdram_resetn ; // Reset Signal
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address,
156,9 → 154,7
output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
output [1:0] sdr_ba ; // SDRAM Bank Enable
output [11:0] sdr_addr ; // SDRAM Address
input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output
 
//------------------------------------------------
// Configuration Parameter
192,6 → 188,22
wire [dw-1:0] app_wr_data ; // sdr write data
wire [dw-1:0] app_rd_data ; // sdr read data
 
/****************************************
* These logic has to be implemented using Pads
* **************************************/
wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
 
 
assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};
assign pad_sdr_din = sdr_dq;
 
// sdram pad clock is routed back through pad
// SDRAM Clock from Pad, used for registering Read Data
wire #(1.0) sdram_pad_clk = sdram_clk;
 
/************** Ends Here **************************/
wb2sdrc u_wb2sdrc (
// WB bus
.wb_rst_i (wb_rst_i ) ,
/rtl/wb2sdrc/wb2sdrc.v
231,6 → 231,7
$display("ERROR:%m COMMAND FIFO WRITE OVERFLOW");
end
end
// synopsys translate_on
// synopsys translate_off
always @(posedge sdram_clk) begin
if (cmdfifo_empty == 1'b1 && cmdfifo_rd == 1'b1) begin
/rtl/core/sdrc.def File deleted
rtl/core/sdrc.def Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: rtl/core/sdrc_bank_fsm.v =================================================================== --- rtl/core/sdrc_bank_fsm.v (revision 36) +++ rtl/core/sdrc_bank_fsm.v (revision 37) @@ -44,7 +44,7 @@ *******************************************************************/ -`include "sdrc.def" +`include "sdrc_define.v" module sdrc_bank_fsm (clk, reset_n,
/rtl/core/sdrc_req_gen.v
64,7 → 64,7
*******************************************************************/
 
`include "sdrc.def"
`include "sdrc_define.v"
 
module sdrc_req_gen (clk,
reset_n,
/rtl/core/sdrc_xfr_ctl.v
61,7 → 61,7
*******************************************************************/
 
`include "sdrc.def"
`include "sdrc_define.v"
 
module sdrc_xfr_ctl (clk,
reset_n,
547,7 → 547,7
sdr_cas_n <= 1'b1;
sdr_we_n <= 1'b1;
sdr_dqm <= {SDR_BW{1'b1}};
sdr_den_n <= {SDR_DW{1'b1}};
sdr_den_n <= {SDR_BW{1'b1}};
end // if (~reset_n)
else begin
sdr_cs_n <= xfr_cmd[3];
/rtl/core/sdrc_bs_convert.v
44,7 → 44,7
*******************************************************************/
 
`include "sdrc.def"
`include "sdrc_define.v"
module sdrc_bs_convert (
clk,
reset_n,
/rtl/core/sdrc_core.v
66,7 → 66,7
*******************************************************************/
 
 
`include "sdrc.def"
`include "sdrc_define.v"
module sdrc_core
(
clk,
/rtl/core/sdrc_define.v
0,0 → 1,27
 
`define SDR_REQ_ID_W 4
 
`define SDR_RFSH_TIMER_W 12
`define SDR_RFSH_ROW_CNT_W 3
 
// B2X Command
 
`define OP_PRE 2'b00
`define OP_ACT 2'b01
`define OP_RD 2'b10
`define OP_WR 2'b11
 
// SDRAM Commands (CS_N, RAS_N, CAS_N, WE_N)
 
`define SDR_DESEL 4'b1111
`define SDR_NOOP 4'b0111
`define SDR_ACTIVATE 4'b0011
`define SDR_READ 4'b0101
`define SDR_WRITE 4'b0100
`define SDR_BT 4'b0110
`define SDR_PRECHARGE 4'b0010
`define SDR_REFRESH 4'b0001
`define SDR_MODE 4'b0000
 
 
 
rtl/core/sdrc_define.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/core/sdrc_bank_ctl.v =================================================================== --- rtl/core/sdrc_bank_ctl.v (revision 36) +++ rtl/core/sdrc_bank_ctl.v (revision 37) @@ -44,7 +44,7 @@ *******************************************************************/ -`include "sdrc.def" +`include "sdrc_define.v" module sdrc_bank_ctl (clk, reset_n,
/verif/log/top_SDR_16BIT_basic_test1.log
1131,5 → 1131,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 73460 ns Iteration: 0 Instance: /tb_top
/verif/log/top_sdr8_sim.log
1465,7 → 1465,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 77860 ns Iteration: 0 Instance: /tb_top
### test 1: basic_test1 --> PASSED
###########################################
/verif/log/top_SDR_8BIT_basic_test1.log
1438,5 → 1438,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 77860 ns Iteration: 0 Instance: /tb_top
/verif/log/top_sdr32_sim.log
52,7 → 52,7
# Loading work.sdrc_xfr_ctl
# Loading work.sdrc_bs_convert
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# Region: /tb_top/u_sdram32
# do run.do
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh
760,7 → 760,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 71260 ns Iteration: 0 Instance: /tb_top
### test 1: basic_test1 --> PASSED
###########################################
/verif/log/top_sdr16_sim.log
1158,7 → 1158,7
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 73460 ns Iteration: 0 Instance: /tb_top
### test 1: basic_test1 --> PASSED
###########################################
/verif/log/top_SDR_32BIT_basic_test1.log
25,7 → 25,7
# Loading work.sdrc_xfr_ctl
# Loading work.sdrc_bs_convert
# Loading work.mt48lc2m32b2
# ** Warning: (vsim-3015) ../tb/tb_top.sv(199): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# ** Warning: (vsim-3015) ../tb/tb_top.sv(182): [PCDPC] - Port size (11 or 11) does not match connection size (12) for port 'Addr'. The port definition is at: ../model/mt48lc2m32b2.v(42).
# Region: /tb_top/u_sdram32
# do run.do
# tb_top.u_sdram32 : at time 10212.0 ns AREF : Auto Refresh
733,5 → 733,5
###############################
# STATUS: SDRAM Write/Read TEST PASSED
###############################
# ** Note: $finish : ../tb/tb_top.sv(304)
# ** Note: $finish : ../tb/tb_top.sv(283)
# Time: 71260 ns Iteration: 0 Instance: /tb_top
/verif/tb/tb_top.sv
89,21 → 89,12
 
`ifdef SDR_32BIT
wire [31:0] Dq ; // SDRAM Read/Write Data Bus
wire [31:0] sdr_dout ; // SDRAM Data Out
wire [31:0] pad_sdr_din ; // SDRAM Data Input
wire [3:0] sdr_den_n ; // SDRAM Data Enable
wire [3:0] sdr_dqm ; // SDRAM DATA Mask
`elsif SDR_16BIT
wire [15:0] Dq ; // SDRAM Read/Write Data Bus
wire [15:0] sdr_dout ; // SDRAM Data Out
wire [15:0] pad_sdr_din ; // SDRAM Data Input
wire [1:0] sdr_den_n ; // SDRAM Data Enable
wire [1:0] sdr_dqm ; // SDRAM DATA Mask
`else
wire [7:0] Dq ; // SDRAM Read/Write Data Bus
wire [7:0] sdr_dout ; // SDRAM Data Out
wire [7:0] pad_sdr_din ; // SDRAM Data Input
wire [0:0] sdr_den_n ; // SDRAM Data Enable
wire [0:0] sdr_dqm ; // SDRAM DATA Mask
`endif
 
113,7 → 104,6
 
// to fix the sdram interface timing issue
wire #(2.0) sdram_clk_d = sdram_clk;
wire #(1.0) sdram_pad_clk = sdram_clk_d;
 
`ifdef SDR_32BIT
 
149,7 → 139,6
 
/* Interface to SDRAMs */
.sdram_clk (sdram_clk ),
.sdram_pad_clk (sdram_pad_clk ),
.sdram_resetn (RESETN ),
.sdr_cs_n (sdr_cs_n ),
.sdr_cke (sdr_cke ),
159,9 → 148,7
.sdr_dqm (sdr_dqm ),
.sdr_ba (sdr_ba ),
.sdr_addr (sdr_addr ),
.pad_sdr_din (Dq ),
.sdr_dout (sdr_dout ),
.sdr_den_n (sdr_den_n ),
.sdr_dq (Dq ),
 
/* Parameters */
.sdr_init_done (sdr_init_done ),
181,10 → 168,6
 
 
`ifdef SDR_32BIT
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
assign Dq[23:16] = (sdr_den_n[2] == 1'b0) ? sdr_dout[23:16] : 8'hZZ;
assign Dq[31:24] = (sdr_den_n[3] == 1'b0) ? sdr_dout[31:24] : 8'hZZ;
mt48lc2m32b2 #(.data_bits(32)) u_sdram32 (
.Dq (Dq ) ,
.Addr (sdr_addr ),
200,9 → 183,6
 
`elsif SDR_16BIT
 
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
assign Dq[15:8] = (sdr_den_n[1] == 1'b0) ? sdr_dout[15:8] : 8'hZZ;
 
IS42VM16400K u_sdram16 (
.dq (Dq ),
.addr (sdr_addr ),
217,7 → 197,6
);
`else
 
assign Dq[7:0] = (sdr_den_n[0] == 1'b0) ? sdr_dout[7:0] : 8'hZZ;
 
mt48lc8m8a2 #(.data_bits(8)) u_sdram8 (
.Dq (Dq ) ,

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