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  • This comparison shows the changes necessary to convert path 
    /sdr_ctrl/trunk
    from Rev 54 to Rev 55
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  •

Rev 54 → Rev 55

/rtl/top/sdrc_top.v
106,7 → 106,7
cfg_sdr_rfmax
);
parameter APP_AW = 30; // Application Address Width
parameter APP_AW = 25; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
135,7 → 135,7
 
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input [25:0] wb_addr_i ;
input wb_we_i ; // 1 - Write, 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0] wb_sel_i ; // Byte enable
176,7 → 176,7
// SDRAM controller Interface
//--------------------------------------------
wire app_req ; // SDRAM request
wire [29:0] app_req_addr ; // SDRAM Request Address
wire [24:0] app_req_addr ; // SDRAM Request Address
wire [bl-1:0] app_req_len ;
wire app_req_wr_n ; // 0 - Write, 1 -> Read
wire app_req_ack ; // SDRAM request Accepted
/rtl/wb2sdrc/wb2sdrc.v
91,7 → 91,7
 
input wb_stb_i ;
output wb_ack_o ;
input [29:0] wb_addr_i ;
input [24:0] wb_addr_i ;
input wb_we_i ; // 1 - Write , 0 - Read
input [dw-1:0] wb_dat_i ;
input [dw/8-1:0] wb_sel_i ; // Byte enable
120,7 → 120,7
input sdram_clk ; // sdram clock
input sdram_resetn ; // sdram reset
output sdr_req ; // SDRAM request
output [29:0] sdr_req_addr ; // SDRAM Request Address
output [24:0] sdr_req_addr ; // SDRAM Request Address
output [bl-1:0] sdr_req_len ;
output sdr_req_wr_n ; // 0 - Write, 1 -> Read
input sdr_req_ack ; // SDRAM request Accepted
213,7 → 213,7
// Application layer to SDRAM Controller
// ------------------------------------------------------------------
// Address + Burst Length + W/R Request
async_fifo #(.W(30+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo (
async_fifo #(.W(25+bl+1),.DP(4),.WR_FAST(1'b0), .RD_FAST(1'b1)) u_cmdfifo (
// Write Path Sys CLock Domain
.wr_clk (wb_clk_i ),
.wr_reset_n (!wb_rst_i ),
/rtl/core/sdrc_bank_fsm.v
90,9 → 90,6
trp_delay, // Precharge to active delay
trcd_delay); // Active to R/W delay
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
222,7 → 219,7
 
always @ (posedge clk) begin
 
bank_row <= (activate_bank) ? b2x_addr : bank_row;
bank_row <= (bank_st == `BANK_ACT) ? b2x_addr : bank_row;
 
if (~reset_n) begin
l_start <= 1'b0;
/rtl/core/sdrc_req_gen.v
108,7 → 108,7
b2r_arb_ok
);
 
parameter APP_AW = 30; // Application Address Width
parameter APP_AW = 25; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
151,10 → 151,11
/****************************************************************************/
// Internal Nets
 
`define REQ_IDLE 1'b0
`define REQ_ACTIVE 1'b1
`define REQ_IDLE 2'b00
`define REQ_ACTIVE 2'b01
`define REQ_PAGE_WRAP 2'b10
 
reg req_st, next_req_st;
reg [1:0] req_st, next_req_st;
reg r2x_idle, req_ack, r2b_req, r2b_start,
r2b_write, req_idle, req_ld, lcl_wrap;
reg [`SDR_REQ_ID_W-1:0] r2b_req_id;
161,6 → 162,7
reg [`REQ_BW-1:0] lcl_req_len;
 
wire r2b_last, page_ovflw;
reg page_ovflw_r;
wire [`REQ_BW-1:0] r2b_len, next_req_len;
wire [12:0] max_r2b_len;
reg [12:0] max_r2b_len_r;
219,24 → 221,27
//
// Note: With Wrap = 0, each request from Application layer will be spilited into two request,
// if the current burst cross the page boundary.
assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len_r) ? ~lcl_wrap : 1'b0;
assign page_ovflw = ({1'b0, req_len_int} > max_r2b_len) ? ~r2b_wrap : 1'b0;
 
assign r2b_len = (page_ovflw) ? max_r2b_len_r : lcl_req_len;
assign r2b_len = r2b_start ? ((page_ovflw_r) ? max_r2b_len_r : lcl_req_len) :
lcl_req_len;
 
assign next_req_len = lcl_req_len - max_r2b_len_r;
assign next_req_len = lcl_req_len - r2b_len;
 
assign next_sdr_addr = curr_sdr_addr + max_r2b_len_r;
assign next_sdr_addr = curr_sdr_addr + r2b_len;
 
 
assign r2b_wrap = lcl_wrap;
 
assign r2b_last = ~page_ovflw;
assign r2b_last = (r2b_start & !page_ovflw_r) | (req_st == `REQ_PAGE_WRAP);
//
//
//
always @ (posedge clk) begin
 
max_r2b_len_r <= max_r2b_len;
page_ovflw_r <= (req_ack) ? page_ovflw: 'h0;
 
max_r2b_len_r <= (req_ack) ? max_r2b_len: 'h0;
r2b_start <= (req_ack) ? 1'b1 :
(b2r_ack) ? 1'b0 : r2b_start;
 
255,6 → 260,12
end // always @ (posedge clk)
always @ (*) begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = 1'b0;
r2b_req = 1'b0;
next_req_st = `REQ_IDLE;
 
case (req_st) // synopsys full_case parallel_case
 
273,8 → 284,16
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1; // req_gen to bank_req
next_req_st = (b2r_ack & r2b_last) ? `REQ_IDLE : `REQ_ACTIVE;
next_req_st = (b2r_ack ) ? ((page_ovflw_r) ? `REQ_PAGE_WRAP :`REQ_IDLE) : `REQ_ACTIVE;
end // case: `REQ_ACTIVE
`REQ_PAGE_WRAP : begin
r2x_idle = 1'b0;
req_idle = 1'b0;
req_ack = 1'b0;
req_ld = b2r_ack;
r2b_req = 1'b1; // req_gen to bank_req
next_req_st = (b2r_ack) ? `REQ_IDLE : `REQ_PAGE_WRAP;
end // case: `REQ_ACTIVE
 
endcase // case(req_st)
 
/rtl/core/sdrc_xfr_ctl.v
129,10 → 129,6
rfsh_time, // time per row (31.25 or 15.6125 uS)
rfsh_rmax); // Number of rows to rfsh at a time (<120uS)
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
 
/rtl/core/sdrc_core.v
125,7 → 125,7
cfg_sdr_rfsh,
cfg_sdr_rfmax);
parameter APP_AW = 30; // Application Address Width
parameter APP_AW = 25; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
parameter APP_RW = 9; // Application Request Width
/rtl/core/sdrc_bank_ctl.v
94,10 → 94,6
trp_delay, // Precharge to active delay
trcd_delay); // Active to R/W delay
parameter APP_AW = 30; // Application Address Width
parameter APP_DW = 32; // Application Data Width
parameter APP_BW = 4; // Application Byte Width
 
parameter SDR_DW = 16; // SDR Data Width
parameter SDR_BW = 2; // SDR Byte Width
input clk, reset_n;

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