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/trunk/bench/cpp/sdspisim.h
0,0 → 1,89
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: sdspisim.h |
// |
// Project: Wishbone Controlled SD-Card Controller over SPI port |
// |
// Purpose: This library simulates the operation of a SPI commanded SD-Card, |
// such as might be found on a XuLA2-LX25 board made by xess.com. |
// |
// This simulator is for testing use in a Verilator/C++ environment, where |
// it would be used in place of the actual hardware. |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
#ifndef SDSPISIM_H |
#define SDSPISIM_H |
|
typedef enum eRESET_STATES { |
SDSPI_POWERUP_RESET, |
SDSPI_CMD0_IDLE, |
SDSPI_RCVD_CMD8, |
SDSPI_RCVD_ACMD41, |
SDSPI_RESET_COMPLETE, |
SDSPI_IN_OPERATION |
} RESET_STATES; |
|
#define SDSPI_RSPLEN 8 |
#define SDSPI_MAXBLKLEN (1+2048+2) |
#define SDSPI_CSDLEN (16) |
#define SDSPI_CIDLEN (16) |
class SDSPISIM { |
FILE *m_dev; |
unsigned long m_devblocks; |
|
int m_last_sck, m_delay, m_mosi; |
bool m_busy, m_debug, m_block_address, m_altcmd_flag, |
m_syncd, m_host_supports_high_capacity, m_reading_data, |
m_have_token; |
|
RESET_STATES m_reset_state; |
|
int m_cmdidx, m_bitpos, m_rspidx, m_rspdly, m_blkdly, |
m_blklen, m_blkidx, m_last_miso, m_powerup_busy, |
m_rxloc; |
char m_cmdbuf[8], m_dat_out, m_dat_in; |
char m_rspbuf[SDSPI_RSPLEN]; |
char m_block_buf[SDSPI_MAXBLKLEN]; |
char m_csd[SDSPI_CSDLEN], m_cid[SDSPI_CIDLEN]; |
|
public: |
SDSPISIM(void); |
void load(const char *fname); |
void debug(const bool dbg) { m_debug = dbg; } |
bool debug(void) const { return m_debug; } |
int operator()(const int csn, const int sck, const int dat); |
unsigned cmdcrc(int ln, char *buf) const; |
bool check_cmdcrc(char *buf) const; |
unsigned blockcrc(int ln, char *buf) const; |
void add_block_crc(int ln, char *buf) const; |
}; |
|
#endif |
/trunk/bench/cpp/sdspisim.cpp
0,0 → 1,511
/////////////////////////////////////////////////////////////////////////// |
// |
// |
// Filename: sdspisim.cpp |
// |
// Project: Wishbone Controlled SD-Card Controller over SPI port |
// |
// Purpose: This library simulates the operation of a SPI commanded SD-Card, |
// such as might be found on a XuLA2-LX25 board made by xess.com. |
// |
// This simulator is for testing use in a Verilator/C++ environment, where |
// it would be used in place of the actual hardware. |
// |
// Creator: Dan Gisselquist |
// Gisselquist Technology, LLC |
// |
/////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2015-2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
/////////////////////////////////////////////////////////////////////////// |
#include <stdio.h> |
#include <string.h> |
#include <assert.h> |
#include <stdlib.h> |
|
#include "sdspisim.h" |
|
static const unsigned |
MICROSECONDS = 80, // Clocks in a microsecond |
MILLISECONDS = MICROSECONDS * 1000, |
tRESET = 4*MILLISECONDS; // Just a wild guess |
/* |
static const unsigned DEVID = 0x0115, |
DEVESD = 0x014, |
MICROSECONDS = 100, |
MILLISECONDS = MICROSECONDS * 1000, |
SECONDS = MILLISECONDS * 1000, |
tW = 50 * MICROSECONDS, // write config cycle time |
tBE = 32 * SECONDS, |
tDP = 10 * SECONDS, |
tRES = 30 * SECONDS, |
// Shall we artificially speed up this process? |
tPP = 12 * MICROSECONDS, |
tSE = 15 * MILLISECONDS; |
// or keep it at the original speed |
// tPP = 1200 * MICROSECONDS, |
// tSE = 1500 * MILLISECONDS; |
*/ |
static const unsigned |
CCS = 1; // 0: SDSC card, 1: SDHC or SDXC card |
|
SDSPISIM::SDSPISIM(void) { |
m_dev = NULL; |
m_last_sck = 1; |
m_block_address = (CCS==1); |
m_host_supports_high_capacity = false; |
m_powerup_busy = -1; |
m_reset_state = SDSPI_POWERUP_RESET; |
// |
m_csd[ 0] = 0; // Normal SDcard, not high capacity |
m_csd[ 1] = 0x0f; |
m_csd[ 2] = 0x0f; |
m_csd[ 3] = 0x32; // Can be either 0x32 (25MHz) or 0x5a (50MHz) |
m_csd[ 4] = 0x5b; // Could also be 0x07b, if we supported more comands(?) |
m_csd[ 5] = 0x59; // 9-> 2^9,or 512 bytes (10->1024, 11->2048, no othrs) |
m_csd[ 6] = 0x00; // partial blocks allowed? |
m_csd[ 7] = 0x00; // C_SIZE, 2'b00, then top 6 bits |
m_csd[ 8] = 0; // C_SIZE, 22-bits, mid 8 bits |
m_csd[ 9] = 0; // C_SIZE, 22-bits, bottom 8 bits |
m_csd[10] = 0x7f; |
m_csd[11] = 0x80; |
m_csd[12] = 0x0a; |
m_csd[13] = 0x40; |
m_csd[14] = 0; // R/W: file format, copy, write protect, etc. |
m_csd[15] = cmdcrc(15, m_csd); |
|
// CID Register |
m_cid[ 0] = 0xba; |
m_cid[ 1] = 0xd0; |
m_cid[ 2] = 0xda; |
m_cid[ 3] = 0xdd; |
m_cid[ 4] = 0; |
m_cid[ 5] = 0xde; |
m_cid[ 6] = 0xad; |
m_cid[ 7] = 0xbe; |
m_cid[ 8] = 0xef; |
m_cid[ 9] = 0x20; |
m_cid[10] = 0x16; |
m_cid[11] = 0x05; |
m_cid[12] = 0x26; |
m_cid[13] = 0; |
m_cid[14] = 0; |
m_cid[15] = cmdcrc(15, m_cid); |
|
// m_write_count = 0; |
// m_ireg = m_oreg = 0; |
// m_sreg = 0x01c; |
// m_creg = 0x001; // Iinitial creg on delivery |
|
// |
m_reading_data = false; |
m_have_token = false; |
} |
|
void SDSPISIM::load(const char *fname) { |
m_dev = fopen(fname, "r+b"); |
|
if (m_dev) { |
unsigned long devln; |
fseek(m_dev, 0l, SEEK_END); |
devln = ftell(m_dev); |
fseek(m_dev, 0l, SEEK_SET); |
|
m_devblocks = devln>>9; |
|
printf("SDCARD: NBLOCKS = %ld\n", m_devblocks); |
} |
} |
|
int SDSPISIM::operator()(const int csn, const int sck, const int mosi) { |
// Keep track of a timer to determine when page program and erase |
// cycles complete. |
|
/* |
if (m_write_count > 0) { |
// |
} |
*/ |
|
m_delay++; |
if (m_powerup_busy>0) |
m_powerup_busy--; |
|
if (csn) { |
m_delay = 0; |
m_cmdidx= 0; |
m_rspidx= 0; |
m_bitpos= 0; |
m_delay = 0; |
m_busy = false; |
m_last_sck = sck; |
m_syncd = false; |
m_last_miso = 1; |
m_dat_out = 0x0ff; |
// Reset everything when not selected |
return 0; |
} else if (sck == m_last_sck) { |
m_last_sck = sck; |
return m_last_miso; |
} else if (!m_last_sck) { |
// Register our input on the rising edge |
m_mosi = mosi; |
m_syncd= true; |
m_last_sck = sck; |
return m_last_miso; |
} if (!m_syncd) { |
m_last_sck = sck; |
return m_last_miso; |
} |
|
// Only change our output on the falling edge |
|
m_last_sck = sck; |
printf("SDSPI: (%3d) [%d,%d,%d] ", m_delay, csn, sck, m_mosi); |
// assert(m_delay > 20); |
|
m_bitpos++; |
m_dat_in = (m_dat_in<<1)|m_mosi; |
|
|
printf("(bitpos=%d,dat_in=%02x)\n", m_bitpos&7, m_dat_in&0x0ff); |
|
if ((m_bitpos&7)==0) { |
printf("SDSPI--RX BYTE %02x\n", m_dat_in&0x0ff); |
m_dat_out = 0xff; |
if (m_reading_data) { |
if (m_have_token) { |
m_block_buf[m_rxloc++] = m_dat_in; |
printf("SDSPI: WR[%3d] = %02x\n", m_rxloc-1, |
m_dat_in&0x0ff); |
if (m_rxloc >= 512+2) { |
unsigned crc, rxcrc; |
crc = blockcrc(512, m_block_buf); |
rxcrc = ((m_block_buf[512]&0x0ff)<<8) |
|(m_block_buf[513]&0x0ff); |
|
printf("LEN = %d\n", m_rxloc); |
printf("CHECKING CRC: (rx) %04x =? %04x (calc)\n", |
crc, rxcrc); |
m_reading_data = false; |
m_have_token = false; |
if (rxcrc == crc) |
m_dat_out = 5; |
else { |
m_dat_out = 0x0b; |
assert(rxcrc == crc); |
} |
} |
} else { |
if ((m_dat_in&0x0ff) == 0x0fe) { |
printf("SDSPI: TOKEN!!\n"); |
m_have_token = true; |
m_rxloc = 0; |
} else printf("SDSPI: waiting on token\n"); |
} |
} else if (m_cmdidx < 6) { |
printf("SDSPI: CMDIDX = %d\n", m_cmdidx); |
// All commands *must* start with a 01... pair of bits. |
if (m_cmdidx == 0) |
assert((m_dat_in&0xc0)==0x40); |
|
// Record the command for later processing |
m_cmdbuf[m_cmdidx++] = m_dat_in; |
} else if (m_cmdidx == 6) { |
// We're going to start a response from here ... |
m_rspidx = 0; |
m_blkdly = 0; |
m_blkidx = SDSPI_MAXBLKLEN; |
printf("SDSPI: CMDIDX = %d -- WE HAVE A COMMAND! [ ", m_cmdidx); |
for(int i=0; i<6; i++) |
printf("%02x ", m_cmdbuf[i] & 0xff); |
printf("]\n"); fflush(stdout); |
|
unsigned arg; |
arg = ((((((m_cmdbuf[1]<<8)|(m_cmdbuf[2]&0x0ff))<<8) |
|(m_cmdbuf[3]&0x0ff))<<8) |
|(m_cmdbuf[4]&0x0ff)); |
arg &= 0x0ffffffff; |
|
// Check the CRC |
if (!check_cmdcrc(m_cmdbuf)) { |
assert(0 && "BAD CRC"); |
m_rspbuf[0] = 0x09; |
m_rspdly = 1; |
} else if (m_altcmd_flag) { |
switch(m_cmdbuf[0]&0x03f) { |
case 41: // ACMD41 -- SD_SEND_OP_COND |
// and start initialization sequence |
assert((m_reset_state == SDSPI_RCVD_CMD8)||(m_reset_state == SDSPI_RCVD_ACMD41)||(m_reset_state == SDSPI_RESET_COMPLETE)); |
if((unsigned)m_powerup_busy>tRESET) |
|
m_powerup_busy = tRESET; |
assert((arg&0x0bfffffff) == 0); |
m_rspbuf[0] = (m_powerup_busy)?1:0; |
m_rspdly = 2; |
m_host_supports_high_capacity = (m_cmdbuf[1]&0x40)?1:0; |
m_reset_state = (m_powerup_busy)? |
SDSPI_RCVD_ACMD41 |
:SDSPI_RESET_COMPLETE; |
break; |
case 51: // ACMD51 |
m_block_buf[0] = 0x0fe; |
for(int j=0; j<8; j++) |
m_block_buf[j+1] = m_csd[j]; |
m_blklen = 8; |
add_block_crc(m_blklen, m_block_buf); |
|
m_blkdly = 0; |
m_blkidx = 0; |
m_dat_out = 0; |
break; |
case 13: // ACMD13 |
case 22: // ACMD22 |
case 23: // ACMD23 |
case 42: // ACMD42 |
default: // Unimplemented command! |
m_rspbuf[0] = 0x04; |
m_rspdly = 4; |
fprintf(stderr, "SDSPI ERR: Alt command ACMD%d not implemented!\n", m_cmdbuf[0]&0x03f); |
assert(0 && "Not Implemented"); |
} m_altcmd_flag = false; |
} else { |
m_altcmd_flag = false; |
memset(m_rspbuf, 0x0ff, SDSPI_RSPLEN); |
printf("SDSPI: Received a command 0x%02x (%d)\n", |
m_cmdbuf[0], m_cmdbuf[0]&0x03f); |
switch(m_cmdbuf[0]&0x3f) { |
case 0: // CMD0 -- GO_IDLE_STATE |
m_rspbuf[0] = 0x01; |
m_rspdly = 4; |
m_reset_state = SDSPI_CMD0_IDLE; |
break; |
case 1: // CMD1 -- SEND_OP_COND |
assert((arg&0x0bfffffff) == 0); |
m_rspbuf[0] = 0x02; |
m_rspdly = 4; |
m_host_supports_high_capacity = (m_cmdbuf[1]&0x40)?1:0; |
break; |
case 8: // CMD8 -- SEND_IF_COND |
assert((arg&0x0fffff000) == 0); |
m_rspbuf[0] = 0x00; |
// See p82 for this format |
m_rspbuf[1] = 0; |
m_rspbuf[2] = 0; |
// If we do not accept the voltage range |
m_rspbuf[3] = 0; |
// Now, check if we accept it |
// We only accept 2.7-3.6V in this |
// simulation. |
if ((arg&0x0f00)==0x0100) |
m_rspbuf[3] = 1; |
m_rspbuf[4] = (char)(arg&0x0ff); |
m_rspdly = 4; |
assert((m_reset_state == SDSPI_CMD0_IDLE)||(m_reset_state == SDSPI_RCVD_CMD8)); |
m_reset_state = SDSPI_RCVD_CMD8; |
break; |
case 9: // CMD9 -- SEND_CSD |
// Block read, returning start token, |
// 16 bytes, then 2 crc bytes |
assert(m_reset_state == SDSPI_IN_OPERATION); |
m_rspbuf[0] = 0x00; |
memset(m_block_buf, 0x0ff, SDSPI_MAXBLKLEN); |
m_block_buf[0] = 0x0fe; |
for(int j=0; j<16; j++) |
m_block_buf[j+1] = m_csd[j]; |
m_blklen = 16; |
add_block_crc(m_blklen, m_block_buf); |
|
m_blkdly = 60; |
m_blkidx = 0; |
break; |
case 10: // CMD10 -- SEND_CID |
// Block read, returning start token, |
// 16 bytes, then 2 crc bytes |
assert(m_reset_state == SDSPI_IN_OPERATION); |
m_rspbuf[0] = 0x00; |
memset(m_block_buf, 0x0ff, SDSPI_MAXBLKLEN); |
m_block_buf[0] = 0x0fe; |
for(int j=0; j<16; j++) |
m_block_buf[j+1] = m_cid[j]; |
m_blklen = 16; |
add_block_crc(m_blklen, m_block_buf); |
|
m_blkdly = 60; |
m_blkidx = 0; |
break; |
case 13: // CMD13 -- SEND_STATUS |
assert(m_reset_state == SDSPI_IN_OPERATION); |
m_rspbuf[0] = 0x00; |
m_rspbuf[1] = 0x00; |
// if (m_wp_fault) m_rspbuf[1]|=0x20; |
// if (m_err) m_rspbuf[1]|=0x04; |
m_rspdly = 4; |
break; |
case 17: // CMD17 -- READ_SINGLE_BLOCK |
assert(m_reset_state == SDSPI_IN_OPERATION); |
m_rspbuf[0] = 0x00; |
memset(m_block_buf, 0x0ff, SDSPI_MAXBLKLEN); |
if (m_dev) { |
printf("Reading from block %08x of %08lx\n", arg, m_devblocks); |
if (m_block_address) { |
assert(arg < m_devblocks); |
fseek(m_dev, arg<<9, SEEK_SET); |
} else { |
assert(arg < m_devblocks<<9); |
fseek(m_dev, arg, SEEK_SET); |
} |
} m_block_buf[0] = 0x0fe; |
m_blklen = 512; // (1<<m_csd[5]); |
if (m_dev) |
fread(&m_block_buf[1], m_blklen, 1, m_dev); |
else |
memset(&m_block_buf[1], 0, m_blklen); |
add_block_crc(m_blklen, m_block_buf); |
|
m_blkdly = 60; |
m_blkidx = 0; |
break; |
case 24: // CMD24 -- WRITE_BLOCK |
m_reading_data = true; |
m_have_token = false; |
m_dat_out = 0; |
break; |
case 55: // CMD55 -- APP_CMD |
m_rspbuf[0] = 0x00; |
m_rspdly = 2; |
m_altcmd_flag = true; |
break; |
case 58: // CMD58 -- READ_OCR, respond R7 |
// argument is stuff bits/dont care |
m_rspbuf[0] = 0x00; |
// See p112, Tbl 5-1 for this format |
m_rspbuf[1] = ((m_powerup_busy)?0x80:0) |
|(CCS?0x40:0); |
m_rspbuf[2] = 0xff;// 2.7-3.6V supported |
m_rspbuf[3] = 0x80; |
m_rspbuf[4] = 0; // No low-voltage supt |
m_rspdly = 4; |
|
if (m_reset_state == SDSPI_RESET_COMPLETE) |
m_reset_state = SDSPI_IN_OPERATION; |
break; |
case 6: // CMD6 -- SWITCH_FUNC |
case 12: // CMD12 -- STOP_TRANSMISSION (!impl) |
case 16: // CMD16 -- SET_BLOCKLEN |
case 18: // CMD18 -- READ_MULTIPLE_BLOCK |
case 25: // CMD25 -- WRITE_MULTIPLE_BLOCK |
case 27: // CMD27 -- PROGRAM_CSD |
case 32: // CMD32 -- ERASE_WR_BLK_START_ADDR |
case 33: // CMD33 -- ERASE_WR_BLK_END_ADDR |
case 38: // CMD38 -- ERASE |
case 56: // CMD56 -- GEN_CMD |
default: // Unimplemented command |
m_rspbuf[0] = 0x04; |
m_rspdly = 4; |
printf("SDSPI ERR: Command CMD%d not implemented!\n", m_cmdbuf[0]&0x03f); |
fflush(stdout); |
assert(0 && "Not Implemented"); |
} |
} m_cmdidx++; |
|
// If we are using blocks, add bytes for the start |
// token and the two CRC bytes |
m_blklen += 3; |
} else if (m_rspdly > 0) { |
assert((m_dat_in&0x0ff) == 0x0ff); |
// A delay until a response is given |
if (m_busy) |
m_dat_out = 0; |
m_rspdly--; |
} else if (m_rspidx < SDSPI_RSPLEN) { |
assert((m_dat_in&0x0ff) == 0x0ff); |
m_dat_out = m_rspbuf[m_rspidx++]; |
} else if (m_blkdly > 0) { |
assert((m_dat_in&0x0ff) == 0x0ff); |
m_blkdly--; |
} else if (m_blkidx < SDSPI_MAXBLKLEN) { |
assert((m_dat_in&0x0ff) == 0x0ff); |
m_dat_out = m_block_buf[m_blkidx++]; |
} |
// else m_dat_out = 0x0ff; // So set already above |
} |
|
int result = (m_dat_out&0x80)?1:0; |
m_dat_out <<= 1; |
m_delay = 0; |
m_last_miso = result; |
fflush(stdout); |
return result; |
} |
|
unsigned SDSPISIM::cmdcrc(int len, char *buf) const { |
unsigned int fill = 0, taps = 0x12; |
|
for(int i=0; i<len; i++) { |
fill ^= buf[i]; |
for(int j=0; j<8; j++) { |
if (fill&0x80) |
fill = (fill<<1)^taps; |
else |
fill <<= 1; |
} |
} |
|
fill &= 0x0fe; fill |= 1; |
return fill; |
} |
|
bool SDSPISIM::check_cmdcrc(char *buf) const { |
unsigned fill = cmdcrc(5, buf); |
printf("SDSPI: CRC-CHECK, should have a CRC of %02x\n", fill); |
return (fill == (buf[5]&0x0ff)); |
} |
|
unsigned SDSPISIM::blockcrc(int len, char *buf) const { |
unsigned int fill = 0, taps = 0x1021; |
bool dbg = (len == 512); |
|
for(int i=0; i<len; i++) { |
if (dbg) { printf("BUF[%3d] = %02x\n", i, buf[i]&0x0ff); } |
fill ^= ((buf[i]&0x0ff) << 8); |
for(int j=0; j<8; j++) { |
if (fill&0x8000) |
fill = (fill<<1)^taps; |
else |
fill <<= 1; |
} |
} |
|
fill &= 0x0ffff; |
if (dbg) { printf("BLOCKCRC(%d,??) = %04x\n", len, fill); } |
return fill; |
} |
|
void SDSPISIM::add_block_crc(int len, char *buf) const { |
unsigned fill = blockcrc(len, &buf[1]); |
|
buf[len+1] = (fill >> 8)&0x0ff; |
buf[len+2] = (fill )&0x0ff; |
} |
|
/trunk/bench/cpp/Makefile
0,0 → 1,43
################################################################################ |
## |
## Filename: Makefile |
## |
## Project: SD-Card controller, using a shared SPI interface |
## |
## Purpose: Nothing currently. Eventually, if I create a proper bench |
## test, rather than just running this on real hardware as part of |
## another project (XuLA2-LX25 SoC), this Makefile will coordinate the |
## building of that bench test software. |
## |
## Creator: Dan Gisselquist, Ph.D. |
## Gisselquist Technology, LLC |
## |
################################################################################ |
## |
## Copyright (C) 2016, Gisselquist Technology, LLC |
## |
## This program is free software (firmware): you can redistribute it and/or |
## modify it under the terms of the GNU General Public License as published |
## by the Free Software Foundation, either version 3 of the License, or (at |
## your option) any later version. |
## |
## This program is distributed in the hope that it will be useful, but WITHOUT |
## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with this program. (It's in the $(ROOT)/doc directory, run make with no |
## target there if the PDF file isn't present.) If not, see |
## <http://www.gnu.org/licenses/> for a copy. |
## |
## License: GPL, v3, as defined and found on www.gnu.org, |
## http://www.gnu.org/licenses/gpl.html |
## |
## |
################################################################################ |
## |
## |
.PHONY: all |
all: |
|
/trunk/rtl/sdspi.v
0,0 → 1,805
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: sdspi.v |
// |
// Project: SD-Card controller, using a shared SPI interface |
// |
// Purpose: |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define SDSPI_CMD_ADDRESS 2'h0 |
`define SDSPI_DAT_ADDRESS 2'h1 |
`define SDSPI_FIFO_A_ADDR 2'h2 |
`define SDSPI_FIFO_B_ADDR 2'h3 |
// |
// `define SDSPI_CMD_ID 3'h0 |
// `define SDSPI_CMD_A1 3'h1 |
// `define SDSPI_CMD_A2 3'h2 |
// `define SDSPI_CMD_A3 3'h3 |
// `define SDSPI_CMD_A4 3'h4 |
// `define SDSPI_CMD_CRC 3'h5 |
// `define SDSPI_CMD_FIFO 3'h6 |
// `define SDSPI_CMD_WAIT 3'h7 |
// |
`define SDSPI_EXPECT_R1 2'b00 |
`define SDSPI_EXPECT_R1B 2'b01 |
`define SDSPI_EXPECT_R3 2'b10 |
// |
`define SDSPI_RSP_NONE 3'h0 // No response yet from device |
`define SDSPI_RSP_BSYWAIT 3'h1 // R1b, wait for device to send nonzero |
`define SDSPI_RSP_GETWORD 3'h2 // Get 32-bit data word from device |
`define SDSPI_RSP_GETTOKEN 3'h4 // Write to device, read from FIFO, wait for completion token |
`define SDSPI_RSP_WAIT_WHILE_BUSY 3'h5 // Read from device |
`define SDSPI_RSP_RDCOMPLETE 3'h6 |
`define SDSPI_RSP_WRITING 3'h7 // Read from device, write into FIFO |
// |
module sdspi(i_clk, |
// Wishbone interface |
i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, |
o_wb_ack, o_wb_stall, o_wb_data, |
// SDCard interface |
o_cs_n, o_sck, o_mosi, i_miso, |
// Our interrupt |
o_int, |
// And whether or not we own the bus |
i_bus_grant, |
// And some wires for debugging it all |
o_debug); |
parameter LGFIFOLN = 7; |
input i_clk; |
// |
input i_wb_cyc, i_wb_stb, i_wb_we; |
input [1:0] i_wb_addr; |
input [31:0] i_wb_data; |
output reg o_wb_ack; |
output wire o_wb_stall; |
output reg [31:0] o_wb_data; |
// |
output wire o_cs_n, o_sck, o_mosi; |
input i_miso; |
// The interrupt |
output reg o_int; |
// .. and whether or not we can use the SPI port |
input i_bus_grant; |
// |
output wire [31:0] o_debug; |
|
// |
// Some WB simplifications: |
// |
reg r_cmd_busy; |
wire wb_stb, write_stb, cmd_stb; // read_stb |
assign wb_stb = ((i_wb_cyc)&&(i_wb_stb)&&(~o_wb_stall)); |
assign write_stb = ((wb_stb)&&( i_wb_we)); |
// assign read_stb = ((wb_stb)&&(~i_wb_we)); |
assign cmd_stb = (~r_cmd_busy)&&(write_stb) |
&&(i_wb_addr==`SDSPI_CMD_ADDRESS); |
|
|
// |
// Access to our lower-level SDSPI driver, the one that actually |
// uses/sets the SPI ports |
// |
reg [6:0] r_sdspi_clk; |
reg ll_cmd_stb; |
reg [7:0] ll_cmd_dat; |
wire ll_out_stb, ll_idle; |
wire [7:0] ll_out_dat; |
llsdspi lowlevel(i_clk, r_sdspi_clk, r_cmd_busy, ll_cmd_stb, ll_cmd_dat, |
o_cs_n, o_sck, o_mosi, i_miso, |
ll_out_stb, ll_out_dat, ll_idle, |
i_bus_grant); |
|
|
// CRC |
reg r_cmd_crc_stb; |
wire [7:0] cmd_crc; |
// State machine |
reg [2:0] r_cmd_state, r_rsp_state; |
// Current status, beyond state |
reg r_have_resp, r_use_fifo, r_fifo_wr, |
ll_fifo_rd_complete, ll_fifo_wr_complete, |
r_fifo_id, |
ll_fifo_wr, ll_fifo_rd, |
r_have_data_response_token, |
r_have_start_token; |
reg [7:0] fifo_byte; |
reg [7:0] r_last_r_one; |
// |
reg [31:0] r_data_reg; |
reg [1:0] r_data_fil, r_cmd_resp; |
// |
// |
wire need_reset; |
reg r_cmd_err; |
reg r_cmd_sent; |
reg [31:0] fifo_a_reg, fifo_b_reg; |
// |
reg q_busy; |
// |
reg [7:0] fifo_a_mem[((1<<(LGFIFOLN+2))-1):0]; |
reg [7:0] fifo_b_mem[((1<<(LGFIFOLN+2))-1):0]; |
reg [(LGFIFOLN-1):0] fifo_wb_addr; |
reg [(LGFIFOLN+1):0] rd_fifo_sd_addr; |
reg [(LGFIFOLN+1):0] wr_fifo_sd_addr; |
// |
reg [(LGFIFOLN+1):0] ll_fifo_addr; |
// |
reg fifo_crc_err; |
reg [1:0] ll_fifo_wr_state; |
reg [7:0] fifo_a_byte, fifo_b_byte; |
// |
reg [2:0] ll_fifo_pkt_state; |
reg fifo_rd_crc_stb, fifo_wr_crc_stb; |
// |
reg [3:0] fifo_rd_crc_count, fifo_wr_crc_count; |
reg [15:0] fifo_rd_crc_reg, fifo_wr_crc_reg; |
// |
reg [3:0] r_cmd_crc_cnt; |
reg [7:0] r_cmd_crc; |
// |
reg r_cmd_crc_ff; |
// |
reg [3:0] r_lgblklen; |
wire [3:0] max_lgblklen; |
assign max_lgblklen = LGFIFOLN; |
// |
reg [25:0] r_watchdog; |
reg r_watchdog_err; |
reg pre_cmd_state; |
|
initial r_cmd_busy = 1'b0; |
initial r_data_reg = 32'h00; |
initial r_last_r_one = 8'hff; |
initial ll_cmd_stb = 1'b0; |
initial ll_fifo_rd = 1'b0; |
initial ll_fifo_wr = 1'b0; |
initial r_rsp_state = 3'h0; |
initial r_cmd_state = 3'h0; |
initial r_use_fifo = 1'b0; |
initial r_data_fil = 2'b00; |
initial r_lgblklen = LGFIFOLN; |
initial r_cmd_err = 1'b0; |
always @(posedge i_clk) |
begin |
if (~ll_cmd_stb) |
begin |
r_have_resp <= 1'b0; |
ll_fifo_wr <= 1'b0; |
ll_fifo_rd <= 1'b0; |
// r_rsp_state <= 3'h0; |
r_cmd_state <= 3'h0; |
r_use_fifo <= 1'b0; |
r_data_fil <= 2'b00; |
r_cmd_resp <= `SDSPI_EXPECT_R1; |
end |
|
r_cmd_crc_stb <= 1'b0; |
if (pre_cmd_state) |
begin // While we are actively sending data, and clocking the |
// interface, do: |
// |
// Here we use the transmit command state, or |
// r_cmd_state, to determine where we are at in this |
// process, and we use (ll_cmd_stb)&&(ll_idle) to |
// determine that we have sent a byte. ll_cmd_dat is |
// set here as well--it's the byte we wish to transmit. |
if (r_cmd_state == 3'h0) |
begin |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_cmd_dat <= r_data_reg[31:24]; |
r_cmd_crc_stb <= 1'b1; |
end else if (r_cmd_state == 3'h1) |
begin |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_cmd_dat <= r_data_reg[23:16]; |
r_cmd_crc_stb <= 1'b1; |
end else if (r_cmd_state == 3'h2) |
begin |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_cmd_dat <= r_data_reg[15:8]; |
r_cmd_crc_stb <= 1'b1; |
end else if (r_cmd_state == 3'h3) |
begin |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_cmd_dat <= r_data_reg[7:0]; |
r_cmd_crc_stb <= 1'b1; |
end else if (r_cmd_state == 3'h4) |
begin |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_cmd_dat <= cmd_crc; |
end else if (r_cmd_state == 3'h5) |
begin |
ll_cmd_dat <= 8'hff; |
if (r_have_resp) |
begin |
if (r_use_fifo) |
r_cmd_state <= r_cmd_state + 3'h1; |
else |
r_cmd_state <= r_cmd_state + 3'h2; |
ll_fifo_rd <= (r_use_fifo)&&(r_fifo_wr); |
if ((r_use_fifo)&&(r_fifo_wr)) |
ll_cmd_dat <= 8'hfe; |
end |
end else if (r_cmd_state == 3'h6) |
begin |
ll_cmd_dat <= 8'hff; |
if (ll_fifo_rd_complete) |
begin // If we've finished reading from the |
// FIFO, then move on |
r_cmd_state <= r_cmd_state + 3'h1; |
ll_fifo_rd <= 1'b0; |
end else if (ll_fifo_rd) |
ll_cmd_dat <= fifo_byte; |
end else // if (r_cmd_state == 7) |
ll_cmd_dat <= 8'hff; |
|
|
// Here we handle the receive portion of the interface. |
// Note that the IF begins with an if of ll_out_stb. |
// That is, if a byte is ready from the lower level. |
// |
// Here we depend upon r_cmd_resp, the response we are |
// expecting from the SDCard, and r_rsp_state, the |
// state machine for where we are at receive what we |
// are expecting. |
if (pre_rsp_state) |
begin |
if (r_rsp_state == `SDSPI_RSP_NONE) |
begin // Waiting on R1 |
if (~ll_out_dat[7]) |
begin |
r_last_r_one <= ll_out_dat; |
if (r_cmd_resp == `SDSPI_EXPECT_R1) |
begin // Expecting R1 alone |
r_have_resp <= 1'b1; |
ll_cmd_stb <= (r_use_fifo); |
r_data_reg <= 32'hffffffff; |
ll_fifo_wr<=(r_use_fifo)&&(~r_fifo_wr); |
end else if (r_cmd_resp == `SDSPI_EXPECT_R1B) |
begin // Go wait on R1b |
r_data_reg <= 32'hffffffff; |
end // else wait on 32-bit rsp |
end |
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT) |
begin // Waiting on R1b, have R1 |
if (nonzero_out) |
r_have_resp <= 1'b1; |
ll_cmd_stb <= (r_use_fifo); |
end else if (r_rsp_state == `SDSPI_RSP_GETWORD) |
begin // Have R1, waiting on all of R2/R3/R7 |
r_data_reg <= { r_data_reg[23:0], ll_out_dat }; |
r_data_fil <= r_data_fil+2'b01; |
if (r_data_fil == 2'b11) |
begin |
ll_cmd_stb <= (r_use_fifo); |
// r_rsp_state <= 3'h3; |
end |
end else if (r_rsp_state == `SDSPI_RSP_WAIT_WHILE_BUSY) |
begin // Wait while device is busy writing |
// if (nonzero_out) |
// begin |
// r_data_reg[31:8] <= 24'h00; |
// r_data_reg[7:0] <= ll_out_dat; |
// // r_rsp_state <= 3'h6; |
// end |
; |
end else if (r_rsp_state == `SDSPI_RSP_RDCOMPLETE) |
begin // Block write command has completed |
ll_cmd_stb <= 1'b0; |
end else if (r_rsp_state == `SDSPI_RSP_WRITING) |
begin // We are reading from the device into |
// our FIFO |
if ((ll_fifo_wr_complete) |
// Or ... we receive an error |
||((~r_have_start_token) |
&&(~ll_out_dat[4]) |
&&(ll_out_dat[0]))) |
begin |
ll_fifo_wr <= 1'b0; |
ll_cmd_stb <= 1'b0; |
end |
end |
end |
|
if (r_watchdog_err) |
ll_cmd_stb <= 1'b0; |
r_cmd_err<= (r_cmd_err)|(fifo_crc_err)|(r_watchdog_err); |
end else if (r_cmd_busy) |
begin |
r_cmd_busy <= (ll_cmd_stb)||(~ll_idle); |
end else if (cmd_stb) |
begin // Command write |
// Clear the error on any write, whether a commanding |
// one or not. -- provided the user requests clearing |
// it (by setting the bit high) |
r_cmd_err <= (r_cmd_err)&&(~i_wb_data[15]); |
// In a similar fashion, we can switch fifos even if |
// not in the middle of a command |
r_fifo_id <= i_wb_data[12]; |
// |
// Doesn't matter what this is set to as long as we |
// aren't busy, so we can set it irrelevantly here. |
ll_cmd_dat <= i_wb_data[7:0]; |
// |
// Note that we only issue a write upon receiving a |
// valid command. Such a command is 8 bits, and must |
// start with its high order bits set to zero and one. |
// Hence ... we test for that here. |
if (i_wb_data[7:6] == 2'b01) |
begin // Issue a command |
// |
r_cmd_busy <= 1'b1; |
// |
ll_cmd_stb <= 1'b1; |
r_cmd_resp <= i_wb_data[9:8]; |
// |
r_cmd_crc_stb <= 1'b1; |
// |
r_fifo_wr <= i_wb_data[10]; |
r_use_fifo <= i_wb_data[11]; |
// |
end else if (i_wb_data[7]) |
// If, on the other hand, the command was invalid, |
// then it must have been an attempt to read our |
// internal configuration. So we'll place that on |
// our data register. |
r_data_reg <= { 8'h00, |
4'h0, max_lgblklen, |
4'h0, r_lgblklen, 1'b0, r_sdspi_clk }; |
end else if ((write_stb)&&(i_wb_addr == `SDSPI_DAT_ADDRESS)) |
begin // Data write |
r_data_reg <= i_wb_data; |
end |
end |
|
always @(posedge i_clk) |
pre_cmd_state <= (ll_cmd_stb)&&(ll_idle); |
|
reg ready_for_response_token; |
always @(posedge i_clk) |
if (~r_cmd_busy) |
ready_for_response_token <= 1'b0; |
else if (ll_fifo_rd) |
ready_for_response_token <= 1'b1; |
always @(posedge i_clk) |
if (~r_cmd_busy) |
r_have_data_response_token <= 1'b0; |
else if ((ll_out_stb)&&(ready_for_response_token)&&(~ll_out_dat[4])) |
r_have_data_response_token <= 1'b1; |
|
reg [2:0] second_rsp_state; |
always @(posedge i_clk) |
if((r_cmd_resp == `SDSPI_EXPECT_R1)&&(r_use_fifo)&&(r_fifo_wr)) |
second_rsp_state <= `SDSPI_RSP_GETTOKEN; |
else if (r_cmd_resp == `SDSPI_EXPECT_R1) |
second_rsp_state <= `SDSPI_RSP_WRITING; |
else if (r_cmd_resp == `SDSPI_EXPECT_R1B) |
second_rsp_state <= `SDSPI_RSP_BSYWAIT; |
else |
second_rsp_state <= `SDSPI_RSP_GETWORD; |
|
reg pre_rsp_state, nonzero_out; |
always @(posedge i_clk) |
if (ll_out_stb) |
nonzero_out <= (|ll_out_dat); |
always @(posedge i_clk) |
pre_rsp_state <= (ll_out_stb)&&(r_cmd_sent); |
|
// Each bit depends upon 8 bits of input |
initial r_rsp_state = 3'h0; |
always @(posedge i_clk) |
if (~r_cmd_sent) |
r_rsp_state <= 3'h0; |
else if (pre_rsp_state) |
begin |
if ((r_rsp_state == `SDSPI_RSP_NONE)&&(~ll_out_dat[7])) |
begin |
r_rsp_state <= second_rsp_state; |
end else if (r_rsp_state == `SDSPI_RSP_BSYWAIT) |
begin // Waiting on R1b, have R1 |
// R1b never uses the FIFO |
if (nonzero_out) |
r_rsp_state <= 3'h6; |
end else if (r_rsp_state == `SDSPI_RSP_GETWORD) |
begin // Have R1, waiting on all of R2/R3/R7 |
if (r_data_fil == 2'b11) |
r_rsp_state <= `SDSPI_RSP_RDCOMPLETE; |
end else if (r_rsp_state == `SDSPI_RSP_GETTOKEN) |
begin // Wait on data token response |
if (r_have_data_response_token) |
r_rsp_state <= `SDSPI_RSP_WAIT_WHILE_BUSY; |
end else if (r_rsp_state == `SDSPI_RSP_WAIT_WHILE_BUSY) |
begin // Wait while device is busy writing |
if (nonzero_out) |
r_rsp_state <= `SDSPI_RSP_RDCOMPLETE; |
end |
//else if (r_rsp_state == 3'h6) |
//begin // Block write command has completed |
// // ll_cmd_stb <= 1'b0; |
// end else if (r_rsp_state == 3'h7) |
// begin // We are reading from the device into |
// // our FIFO |
// end |
end |
|
always @(posedge i_clk) |
r_cmd_sent <= (ll_cmd_stb)&&(r_cmd_state >= 3'h5); |
|
// initial r_sdspi_clk = 6'h3c; |
initial r_sdspi_clk = 7'h63; |
always @(posedge i_clk) |
begin |
// Update our internal configuration parameters, unconnected |
// with the card. These include the speed of the interface, |
// and the size of the block length to expect as part of a FIFO |
// command. |
if ((cmd_stb)&&(i_wb_data[7:6]==2'b11)&&(~r_data_reg[7]) |
&&(r_data_reg[15:12]==4'h00)) |
begin |
if (|r_data_reg[6:0]) |
r_sdspi_clk <= r_data_reg[6:0]; |
if (|r_data_reg[11:8]) |
r_lgblklen <= r_data_reg[11:8]; |
end if (r_lgblklen > max_lgblklen) |
r_lgblklen <= max_lgblklen; |
end |
|
assign need_reset = 1'b0; |
always @(posedge i_clk) |
case(i_wb_addr) |
`SDSPI_CMD_ADDRESS: |
o_wb_data <= { need_reset, 11'h00, |
3'h0, fifo_crc_err, |
r_cmd_err, r_cmd_busy, 1'b0, r_fifo_id, |
r_use_fifo, r_fifo_wr, r_cmd_resp, |
r_last_r_one }; |
`SDSPI_DAT_ADDRESS: |
o_wb_data <= r_data_reg; |
`SDSPI_FIFO_A_ADDR: |
o_wb_data <= fifo_a_reg; |
`SDSPI_FIFO_B_ADDR: |
o_wb_data <= fifo_b_reg; |
endcase |
|
always @(posedge i_clk) |
o_wb_ack <= wb_stb; |
|
initial q_busy = 1'b1; |
always @(posedge i_clk) |
q_busy <= r_cmd_busy; |
always @(posedge i_clk) |
o_int <= (~r_cmd_busy)&&(q_busy); |
|
assign o_wb_stall = 1'b0; |
|
// |
// Let's work with our FIFO memory here ... |
// |
// |
always @(posedge i_clk) |
begin |
if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)) |
begin // Command write |
// Clear the read/write address |
fifo_wb_addr <= {(LGFIFOLN){1'b0}}; |
end else if ((wb_stb)&&(i_wb_addr[1])) |
begin // On read or write, of either FIFO, |
// we increase our pointer |
fifo_wb_addr <= fifo_wb_addr + 1; |
// And let ourselves know we need to update ourselves |
// on the next clock |
end |
end |
|
// Prepare reading of the FIFO for the WB bus read |
// Memory read #1 |
always @(posedge i_clk) |
begin |
fifo_a_reg <= { |
fifo_a_mem[{ fifo_wb_addr, 2'b00 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b01 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b10 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] }; |
fifo_b_reg <= { |
fifo_b_mem[{ fifo_wb_addr, 2'b00 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b01 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b10 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] }; |
end |
|
// Okay, now ... writing our FIFO ... |
reg pre_fifo_addr_inc_rd; |
reg pre_fifo_addr_inc_wr; |
initial pre_fifo_addr_inc_rd = 1'b0; |
initial pre_fifo_addr_inc_wr = 1'b0; |
always @(posedge i_clk) |
pre_fifo_addr_inc_wr <= ((ll_fifo_wr)&&(ll_out_stb)&&(r_have_start_token)); |
always @(posedge i_clk) |
pre_fifo_addr_inc_rd <= ((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle));//&&(ll_fifo_pkt_state[2:0]!=3'b000)); |
always @(posedge i_clk) |
begin |
// if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)&&(i_wb_data[11])) |
// ll_fifo_addr <= {(LGFIFOLN+2){1'b0}}; |
if (~r_cmd_busy) |
ll_fifo_addr <= {(LGFIFOLN+2){1'b0}}; |
else if ((pre_fifo_addr_inc_wr)||(pre_fifo_addr_inc_rd)) |
ll_fifo_addr <= ll_fifo_addr + 1; |
end |
|
// Look for that start token |
always @(posedge i_clk) |
if (~r_cmd_busy) |
r_have_start_token <= 1'b0; |
else if ((ll_fifo_wr)&&(ll_out_stb)&&(ll_out_dat==8'hfe)) |
r_have_start_token <= 1'b1; |
|
reg last_fifo_byte; |
initial last_fifo_byte = 1'b0; |
always @(posedge i_clk) |
if (ll_fifo_wr) |
last_fifo_byte <= (ll_fifo_addr == w_blklimit); |
else |
last_fifo_byte <= 1'b0; |
|
// This is the one (and only allowed) write to the FIFO memory always |
// block. |
// |
// If ll_fifo_wr is true, we'll be writing to the FIFO, and we'll do |
// that here. This is different from r_fifo_wr, which specifies that |
// we will be writing to the SDCard from the FIFO, and hence READING |
// from the FIFO. |
// |
reg pre_fifo_a_wr, pre_fifo_b_wr, pre_fifo_crc_a, pre_fifo_crc_b, |
clear_fifo_crc; |
always @(posedge i_clk) |
begin |
pre_fifo_a_wr <= (ll_fifo_wr)&&(ll_out_stb)&&(~r_fifo_id)&&(ll_fifo_wr_state == 2'b00); |
pre_fifo_b_wr <= (ll_fifo_wr)&&(ll_out_stb)&&( r_fifo_id)&&(ll_fifo_wr_state == 2'b00); |
fifo_wr_crc_stb <= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b00)&&(r_have_start_token); |
pre_fifo_crc_a<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b01); |
pre_fifo_crc_b<= (ll_fifo_wr)&&(ll_out_stb)&&(ll_fifo_wr_state == 2'b10); |
clear_fifo_crc <= (cmd_stb)&&(i_wb_data[15]); |
end |
|
initial fifo_crc_err = 1'b0; |
always @(posedge i_clk) |
begin // One and only memory write allowed |
if ((write_stb)&&(i_wb_addr[1:0]==2'b10)) |
{fifo_a_mem[{ fifo_wb_addr, 2'b00 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b01 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b10 }], |
fifo_a_mem[{ fifo_wb_addr, 2'b11 }] } |
<= i_wb_data; |
else if (pre_fifo_a_wr) |
fifo_a_mem[{ ll_fifo_addr }] <= ll_out_dat; |
|
if ((write_stb)&&(i_wb_addr[1:0]==2'b11)) |
{fifo_b_mem[{fifo_wb_addr, 2'b00 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b01 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b10 }], |
fifo_b_mem[{ fifo_wb_addr, 2'b11 }] } |
<= i_wb_data; |
else if (pre_fifo_b_wr) |
fifo_b_mem[{ ll_fifo_addr }] <= ll_out_dat; |
|
if (~r_cmd_busy) |
ll_fifo_wr_complete <= 1'b0; |
|
if (~r_cmd_busy) |
ll_fifo_wr_state <= 2'b00; |
else if ((pre_fifo_a_wr)||(pre_fifo_b_wr)) |
ll_fifo_wr_state <= (last_fifo_byte)? 2'b01:2'b00; |
|
if (pre_fifo_crc_a) |
begin |
fifo_crc_err <= fifo_crc_err | (fifo_wr_crc_reg[15:8]!=ll_out_dat); |
ll_fifo_wr_state <= ll_fifo_wr_state + 2'b01; |
end if (pre_fifo_crc_b) |
begin |
fifo_crc_err <= fifo_crc_err | (fifo_wr_crc_reg[7:0]!=ll_out_dat); |
ll_fifo_wr_state <= ll_fifo_wr_state + 2'b01; |
ll_fifo_wr_complete <= 1'b1; |
end else if (clear_fifo_crc) |
fifo_crc_err <= 1'b0; |
end |
|
always @(posedge i_clk) |
begin // Second memory read, this time for the FIFO |
fifo_a_byte <= fifo_a_mem[ ll_fifo_addr ]; |
fifo_b_byte <= fifo_b_mem[ ll_fifo_addr ]; |
end |
|
reg [(LGFIFOLN-1):0] r_blklimit; |
wire [(LGFIFOLN+1):0] w_blklimit; |
always @(posedge i_clk) |
r_blklimit[(LGFIFOLN-1):0] = (1<<r_lgblklen)-1; |
assign w_blklimit = { r_blklimit, 2'b11 }; |
|
// Package the FIFO reads up into a packet |
always @(posedge i_clk) |
begin |
fifo_rd_crc_stb <= 1'b0; |
if (r_cmd_busy) |
begin |
if (ll_fifo_pkt_state[2:0] == 3'b000) |
begin |
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
ll_fifo_pkt_state <= ll_fifo_pkt_state + 3'b001; |
end |
end else if (ll_fifo_pkt_state[2:0] == 3'b001) |
begin |
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
ll_fifo_pkt_state <= ll_fifo_pkt_state + 3'b001; |
fifo_byte <= (r_fifo_id) |
? fifo_b_byte : fifo_a_byte; |
fifo_rd_crc_stb <= 1'b1; |
end |
end else if (ll_fifo_pkt_state[2:0] == 3'b010) |
begin |
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
fifo_byte <= (r_fifo_id) |
? fifo_b_byte : fifo_a_byte; |
fifo_rd_crc_stb <= 1'b1; |
end |
if (ll_fifo_addr == 0) |
ll_fifo_pkt_state <= 3'b011; |
end else if (ll_fifo_pkt_state == 3'b011) |
begin // 1st CRC byte |
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
fifo_byte <= fifo_rd_crc_reg[15:8]; |
ll_fifo_pkt_state <= 3'b100; |
end |
end else if (ll_fifo_pkt_state == 3'b100) |
begin // 2nd CRC byte |
if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
fifo_byte <= fifo_rd_crc_reg[7:0]; |
ll_fifo_pkt_state <= 3'b101; |
end |
end else if((ll_fifo_rd)&&(ll_cmd_stb)&&(ll_idle)) |
begin |
// Idle the channel |
ll_fifo_rd_complete <= 1'b1; |
fifo_byte <= 8'hff; |
end |
end else if ((write_stb)&&(i_wb_addr == `SDSPI_CMD_ADDRESS)) |
begin |
ll_fifo_pkt_state <= 3'h0; |
ll_fifo_rd_complete <= 1'b0; |
fifo_byte <= (i_wb_data[12]) ? fifo_b_byte : fifo_a_byte; |
fifo_rd_crc_stb <= 1'b1; |
end else begin // Packet state is IDLE (clear the CRC registers) |
ll_fifo_pkt_state <= 3'b111; |
ll_fifo_rd_complete <= 1'b1; |
end |
end |
|
always @(posedge i_clk) |
begin |
if (~ll_fifo_wr) |
fifo_wr_crc_reg <= 16'h00; |
else if (fifo_wr_crc_stb) |
begin |
fifo_wr_crc_reg[15:8] <=fifo_wr_crc_reg[15:8]^ll_out_dat; |
fifo_wr_crc_count <= 4'h8; |
end else if (|fifo_wr_crc_count) |
begin |
fifo_wr_crc_count <= fifo_wr_crc_count - 4'h1; |
if (fifo_wr_crc_reg[15]) |
fifo_wr_crc_reg <= { fifo_wr_crc_reg[14:0], 1'b0 } |
^ 16'h1021; |
else |
fifo_wr_crc_reg <= { fifo_wr_crc_reg[14:0], 1'b0 }; |
end |
end |
|
always @(posedge i_clk) |
begin |
if (~r_cmd_busy) |
begin |
fifo_rd_crc_reg <= 16'h00; |
fifo_rd_crc_count <= 4'h0; |
end else if (fifo_rd_crc_stb) |
begin |
fifo_rd_crc_reg[15:8] <=fifo_rd_crc_reg[15:8]^fifo_byte; |
fifo_rd_crc_count <= 4'h8; |
end else if (|fifo_rd_crc_count) |
begin |
fifo_rd_crc_count <= fifo_rd_crc_count - 4'h1; |
if (fifo_rd_crc_reg[15]) |
fifo_rd_crc_reg <= { fifo_rd_crc_reg[14:0], 1'b0 } |
^ 16'h1021; |
else |
fifo_rd_crc_reg <= { fifo_rd_crc_reg[14:0], 1'b0 }; |
end |
end |
|
// |
// Calculate a CRC for the command section of our output |
// |
initial r_cmd_crc_ff = 1'b0; |
always @(posedge i_clk) |
begin |
if (~r_cmd_busy) |
begin |
r_cmd_crc <= 8'h00; |
r_cmd_crc_cnt <= 4'hf; |
r_cmd_crc_ff <= 1'b0; |
end else if (~r_cmd_crc_cnt[3]) |
begin |
r_cmd_crc_cnt <= r_cmd_crc_cnt - 4'h1; |
if (r_cmd_crc[7]) |
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 } ^ 8'h12; |
else |
r_cmd_crc <= { r_cmd_crc[6:0], 1'b0 }; |
r_cmd_crc_ff <= (r_cmd_crc_ff)||(r_cmd_crc_stb); |
end else if ((r_cmd_crc_stb)||(r_cmd_crc_ff)) |
begin |
r_cmd_crc <= r_cmd_crc ^ ll_cmd_dat; |
r_cmd_crc_cnt <= 4'h7; |
r_cmd_crc_ff <= 1'b0; |
end |
end |
assign cmd_crc = { r_cmd_crc[7:1], 1'b1 }; |
|
// |
// Some watchdog logic for us. This way, if we are waiting for the |
// card to respond, and something goes wrong, we can timeout the |
// transaction and ... figure out what to do about it later. At least |
// we'll have an error indication. |
// |
initial r_watchdog = 26'h3ffffff; |
initial r_watchdog_err = 1'b0; |
always @(posedge i_clk) |
if (~r_cmd_busy) |
r_watchdog_err <= 1'b0; |
else if (r_watchdog == 0) |
r_watchdog_err <= 1'b1; |
always @(posedge i_clk) |
if (~r_cmd_busy) |
r_watchdog <= 26'h3fffff; |
else if (|r_watchdog) |
r_watchdog <= r_watchdog - 26'h1; |
|
assign o_debug = { ((ll_cmd_stb)&&(ll_idle))||(ll_out_stb), |
ll_cmd_stb, ll_idle, ll_out_stb, // 4'h |
o_cs_n, o_sck, o_mosi, i_miso, // 4'h |
r_cmd_state, i_bus_grant, // 4'h |
r_rsp_state, r_cmd_busy, // 4'h |
ll_cmd_dat, // 8'b |
ll_out_dat }; // 8'b |
endmodule |
|
/trunk/rtl/Makefile
0,0 → 1,12
all: rtl export.v |
# VOB := $(HOME)/src/verilog/vopro |
VOB := cat |
VOBJ:= obj_dir |
|
.PHONY: rtl |
rtl: $(VOBJ)/Vsdspi.h |
$(VOBJ)/Vsdspi.h: sdspi.v llsdspi.v |
verilator -cc sdspi.v |
|
export.v: sdspi.v llsdspi.v |
$(VOB) $^ > $@ |
/trunk/rtl/llsdspi.v
0,0 → 1,230
//////////////////////////////////////////////////////////////////////////////// |
// |
// Filename: llsdspi.v |
// |
// Project: SD-Card controller, using a shared SPI interface |
// |
// Purpose: This file implements the "lower-level" interface to the |
// SD-Card controller. Specifically, it turns byte-level |
// interaction requests into SPI bit-wise interactions. Further, it |
// handles the request and grant for the SPI wires (i.e., it requests |
// the SPI port by pulling o_cs_n low, and then waits for i_bus_grant |
// to be true before continuing.). Finally, the speed/clock rate of the |
// communication is adjustable as a division of the current clock rate. |
// |
// i_speed |
// This is the number of clocks (minus one) between SPI clock |
// transitions. Hence a '0' (not tested, doesn't work) would |
// result in a SPI clock that alternated on every input clock |
// equivalently dividing the input clock by two, whereas a '1' |
// would divide the input clock by four. |
// |
// In general, the SPI clock frequency will be given by the |
// master clock frequency divided by twice this number plus one. |
// In other words, |
// |
// SPIFREQ=(i_clk FREQ) / (2*(i_speed+1)) |
// |
// i_stb |
// True if the master controller is requesting to send a byte. |
// This will be ignored unless o_idle is false. |
// |
// i_byte |
// The byte that the master controller wishes to send across the |
// interface. |
// |
// (The external SPI interface) |
// |
// o_stb |
// Only true for one clock--when a byte is valid coming in from the |
// interface, this will be true for one clock (a strobe) indicating |
// that a valid byte is ready to be read. |
// |
// o_byte |
// The value of the byte coming in. |
// |
// o_idle |
// True if this low-level device handler is ready to accept a |
// byte from the incoming interface, false otherwise. |
// |
// i_bus_grant |
// True if the SPI bus has been granted to this interface, false |
// otherwise. This has been placed here so that the interface of |
// the XuLA2 board may be shared between SPI-Flash and the SPI |
// based SDCard. An external arbiter will determine which of the |
// two gets to control the clock and mosi outputs given their |
// cs_n requests. If control is not granted, i_bus_grant will |
// remain low as will the actual cs_n going out of the FPGA. |
// |
// |
// |
// Creator: Dan Gisselquist, Ph.D. |
// Gisselquist Technology, LLC |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// Copyright (C) 2016, Gisselquist Technology, LLC |
// |
// This program is free software (firmware): you can redistribute it and/or |
// modify it under the terms of the GNU General Public License as published |
// by the Free Software Foundation, either version 3 of the License, or (at |
// your option) any later version. |
// |
// This program is distributed in the hope that it will be useful, but WITHOUT |
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with this program. (It's in the $(ROOT)/doc directory, run make with no |
// target there if the PDF file isn't present.) If not, see |
// <http://www.gnu.org/licenses/> for a copy. |
// |
// License: GPL, v3, as defined and found on www.gnu.org, |
// http://www.gnu.org/licenses/gpl.html |
// |
// |
//////////////////////////////////////////////////////////////////////////////// |
// |
// |
`define LLSDSPI_IDLE 4'h0 |
`define LLSDSPI_HOTIDLE 4'h1 |
`define LLSDSPI_WAIT 4'h2 |
`define LLSDSPI_START 4'h3 |
// |
module llsdspi(i_clk, i_speed, i_cs, i_stb, i_byte, |
o_cs_n, o_sclk, o_mosi, i_miso, |
o_stb, o_byte, o_idle, i_bus_grant); |
parameter SPDBITS = 7; |
// |
input i_clk; |
// Parameters/setup |
input [(SPDBITS-1):0] i_speed; |
// The incoming interface |
input i_cs; |
input i_stb; |
input [7:0] i_byte; |
// The actual SPI interface |
output reg o_cs_n, o_sclk, o_mosi; |
input i_miso; |
// The outgoing interface |
output reg o_stb; |
output reg [7:0] o_byte; |
output wire o_idle; |
// And whether or not we actually own the interface (yet) |
input i_bus_grant; |
|
reg r_z_counter; |
reg [(SPDBITS-1):0] r_clk_counter; |
reg r_idle; |
reg [3:0] r_state; |
reg [7:0] r_byte, r_ireg; |
|
wire byte_accepted; |
assign byte_accepted = (i_stb)&&(o_idle); |
|
initial r_clk_counter = 7'h0; |
always @(posedge i_clk) |
begin |
if ((~i_cs)||(~i_bus_grant)) |
r_clk_counter <= 0; |
else if (byte_accepted) |
r_clk_counter <= i_speed; |
else if (~r_z_counter) |
r_clk_counter <= (r_clk_counter - {{(SPDBITS-1){1'b0}},1'b1}); |
else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE)) |
r_clk_counter <= (i_speed); |
// else |
// r_clk_counter <= 16'h00; |
end |
|
initial r_z_counter = 1'b1; |
always @(posedge i_clk) |
begin |
if ((~i_cs)||(~i_bus_grant)) |
r_z_counter <= 1'b1; |
else if (byte_accepted) |
r_z_counter <= 1'b0; |
else if (~r_z_counter) |
r_z_counter <= (r_clk_counter == 1); |
else if ((r_state != `LLSDSPI_IDLE)&&(r_state != `LLSDSPI_HOTIDLE)) |
r_z_counter <= 1'b0; |
end |
|
initial r_state = `LLSDSPI_IDLE; |
always @(posedge i_clk) |
begin |
o_stb <= 1'b0; |
o_cs_n <= ~i_cs; |
if (~i_cs) |
begin |
r_state <= `LLSDSPI_IDLE; |
r_idle <= 1'b0; |
o_sclk <= 1'b1; |
end else if (~r_z_counter) |
begin |
r_idle <= 1'b0; |
if (byte_accepted) |
begin // Will only happen within a hot idle state |
r_byte <= { i_byte[6:0], 1'b1 }; |
r_state <= `LLSDSPI_START+1; |
o_mosi <= i_byte[7]; |
end |
end else if (r_state == `LLSDSPI_IDLE) |
begin |
o_sclk <= 1'b1; |
if (byte_accepted) |
begin |
r_byte <= i_byte[7:0]; |
r_state <= (i_bus_grant)?`LLSDSPI_START:`LLSDSPI_WAIT; |
r_idle <= 1'b0; |
o_mosi <= i_byte[7]; |
end else begin |
r_idle <= 1'b1; |
end |
end else if (r_state == `LLSDSPI_WAIT) |
begin |
r_idle <= 1'b0; |
if (i_bus_grant) |
r_state <= `LLSDSPI_START; |
end else if (r_state == `LLSDSPI_HOTIDLE) |
begin |
// The clock is low, the bus is granted, we're just |
// waiting for the next byte to transmit |
o_sclk <= 1'b0; |
if (byte_accepted) |
begin |
r_byte <= i_byte[7:0]; |
r_state <= `LLSDSPI_START; |
r_idle <= 1'b0; |
o_mosi <= i_byte[7]; |
end else |
r_idle <= 1'b1; |
// end else if (r_state == `LLSDSPI_START) |
// begin |
// o_sclk <= 1'b0; |
// r_state <= r_state + 1; |
end else if (o_sclk) |
begin |
o_mosi <= r_byte[7]; |
r_byte <= { r_byte[6:0], 1'b1 }; |
r_state <= r_state + 1; |
o_sclk <= 1'b0; |
if (r_state >= `LLSDSPI_START+8) |
begin |
r_state <= `LLSDSPI_HOTIDLE; |
r_idle <= 1'b1; |
o_stb <= 1'b1; |
o_byte <= r_ireg; |
end else |
r_state <= r_state + 1; |
end else begin |
r_ireg <= { r_ireg[6:0], i_miso }; |
o_sclk <= 1'b1; |
end |
end |
|
assign o_idle = (r_idle)&&( (i_cs)&&(i_bus_grant) ); |
endmodule |
|
|
/trunk/doc/spec.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
trunk/doc/spec.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/doc/src/gpl-3.0.tex
===================================================================
--- trunk/doc/src/gpl-3.0.tex (nonexistent)
+++ trunk/doc/src/gpl-3.0.tex (revision 2)
@@ -0,0 +1,719 @@
+\documentclass[11pt]{article}
+
+\title{GNU GENERAL PUBLIC LICENSE}
+\date{Version 3, 29 June 2007}
+
+\begin{document}
+\maketitle
+
+\begin{center}
+{\parindent 0in
+
+Copyright \copyright\ 2007 Free Software Foundation, Inc. \texttt{http://fsf.org/}
+
+\bigskip
+Everyone is permitted to copy and distribute verbatim copies of this
+
+license document, but changing it is not allowed.}
+
+\end{center}
+
+\renewcommand{\abstractname}{Preamble}
+\begin{abstract}
+The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works. By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users. We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors. You can apply it to
+your programs, too.
+
+When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights. Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received. You must make sure that they, too, receive
+or can get the source code. And you must show them these terms so they
+know their rights.
+
+Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software. For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
+can do so. This is fundamentally incompatible with the aim of
+protecting users' freedom to change the software. The systematic
+pattern of such abuse occurs in the area of products for individuals to
+use, which is precisely where it is most unacceptable. Therefore, we
+have designed this version of the GPL to prohibit the practice for those
+products. If such problems arise substantially in other domains, we
+stand ready to extend this provision to those domains in future versions
+of the GPL, as needed to protect the freedom of users.
+
+Finally, every program is threatened constantly by software patents.
+States should not allow patents to restrict development and use of
+software on general-purpose computers, but in those that do, we wish to
+avoid the special danger that patents applied to a free program could
+make it effectively proprietary. To prevent this, the GPL assures that
+patents cannot be used to render the program non-free.
+
+The precise terms and conditions for copying, distribution and
+modification follow.
+\end{abstract}
+
+\begin{center}
+{\Large \sc Terms and Conditions}
+\end{center}
+
+
+\begin{enumerate}
+
+\addtocounter{enumi}{-1}
+
+\item Definitions.
+
+``This License'' refers to version 3 of the GNU General Public License.
+
+``Copyright'' also means copyright-like laws that apply to other kinds of
+works, such as semiconductor masks.
+
+``The Program'' refers to any copyrightable work licensed under this
+License. Each licensee is addressed as ``you''. ``Licensees'' and
+``recipients'' may be individuals or organizations.
+
+To ``modify'' a work means to copy from or adapt all or part of the work
+in a fashion requiring copyright permission, other than the making of an
+exact copy. The resulting work is called a ``modified version'' of the
+earlier work or a work ``based on'' the earlier work.
+
+A ``covered work'' means either the unmodified Program or a work based
+on the Program.
+
+To ``propagate'' a work means to do anything with it that, without
+permission, would make you directly or secondarily liable for
+infringement under applicable copyright law, except executing it on a
+computer or modifying a private copy. Propagation includes copying,
+distribution (with or without modification), making available to the
+public, and in some countries other activities as well.
+
+To ``convey'' a work means any kind of propagation that enables other
+parties to make or receive copies. Mere interaction with a user through
+a computer network, with no transfer of a copy, is not conveying.
+
+An interactive user interface displays ``Appropriate Legal Notices''
+to the extent that it includes a convenient and prominently visible
+feature that (1) displays an appropriate copyright notice, and (2)
+tells the user that there is no warranty for the work (except to the
+extent that warranties are provided), that licensees may convey the
+work under this License, and how to view a copy of this License. If
+the interface presents a list of user commands or options, such as a
+menu, a prominent item in the list meets this criterion.
+
+\item Source Code.
+
+The ``source code'' for a work means the preferred form of the work
+for making modifications to it. ``Object code'' means any non-source
+form of a work.
+
+A ``Standard Interface'' means an interface that either is an official
+standard defined by a recognized standards body, or, in the case of
+interfaces specified for a particular programming language, one that
+is widely used among developers working in that language.
+
+The ``System Libraries'' of an executable work include anything, other
+than the work as a whole, that (a) is included in the normal form of
+packaging a Major Component, but which is not part of that Major
+Component, and (b) serves only to enable use of the work with that
+Major Component, or to implement a Standard Interface for which an
+implementation is available to the public in source code form. A
+``Major Component'', in this context, means a major essential component
+(kernel, window system, and so on) of the specific operating system
+(if any) on which the executable work runs, or a compiler used to
+produce the work, or an object code interpreter used to run it.
+
+The ``Corresponding Source'' for a work in object code form means all
+the source code needed to generate, install, and (for an executable
+work) run the object code and to modify the work, including scripts to
+control those activities. However, it does not include the work's
+System Libraries, or general-purpose tools or generally available free
+programs which are used unmodified in performing those activities but
+which are not part of the work. For example, Corresponding Source
+includes interface definition files associated with source files for
+the work, and the source code for shared libraries and dynamically
+linked subprograms that the work is specifically designed to require,
+such as by intimate data communication or control flow between those
+subprograms and other parts of the work.
+
+The Corresponding Source need not include anything that users
+can regenerate automatically from other parts of the Corresponding
+Source.
+
+The Corresponding Source for a work in source code form is that
+same work.
+
+\item Basic Permissions.
+
+All rights granted under this License are granted for the term of
+copyright on the Program, and are irrevocable provided the stated
+conditions are met. This License explicitly affirms your unlimited
+permission to run the unmodified Program. The output from running a
+covered work is covered by this License only if the output, given its
+content, constitutes a covered work. This License acknowledges your
+rights of fair use or other equivalent, as provided by copyright law.
+
+You may make, run and propagate covered works that you do not
+convey, without conditions so long as your license otherwise remains
+in force. You may convey covered works to others for the sole purpose
+of having them make modifications exclusively for you, or provide you
+with facilities for running those works, provided that you comply with
+the terms of this License in conveying all material for which you do
+not control copyright. Those thus making or running the covered works
+for you must do so exclusively on your behalf, under your direction
+and control, on terms that prohibit them from making any copies of
+your copyrighted material outside their relationship with you.
+
+Conveying under any other circumstances is permitted solely under
+the conditions stated below. Sublicensing is not allowed; section 10
+makes it unnecessary.
+
+\item Protecting Users' Legal Rights From Anti-Circumvention Law.
+
+No covered work shall be deemed part of an effective technological
+measure under any applicable law fulfilling obligations under article
+11 of the WIPO copyright treaty adopted on 20 December 1996, or
+similar laws prohibiting or restricting circumvention of such
+measures.
+
+When you convey a covered work, you waive any legal power to forbid
+circumvention of technological measures to the extent such circumvention
+is effected by exercising rights under this License with respect to
+the covered work, and you disclaim any intention to limit operation or
+modification of the work as a means of enforcing, against the work's
+users, your or third parties' legal rights to forbid circumvention of
+technological measures.
+
+\item Conveying Verbatim Copies.
+
+You may convey verbatim copies of the Program's source code as you
+receive it, in any medium, provided that you conspicuously and
+appropriately publish on each copy an appropriate copyright notice;
+keep intact all notices stating that this License and any
+non-permissive terms added in accord with section 7 apply to the code;
+keep intact all notices of the absence of any warranty; and give all
+recipients a copy of this License along with the Program.
+
+You may charge any price or no price for each copy that you convey,
+and you may offer support or warranty protection for a fee.
+
+\item Conveying Modified Source Versions.
+
+You may convey a work based on the Program, or the modifications to
+produce it from the Program, in the form of source code under the
+terms of section 4, provided that you also meet all of these conditions:
+ \begin{enumerate}
+ \item The work must carry prominent notices stating that you modified
+ it, and giving a relevant date.
+
+ \item The work must carry prominent notices stating that it is
+ released under this License and any conditions added under section
+ 7. This requirement modifies the requirement in section 4 to
+ ``keep intact all notices''.
+
+ \item You must license the entire work, as a whole, under this
+ License to anyone who comes into possession of a copy. This
+ License will therefore apply, along with any applicable section 7
+ additional terms, to the whole of the work, and all its parts,
+ regardless of how they are packaged. This License gives no
+ permission to license the work in any other way, but it does not
+ invalidate such permission if you have separately received it.
+
+ \item If the work has interactive user interfaces, each must display
+ Appropriate Legal Notices; however, if the Program has interactive
+ interfaces that do not display Appropriate Legal Notices, your
+ work need not make them do so.
+\end{enumerate}
+A compilation of a covered work with other separate and independent
+works, which are not by their nature extensions of the covered work,
+and which are not combined with it such as to form a larger program,
+in or on a volume of a storage or distribution medium, is called an
+``aggregate'' if the compilation and its resulting copyright are not
+used to limit the access or legal rights of the compilation's users
+beyond what the individual works permit. Inclusion of a covered work
+in an aggregate does not cause this License to apply to the other
+parts of the aggregate.
+
+\item Conveying Non-Source Forms.
+
+You may convey a covered work in object code form under the terms
+of sections 4 and 5, provided that you also convey the
+machine-readable Corresponding Source under the terms of this License,
+in one of these ways:
+ \begin{enumerate}
+ \item Convey the object code in, or embodied in, a physical product
+ (including a physical distribution medium), accompanied by the
+ Corresponding Source fixed on a durable physical medium
+ customarily used for software interchange.
+
+ \item Convey the object code in, or embodied in, a physical product
+ (including a physical distribution medium), accompanied by a
+ written offer, valid for at least three years and valid for as
+ long as you offer spare parts or customer support for that product
+ model, to give anyone who possesses the object code either (1) a
+ copy of the Corresponding Source for all the software in the
+ product that is covered by this License, on a durable physical
+ medium customarily used for software interchange, for a price no
+ more than your reasonable cost of physically performing this
+ conveying of source, or (2) access to copy the
+ Corresponding Source from a network server at no charge.
+
+ \item Convey individual copies of the object code with a copy of the
+ written offer to provide the Corresponding Source. This
+ alternative is allowed only occasionally and noncommercially, and
+ only if you received the object code with such an offer, in accord
+ with subsection 6b.
+
+ \item Convey the object code by offering access from a designated
+ place (gratis or for a charge), and offer equivalent access to the
+ Corresponding Source in the same way through the same place at no
+ further charge. You need not require recipients to copy the
+ Corresponding Source along with the object code. If the place to
+ copy the object code is a network server, the Corresponding Source
+ may be on a different server (operated by you or a third party)
+ that supports equivalent copying facilities, provided you maintain
+ clear directions next to the object code saying where to find the
+ Corresponding Source. Regardless of what server hosts the
+ Corresponding Source, you remain obligated to ensure that it is
+ available for as long as needed to satisfy these requirements.
+
+ \item Convey the object code using peer-to-peer transmission, provided
+ you inform other peers where the object code and Corresponding
+ Source of the work are being offered to the general public at no
+ charge under subsection 6d.
+ \end{enumerate}
+
+A separable portion of the object code, whose source code is excluded
+from the Corresponding Source as a System Library, need not be
+included in conveying the object code work.
+
+A ``User Product'' is either (1) a ``consumer product'', which means any
+tangible personal property which is normally used for personal, family,
+or household purposes, or (2) anything designed or sold for incorporation
+into a dwelling. In determining whether a product is a consumer product,
+doubtful cases shall be resolved in favor of coverage. For a particular
+product received by a particular user, ``normally used'' refers to a
+typical or common use of that class of product, regardless of the status
+of the particular user or of the way in which the particular user
+actually uses, or expects or is expected to use, the product. A product
+is a consumer product regardless of whether the product has substantial
+commercial, industrial or non-consumer uses, unless such uses represent
+the only significant mode of use of the product.
+
+``Installation Information'' for a User Product means any methods,
+procedures, authorization keys, or other information required to install
+and execute modified versions of a covered work in that User Product from
+a modified version of its Corresponding Source. The information must
+suffice to ensure that the continued functioning of the modified object
+code is in no case prevented or interfered with solely because
+modification has been made.
+
+If you convey an object code work under this section in, or with, or
+specifically for use in, a User Product, and the conveying occurs as
+part of a transaction in which the right of possession and use of the
+User Product is transferred to the recipient in perpetuity or for a
+fixed term (regardless of how the transaction is characterized), the
+Corresponding Source conveyed under this section must be accompanied
+by the Installation Information. But this requirement does not apply
+if neither you nor any third party retains the ability to install
+modified object code on the User Product (for example, the work has
+been installed in ROM).
+
+The requirement to provide Installation Information does not include a
+requirement to continue to provide support service, warranty, or updates
+for a work that has been modified or installed by the recipient, or for
+the User Product in which it has been modified or installed. Access to a
+network may be denied when the modification itself materially and
+adversely affects the operation of the network or violates the rules and
+protocols for communication across the network.
+
+Corresponding Source conveyed, and Installation Information provided,
+in accord with this section must be in a format that is publicly
+documented (and with an implementation available to the public in
+source code form), and must require no special password or key for
+unpacking, reading or copying.
+
+\item Additional Terms.
+
+``Additional permissions'' are terms that supplement the terms of this
+License by making exceptions from one or more of its conditions.
+Additional permissions that are applicable to the entire Program shall
+be treated as though they were included in this License, to the extent
+that they are valid under applicable law. If additional permissions
+apply only to part of the Program, that part may be used separately
+under those permissions, but the entire Program remains governed by
+this License without regard to the additional permissions.
+
+When you convey a copy of a covered work, you may at your option
+remove any additional permissions from that copy, or from any part of
+it. (Additional permissions may be written to require their own
+removal in certain cases when you modify the work.) You may place
+additional permissions on material, added by you to a covered work,
+for which you have or can give appropriate copyright permission.
+
+Notwithstanding any other provision of this License, for material you
+add to a covered work, you may (if authorized by the copyright holders of
+that material) supplement the terms of this License with terms:
+ \begin{enumerate}
+ \item Disclaiming warranty or limiting liability differently from the
+ terms of sections 15 and 16 of this License; or
+
+ \item Requiring preservation of specified reasonable legal notices or
+ author attributions in that material or in the Appropriate Legal
+ Notices displayed by works containing it; or
+
+ \item Prohibiting misrepresentation of the origin of that material, or
+ requiring that modified versions of such material be marked in
+ reasonable ways as different from the original version; or
+
+ \item Limiting the use for publicity purposes of names of licensors or
+ authors of the material; or
+
+ \item Declining to grant rights under trademark law for use of some
+ trade names, trademarks, or service marks; or
+
+ \item Requiring indemnification of licensors and authors of that
+ material by anyone who conveys the material (or modified versions of
+ it) with contractual assumptions of liability to the recipient, for
+ any liability that these contractual assumptions directly impose on
+ those licensors and authors.
+ \end{enumerate}
+
+All other non-permissive additional terms are considered ``further
+restrictions'' within the meaning of section 10. If the Program as you
+received it, or any part of it, contains a notice stating that it is
+governed by this License along with a term that is a further
+restriction, you may remove that term. If a license document contains
+a further restriction but permits relicensing or conveying under this
+License, you may add to a covered work material governed by the terms
+of that license document, provided that the further restriction does
+not survive such relicensing or conveying.
+
+If you add terms to a covered work in accord with this section, you
+must place, in the relevant source files, a statement of the
+additional terms that apply to those files, or a notice indicating
+where to find the applicable terms.
+
+Additional terms, permissive or non-permissive, may be stated in the
+form of a separately written license, or stated as exceptions;
+the above requirements apply either way.
+
+\item Termination.
+
+You may not propagate or modify a covered work except as expressly
+provided under this License. Any attempt otherwise to propagate or
+modify it is void, and will automatically terminate your rights under
+this License (including any patent licenses granted under the third
+paragraph of section 11).
+
+However, if you cease all violation of this License, then your
+license from a particular copyright holder is reinstated (a)
+provisionally, unless and until the copyright holder explicitly and
+finally terminates your license, and (b) permanently, if the copyright
+holder fails to notify you of the violation by some reasonable means
+prior to 60 days after the cessation.
+
+Moreover, your license from a particular copyright holder is
+reinstated permanently if the copyright holder notifies you of the
+violation by some reasonable means, this is the first time you have
+received notice of violation of this License (for any work) from that
+copyright holder, and you cure the violation prior to 30 days after
+your receipt of the notice.
+
+Termination of your rights under this section does not terminate the
+licenses of parties who have received copies or rights from you under
+this License. If your rights have been terminated and not permanently
+reinstated, you do not qualify to receive new licenses for the same
+material under section 10.
+
+\item Acceptance Not Required for Having Copies.
+
+You are not required to accept this License in order to receive or
+run a copy of the Program. Ancillary propagation of a covered work
+occurring solely as a consequence of using peer-to-peer transmission
+to receive a copy likewise does not require acceptance. However,
+nothing other than this License grants you permission to propagate or
+modify any covered work. These actions infringe copyright if you do
+not accept this License. Therefore, by modifying or propagating a
+covered work, you indicate your acceptance of this License to do so.
+
+\item Automatic Licensing of Downstream Recipients.
+
+Each time you convey a covered work, the recipient automatically
+receives a license from the original licensors, to run, modify and
+propagate that work, subject to this License. You are not responsible
+for enforcing compliance by third parties with this License.
+
+An ``entity transaction'' is a transaction transferring control of an
+organization, or substantially all assets of one, or subdividing an
+organization, or merging organizations. If propagation of a covered
+work results from an entity transaction, each party to that
+transaction who receives a copy of the work also receives whatever
+licenses to the work the party's predecessor in interest had or could
+give under the previous paragraph, plus a right to possession of the
+Corresponding Source of the work from the predecessor in interest, if
+the predecessor has it or can get it with reasonable efforts.
+
+You may not impose any further restrictions on the exercise of the
+rights granted or affirmed under this License. For example, you may
+not impose a license fee, royalty, or other charge for exercise of
+rights granted under this License, and you may not initiate litigation
+(including a cross-claim or counterclaim in a lawsuit) alleging that
+any patent claim is infringed by making, using, selling, offering for
+sale, or importing the Program or any portion of it.
+
+\item Patents.
+
+A ``contributor'' is a copyright holder who authorizes use under this
+License of the Program or a work on which the Program is based. The
+work thus licensed is called the contributor's ``contributor version''.
+
+A contributor's ``essential patent claims'' are all patent claims
+owned or controlled by the contributor, whether already acquired or
+hereafter acquired, that would be infringed by some manner, permitted
+by this License, of making, using, or selling its contributor version,
+but do not include claims that would be infringed only as a
+consequence of further modification of the contributor version. For
+purposes of this definition, ``control'' includes the right to grant
+patent sublicenses in a manner consistent with the requirements of
+this License.
+
+Each contributor grants you a non-exclusive, worldwide, royalty-free
+patent license under the contributor's essential patent claims, to
+make, use, sell, offer for sale, import and otherwise run, modify and
+propagate the contents of its contributor version.
+
+In the following three paragraphs, a ``patent license'' is any express
+agreement or commitment, however denominated, not to enforce a patent
+(such as an express permission to practice a patent or covenant not to
+sue for patent infringement). To ``grant'' such a patent license to a
+party means to make such an agreement or commitment not to enforce a
+patent against the party.
+
+If you convey a covered work, knowingly relying on a patent license,
+and the Corresponding Source of the work is not available for anyone
+to copy, free of charge and under the terms of this License, through a
+publicly available network server or other readily accessible means,
+then you must either (1) cause the Corresponding Source to be so
+available, or (2) arrange to deprive yourself of the benefit of the
+patent license for this particular work, or (3) arrange, in a manner
+consistent with the requirements of this License, to extend the patent
+license to downstream recipients. ``Knowingly relying'' means you have
+actual knowledge that, but for the patent license, your conveying the
+covered work in a country, or your recipient's use of the covered work
+in a country, would infringe one or more identifiable patents in that
+country that you have reason to believe are valid.
+
+If, pursuant to or in connection with a single transaction or
+arrangement, you convey, or propagate by procuring conveyance of, a
+covered work, and grant a patent license to some of the parties
+receiving the covered work authorizing them to use, propagate, modify
+or convey a specific copy of the covered work, then the patent license
+you grant is automatically extended to all recipients of the covered
+work and works based on it.
+
+A patent license is ``discriminatory'' if it does not include within
+the scope of its coverage, prohibits the exercise of, or is
+conditioned on the non-exercise of one or more of the rights that are
+specifically granted under this License. You may not convey a covered
+work if you are a party to an arrangement with a third party that is
+in the business of distributing software, under which you make payment
+to the third party based on the extent of your activity of conveying
+the work, and under which the third party grants, to any of the
+parties who would receive the covered work from you, a discriminatory
+patent license (a) in connection with copies of the covered work
+conveyed by you (or copies made from those copies), or (b) primarily
+for and in connection with specific products or compilations that
+contain the covered work, unless you entered into that arrangement,
+or that patent license was granted, prior to 28 March 2007.
+
+Nothing in this License shall be construed as excluding or limiting
+any implied license or other defenses to infringement that may
+otherwise be available to you under applicable patent law.
+
+\item No Surrender of Others' Freedom.
+
+If conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot convey a
+covered work so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you may
+not convey it at all. For example, if you agree to terms that obligate you
+to collect a royalty for further conveying from those to whom you convey
+the Program, the only way you could satisfy both those terms and this
+License would be to refrain entirely from conveying the Program.
+
+\item Use with the GNU Affero General Public License.
+
+Notwithstanding any other provision of this License, you have
+permission to link or combine any covered work with a work licensed
+under version 3 of the GNU Affero General Public License into a single
+combined work, and to convey the resulting work. The terms of this
+License will continue to apply to the part which is the covered work,
+but the special requirements of the GNU Affero General Public License,
+section 13, concerning interaction through a network will apply to the
+combination as such.
+
+\item Revised Versions of this License.
+
+The Free Software Foundation may publish revised and/or new versions of
+the GNU General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the
+Program specifies that a certain numbered version of the GNU General
+Public License ``or any later version'' applies to it, you have the
+option of following the terms and conditions either of that numbered
+version or of any later version published by the Free Software
+Foundation. If the Program does not specify a version number of the
+GNU General Public License, you may choose any version ever published
+by the Free Software Foundation.
+
+If the Program specifies that a proxy can decide which future
+versions of the GNU General Public License can be used, that proxy's
+public statement of acceptance of a version permanently authorizes you
+to choose that version for the Program.
+
+Later license versions may give you additional or different
+permissions. However, no additional obligations are imposed on any
+author or copyright holder as a result of your choosing to follow a
+later version.
+
+\item Disclaimer of Warranty.
+
+\begin{sloppypar}
+ THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
+ APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE
+ COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS''
+ WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED,
+ INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE
+ RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU.
+ SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL
+ NECESSARY SERVICING, REPAIR OR CORRECTION.
+\end{sloppypar}
+
+\item Limitation of Liability.
+
+ IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN
+ WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES
+ AND/OR CONVEYS THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR
+ DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL
+ DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM
+ (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED
+ INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE
+ OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH
+ HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ DAMAGES.
+
+\item Interpretation of Sections 15 and 16.
+
+If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+\begin{center}
+{\Large\sc End of Terms and Conditions}
+
+\bigskip
+How to Apply These Terms to Your New Programs
+\end{center}
+
+If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the ``copyright'' line and a pointer to where the full notice is found.
+
+{\footnotesize
+\begin{verbatim}
+
+
+Copyright (C)
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see .
+\end{verbatim}
+}
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+{\footnotesize
+\begin{verbatim}
+ Copyright (C)
+
+This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+This is free software, and you are welcome to redistribute it
+under certain conditions; type `show c' for details.
+\end{verbatim}
+}
+
+The hypothetical commands {\tt show w} and {\tt show c} should show
+the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an ``about box''.
+
+You should also get your employer (if you work as a programmer) or
+school, if any, to sign a ``copyright disclaimer'' for the program, if
+necessary. For more information on this, and how to apply and follow
+the GNU GPL, see \texttt{http://www.gnu.org/licenses/}.
+
+The GNU General Public License does not permit incorporating your
+program into proprietary programs. If your program is a subroutine
+library, you may consider it more useful to permit linking proprietary
+applications with the library. If this is what you want to do, use
+the GNU Lesser General Public License instead of this License. But
+first, please read \texttt{http://www.gnu.org/philosophy/why-not-lgpl.html}.
+
+\end{enumerate}
+
+\end{document}
Index: trunk/doc/src/GT.eps
===================================================================
--- trunk/doc/src/GT.eps (nonexistent)
+++ trunk/doc/src/GT.eps (revision 2)
@@ -0,0 +1,94 @@
+%!PS-Adobe-3.0 EPSF-3.0
+%%BoundingBox: 0 0 504 288
+%%Creator: Gisselquist Technology LLC
+%%Title: Gisselquist Technology Logo
+%%CreationDate: 11 Mar 2014
+%%EndComments
+%%BeginProlog
+/black { 0 setgray } def
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+
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+ newpath
+ height 2 div 1.25 mul height moveto
+ height 2 div height 4 div sub height lineto
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+ height height 4 div lineto
+ height height 2 div lineto
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+ height lw sub height 2 div lineto
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+ height 3 4 div mul lw 2 div sub lw lineto
+ height 4 div lw 2 div add lw lineto
+ lw height 4 div lw 2 div add lineto
+ lw height 3 4 div mul lw 2 div sub lineto
+ height 4 div lw 2 div add height lw sub lineto
+ height 2 div 1.25 mul height lw sub lineto
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+ height 2 div height 2 div moveto
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+height 2 div 1.25 mul lw add 0 translate
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+ 0 lw rlineto
+ closepath fill
+} if
+
+true { % The "T" of "GT".
+ newpath
+ 0 height moveto
+ height lw add 2 div 0 rlineto
+ 0 height neg rlineto
+ lw neg 0 rlineto
+ 0 height lw sub rlineto
+ height lw sub 2 div neg 0 rlineto
+ closepath fill
+
+ % The right half of the top of the "T"
+ newpath
+ % (height + lw)/2 + lw
+ height lw add 2 div lw add height moveto
+ % height - (above) = height - height/2 - 3/2 lw = height/2-3/2lw
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+
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+showpage
+%%EOF
Index: trunk/doc/src/gqtekspec.cls
===================================================================
--- trunk/doc/src/gqtekspec.cls (nonexistent)
+++ trunk/doc/src/gqtekspec.cls (revision 2)
@@ -0,0 +1,298 @@
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%/
+%
+% Copyright (C) 2015, Gisselquist Technology, LLC
+%
+% This template is free software: you can redistribute it and/or modify it
+% under the terms of the GNU General Public License as published by the
+% Free Software Foundation, either version 3 of the License, or (at your
+% option) any later version.
+%
+% This template is distributed in the hope that it will be useful, but WITHOUT
+% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+% for more details.
+%
+% You should have received a copy of the GNU General Public License along
+% with this program. If not, see for a copy.
+%
+% License: GPL, v3, as defined and found on www.gnu.org,
+% http://www.gnu.org/licenses/gpl.html
+%
+%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+% \NeedsTeXFormat{LaTeX2e}[1995/12/01]
+\ProvidesClass{gqtekspec}[2015/03/03 v0.1 -- Gisselquist Technology Specification]
+\typeout{by Dan Gisselquist}
+\LoadClassWithOptions{report}
+\usepackage{datetime}
+\usepackage{graphicx}
+\usepackage[dvips]{pstricks}
+\usepackage{hhline}
+\usepackage{colortbl}
+\definecolor{webgreen}{rgb}{0,0.5,0}
+\usepackage[dvips,colorlinks=true,linkcolor=webgreen]{hyperref}
+\newdateformat{headerdate}{\THEYEAR/\twodigit{\THEMONTH}/\twodigit{\THEDAY}}
+\setlength{\hoffset}{0.25in}
+\setlength{\voffset}{-0.5in}
+\setlength{\marginparwidth}{0in}
+\setlength{\marginparsep}{0in}
+\setlength{\textwidth}{6in}
+\setlength{\oddsidemargin}{0in}
+
+% **************************************
+% * APPENDIX *
+% **************************************
+%
+\newcommand\appfl@g{\appendixname} %used to test \@chapapp
+%
+% \renewcommand\appendix{\par\clearpage
+ % \setcounter{chapter}{0}%
+ % \setcounter{section}{0}%
+ % \renewcommand\@chapapp{\appendixname}%
+ % \renewcommand\thechapter{\Alph{chapter}}
+ % \if@nosectnum\else
+ % \renewcommand\thesection{\Alph{chapter}.\arabic{section}}
+ % \fi
+% }
+
+
+% FIGURE
+% redefine the @caption command to put a period after the figure or
+% table number in the lof and lot tables
+\long\def\@caption#1[#2]#3{\par\addcontentsline{\csname
+ ext@#1\endcsname}{#1}{\protect\numberline{\csname
+ the#1\endcsname.}{\ignorespaces #2}}\begingroup
+ \@parboxrestore
+ \normalsize
+ \@makecaption{\csname fnum@#1\endcsname}{\ignorespaces #3}\par
+ \endgroup}
+
+% ****************************************
+% * TABLE OF CONTENTS, ETC. *
+% ****************************************
+
+\renewcommand\contentsname{Contents}
+\renewcommand\listfigurename{Figures}
+\renewcommand\listtablename{Tables}
+
+\newif\if@toc \@tocfalse
+\renewcommand\tableofcontents{%
+ \begingroup% temporarily set if@toc so that \@schapter will not
+ % put Table of Contents in the table of contents.
+ \@toctrue
+ \chapter*{\contentsname}
+ \endgroup
+ \thispagestyle{gqtekspecplain}
+
+ \baselineskip=10pt plus .5pt minus .5pt
+
+ {\raggedleft Page \par\vskip-\parskip}
+ \@starttoc{toc}%
+ \baselineskip=\normalbaselineskip
+ }
+
+\def\l@appendix{\pagebreak[3]
+ \vskip 1.0em plus 1pt % space above appendix line
+ \@dottedtocline{0}{0em}{8em}}
+
+\def\l@chapter{\pagebreak[3]
+ \vskip 1.0em plus 1pt % space above appendix line
+ \@dottedtocline{0}{0em}{4em}}
+
+% \if@nosectnum\else
+ % \renewcommand\l@section{\@dottedtocline{1}{5.5em}{2.4em}}
+ % \renewcommand\l@subsection{\@dottedtocline{2}{8.5em}{3.2em}}
+ % \renewcommand\l@subsubsection{\@dottedtocline{3}{11em}{4.1em}}
+ % \renewcommand\l@paragraph{\@dottedtocline{4}{13.5em}{5em}}
+ % \renewcommand\l@subparagraph{\@dottedtocline{5}{16em}{6em}}
+% \fi
+
+% LIST OF FIGURES
+%
+\def\listoffigures{%
+ \begingroup
+ \chapter*{\listfigurename}%
+ \endgroup
+ \thispagestyle{gqtekspecplain}%
+
+ \baselineskip=10pt plus .5pt minus .5pt%
+
+ {\hbox to \hsize{Figure\hfil Page} \par\vskip-\parskip}%
+
+ \rule[2mm]{\textwidth}{0.5mm}\par
+
+ \@starttoc{lof}%
+ \baselineskip=\normalbaselineskip}%
+
+\def\l@figure{\@dottedtocline{1}{1em}{4.0em}}
+
+% LIST OF TABLES
+%
+\def\listoftables{%
+ \begingroup
+ \chapter*{\listtablename}%
+ \endgroup
+ \thispagestyle{gqtekspecplain}%
+ \baselineskip=10pt plus .5pt minus .5pt%
+ {\hbox to \hsize{Table\hfil Page} \par\vskip-\parskip}%
+
+ % Added line underneath headings, 20 Jun 01, Capt Todd Hale.
+ \rule[2mm]{\textwidth}{0.5mm}\par
+
+ \@starttoc{lot}%
+ \baselineskip=\normalbaselineskip}%
+
+\let\l@table\l@figure
+
+% ****************************************
+% * PAGE STYLES *
+% ****************************************
+%
+\def\ps@gqtekspectoc{%
+ \let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspectocn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm \hfil\raisebox{10pt}{Page}}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspectocn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspeclof{\let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspeclofn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm
+ \parbox{\textwidth}{\raisebox{0pt}{Figure}\hfil\raisebox{0pt}{Page} %
+ \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }}
+
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclofn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspeclot{\let\@mkboth\@gobbletwo
+ \def \@oddhead{}
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+\def\ps@gqtekspeclotn{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rm
+ \parbox{\textwidth}{\raisebox{0pt}{Table}\hfil\raisebox{0pt}{Page} %
+ \raisebox{20pt}{\rule[10pt]{\textwidth}{0.5mm}} }}
+
+ \def \@oddfoot{\rm
+ \hfil\raisebox{-9pt}{\thepage}\hfil\thispagestyle{gqtekspeclotn}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+\def\ps@gqtekspecplain{\let\@mkboth\@gobbletwo
+ \def \@oddhead{\rput(0,-2pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{\includegraphics[height=0.8\headheight]{GT.eps} Gisselquist Technology, LLC}\hfil\hbox{\@title}\hfil\hbox to 1in{\hfil\headerdate\@date}}
+ \def \@oddfoot{\rput(0,9pt){\psline(0,0)(\textwidth,0)}\rm \hbox to 1in{www.opencores.com\hfil}\hfil\hbox{\r@vision}\hfil\hbox to 1in{\hfil{\thepage}}}
+ \let \@evenhead\@oddhead \let \@evenfoot\@oddfoot}
+
+% \def\author#1{\def\auth@r{#1}}
+% \def\title#1{\def\ti@tle{#1}}
+
+\def\logo{\begin{pspicture}(0,0)(5.67in,0.75in)
+ \rput[lb](0.05in,0.10in){\includegraphics[height=0.75in]{GT.eps}}
+ \rput[lb](1.15in,0.05in){\scalebox{1.8}{\parbox{2.0in}{Gisselquist\\Technology, LLC}}}
+ \end{pspicture}}
+% TITLEPAGE
+%
+\def\titlepage{\setcounter{page}{1}
+ \typeout{^^JTitle Page.}
+ \thispagestyle{empty}
+ \leftline{\rput(0,0){\psline(0,0)(\textwidth,0)}\hfill}
+ \vskip 2\baselineskip
+ \logo\hfil % Original is 3.91 in x 1.26 in, let's match V thus
+ \vskip 2\baselineskip
+ \vspace*{10pt}\vfil
+ \begin{minipage}{\textwidth}\raggedleft
+ \ifproject{\Huge\bfseries\MakeUppercase\@project} \\\fi
+ \vspace*{15pt}
+ {\Huge\bfseries\MakeUppercase\@title} \\
+ \vskip 10\baselineskip
+ \Large \@author \\
+ \ifemail{\Large \@email}\\\fi
+ \vskip 6\baselineskip
+ \Large \usdate\@date \\
+ \end{minipage}
+ % \baselineskip 22.5pt\large\rm\MakeUppercase\ti@tle
+ \vspace*{30pt}
+ \vfil
+ \newpage\baselineskip=\normalbaselineskip}
+
+\newenvironment{license}{\clearpage\typeout{^^JLicense Page.}\ \vfill\noindent}%
+ {\vfill\newpage}
+% ****************************************
+% * CHAPTER DEFINITIONS *
+% ****************************************
+%
+\renewcommand\chapter{\if@openright\cleardoublepage\else\clearpage\fi
+ \thispagestyle{gqtekspecplain}%
+ \global\@topnum\z@
+ \@afterindentfalse
+ \secdef\@chapter\@schapter}
+\renewcommand\@makechapterhead[1]{%
+ \hbox to \textwidth{\hfil{\Huge\bfseries \thechapter.}}\vskip 10\p@
+ \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip \p@
+ \hbox to \textwidth{\rput(0,0){\psline[linewidth=0.04in](0,0)(\textwidth,0)}}\vskip 10\p@
+ \hbox to \textwidth{\hfill{\Huge\bfseries #1}}%
+ \par\nobreak\vskip 40\p@}
+\renewcommand\@makeschapterhead[1]{%
+ \hbox to \textwidth{\hfill{\Huge\bfseries #1}}%
+ \par\nobreak\vskip 40\p@}
+% ****************************************
+% * INITIALIZATION *
+% ****************************************
+%
+% Default initializations
+
+\ps@gqtekspecplain % 'gqtekspecplain' page style with lowered page nos.
+\onecolumn % Single-column.
+\pagenumbering{roman} % the first chapter will change pagenumbering
+ % to arabic
+\setcounter{page}{1} % in case a titlepage is not requested
+ % otherwise titlepage sets page to 1 since the
+ % flyleaf is not counted as a page
+\widowpenalty 10000 % completely discourage widow lines
+\clubpenalty 10000 % completely discourage club (orphan) lines
+\raggedbottom % don't force alignment of bottom of pages
+
+\date{\today}
+\newif\ifproject\projectfalse
+\def\project#1{\projecttrue\gdef\@project{#1}}
+\def\@project{}
+\newif\ifemail\emailfalse
+\def\email#1{\emailtrue\gdef\@email{#1}}
+\def\@email{}
+\def\revision#1{\gdef\r@vision{#1}}
+\def\r@vision{}
+\def\at{\makeatletter @\makeatother}
+\newdateformat{theyear}{\THEYEAR}
+\newenvironment{revisionhistory}{\clearpage\typeout{^^JRevision History.}%
+ \hbox to \textwidth{\hfil\scalebox{1.8}{\large\bfseries Revision History}}\vskip 10\p@\noindent%
+ \begin{tabular}{|p{0.5in}|p{1in}|p{1in}|p{2.875in}|}\hline
+ \rowcolor[gray]{0.8} Rev. & Date & Author & Description\\\hline\hline}
+ {\end{tabular}\clearpage}
+\newenvironment{clocklist}{\begin{tabular}{|p{0.75in}|p{0.5in}|l|l|p{2.875in}|}\hline
+ \rowcolor[gray]{0.85} Name & Source & \multicolumn{2}{l|}{Rates (MHz)} & Description \\\hhline{~|~|-|-|~}%
+ \rowcolor[gray]{0.85} & & Max & Min & \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{reglist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.5in}|p{0.5in}|p{2.875in}|}\hline
+ \rowcolor[gray]{0.85} Name & Address & Width & Access & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{bitlist}{\begin{tabular}{|p{0.5in}|p{0.5in}|p{3.875in}|}\hline
+ \rowcolor[gray]{0.85} Bit \# & Access & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{portlist}{\begin{tabular}{|p{0.75in}|p{0.5in}|p{0.75in}|p{3.375in}|}\hline
+ \rowcolor[gray]{0.85} Port & Width & Direction & Description \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{wishboneds}{\begin{tabular}{|p{2.5in}|p{2.5in}|}\hline
+ \rowcolor[gray]{0.85} Description & Specification \\\hline\hline}%
+ {\end{tabular}}
+\newenvironment{preface}{\chapter*{Preface}}{\par\bigskip\bigskip\leftline{\hfill\@author}}
+\endinput
Index: trunk/doc/src/spec.tex
===================================================================
--- trunk/doc/src/spec.tex (nonexistent)
+++ trunk/doc/src/spec.tex (revision 2)
@@ -0,0 +1,799 @@
+\documentclass{gqtekspec}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%% Filename: spec.tex
+%%
+%% Project: SD-Card controller, using a shared SPI interface
+%%
+%% Purpose: This LaTeX file contains all of the documentation/description
+%% currently provided with the SDSPI controller core. For those
+%% looking into here, this document is not nearly as interesting as the
+%% spec.pdf file it creates, so I'd strongly recommend reading that before
+%% diving into this document. However, if you are interested in producing
+%% documents looking like this one, or using LaTeX in a similar fashion,
+%% you may find this document of use.
+%%
+%% You should be able to find the PDF this file produces in the SVN
+%% distribution together with this LaTeX file and a copy of the GPL-3.0
+%% license this file is distributed under. If not, just type 'make' in
+%% the doc directory (one up from this one), and it (should) build both
+%% pdf's without a problem.
+%%
+%% Creator: Dan Gisselquist, Ph.D.
+%% Gisselquist Technology, LLC
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%% Copyright (C) 2016, Gisselquist Technology, LLC
+%%
+%% This program is free software (firmware): you can redistribute it and/or
+%% modify it under the terms of the GNU General Public License as published
+%% by the Free Software Foundation, either version 3 of the License, or (at
+%% your option) any later version.
+%%
+%% This program is distributed in the hope that it will be useful, but WITHOUT
+%% ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+%% FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+%% for more details.
+%%
+%% You should have received a copy of the GNU General Public License along
+%% with this program. (It's in the $(ROOT)/doc directory, run make with no
+%% target there if the PDF file isn't present.) If not, see
+%% for a copy.
+%%
+%% License: GPL, v3, as defined and found on www.gnu.org,
+%% http://www.gnu.org/licenses/gpl.html
+%%
+%%
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+%%
+%%
+\usepackage{import}
+\usepackage{bytefield}
+\project{SDSPI Controller}
+\title{Specification}
+\author{Dan Gisselquist, Ph.D.}
+\email{dgisselq (at) opencores.org}
+\revision{Rev.~0.1}
+\begin{document}
+\pagestyle{gqtekspecplain}
+\titlepage
+\begin{license}
+Copyright (C) \theyear\today, Gisselquist Technology, LLC
+
+This project is free software (firmware): you can redistribute it and/or
+modify it under the terms of the GNU General Public License as published
+by the Free Software Foundation, either version 3 of the License, or (at
+your option) any later version.
+
+This program is distributed in the hope that it will be useful, but WITHOUT
+ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program. If not, see \texttt{http://www.gnu.org/licenses/} for a copy.
+\end{license}
+\begin{revisionhistory}
+0.1 & 6/18/2016 & Gisselquist & First Draft \\\hline
+\end{revisionhistory}
+% Revision History
+% Table of Contents, named Contents
+\tableofcontents
+\listoffigures
+\listoftables
+\begin{preface}
+When I started this project, I was informed that other projects similar to this
+one existed. The OpenRISC project has used an SD--Card controller, for example,
+as has the Google project vault. Of these two, the first uses the full SD--Card
+interface which is unavailable on the XuLA2 board, and I could never find the
+code for the second.
+
+Still, had I found such interfaces, I would've still had another reason for
+building my own: controlling the license. By rolling my own interface, I can
+offer it to anyone interested in it under the GPL license, such as you have
+here. Further, by not using code belonging to others, I am not restricted or
+encumbered by any of their licenses--whether it be the GPL or otherwise. This
+code, and specification document, are therefore completely the product of
+Gisselquist Technology, LLC.
+
+That said, I am indebted to Mr.~Tambe for sharing his interface. While the
+current work does not use his approach and represents a complete rewrite, his
+approach was valuable in helping me understand what the SD--Card specification
+meant at several points along the way.
+\end{preface}
+
+\chapter{Introduction}
+\pagenumbering{arabic}
+\setcounter{page}{1}
+
+% What is old
+This Verilog core exports an SD card controller interface from internal to an
+FPGA to the rest of the FPGA core, while taking care of the lower level details
+internal to the interface.
+% What does the old lack?
+Unlike the other OpenCores SD Card controller\footnote{See
+\texttt{http://www.opencores.org/project,sdcard\_mass\_storage\_controller}.}
+which offers a full SD--interface, this controller focuses on the SPI interface
+of the SD Card. While this is a slower interface, the SPI interface is
+necessary to access the card when using a XuLA2
+board\footnote{See \texttt{http://www.xess.com/shop/product/xula2-lx25/}}, or
+in general any time the full 9--bit, bi--directional interface to the SD card
+has not been implemented.
+Further, for those who are die--hard Verilog authors, this core is written in
+Verilog as opposed to the XESS provided demonstration SD Card controller
+found on GitHub\footnote{See
+\texttt{https://github.com/xesscorp/VHDL\_Lib/SDCard.vhd}}, which was written
+in VHDL. For those who are not such die--hard Verilog authors, this controller
+provides a lower level interface to the card than these other controllers.
+Whereas the XESS controller will automatically start up the card and interact
+with it, this controller requires external software to be used when interacting
+with the card. This makes the SDSPI controller both more versatile, in the
+face of potential changes to the card interface, but also less--turn key.
+% What is new
+% What does the new have that the old lacks
+% What performance gain can be expected?
+
+While this core was written for the purpose of being used with the ZipCPU,
+as enhanced by the Wishbone DMA controller used by the ZipCPU, nothing in this
+core prevents it from being used with any other architecture that supports
+the 32--bit Wishbone interface of this core.
+
+This core has been written as a wishbone slave, not a master. Using the core
+together with a separate master, such as a CPU or a DMA controller, only makes
+sense. This design, however, also restricts the core from being able to use
+the multiple block write or multiple block read commands, restricting us to
+single block read and write commands alone.
+
+\chapter{Architecture}\label{ch:arch}
+
+This SD Card interface is designed to provide a means of commanding an SD Card,
+via the SPI port, and returning its results.
+
+The first thing to know about the SDSPI interface is that it is designed to work
+over a shared SPI port. Hence, when the SDSPI controller lowers the CS line to
+select the SD--Card, the lowered line is only a request to an external
+controller. Once that external controller grants access to the SPI port to this
+device, it will tell this controller and processing can continue. If your
+application does not have any contention for the SPI interface, you may simply
+wire this grant line high. The controller will still work, although it will
+wait one clock more than necessary in that case before starting any transaction.
+
+Second, the SDSPI core is completely controlled via the wishbone bus. In
+particular a command register is used to initiate interaction across the bus.
+A separate data register is used to provide an argument to the command, and
+two FIFO registers are used when transferring larger amounts of data to the
+card. We'll examine each of these interactions in turn.
+
+Writes to the command register (CMD) will initiate actions across the port,
+whether they be reads from or writes to the card. These writes take the
+form of sending a 48--bit command to the card. The command sent to the card
+is taken from the lower 8--bits of the command register, and the argument to the
+command is taken from the DATA register. The last 8--bits of the command sent
+to the card are formed from a command CRC byte which the core generates
+internally. From the perspective of the Wishbone bus, writes to the register
+will complete immediately, even though the action they initiate will may take
+much longer to complete. Further, writes made to the CMD register will be
+silently ignored if the device is already busy.
+
+Reads from the CMD register will always return immediately. In particular, the
+{\tt busy} bit, as returned by the CMD register, can be used to determine if the
+interface is busy.
+
+There is one exception to the rule that writes take many clocks to complete,
+and that is writes which configure the SDSPI port. Internal to the SDSPI
+port is a configuration register, which determines the speed of the port
+clock as well as the length of the FIFO (up to 128~samples, or 512--bytes).
+To read the current speed and FIFO configuration, write an {\tt 0x00bf} value to
+the command register. This will cause the DATA register to be filled with
+the internal configuration register. Likewise writing a {\tt 0x0ff} to the
+CMD register will cause the current DATA value, or specifically those non-zero
+parts, to be transferred to the internal configuration register possibly setting
+the clock divider and/or the FIFO length.
+
+As part of each write to the CMD register, the controller must also be told
+which type of response to expect from the SDSPI card. Responses can be either
+R1 (single byte), R1b (single byte, followed by a variable delay), or R1
+followed by up to four bytes, such as the R2, R3, or R7 responses.
+(Expected responses for particular commands may be found in the SD
+Specifications documents.\footnote{This particular interface, and the examples
+using it, were built using the SD Specifications, Part 1: Physical Layer
+Simplified Specification, Version 4.10, dated 22 January, 2013.}
+
+Finally, individual commands may or may not use the FIFO. Commands that need
+use of the FIFO will be specified by the {\tt use\_fifo} bit of the CMD
+register. Commands writing to the device will also set the {\tt fifo\_wr} bit
+of the CMD register, whereas commands simply reading from the fifo will set the
+{\tt use\_fifo} bit alone.
+
+The DATA register is used during these transactions to first provide the
+argument to the CMD interaction, and second to provide a place to put the
+R2, R3, or R7 response after the transaction has completed. The register will
+be set to {\tt 0xffffffff} if not set by the response.
+
+Finally, this core supports two separate FIFO's. This allows a program to
+fill (or read) one FIFO while the second FIFO can be read/written from the
+SD card. The FIFO internal address will be cleared and reset to the beginning
+upon any write to the CMD register. After clearing, the FIFO may be written
+(read) one value at a time. Reading both FIFO's in any interleaved fashion,
+however, is not allowed as they share a common internal address.
+
+Currently, the core will detect two types of errors in the interface. The
+first is a CRC error, and the second a timeout error. Either error will set
+an error bit in the CMD register. Once set, only writing the error bit back
+to the CMD register will clear it.
+
+Now, if this discussion isn't thoroughly confusing, let's move on to the
+Operation chapter to see some examples of how this might be used.
+
+\chapter{Operation}\label{ch:ops}
+This chapter will walk through some constants that can be used to simplify
+interaction with the controller, the logic necessary to start up the card,
+to read its registers, and then examples of how to read and write sectors
+from the SD Card using this interface.
+
+\section{Constants}
+Since so much of the interface is controlled by the CMD register, it helps to
+define several constants which can be used when issuing commands to the SD
+Card. Lets discuss some of these constants.
+
+First, as discussed in the last chapter, the SDSPI core maintains an auxiliary
+register to handle FIFO length and clock speed. To set this register, we
+define {\tt SD\_SETAUX} to {\tt 0x0ff}. Thus, when {\tt SD\_SETAUX} is written
+to the CMD register, the value of the DATA register is transferred to the
+internal configuration. Likewise, we also define {\tt SD\_READAUX} to
+{\tt 0x0bf}. When this value is written to the SD--Card, the internal
+configuration registers value will be copied to the DATA regiseter.
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_SETAUX} & {\tt 0x0ff} \\
+{\tt \#define} & {\tt SD\_READAUX} & {\tt 0x0bf}
+\end{tabular}
+
+Second, every command to the SD--Card starts with a single byte. Of that byte,
+bit-7 must be clear and bit 6 set. For this purpose, we define {\tt SD\_CMD}
+to be {\tt 0x040}. Thus, {\tt SD\_CMD+0} can be used to send an SD command
+{\tt CMD0}, and {\tt SD\_CMD+1} can be used to send an SD command {\tt CMD1}.
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_CMD} & {\tt 0x040}
+\end{tabular}
+
+Third, for those commands that will read an SD--Card register, such as those
+expecting an R2, R3, or R7 response from the card, we define {\tt SD\_READREG}
+to be {\tt 0x0200}. Thus, we can send a CMD8 by writing
+\hbox{\tt SD\_CMD|SD\_READREG} to the port.
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_READREG} & {\tt 0x0200}
+\end{tabular}
+
+The next thing we'll want to be able to do is use the FIFO. There are two
+types of commands that use the FIFO, those that read from the card and those
+that write to the card. Both need the FIFO bit set, so we'll set
+{\tt SD\_FIFO\_OP} to {\tt 0x0800} to be a read operation from the card, and
+the same but with the write bit set {\tt SD\_WRITEOP} will be set to
+{\tt 0x0c00} to write to the card.
+
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_FIFO\_OP} & {\tt 0x800} \\
+{\tt \#define} & {\tt SD\_WRITEOP} & {\tt 0xc00}
+\end{tabular}
+
+Finally, we want to be able to choose which FIFO we are using. For this
+purpose, we define {\tt SD\_ALTFIFO} to be {\tt 0x01000}. When this bitmask
+is included in a command, FIFO number one will be used for the command data,
+otherwise FIFO zero. (Note that this is separate from the DATA register,
+which is still used for any command argument.)
+
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_ALTFIFO} & {\tt 0x1000}
+\end{tabular}
+
+Two other constants are necessary: {\tt SD\_BUSY}, set to {\tt 0x04000}, which
+can be used to test when the SD interface is still busy, and {\tt SD\_ERROR},
+set to {\tt 0x08000} which can be used to tell if an error has occurred.
+Clearing an error may be done by writing {\tt SD\_ERROR} back to the card, but
+to make things simpler we also create {\tt SD\_CLEARERR} for the same purpose.
+
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_BUSY} & {\tt 0x4000} \\
+{\tt \#define} & {\tt SD\_ERROR} & {\tt 0x8000} \\
+{\tt \#define} & {\tt SD\_CLEARERR} & {\tt 0x8000}
+\end{tabular}
+
+The two most important commands, though, are probably going to be those that
+read and write a sector. For these, we shall define {\tt SD\_READ\_SECTOR}
+and {\tt SD\_WRITE\_SECTOR}. As the first is a CMD17 to the card and the second
+a CMD24, these can be defined as:
+
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_READ\_SECTOR} & {\tt ((SD\_CMD|SD\_CLEARERR|SD\_FIFO\_OP)+17)} \\
+{\tt \#define} & {\tt SD\_WRITE\_SECTOR} & {\tt ((SD\_CMD|SD\_CLEARERR|SD\_WRITEOP)+24)}
+\end{tabular}
+
+`Or'ing the {\tt SD\_ALTFIFO} mask to either of these commands will cause the
+interface to read from or write to the alternate FIFO.
+
+As a very last \#define, we can define the macro {\tt SD\_WAIT\_WHILE\_BUSY}
+to wait until the SD operation completes:
+
+\begin{tabular}{lll}
+{\tt \#define} & {\tt SD\_WAIT\_WHILE\_BUSY}&{\tt while(CMD \& SD\_BUSY)}
+\end{tabular}
+
+Alternatively, we could wait for an interrupt instead since the SDSPI core
+will create an interrupt upon completion. For now, and for this example,
+we'll ignore interrupts.
+
+\section{SD--Card Setup}
+Setting up an SD--Card takes a bit of work. There's a series of commands
+and interactions that need to take place with the card before the card can
+be used. You can read about how to do this within the SD--Specification, so
+we won't repeat the how's or why's here. Instead, let's focus for now on
+how this interaction can be made to take place using this controller.
+
+The first step in any start up sequence is to clear the card from any
+prior condition. Hence we wait for the card to be no longer busy (it
+shouldn't be busy anyway), and we then clear any errors:
+\begin{tabbing}
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt CMD} \= {\tt SD\_CLEARERR};
+\end{tabbing}
+
+Now that the controller is idle (which it should've been from startup anyway),
+we can now set up our interface. For this, we'll set our clock rate to 400~KHz.
+The clock division register, sometimes erroneously called the speed, is found
+in the lower eight bits of the soft-core configuration register. The actual
+SPI clock frequency, given this value, will be:
+\begin{eqnarray}
+f_{\mbox{\tiny SDSPI}} &=& \frac{f_{\mbox{\tiny CLK}}}{2\left(\mbox{\tt CLKDIV}+1\right)}
+\end{eqnarray}
+Hence, since the XuLA2-LX25 SoC runs at an 80~MHz clock, setting this value to
+{\tt 0x63} sets the SPI clock to 400~kHz.
+\begin{tabbing}
+{\tt DATA} \= {\tt = 0x063}; \\
+{\tt CMD} \> {\tt = SD\_SETAUX};
+\end{tabbing}
+Note that we could have also set the higher order configuration bits to set
+the size of the FIFO. In particular, the next four bits, bits 8--11, set
+the FIFO length. Setting these to zero will cause the controller to ignore
+the change, whereas setting the value to three will set the FIFO length to
+$4\cdot2^3$ bytes, and setting it to seven will set the FIFO length to the
+nominal $4\cdot 2^7$ or $512$~bytes.
+
+The controller is now ready to send commands to the SD card. The first command
+to the card is always a command zero, with zero data. This is sometimes
+called the \hbox{\tt GO\_IDLE\_STATE} command. We then wait for the
+command to complete:
+\begin{tabbing}
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = SD\_CMD+0;} \\
+{\tt SD\_WAIT\_WHILE\_BUSY;}
+\end{tabbing}
+The card should now be in its idle state.
+
+The next part of the negotiation tells the card whether or not we are able to
+handle high capacity cards. For this, we send a command one,
+\hbox{\tt SEND\_OP\_COND}, with an argument of {\tt 0x40000000} to tell it
+that we are able to support high capacity cards. (An argument of zero would
+mean that we could not.)
+\begin{tabbing}
+{\tt DATA} \= {\tt = 0x40000000;} \\
+{\tt CMD} \> {\tt = SD\_CMD+1;} \\
+{\tt SD\_WAIT\_WHILE\_BUSY;}
+\end{tabbing}
+
+Then the card needs to know what voltage it will be run at. We communicate this
+via a \hbox{\tt SEND\_IF\_COND} command, or CMD8. Since the XuLA2
+only operates the card at 3.3V, we tell the card we wish to run at 3.3V in the
+argument. The last eight bits of the argument, however, are simply to determine
+whether communication has taken place. We set these bits to {\tt 0x0a5},
+although they could be anything. The card will echo this value back in the
+response:
+\begin{tabbing}
+{\tt DATA} \= {\tt = 0x1a5;} \\
+{\tt CMD} \> {\tt = SD\_CMD+8;} \\
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\em // assert((DATA\&0x0ff)==0x01a5);}
+\end{tabbing}
+The card will also echo back the voltage range, if it accepts it. Thus,
+we should receive {\tt 0x01a5} as a response.
+
+The card will now try to start up its own internal state machines. This could
+take a while. We therefore poll the device, and wait for its startup sequence
+to complete:
+\begin{tabbing}
+{\tt bool dev\_busy = false;} \\
+{\tt do \{}\=\\
+\> {\em // CMD55 gives us access to SD specific commands}\\
+\> {\tt DATA = 0;}\\
+\> {\tt CMD = SD\_CMD+55;}\\
+\> {\tt SD\_WAIT\_WHILE\_BUSY;}\\
+\\
+\> {\em // Now we can issue the ACMD41, to get the idle}\\
+\> {\em // status}\\
+\> {\tt DATA = 0x40000000;} \\
+\> {\tt CMD = SD\_CMD+41;} \\
+\> {\tt DATA} \= {\tt = 0x1a5;} \\
+\> {\tt CMD} \> {\tt = SD\_CMD+8;} \\
+\> {\tt SD\_WAIT\_WHILE\_BUSY;} \\
+\\
+\> {\em // The R1 response can be found in the lower 8 bits}\\
+\> {\em // of the CMD register after the command is complete.}\\
+\> {\em // Bit 1 of R1 indicates the card hasn't finished its}\\
+\> {\em // startup}\\
+\> {\tt dev\_busy = CMD\&1;}\\
+{\tt \} while(dev\_busy);}
+\end{tabbing}
+
+\section{Reading Card Registers}
+
+Once the card has started, we can request its operating conditions register,
+or OCR register as it is called. For this, we issue a {\tt READ\_OCR} command,
+or CMD58 by number. Since this command returns a 32--bit value, we use the
+{\tt SD\_READREG} macro as well:
+\begin{tabbing}
+{\tt int OCR;}\\
+\\
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = (SD\_READREG|SD\_CMD)+58;} \\
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt OCR} \= {\tt = DATA;}\\
+\end{tabbing}
+When I issue this command on my card, I get a {\tt 0xc0ff8000} response telling
+me that my card can handle between 2.7 and 3.6~Volts, that it is a higher
+capacity card, and that it has completed its startup sequence.
+
+Now let's switch up to a higher speed, and read the 16--byte Card Specific
+Data (CSD) register field from the card. First, the switch to a 20~MHz clock
+and a 16--byte fifo,
+\begin{tabbing}
+{\tt DATA} \= {\tt = 0x0201}; \\
+{\tt CMD} \> {\tt = SD\_SETAUX};
+\end{tabbing}
+Remember that the {\tt 0x0200} switches to a FIFO of length~$2^2$ words, or
+equivalently $4\cdot 2^2=16$ bytes. Likewise the {\tt 0x01} component switches
+our frequency to 20~MHz. Now we can issue the {\tt SEND\_CSD\_COND}, or
+CMD9, command itself. Note that we didn't need to wait for the {\tt SD\_SETAUX}
+command to complete. Further, since this command is going to read from our
+FIFO, we need to include the {\tt SD\_FIFO\_OP} part of the command:
+\begin{tabbing}
+{\tt int CSD[4];}\\
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = (SD\_FIFO\_OP|SD\_CMD)+9;}
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt for(int i=0; i<4; i++) } \\
+\> {\tt CSD[i] = FIFO[0];}
+\end{tabbing}
+Once the command is complete, we can read the four 32--bit words of the CSD
+register from the FIFO, as shown above. Alternatively, we could have issued
+another command first, before reading that FIFO result.
+
+We could read the Card Identification (CID) register as well, but this would've
+been the same sequence as above, save only that we would've written a
+{\tt (SD\_READREG|SD\_CMD)+10)} to CMD.
+
+Reading the STATUS is similar, only the response to the {\tt SEND\_STATUS}
+command is an 8--bit value from an R2 response, not the 32--bit values of
+the R3 (OCR) or R7 responses. Still, the R2 response is provided in the
+DATA register, so we only need to send {\tt (SD\_READREG|SD\_CMD)+13} to
+the CMD register in order to read its result from the DATA register. The status
+register will be returned in the top eight bits of the DATA register (the
+interface still reads 32--bits, even though the other 24 can be ignored), so:
+\begin{tabbing}
+{\tt int card\_status;}\\
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = (SD\_READREG|SD\_CMD)+13;}
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt card\_status = DATA>>24;}
+\end{tabbing}
+
+As a final register example, let's read the SD Card Configuration Register
+(SCR). This register is read in a fashion very similar to the CSD register,
+except that because of its width the FIFO needs to be set for a shorter
+register width:
+\begin{tabbing}
+{\tt int SCR[2];}\\
+{\em // Set the FIFO length to two words, $2^1$.}\\
+{\tt DATA} \= {\tt = 0x0100}; \\
+{\tt CMD} \> {\tt = SD\_SETAUX};\\
+{\em // Issue an ALT command, to get the other command set.}\\
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = (SD\_CMD)+55;}\\
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\em // Now get the SCR register.}\\
+{\tt DATA} \= {\tt = 0;} \\
+{\tt CMD} \> {\tt = (SD\_FIFO\_OP|SD\_CMD)+51;}\\
+{\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt for(int i=0; i<2; i++) } \\
+\> {\tt SCR[i] = FIFO[0];}\\
+\end{tabbing}
+
+
+\section{Reading and Writing}
+
+For our first example, let's read the boot sector from our card. For this,
+we set our FIFO back to 128~words (512~bytes), and then issue a read sector
+command:
+\begin{tabbing}
+{\tt void} \= {\tt read(int sector\_num, int *buf) \{}\\
+\> {\em // Set the FIFO length to 128 words, $2^7$.}\\
+\> {\tt DATA} \= {\tt = 0x0700}; \\
+\> {\tt CMD} \> {\tt = SD\_SETAUX};\\
+\> {\em // Read from the requested sector}\\
+\> {\tt DATA} \= {\tt = sector\_num;} \\
+\> {\tt CMD} \> {\tt = SD\_READ\_SECTOR;}\\
+\> {\tt SD\_WAIT\_WHILE\_BUSY;} \\
+\> {\tt for(int i=0; i<128; i++) } \\
+\> \> {\tt buf[i] = FIFO[0];}\\
+{\tt \}}
+\end{tabbing}
+
+We could also write to any sector on the card in a very similar fashion:
+\begin{tabbing}
+{\tt void} \= {\tt write(int sector\_num, int *buf) \{}\\
+\> {\em // Set the FIFO length to 128 words, $2^7$.}\\
+\> {\tt DATA} \= {\tt = 0x0700}; \\
+\> {\tt CMD} \> {\tt = SD\_SETAUX};\\
+\> {\em // Fill the FIFO with our data}\\
+\> {\tt for(int i=0; i<128; i++) } \\
+\> \> {\tt FIFO[0] = buf[i];}\\
+\> {\em // Issue the write command}\\
+\> {\tt DATA} \= {\tt = sector\_num;} \\
+\> {\tt CMD} \> {\tt = SD\_WRITE\_SECTOR;}\\
+\> {\tt SD\_WAIT\_WHILE\_BUSY;} \\
+{\tt \}}
+\end{tabbing}
+
+As mentioned in the introductory chapter, this interface does not support
+reading or writing multiple blocks at once. Hence, I expect all interaction
+using this card controller to be accomplished through these two commands:
+reading a single sector, and writing to a single sector.
+
+\chapter{Registers}\label{ch:regs}
+
+As mentioned in the last two chapters, the SDSPI core has only four registers,
+and one internal register. These are shown in Tbl.~\ref{tbl:ioregs}.
+\begin{table}[htbp]
+\begin{center}\begin{reglist}
+CMD &{\tt 0x00} & 32 & R/W & SDSPI Command register\\\hline
+DAT &{\tt 0x01} & 32 & R/W & SDSPI return data/argument register\\\hline
+FIFO[0] &{\tt 0x02} & 32 & R/W & FIFO[0] data\\\hline
+FIFO[1] &{\tt 0x03} & 32 & R/W & FIFO[1] data\\\hline
+CONFIG & & 12 & R/W & Internal configuration register\\\hline
+\end{reglist}
+\caption{I/O Peripheral Registers}\label{tbl:ioregs}
+\end{center}\end{table}
+The most powerful of these is the command register, CMD, so we'll spend most of
+our time discussing that one.
+
+\section{CMD Register}
+Writes to the CMD register will cause the device to act, or if the device is
+already busy then any writes will be ignored. The CMD register itself is
+composed of several packed bit fields, as shown in Fig.~\ref{fig:CMD}.
+\begin{figure}\begin{center}
+\begin{bytefield}[endianness=big]{32}
+\bitheader{0-31}\\
+\bitbox{15}{Unused}
+\bitbox{1}{C}
+\bitbox{1}{E}
+\bitbox{1}{B}
+\bitbox{1}{0}
+\bitbox{1}{I}
+\bitbox{1}{F}
+\bitbox{1}{W}
+\bitbox{2}{R}
+\bitbox{8}{R1/CMD}
+\end{bytefield}
+\caption{CMD Register fields}\label{fig:CMD}
+\end{center}\end{figure}
+Perhaps the most important of these is the R1/CMD field. If bits 7--6 are
+the two bits 2'b01, then the write is a command and the bottom six bits
+specify the rest of the 8--bit command identifier. Once the command is
+complete, these 8--bits represent the R1 response from the device. R1
+should be one while the device is still starting, or zero in the case of no
+error. Further interpretation of this value may be found in the SD--Card
+Specification.
+
+Of next importance is the $R$ field. This specifies the response the
+controller should expect from the card given the command that was issued
+to the card. There are three possible values for this field: $2'b00$, meaning
+the controller should expect an R1 response, $2'b01$, meaning the controller
+should expect an R1b response, and $2'b10$ meaning the controller should
+expect an R2/R3/R7 32--bit response.
+
+The $F$, or FIFO, field should be set if the command being given requires the
+use of the FIFO. $W$ should be set at the same time if the controller will be
+writing to the card from the FIFO, and cleared if the controller will be
+reading from the card into the FIFO. Finally, $I$ specifies which FIFO will
+be used: 0 for the primary, or 1 for the alternate.
+
+While the command is running, the BUSY or $B$ bit will be set.
+
+Once the command has completed, the $E$ bit may be set if either the command
+timed out, or a CRC error was noted while reading from the card. (To detect
+a CRC error when writing to the card, check the R1 response according to the
+SD Card specification.) Errors may be cleared by writing a 1 to this bit.
+Until such time as an error is cleared, the error condition will simply
+persist.
+
+\section{DATA Register}
+Compared to the CMD register, the DATA register is quite simple. Like the
+CMD register, the DATA register may only be written when the interface is
+idle. When issuing a command to the device, the 32--bit argument for the
+command is taken from the DATA register. When reading the results of a device
+command, the DATA register will contain the R2 response in the upper 8--bits,
+or an R3 or R7 response in the full 32--bits.
+
+\section{FIFO Registers}
+The SDSPI controller maintains two 128~word (512~byte) FIFOs. Reads from the
+card will read data into one of the two FIFO's, whereas writes to the card will
+write data out from one of the FIFO's. Which FIFO the card uses is determined
+by the $I$ bit in the CMD register (above).
+
+Further, upon any write to the CMD register, the FIFO address will be set
+to point to the beginning of the FIFO.
+
+The purpose of the FIFO's is to allow one to issue a command to read into one
+FIFO, then when that command is complete to read into a second FIFO. While
+the second command is ongoing, a CPU or DMA may read the data out of the first
+FIFO and place it wherever into memory. Then, when the second read is complete,
+a third read may be issued into the first buffer while the data is read out of
+the second and so forth.
+
+This interleaving approach, sometimes called ping-pong buffering, can also be
+used for writing: Write into one FIFO, issue a write command, write into the
+second FIFO, wait for the first write command to complete, issue a second
+write command, and so forth.
+
+One item to note before closing: there is only one internal address register
+when accessing the FIFO from the wishbone bus. Attempts to read from or write
+to either FIFO from the wishbone bus will increment this address register.
+Interleaved read, or write attempts, such as reading one item from
+FIFO[0] and writing another item to FIFO[1], will each increment the internal
+address pointer so that the result is likely to be undesirable. For this
+reason, it is recommended that only one FIFO be read from or written by the
+wishbone bus at a time.
+
+\section{CONFIG Register}
+The CONFIG register controls the SPI clock rate and the FIFO size.
+Specifically, with regards to the FIFO size, it controls how many bytes will
+be written into the FIFO (which is really of a fixed size) before the expecting
+a CRC, or equivalently how many bytes to read out of the FIFO before adding a
+CRC. The fields of this register are shown in Fig.~\ref{fig:CONFIG}.
+\begin{figure}\begin{center}
+\begin{bytefield}[endianness=big]{32}
+\bitheader{0-31}\\
+\bitbox{8}{Unused}
+\bitbox{8}{Max LgFIFO}
+\bitbox{8}{LgFIFO}
+\bitbox{2}{0}
+\bitbox{6}{CLKDIV}
+\end{bytefield}
+\caption{CONFIG Register fields}\label{fig:CONFIG}
+\end{center}\end{figure}
+
+The CLKDIV field sets a divisor from the current clock to create a SPI clock.
+The minimum value of this field is `1', corresponding to dividing the input
+clock by `4'. As discussed earlier, the input clock will be divided by
+twice this field plus one. Hence, setting this field to one will cause the
+original clock to be divided by $2(1+{\tt CLKDIV})$ or $4$. Thus an 80~MHz
+input clock will become a 20~MHz SPI clock. Setting this value to zero will
+cause the set to be ignored.
+
+The LgFIFO field sets the log, base two, of the FIFO size. The actual FIFO
+size used will be $2^{\mbox{\tiny LGFIFO}}$ words. The maximum size the
+device will support is returned by the {\tt Max LgFIFO} field, which is
+currently set to $7$ for a 128~word (512~byte) FIFO.
+
+To set the CONFIG register, first set the DATA register to the new config
+value (or zero for the fields that will not change), and then write
+{\tt 0x0ff} to the CMD register. Likewise, to read the CONFIG register
+write a {\tt 0x0bf} to the CMD register and read the CONFIG register from the
+DATA register.
+
+\chapter{Wishbone Datasheet}\label{ch:wb}
+Tbl.~\ref{tbl:wishbone}
+\begin{table}[htbp]
+\begin{center}
+\begin{wishboneds}
+Revision level of wishbone & WB B4 spec \\\hline
+Type of interface & Slave, (Block/pipelined) Read/Write \\\hline
+Port size & 32--bit \\\hline
+Port granularity & 32--bit \\\hline
+Maximum Operand Size & 32--bit \\\hline
+Data transfer ordering & Big Endian \\\hline
+Clock constraints & (See below)\\\hline
+Signal Names & \begin{tabular}{ll}
+ Signal Name & Wishbone Equivalent \\\hline
+ {\tt i\_clk} & {\tt CLK\_I} \\
+ {\tt i\_wb\_cyc} & {\tt CYC\_I} \\
+ {\tt i\_wb\_stb} & {\tt STB\_I} \\
+ {\tt i\_wb\_we} & {\tt WE\_I} \\
+ {\tt i\_wb\_addr} & {\tt ADR\_I} \\
+ {\tt i\_wb\_data} & {\tt DAT\_I} \\
+ {\tt o\_wb\_ack} & {\tt ACK\_O} \\
+ {\tt o\_wb\_stall} & {\tt STALL\_O} \\
+ {\tt o\_wb\_data} & {\tt DAT\_O}
+ \end{tabular}\\\hline
+\end{wishboneds}
+\caption{Wishbone Slave Datasheet}\label{tbl:wishbone}
+\end{center}\end{table}
+is required by the wishbone specification, and so it is included here. Note
+that all wishbone operations may be pipelined, to include FIFO operations,
+for speed.
+
+The particular constraint on the clock is not really a wishbone constraint, but
+rather an SD--Card constraint. Not all cards can handle clocks faster than
+25~MHz. For this reason, the wishbone clock, which forms the master clock for
+this entire controller, must be divided down so that the SPI clock is within
+the limits the card can handle.
+
+\chapter{Clocks}\label{ch:clk}
+
+This core is based upon the XuLA2-LX25 SoC design. The XuLA2 development board
+contains one external 12~MHz clock, which is internally boosted within the SoC
+to 80~MHz. This clock is divided by a programmable divider, often set to
+four, to create the 20~MHz clock used to drive the device. (Maximum device
+speed is usually 25MHz, although some devices can run at 50~MHz.) This
+controller does not support setting the SPI clock frequency any faster than
+one quarter of the input clock rate.
+
+\chapter{I/O Ports}\label{ch:io}
+
+Table.~\ref{tbl:ioports}
+\begin{table}[htbp]
+\begin{center}
+\begin{portlist}
+i\_clk & 1 & Input & Clock\\\hline\hline
+i\_wb\_cyc & 1 & Output & Wishbone bus cycle active\\\hline
+i\_wb\_stb & 1 & Output & Wishbone Strobe, true one clock only for each interaction\\\hline
+i\_wb\_we & 1 & Output & Wishbone Write-Enable line\\\hline
+i\_wb\_addr & 2 & Output & Selects our I/O register\\\hline
+i\_wb\_data & 32 & Output & Incoming wishbone bus data\\\hline
+o\_wb\_ack & 1 & Output & Acknowledge a WB request, always true one clock after the request\\\hline
+o\_wb\_stall & 1 & Output & Always zero\\\hline
+o\_wb\_data & 32 & Output & 32--bit wishbone data response\\\hline\hline
+o\_cs\_n & 1 & Output & Chip--select and SPI request line\\\hline
+o\_sck & 1 & Output & SD Card clock\\\hline
+o\_mosi & 1 & Output & Output data wire to the SD Card\\\hline
+i\_miso & 1 & Input & Input data wire from the SD Card\\\hline\hline
+o\_int & 1 & Output & An interrupt line to the CPU controller\\\hline
+i\_bus\_grant & 1 & Input & True if the SDSPI controller is controlling the bus\\\hline
+o\_debug & 32 & Output & See Verilog for details\\\hline
+\end{portlist}
+\caption{List of IO ports}\label{tbl:ioports}
+\end{center}\end{table}
+lists all of the input and output ports to this core. You may notice these
+inputs and outputs are divided into sections: the master clock, the wishbone
+bus, the SPI interface to the card, and three other wires. Of these, the
+last two chapters discussed the wishbone bus interface and the clock. The
+SPI interface should be fairly straightforward, so we'll move on and discuss
+the other three wires.
+
+This controller supports an interrupt line, {\tt o\_int}. Upon completion of
+any operation, when the SPI chip select line is deactivated (raised high),
+{\tt o\_int} will be strobed for one cycle. It is up to the logic using this
+chip to catch and use that interrupt line or ignore it. In particular, it is
+possible to use that interrupt line to trigger a DMA service to move data
+in or out of the FIFO, although the details of that are beyond this discussion
+here.
+
+The second wire, {\tt i\_bus\_grant}, exists because this controller is
+expected to operate together with other SPI controllers that may also wish
+to drive the same three wires ({\tt o\_sck} and {\tt o\_mosi} to the device,
+and {\tt i\_miso} from the device). When the controller therefore lowers the
+{\tt o\_cs\_n} line to make it active, it then waits for {\tt i\_bus\_grant}
+to go high. This is its signal, from the outside world, that its chip has been
+selected and that it is now driving the {\tt o\_sck} and {\tt o\_mosi} pins.
+Should you not need this in your environment, you can simply leave this line
+wired high.
+
+The final bus of 32--wires, {\tt o\_debug}, is defined internally and used
+when/if necessary to debug the core and watch what is going on within it.
+These wires may be left unconnected in most implementations, as they are not
+necessary for using the actually controller.
+
+% Appendices
+% Index
+\end{document}
+
+
Index: trunk/doc/gpl-3.0.pdf
===================================================================
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Index: trunk/doc/gpl-3.0.pdf
===================================================================
--- trunk/doc/gpl-3.0.pdf (nonexistent)
+++ trunk/doc/gpl-3.0.pdf (revision 2)
trunk/doc/gpl-3.0.pdf
Property changes :
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
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Index: trunk/doc/Makefile
===================================================================
--- trunk/doc/Makefile (nonexistent)
+++ trunk/doc/Makefile (revision 2)
@@ -0,0 +1,29 @@
+all: gpl-3.0.pdf spec.pdf
+DSRC := src
+
+gpl-3.0.pdf: $(DSRC)/gpl-3.0.tex
+ latex $(DSRC)/gpl-3.0.tex
+ latex $(DSRC)/gpl-3.0.tex
+ dvips -q -z -t letter -P pdf -o gpl-3.0.ps gpl-3.0.dvi
+ ps2pdf -dAutoRotatePages=/All gpl-3.0.ps gpl-3.0.pdf
+ rm gpl-3.0.dvi gpl-3.0.log gpl-3.0.aux gpl-3.0.ps
+
+spec.pdf: $(DSRC)/spec.tex $(DSRC)/gqtekspec.cls $(DSRC)/GT.eps
+ cd $(DSRC)/; latex spec.tex
+ cd $(DSRC)/; latex spec.tex
+ cd $(DSRC)/; dvips -q -z -t letter -P pdf -o ../spec.ps spec.dvi
+ ps2pdf -dAutoRotatePages=/All spec.ps spec.pdf
+ -grep -i warning $(DSRC)/spec.log
+ @rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log
+ @rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc
+ @rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof
+ @rm -f $(DSRC)/spec.out spec.ps
+
+.PHONY: clean
+clean:
+ rm -f $(DSRC)/spec.dvi $(DSRC)/spec.log
+ rm -f $(DSRC)/spec.aux $(DSRC)/spec.toc
+ rm -f $(DSRC)/spec.lot $(DSRC)/spec.lof
+ rm -f $(DSRC)/spec.out spec.ps spec.pdf
+ rm -f gpl-3.0.pdf
+
Index: trunk/Makefile
===================================================================
--- trunk/Makefile (nonexistent)
+++ trunk/Makefile (revision 2)
@@ -0,0 +1,75 @@
+################################################################################
+##
+## Filename: Makefile
+##
+## Project: SD-Card controller, using a shared SPI interface
+##
+## Purpose: Coordinate building the specification for this core, the
+## Verilator Verilog check, and any bench software.
+##
+## Creator: Dan Gisselquist, Ph.D.
+## Gisselquist Technology, LLC
+##
+################################################################################
+##
+## Copyright (C) 2016, Gisselquist Technology, LLC
+##
+## This program is free software (firmware): you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as published
+## by the Free Software Foundation, either version 3 of the License, or (at
+## your option) any later version.
+##
+## This program is distributed in the hope that it will be useful, but WITHOUT
+## ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with this program. (It's in the $(ROOT)/doc directory, run make with no
+## target there if the PDF file isn't present.) If not, see
+## for a copy.
+##
+## License: GPL, v3, as defined and found on www.gnu.org,
+## http://www.gnu.org/licenses/gpl.html
+##
+##
+################################################################################
+##
+##
+.PHONY: all
+all: verilated bench
+BENCH := `find bench -name Makefile` `find bench -name "*.cpp"` `find bench -name "*.h"`
+RTL := `find rtl -name "*.v"` `find rtl -name Makefile`
+NOTES := # `find . -name "*.txt"` `find . -name "*.html"`
+SW=
+#SW := `find sw -name "*.cpp"` `find sw -name "*.h"` \
+# `find sw -name "*.sh"` `find sw -name "*.py"` \
+# `find sw -name "*.pl"` `find sw -name Makefile`
+DEVSW=
+YYMMDD:=`date +%Y%m%d`
+
+.PHONY: archive
+archive:
+ tar --transform s,^,$(YYMMDD)-sdspi/, -chjf $(YYMMDD)-sdspi.tjz $(BENCH) $(SW) $(RTL) $(NOTES)
+
+.PHONY: verilated
+verilated:
+ cd rtl ; $(MAKE) --no-print-directory
+
+# The documents target does not get, nor should it be, made automatically. This
+# is because the project is intended to be shipped with the documents
+# automatically built, and I don't necessarily expect all those who download
+# this "core" to have LaTeX distribution necessary to rebuild the specification
+# and GPL LaTeX documents into their PDF results.
+.PHONY: doc
+doc:
+ cd doc ; $(MAKE) --no-print-directory
+
+.PHONY: bench
+bench:
+ cd bench/cpp ; $(MAKE) --no-print-directory
+
+#.PHONY: sw
+# sw:
+# cd sw ; $(MAKE) --no-print-directory
+