URL
https://opencores.org/ocsvn/securehash256bits/securehash256bits/trunk
Subversion Repositories securehash256bits
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Rev 4 → Rev 5
/securehash256bits/trunk/sha256compressionCore.vhd
1,4 → 1,4
--(Maximum Frequency: 339.997MHz) |
--(Maximum Frequency: 301.051MHz) |
|
LIBRARY IEEE; |
use IEEE.std_logic_1164.all; |
50,7 → 50,7
end if; |
end process; |
--main_loop_pipe asynchron circuitry |
su1 <= (temp1(5 downto 0) & temp1(31 downto 6)) xor (temp1(10 downto 0) & temp1(31 downto 11)) xor (temp1(24 downto 0) & temp1(31 downto 25)); |
su1 <= (sum(5 downto 0) & sum(31 downto 6)) xor (sum(10 downto 0) & sum(31 downto 11)) xor (sum(24 downto 0) & sum(31 downto 25)); |
ch <= (sum and f) xor ((not sum) and g); |
su0 <= (temp2(1 downto 0) & temp2(31 downto 2)) xor (temp2(12 downto 0) & temp2(31 downto 13)) xor (temp2(21 downto 0) & temp2(31 downto 22)); |
maj <= (temp2 and (b xor c)) xor (b and c); |