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URL https://opencores.org/ocsvn/sha256core/sha256core/trunk

Subversion Repositories sha256core

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    from Rev 1 to Rev 2
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Rev 1 → Rev 2

/trunk/test/sha_256.do
0,0 → 1,40
 
vlib work
 
# libs
 
vcom -explicit -93 "dual_mem.vhd"
vcom -explicit -93 "sha_fun.vhd"
vcom -explicit -93 "ff_bank.vhd"
vcom -explicit -93 "sh_reg.vhd"
vcom -explicit -93 "msg_comp.vhd"
vcom -explicit -93 "sha_256.vhd"
vcom -explicit -93 "tb_sha_256.vhd"
 
# Sim
 
vsim -lib work -t 1ps tb_sha_256
 
view wave
view source
view structure
view signals
add wave *
 
mem load -infile mem/k.mem -format hex tb_sha_256/uut/k_mem
 
add wave \
{sim:/tb_sha_256/uut/k_mem/* }
 
add wave \
{sim:/tb_sha_256/uut/state }
 
add wave \
{sim:/tb_sha_256/uut/message_compression/t_1 } \
{sim:/tb_sha_256/uut/message_compression/t_2 }
add wave \
{sim:/tb_sha_256/uut/message_compression/w_i } \
{sim:/tb_sha_256/uut/message_compression/k_i }
 
run 16 us
 
/trunk/test/tb_sha_256.vhd
0,0 → 1,246
 
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_sha_256 IS
END tb_sha_256;
ARCHITECTURE behavior OF tb_sha_256 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT sha_256
PORT(
clk : IN std_logic;
rst : IN std_logic;
gen_hash : in std_logic;
msg_0 : IN std_logic_vector(31 downto 0);
msg_1 : IN std_logic_vector(31 downto 0);
msg_2 : IN std_logic_vector(31 downto 0);
msg_3 : IN std_logic_vector(31 downto 0);
msg_4 : IN std_logic_vector(31 downto 0);
msg_5 : IN std_logic_vector(31 downto 0);
msg_6 : IN std_logic_vector(31 downto 0);
msg_7 : IN std_logic_vector(31 downto 0);
msg_8 : IN std_logic_vector(31 downto 0);
msg_9 : IN std_logic_vector(31 downto 0);
msg_10 : IN std_logic_vector(31 downto 0);
msg_11 : IN std_logic_vector(31 downto 0);
msg_12 : IN std_logic_vector(31 downto 0);
msg_13 : IN std_logic_vector(31 downto 0);
msg_14 : IN std_logic_vector(31 downto 0);
msg_15 : IN std_logic_vector(31 downto 0);
a_out : OUT std_logic_vector(31 downto 0);
b_out : OUT std_logic_vector(31 downto 0);
c_out : OUT std_logic_vector(31 downto 0);
d_out : OUT std_logic_vector(31 downto 0);
e_out : OUT std_logic_vector(31 downto 0);
f_out : OUT std_logic_vector(31 downto 0);
g_out : OUT std_logic_vector(31 downto 0);
h_out : OUT std_logic_vector(31 downto 0);
block_ready : out std_logic;
hash : out std_logic_vector(255 downto 0));
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal gen_hash : std_logic := '0';
signal msg_0 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_1 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_2 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_3 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_4 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_5 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_6 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_7 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_8 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_9 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_10 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_11 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_12 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_13 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_14 : std_logic_vector(31 downto 0) := (others => '0');
signal msg_15 : std_logic_vector(31 downto 0) := (others => '0');
 
--Outputs
signal a_out : std_logic_vector(31 downto 0);
signal b_out : std_logic_vector(31 downto 0);
signal c_out : std_logic_vector(31 downto 0);
signal d_out : std_logic_vector(31 downto 0);
signal e_out : std_logic_vector(31 downto 0);
signal f_out : std_logic_vector(31 downto 0);
signal g_out : std_logic_vector(31 downto 0);
signal h_out : std_logic_vector(31 downto 0);
signal block_ready : std_logic;
signal hash : std_logic_vector(255 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: sha_256 PORT MAP (
clk => clk,
rst => rst,
gen_hash => gen_hash,
msg_0 => msg_0,
msg_1 => msg_1,
msg_2 => msg_2,
msg_3 => msg_3,
msg_4 => msg_4,
msg_5 => msg_5,
msg_6 => msg_6,
msg_7 => msg_7,
msg_8 => msg_8,
msg_9 => msg_9,
msg_10 => msg_10,
msg_11 => msg_11,
msg_12 => msg_12,
msg_13 => msg_13,
msg_14 => msg_14,
msg_15 => msg_15,
a_out => a_out,
b_out => b_out,
c_out => c_out,
d_out => d_out,
e_out => e_out,
f_out => f_out,
g_out => g_out,
h_out => h_out,
block_ready => block_ready,
hash => hash
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
-- Example from "APPENDIX B: SHA-256 EXAMPLES",
-- B.1 SHA-256 Example (One-Block Message)
-- FIPS 180-26
msg_0 <= X"00000018";
msg_1 <= X"00000000";
msg_2 <= X"00000000";
msg_3 <= X"00000000";
msg_4 <= X"00000000";
msg_5 <= X"00000000";
msg_6 <= X"00000000";
msg_7 <= X"00000000";
msg_8 <= X"00000000";
msg_9 <= X"00000000";
msg_10 <= X"00000000";
msg_11 <= X"00000000";
msg_12 <= X"00000000";
msg_13 <= X"00000000";
msg_14 <= X"00000000";
msg_15 <= X"61626380";
rst <= '1';
wait for clk_period;
rst <= '0';
gen_hash <= '1';
wait for 0.66 us + clk_period;
 
assert hash = X"ba7816bf8f01cfea414140de5dae2223b00361a396177a9cb410ff61f20015ad"
report "B.1 Hash output ERROR" severity FAILURE;
-- Example from "APPENDIX B: SHA-256 EXAMPLES",
-- B.1 SHA-256 Example (One-Block Message)
-- FIPS 180-26
gen_hash <= '0';
wait for clk_period;
rst <= '1';
wait for clk_period;
rst <= '0';
msg_15 <= X"61626364";
msg_14 <= X"62636465";
msg_13 <= X"63646566";
msg_12 <= X"64656667";
msg_11 <= X"65666768";
msg_10 <= X"66676869";
msg_9 <= X"6768696A";
msg_8 <= X"68696A6B";
msg_7 <= X"696A6B6C";
msg_6 <= X"6A6B6C6D";
msg_5 <= X"6B6C6D6E";
msg_4 <= X"6C6D6E6F";
msg_3 <= X"6D6E6F70";
msg_2 <= X"6E6F7071";
msg_1 <= X"80000000";
msg_0 <= X"00000000";
gen_hash <= '1';
wait for 0.66 us + clk_period;
 
assert hash = X"85e655d6417a17953363376a624cde5c76e09589cac5f811cc4b32c1f20e533a"
report "B.2 (Part 1) Hash output ERROR" severity FAILURE;
gen_hash <= '0';
wait for clk_period;
 
msg_15 <= X"00000000";
msg_14 <= X"00000000";
msg_13 <= X"00000000";
msg_12 <= X"00000000";
msg_11 <= X"00000000";
msg_10 <= X"00000000";
msg_9 <= X"00000000";
msg_8 <= X"00000000";
msg_7 <= X"00000000";
msg_6 <= X"00000000";
msg_5 <= X"00000000";
msg_4 <= X"00000000";
msg_3 <= X"00000000";
msg_2 <= X"00000000";
msg_1 <= X"00000000";
msg_0 <= X"000001c0";
 
gen_hash <= '1';
 
wait for 0.66 us + clk_period;
 
assert hash = X"248d6a61d20638b8e5c026930c3e6039a33ce45964ff2167f6ecedd419db06c1"
report "B.2 (Part 2) Hash output ERROR" severity FAILURE;
gen_hash <= '0';
wait;
end process;
 
END;
/trunk/rtl/dual_mem.vhd
0,0 → 1,59
 
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
 
entity dual_mem is
generic (ADDR_LENGTH : integer := 6;
DATA_LENGTH : integer := 32;
N_ADDR : integer := 64);
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
di : in std_logic_vector(DATA_LENGTH - 1 downto 0);
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0);
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0));
end dual_mem;
 
architecture rtl of dual_mem is
type ram_type is array (N_ADDR - 1 downto 0)
of std_logic_vector (DATA_LENGTH - 1 downto 0);
signal RAM : ram_type;
signal read_a : std_logic_vector(ADDR_LENGTH - 1 downto 0);
signal read_dpra : std_logic_vector(ADDR_LENGTH - 1 downto 0);
 
attribute ram_style: string;
attribute ram_style of RAM: signal is "block";
 
begin
process (clk)
begin
if rising_edge(clk) then
if (we = '1') then
RAM(conv_integer(a)) <= di;
end if;
read_a <= a;
read_dpra <= dpra;
end if;
end process;
spo <= RAM(conv_integer(read_a));
dpo <= RAM(conv_integer(read_dpra));
end rtl;
/trunk/rtl/sha_fun.vhd
0,0 → 1,131
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
package sha_fun is
 
function sigma_0 (signal x : in std_logic_vector) return std_logic_vector;
function sigma_1 (signal x : in std_logic_vector) return std_logic_vector;
 
function sum_0 (signal x : in std_logic_vector) return std_logic_vector;
function sum_1 (signal x : in std_logic_vector) return std_logic_vector;
 
function chi (signal x : in std_logic_vector;
signal y : in std_logic_vector;
signal z : in std_logic_vector) return std_logic_vector;
 
function maj (signal x : in std_logic_vector;
signal y : in std_logic_vector;
signal z : in std_logic_vector) return std_logic_vector;
end sha_fun;
 
 
package body sha_fun is
 
function sigma_0 (signal x : in std_logic_vector) return std_logic_vector is
variable tmp_0 : std_logic_vector(31 downto 0);
variable tmp_1 : std_logic_vector(31 downto 0);
variable tmp_2 : std_logic_vector(31 downto 0);
variable r : std_logic_vector(31 downto 0);
begin
tmp_0 := x(6 downto 0) & x(31 downto 7);
tmp_1 := x(17 downto 0) & x(31 downto 18);
tmp_2 := "000" & x(31 downto 3);
r := tmp_0 xor tmp_1 xor tmp_2;
return r;
end sigma_0;
 
function sigma_1 (signal x : in std_logic_vector) return std_logic_vector is
variable tmp_0 : std_logic_vector(31 downto 0);
variable tmp_1 : std_logic_vector(31 downto 0);
variable tmp_2 : std_logic_vector(31 downto 0);
variable r : std_logic_vector(31 downto 0);
begin
tmp_0 := x(16 downto 0) & x(31 downto 17);
tmp_1 := x(18 downto 0) & x(31 downto 19);
tmp_2 := "0000000000" & x(31 downto 10);
r := tmp_0 xor tmp_1 xor tmp_2;
return r;
end sigma_1;
 
function chi (signal x : in std_logic_vector;
signal y : in std_logic_vector;
signal z : in std_logic_vector) return std_logic_vector is
variable r : std_logic_vector(31 downto 0);
begin
r := (x and y) xor (not(x) and z);
return r;
end chi;
 
function maj (signal x : in std_logic_vector;
signal y : in std_logic_vector;
signal z : in std_logic_vector) return std_logic_vector is
variable r : std_logic_vector(31 downto 0);
begin
r := (x and y) xor (x and z) xor (y and z);
return r;
 
end maj;
 
 
function sum_0 (signal x : in std_logic_vector) return std_logic_vector is
variable tmp_0 : std_logic_vector(31 downto 0);
variable tmp_1 : std_logic_vector(31 downto 0);
variable tmp_2 : std_logic_vector(31 downto 0);
variable r : std_logic_vector(31 downto 0);
begin
tmp_0 := x(1 downto 0) & x(31 downto 2);
tmp_1 := x(12 downto 0) & x(31 downto 13);
tmp_2 := x(21 downto 0) & x(31 downto 22);
r := tmp_0 xor tmp_1 xor tmp_2;
return r;
end sum_0;
function sum_1 (signal x : in std_logic_vector) return std_logic_vector is
variable tmp_0 : std_logic_vector(31 downto 0);
variable tmp_1 : std_logic_vector(31 downto 0);
variable tmp_2 : std_logic_vector(31 downto 0);
variable r : std_logic_vector(31 downto 0);
begin
 
tmp_0 := x(5 downto 0) & x(31 downto 6);
tmp_1 := x(10 downto 0) & x(31 downto 11);
tmp_2 := x(24 downto 0) & x(31 downto 25);
r := tmp_0 xor tmp_1 xor tmp_2;
return r;
end sum_1;
end sha_fun;
/trunk/rtl/msg_comp.vhd
0,0 → 1,179
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.sha_fun.ALL;
 
entity msg_comp is
port(clk : in std_logic;
rst : in std_logic;
h_0 : in std_logic_vector(31 downto 0);
h_1 : in std_logic_vector(31 downto 0);
h_2 : in std_logic_vector(31 downto 0);
h_3 : in std_logic_vector(31 downto 0);
h_4 : in std_logic_vector(31 downto 0);
h_5 : in std_logic_vector(31 downto 0);
h_6 : in std_logic_vector(31 downto 0);
h_7 : in std_logic_vector(31 downto 0);
w_i : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(31 downto 0);
a : out std_logic_vector(31 downto 0);
b : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
d : out std_logic_vector(31 downto 0);
e : out std_logic_vector(31 downto 0);
f : out std_logic_vector(31 downto 0);
g : out std_logic_vector(31 downto 0);
h : out std_logic_vector(31 downto 0));
end msg_comp;
 
architecture structural of msg_comp is
 
component ff_bank is
port(clk : in std_logic;
d : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
 
signal d_a_tmp : std_logic_vector(31 downto 0);
signal d_b_tmp : std_logic_vector(31 downto 0);
signal d_c_tmp : std_logic_vector(31 downto 0);
signal d_d_tmp : std_logic_vector(31 downto 0);
signal d_e_tmp : std_logic_vector(31 downto 0);
signal d_f_tmp : std_logic_vector(31 downto 0);
signal d_g_tmp : std_logic_vector(31 downto 0);
signal d_h_tmp : std_logic_vector(31 downto 0);
signal q_a_tmp : std_logic_vector(31 downto 0);
signal q_b_tmp : std_logic_vector(31 downto 0);
signal q_c_tmp : std_logic_vector(31 downto 0);
signal q_d_tmp : std_logic_vector(31 downto 0);
signal q_e_tmp : std_logic_vector(31 downto 0);
signal q_f_tmp : std_logic_vector(31 downto 0);
signal q_g_tmp : std_logic_vector(31 downto 0);
signal q_h_tmp : std_logic_vector(31 downto 0);
signal t_1, t_2 : std_logic_vector(31 downto 0);
begin
 
mux_ff_a:process(rst, h_0, t_1, t_2)
begin
if rst = '1' then
d_a_tmp <= h_0;
else
d_a_tmp <= std_logic_vector(unsigned(t_1) + unsigned(t_2));
end if;
end process;
 
mux_ff_b:process(rst, h_1, q_a_tmp)
begin
if rst = '1' then
d_b_tmp <= h_1;
else
d_b_tmp <= q_a_tmp;
end if;
end process;
 
mux_ff_c:process(rst, h_2, q_b_tmp)
begin
if rst = '1' then
d_c_tmp <= h_2;
else
d_c_tmp <= q_b_tmp;
end if;
end process;
 
mux_ff_d:process(rst, h_3, q_c_tmp)
begin
if rst = '1' then
d_d_tmp <= h_3;
else
d_d_tmp <= q_c_tmp;
end if;
end process;
 
mux_ff_e:process(rst, h_4, q_d_tmp, t_1)
begin
if rst = '1' then
d_e_tmp <= h_4;
else
d_e_tmp <= std_logic_vector(unsigned(q_d_tmp) + unsigned(t_1));
end if;
end process;
mux_ff_f:process(rst, h_5, q_e_tmp)
begin
if rst = '1' then
d_f_tmp <= h_5;
else
d_f_tmp <= q_e_tmp;
end if;
end process;
 
mux_ff_g:process(rst, h_6, q_f_tmp)
begin
if rst = '1' then
d_g_tmp <= h_6;
else
d_g_tmp <= q_f_tmp;
end if;
end process;
 
mux_ff_h:process(rst, h_7, q_g_tmp)
begin
if rst = '1' then
d_h_tmp <= h_7;
else
d_h_tmp <= q_g_tmp;
end if;
end process;
ff_a : ff_bank port map (clk, d_a_tmp, q_a_tmp);
ff_b : ff_bank port map (clk, d_b_tmp, q_b_tmp);
ff_c : ff_bank port map (clk, d_c_tmp, q_c_tmp);
ff_d : ff_bank port map (clk, d_d_tmp, q_d_tmp);
ff_e : ff_bank port map (clk, d_e_tmp, q_e_tmp);
ff_f : ff_bank port map (clk, d_f_tmp, q_f_tmp);
ff_g : ff_bank port map (clk, d_g_tmp, q_g_tmp);
ff_h : ff_bank port map (clk, d_h_tmp, q_h_tmp);
a <= d_a_tmp;
b <= d_b_tmp;
c <= d_c_tmp;
d <= d_d_tmp;
e <= d_e_tmp;
f <= d_f_tmp;
g <= d_g_tmp;
h <= d_h_tmp;
t_1 <= std_logic_vector(unsigned(q_h_tmp) +
unsigned(sum_1(q_e_tmp)) +
unsigned(chi(q_e_tmp, q_f_tmp, q_g_tmp)) +
unsigned(k_i) +
unsigned(w_i));
t_2 <= std_logic_vector(unsigned(sum_0(q_a_tmp)) +
unsigned(maj(q_a_tmp, q_b_tmp, q_c_tmp)));
end structural;
/trunk/rtl/ff_bank.vhd
0,0 → 1,36
 
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity ff_bank is
port(clk : in std_logic;
d : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end ff_bank;
 
architecture rtl of ff_bank is
begin
process(clk)
begin
if rising_edge(clk) then
q <= d;
end if;
end process;
end rtl;
 
/trunk/rtl/sh_reg.vhd
0,0 → 1,260
 
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.sha_fun.ALL;
 
entity sh_reg is
port(clk : in std_logic;
rst : in std_logic;
msg_0 : in std_logic_vector(31 downto 0);
msg_1 : in std_logic_vector(31 downto 0);
msg_2 : in std_logic_vector(31 downto 0);
msg_3 : in std_logic_vector(31 downto 0);
msg_4 : in std_logic_vector(31 downto 0);
msg_5 : in std_logic_vector(31 downto 0);
msg_6 : in std_logic_vector(31 downto 0);
msg_7 : in std_logic_vector(31 downto 0);
msg_8 : in std_logic_vector(31 downto 0);
msg_9 : in std_logic_vector(31 downto 0);
msg_10 : in std_logic_vector(31 downto 0);
msg_11 : in std_logic_vector(31 downto 0);
msg_12 : in std_logic_vector(31 downto 0);
msg_13 : in std_logic_vector(31 downto 0);
msg_14 : in std_logic_vector(31 downto 0);
msg_15 : in std_logic_vector(31 downto 0);
w_j : out std_logic_vector(31 downto 0));
end sh_reg;
 
architecture structural of sh_reg is
 
component ff_bank is
port(clk : in std_logic;
d : in std_logic_vector(31 downto 0);
q : out std_logic_vector(31 downto 0));
end component;
 
signal d_0_tmp : std_logic_vector(31 downto 0);
signal d_1_tmp : std_logic_vector(31 downto 0);
signal d_2_tmp : std_logic_vector(31 downto 0);
signal d_3_tmp : std_logic_vector(31 downto 0);
signal d_4_tmp : std_logic_vector(31 downto 0);
signal d_5_tmp : std_logic_vector(31 downto 0);
signal d_6_tmp : std_logic_vector(31 downto 0);
signal d_7_tmp : std_logic_vector(31 downto 0);
signal d_8_tmp : std_logic_vector(31 downto 0);
signal d_9_tmp : std_logic_vector(31 downto 0);
signal d_10_tmp : std_logic_vector(31 downto 0);
signal d_11_tmp : std_logic_vector(31 downto 0);
signal d_12_tmp : std_logic_vector(31 downto 0);
signal d_13_tmp : std_logic_vector(31 downto 0);
signal d_14_tmp : std_logic_vector(31 downto 0);
signal d_15_tmp : std_logic_vector(31 downto 0);
signal q_0_tmp : std_logic_vector(31 downto 0);
signal q_1_tmp : std_logic_vector(31 downto 0);
signal q_2_tmp : std_logic_vector(31 downto 0);
signal q_3_tmp : std_logic_vector(31 downto 0);
signal q_4_tmp : std_logic_vector(31 downto 0);
signal q_5_tmp : std_logic_vector(31 downto 0);
signal q_6_tmp : std_logic_vector(31 downto 0);
signal q_7_tmp : std_logic_vector(31 downto 0);
signal q_8_tmp : std_logic_vector(31 downto 0);
signal q_9_tmp : std_logic_vector(31 downto 0);
signal q_10_tmp : std_logic_vector(31 downto 0);
signal q_11_tmp : std_logic_vector(31 downto 0);
signal q_12_tmp : std_logic_vector(31 downto 0);
signal q_13_tmp : std_logic_vector(31 downto 0);
signal q_14_tmp : std_logic_vector(31 downto 0);
signal q_15_tmp : std_logic_vector(31 downto 0);
signal w_j_tmp : std_logic_vector(31 downto 0);
begin
 
mux_ff_0:process(rst, msg_0, w_j_tmp)
begin
if rst = '1' then
d_0_tmp <= msg_0;
else
d_0_tmp <= w_j_tmp;
end if;
end process;
 
mux_ff_1:process(rst, msg_1, q_0_tmp)
begin
if rst = '1' then
d_1_tmp <= msg_1;
else
d_1_tmp <= q_0_tmp;
end if;
end process;
 
mux_ff_2:process(rst, msg_2, q_1_tmp)
begin
if rst = '1' then
d_2_tmp <= msg_2;
else
d_2_tmp <= q_1_tmp;
end if;
end process;
 
mux_ff_3:process(rst, msg_3, q_2_tmp)
begin
if rst = '1' then
d_3_tmp <= msg_3;
else
d_3_tmp <= q_2_tmp;
end if;
end process;
 
mux_ff_4:process(rst, msg_4, q_3_tmp)
begin
if rst = '1' then
d_4_tmp <= msg_4;
else
d_4_tmp <= q_3_tmp;
end if;
end process;
mux_ff_5:process(rst, msg_5, q_4_tmp)
begin
if rst = '1' then
d_5_tmp <= msg_5;
else
d_5_tmp <= q_4_tmp;
end if;
end process;
 
mux_ff_6:process(rst, msg_6, q_5_tmp)
begin
if rst = '1' then
d_6_tmp <= msg_6;
else
d_6_tmp <= q_5_tmp;
end if;
end process;
 
mux_ff_7:process(rst, msg_7, q_6_tmp)
begin
if rst = '1' then
d_7_tmp <= msg_7;
else
d_7_tmp <= q_6_tmp;
end if;
end process;
 
mux_ff_8:process(rst, msg_8, q_7_tmp)
begin
if rst = '1' then
d_8_tmp <= msg_8;
else
d_8_tmp <= q_7_tmp;
end if;
end process;
 
mux_ff_9:process(rst, msg_9, q_8_tmp)
begin
if rst = '1' then
d_9_tmp <= msg_9;
else
d_9_tmp <= q_8_tmp;
end if;
end process;
 
mux_ff_10:process(rst, msg_10, q_9_tmp)
begin
if rst = '1' then
d_10_tmp <= msg_10;
else
d_10_tmp <= q_9_tmp;
end if;
end process;
 
mux_ff_11:process(rst, msg_11, q_10_tmp)
begin
if rst = '1' then
d_11_tmp <= msg_11;
else
d_11_tmp <= q_10_tmp;
end if;
end process;
 
mux_ff_12:process(rst, msg_12, q_11_tmp)
begin
if rst = '1' then
d_12_tmp <= msg_12;
else
d_12_tmp <= q_11_tmp;
end if;
end process;
 
mux_ff_13:process(rst, msg_13, q_12_tmp)
begin
if rst = '1' then
d_13_tmp <= msg_13;
else
d_13_tmp <= q_12_tmp;
end if;
end process;
 
mux_ff_14:process(rst, msg_14, q_13_tmp)
begin
if rst = '1' then
d_14_tmp <= msg_14;
else
d_14_tmp <= q_13_tmp;
end if;
end process;
 
mux_ff_15:process(rst, msg_15, q_14_tmp)
begin
if rst = '1' then
d_15_tmp <= msg_15;
else
d_15_tmp <= q_14_tmp;
end if;
end process;
ff_0 : ff_bank port map (clk, d_0_tmp, q_0_tmp);
ff_1 : ff_bank port map (clk, d_1_tmp, q_1_tmp);
ff_2 : ff_bank port map (clk, d_2_tmp, q_2_tmp);
ff_3 : ff_bank port map (clk, d_3_tmp, q_3_tmp);
ff_4 : ff_bank port map (clk, d_4_tmp, q_4_tmp);
ff_5 : ff_bank port map (clk, d_5_tmp, q_5_tmp);
ff_6 : ff_bank port map (clk, d_6_tmp, q_6_tmp);
ff_7 : ff_bank port map (clk, d_7_tmp, q_7_tmp);
ff_8 : ff_bank port map (clk, d_8_tmp, q_8_tmp);
ff_9 : ff_bank port map (clk, d_9_tmp, q_9_tmp);
ff_10 : ff_bank port map (clk, d_10_tmp, q_10_tmp);
ff_11 : ff_bank port map (clk, d_11_tmp, q_11_tmp);
ff_12 : ff_bank port map (clk, d_12_tmp, q_12_tmp);
ff_13 : ff_bank port map (clk, d_13_tmp, q_13_tmp);
ff_14 : ff_bank port map (clk, d_14_tmp, q_14_tmp);
ff_15 : ff_bank port map (clk, d_15_tmp, q_15_tmp);
w_j_tmp <= std_logic_vector(unsigned(sigma_0(q_14_tmp)) + unsigned(q_15_tmp) +
unsigned(sigma_1(q_1_tmp)) + unsigned(q_6_tmp));
w_j <= w_j_tmp;
end structural;
/trunk/rtl/sha_256.vhd
0,0 → 1,422
 
 
-- Copyright (c) 2013 Antonio de la Piedra
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity sha_256 is
port(clk : in std_logic;
rst : in std_logic;
gen_hash : in std_logic;
msg_0 : in std_logic_vector(31 downto 0);
msg_1 : in std_logic_vector(31 downto 0);
msg_2 : in std_logic_vector(31 downto 0);
msg_3 : in std_logic_vector(31 downto 0);
msg_4 : in std_logic_vector(31 downto 0);
msg_5 : in std_logic_vector(31 downto 0);
msg_6 : in std_logic_vector(31 downto 0);
msg_7 : in std_logic_vector(31 downto 0);
msg_8 : in std_logic_vector(31 downto 0);
msg_9 : in std_logic_vector(31 downto 0);
msg_10 : in std_logic_vector(31 downto 0);
msg_11 : in std_logic_vector(31 downto 0);
msg_12 : in std_logic_vector(31 downto 0);
msg_13 : in std_logic_vector(31 downto 0);
msg_14 : in std_logic_vector(31 downto 0);
msg_15 : in std_logic_vector(31 downto 0);
 
a_out : out std_logic_vector(31 downto 0);
b_out : out std_logic_vector(31 downto 0);
c_out : out std_logic_vector(31 downto 0);
d_out : out std_logic_vector(31 downto 0);
e_out : out std_logic_vector(31 downto 0);
f_out : out std_logic_vector(31 downto 0);
g_out : out std_logic_vector(31 downto 0);
h_out : out std_logic_vector(31 downto 0);
block_ready : out std_logic;
hash : out std_logic_vector(255 downto 0));
end sha_256;
 
architecture Behavioral of sha_256 is
 
component msg_comp is
port(clk : in std_logic;
rst : in std_logic;
h_0 : in std_logic_vector(31 downto 0);
h_1 : in std_logic_vector(31 downto 0);
h_2 : in std_logic_vector(31 downto 0);
h_3 : in std_logic_vector(31 downto 0);
h_4 : in std_logic_vector(31 downto 0);
h_5 : in std_logic_vector(31 downto 0);
h_6 : in std_logic_vector(31 downto 0);
h_7 : in std_logic_vector(31 downto 0);
w_i : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(31 downto 0);
a : out std_logic_vector(31 downto 0);
b : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
d : out std_logic_vector(31 downto 0);
e : out std_logic_vector(31 downto 0);
f : out std_logic_vector(31 downto 0);
g : out std_logic_vector(31 downto 0);
h : out std_logic_vector(31 downto 0));
end component;
 
component sh_reg is
port(clk : in std_logic;
rst : in std_logic;
msg_0 : in std_logic_vector(31 downto 0);
msg_1 : in std_logic_vector(31 downto 0);
msg_2 : in std_logic_vector(31 downto 0);
msg_3 : in std_logic_vector(31 downto 0);
msg_4 : in std_logic_vector(31 downto 0);
msg_5 : in std_logic_vector(31 downto 0);
msg_6 : in std_logic_vector(31 downto 0);
msg_7 : in std_logic_vector(31 downto 0);
msg_8 : in std_logic_vector(31 downto 0);
msg_9 : in std_logic_vector(31 downto 0);
msg_10 : in std_logic_vector(31 downto 0);
msg_11 : in std_logic_vector(31 downto 0);
msg_12 : in std_logic_vector(31 downto 0);
msg_13 : in std_logic_vector(31 downto 0);
msg_14 : in std_logic_vector(31 downto 0);
msg_15 : in std_logic_vector(31 downto 0);
w_j : out std_logic_vector(31 downto 0));
end component;
 
component dual_mem is
generic (ADDR_LENGTH : integer := 6;
DATA_LENGTH : integer := 32;
N_ADDR : integer := 64);
port (clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
dpra : in std_logic_vector(ADDR_LENGTH - 1 downto 0);
di : in std_logic_vector(DATA_LENGTH - 1 downto 0);
spo : out std_logic_vector(DATA_LENGTH - 1 downto 0);
dpo : out std_logic_vector(DATA_LENGTH - 1 downto 0));
end component;
 
signal w_j_tmp : std_logic_vector(31 downto 0);
 
signal h_0_tmp : std_logic_vector(31 downto 0);
signal h_1_tmp : std_logic_vector(31 downto 0);
signal h_2_tmp : std_logic_vector(31 downto 0);
signal h_3_tmp : std_logic_vector(31 downto 0);
signal h_4_tmp : std_logic_vector(31 downto 0);
signal h_5_tmp : std_logic_vector(31 downto 0);
signal h_6_tmp : std_logic_vector(31 downto 0);
signal h_7_tmp : std_logic_vector(31 downto 0);
 
signal k_i_tmp : std_logic_vector(31 downto 0);
signal start_cnt_tmp, rst_sch_tmp, rst_comp_tmp : std_logic;
signal cnt_s : std_logic_vector(5 downto 0);
signal m_tmp : std_logic_vector(31 downto 0);
type state_type is (idle, init, run, m_1, m_2, m_3, m_4, m_5, m_6, m_7,
m_8, m_9, m_10, m_11, m_12, m_13, m_14, m_15, w_s);
signal state, next_state: state_type ;
type delay_buffer_t is array(67 downto 0) of
std_logic;
signal hash_delay : delay_buffer_t;
 
signal a_out_tmp : std_logic_vector(31 downto 0);
signal b_out_tmp : std_logic_vector(31 downto 0);
signal c_out_tmp : std_logic_vector(31 downto 0);
signal d_out_tmp : std_logic_vector(31 downto 0);
signal e_out_tmp : std_logic_vector(31 downto 0);
signal f_out_tmp : std_logic_vector(31 downto 0);
signal g_out_tmp : std_logic_vector(31 downto 0);
signal h_out_tmp : std_logic_vector(31 downto 0);
signal gen_hash_tmp : std_logic;
signal rst_cnt_s : std_logic;
begin
 
process1: process (clk, rst)
begin
if (rst ='1') then
state <= idle;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process process1;
 
process2 : process (state, gen_hash, m_tmp, msg_0, msg_1, w_j_tmp, hash_delay(66))
begin
next_state <= state;
 
rst_sch_tmp <= '0';
rst_comp_tmp <= '0';
rst_cnt_s <= '0';
start_cnt_tmp <= '0';
m_tmp <= (others => '0');
gen_hash_tmp <= '0';
case state is
when idle =>
if gen_hash = '1' then
gen_hash_tmp <= '1';
rst_cnt_s <= '1';
next_state <= init;
else
next_state <= idle;
end if;
when init =>
rst_comp_tmp <= '1';
start_cnt_tmp <= '1';
next_state <= run;
when run =>
rst_comp_tmp <= '0';
start_cnt_tmp <= '1';
m_tmp <= msg_15;
next_state <= m_1;
when m_1 =>
m_tmp <= msg_14;
start_cnt_tmp <= '1';
next_state <= m_2;
when m_2 =>
m_tmp <= msg_13;
start_cnt_tmp <= '1';
next_state <= m_3;
when m_3 =>
m_tmp <= msg_12;
start_cnt_tmp <= '1';
next_state <= m_4;
when m_4 =>
m_tmp <= msg_11;
start_cnt_tmp <= '1';
next_state <= m_5;
when m_5 =>
m_tmp <= msg_10;
start_cnt_tmp <= '1';
next_state <= m_6;
when m_6 =>
m_tmp <= msg_9;
start_cnt_tmp <= '1';
next_state <= m_7;
when m_7 =>
m_tmp <= msg_8;
start_cnt_tmp <= '1';
next_state <= m_8;
when m_8 =>
m_tmp <= msg_7;
start_cnt_tmp <= '1';
next_state <= m_9;
when m_9 =>
m_tmp <= msg_6;
start_cnt_tmp <= '1';
next_state <= m_10;
when m_10 =>
m_tmp <= msg_5;
start_cnt_tmp <= '1';
next_state <= m_11;
when m_11 =>
m_tmp <= msg_4;
start_cnt_tmp <= '1';
next_state <= m_12;
when m_12 =>
m_tmp <= msg_3;
start_cnt_tmp <= '1';
next_state <= m_13;
when m_13 =>
m_tmp <= msg_2;
start_cnt_tmp <= '1';
next_state <= m_14;
when m_14 =>
m_tmp <= msg_1;
start_cnt_tmp <= '1';
next_state <= m_15;
when m_15 =>
m_tmp <= msg_0;
start_cnt_tmp <= '1';
rst_sch_tmp <= '1';
next_state <= w_s;
when w_s =>
m_tmp <= w_j_tmp;
start_cnt_tmp <= '1';
if hash_delay(66) = '1' then
next_state <= idle;
else
next_state <= w_s;
end if;
end case;
 
end process;
 
message_schedule: sh_reg port map (clk,
rst_sch_tmp,
msg_0,
msg_1,
msg_2,
msg_3,
msg_4,
msg_5,
msg_6,
msg_7,
msg_8,
msg_9,
msg_10,
msg_11,
msg_12,
msg_13,
msg_14,
msg_15,
w_j_tmp);
message_compression: msg_comp port map (clk,
rst_comp_tmp,
h_0_tmp,
h_1_tmp,
h_2_tmp,
h_3_tmp,
h_4_tmp,
h_5_tmp,
h_6_tmp,
h_7_tmp,
m_tmp,
k_i_tmp,
a_out_tmp,
b_out_tmp,
c_out_tmp,
d_out_tmp,
e_out_tmp,
f_out_tmp,
g_out_tmp,
h_out_tmp);
 
a_out <= a_out_tmp;
b_out <= b_out_tmp;
c_out <= c_out_tmp;
d_out <= d_out_tmp;
e_out <= e_out_tmp;
f_out <= f_out_tmp;
g_out <= g_out_tmp;
h_out <= h_out_tmp;
k_mem: dual_mem port map(clk,
'0',
cnt_s, --cnt_s,
(others => '0'),
(others => '0'),
k_i_tmp,
open);
 
cnt_k_pr: process(clk, rst_cnt_s, start_cnt_tmp)
variable cnt_v : unsigned(5 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if rst_cnt_s = '1' then
cnt_v := (others => '0');
elsif
start_cnt_tmp = '1' then
cnt_v := cnt_v + 1;
end if;
end if;
cnt_s <= std_logic_vector(cnt_v);
end process;
hash_delay(0) <= gen_hash_tmp;
 
delay_chain: for i in 1 to 66 generate
delay_ff_proc: process(clk)
begin
if rising_edge(clk) then
hash_delay(i) <= hash_delay(i-1);
end if;
end process delay_ff_proc;
end generate delay_chain;
 
block_ready <= hash_delay(66);
final_block: process(clk, rst, gen_hash, hash_delay(65),
a_out_tmp,
b_out_tmp,
c_out_tmp,
d_out_tmp,
e_out_tmp,
f_out_tmp,
g_out_tmp,
h_out_tmp)
variable h_0_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_1_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_2_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_3_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_4_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_5_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_6_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
variable h_7_tmp_v : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if rst = '1' then
h_0_tmp_v := X"6a09e667";
h_1_tmp_v := X"bb67ae85";
h_2_tmp_v := X"3c6ef372";
h_3_tmp_v := X"a54ff53a";
h_4_tmp_v := X"510e527f";
h_5_tmp_v := X"9b05688c";
h_6_tmp_v := X"1f83d9ab";
h_7_tmp_v := X"5be0cd19";
elsif hash_delay(65) = '1' then
h_0_tmp_v := std_logic_vector(unsigned(h_0_tmp_v) + unsigned(a_out_tmp));
h_1_tmp_v := std_logic_vector(unsigned(h_1_tmp_v) + unsigned(b_out_tmp));
h_2_tmp_v := std_logic_vector(unsigned(h_2_tmp_v) + unsigned(c_out_tmp));
h_3_tmp_v := std_logic_vector(unsigned(h_3_tmp_v) + unsigned(d_out_tmp));
h_4_tmp_v := std_logic_vector(unsigned(h_4_tmp_v) + unsigned(e_out_tmp));
h_5_tmp_v := std_logic_vector(unsigned(h_5_tmp_v) + unsigned(f_out_tmp));
h_6_tmp_v := std_logic_vector(unsigned(h_6_tmp_v) + unsigned(g_out_tmp));
h_7_tmp_v := std_logic_vector(unsigned(h_7_tmp_v) + unsigned(h_out_tmp));
end if;
end if;
h_0_tmp <= h_0_tmp_v;
h_1_tmp <= h_1_tmp_v;
h_2_tmp <= h_2_tmp_v;
h_3_tmp <= h_3_tmp_v;
h_4_tmp <= h_4_tmp_v;
h_5_tmp <= h_5_tmp_v;
h_6_tmp <= h_6_tmp_v;
h_7_tmp <= h_7_tmp_v;
end process;
hash <= h_0_tmp & h_1_tmp &
h_2_tmp & h_3_tmp &
h_4_tmp & h_5_tmp &
h_6_tmp & h_7_tmp;
end Behavioral;
 
/trunk/rtl/mem/k.mem
0,0 → 1,64
428a2f98
71374491
b5c0fbcf
e9b5dba5
3956c25b
59f111f1
923f82a4
ab1c5ed5
d807aa98
12835b01
243185be
550c7dc3
72be5d74
80deb1fe
9bdc06a7
c19bf174
e49b69c1
efbe4786
0fc19dc6
240ca1cc
2de92c6f
4a7484aa
5cb0a9dc
76f988da
983e5152
a831c66d
b00327c8
bf597fc7
c6e00bf3
d5a79147
06ca6351
14292967
27b70a85
2e1b2138
4d2c6dfc
53380d13
650a7354
766a0abb
81c2c92e
92722c85
a2bfe8a1
a81a664b
c24b8b70
c76c51a3
d192e819
d6990624
f40e3585
106aa070
19a4c116
1e376c08
2748774c
34b0bcb5
391c0cb3
4ed8aa4a
5b9cca4f
682e6ff3
748f82ee
78a5636f
84c87814
8cc70208
90befffa
a4506ceb
bef9a3f7
c67178f2

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