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https://opencores.org/ocsvn/simon_core/simon_core/trunk
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/simon_core/codes/Simon_bit_serial_key_expansion_FPGA.v
0,0 → 1,241
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Team: Virginia Tech Secure Embedded Systems (SES) Lab |
// Implementer: Ege Gulcan |
// |
// Create Date: 16:55:06 11/12/2013 |
// Design Name: |
// Module Name: simon_key_expansion_shiftreg |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
|
module simon_key_expansion_shiftreg(clk,data_in,key_out,data_rdy,bit_counter,round_counter_out); |
|
input clk; |
input data_in; |
input [1:0] data_rdy; |
input [5:0] bit_counter; |
output key_out; |
output round_counter_out; |
|
|
reg [59:0] shifter1; |
reg [63:0] shifter2; |
reg shift_in1,shift_in2; |
wire shift_out1,shift_out2; |
reg shifter_enable1,shifter_enable2; |
|
reg lut_ff_enable,fifo_ff_enable; |
wire lut_out; |
reg lut_in3; |
reg s2,s3; |
reg [1:0] s1; |
reg [6:0] round_counter; |
reg z_value; |
|
reg fifo_ff0,fifo_ff1,fifo_ff2,fifo_ff3; |
|
//(* shreg_extract = "no" *) |
reg lut_ff0,lut_ff1,lut_ff2,lut_ff3; |
//Constant value Z ROM |
reg [0:67] Z = 68'b10101111011100000011010010011000101000010001111110010110110011101011; |
reg c; |
|
|
///////////////////////////////////////// |
//// BEGIN CODE //////////////////////// |
/////////////////////////////////////// |
|
// Least bit of the round counter is sent to the datapath to check if it is even or odd |
assign round_counter_out = round_counter[0]; |
|
// Shift Register1 FIFO 60x1 Begin |
// 60x1 shift register storing the 60 most significant bits of the upper word of the key |
always @(posedge clk) |
begin |
if(shifter_enable1) |
begin |
shifter1 <= {shift_in1, shifter1[59:1]}; |
end |
end |
|
assign shift_out1 = shifter1[0]; |
// Shift Register1 End |
|
// Shift Register2 FIFO 64x1 Begin |
// 64x1 shift register storing the lower word of the key |
always @(posedge clk) |
begin |
if(shifter_enable2) |
begin |
shifter2 <= {shift_in2, shifter2[63:1]}; |
end |
end |
|
assign shift_out2 = shifter2[0]; |
// Shift Register2 End |
|
// 4 flip-flops storing the least significant 4 bits of the upper word in the first round |
always @(posedge clk) |
begin |
if(fifo_ff_enable) |
begin |
fifo_ff3 <= shift_out1; |
fifo_ff2 <= fifo_ff3; |
fifo_ff1 <= fifo_ff2; |
fifo_ff0 <= fifo_ff1; |
end |
end |
|
// 4 flip-flops storing the least significant 4 bits of the upper word after the first round |
always@(posedge clk) |
begin |
if(lut_ff_enable) |
begin |
lut_ff3 <= lut_out; |
lut_ff2 <= lut_ff3; |
lut_ff1 <= lut_ff2; |
lut_ff0 <= lut_ff1; |
end |
end |
|
//FIFO 64x1 Input MUX |
always@(*) |
begin |
if(data_rdy==2) |
shift_in2 = fifo_ff0; |
else if(data_rdy==3 && (round_counter<1 || bit_counter>3)) |
shift_in2 = fifo_ff0; |
else if(data_rdy==3 && bit_counter<4 && round_counter>0) |
shift_in2 = lut_ff0; |
else |
shift_in2 = 1'bx; |
end |
|
//LUT >>3 Input MUX |
always@(*) |
begin |
if(s2==0) |
lut_in3 = fifo_ff3; |
else |
lut_in3 = lut_ff3; |
end |
|
//FIFO 60x1 Input MUX |
always@(*) |
begin |
if(s1==0) |
shift_in1 = fifo_ff0; |
else if(s1==1) |
shift_in1 = data_in; |
else if(s1==2) |
shift_in1 = lut_out; |
else if(s1==3) |
shift_in1 = lut_ff0; |
else |
shift_in1 = 1'bx; |
end |
|
//S2 MUX |
always@(*) |
begin |
if(bit_counter==0 && round_counter!=0) |
s2 = 1; |
else |
s2 = 0; |
end |
|
//S1 MUX |
always@(*) |
begin |
if(data_rdy==2) |
s1 = 1; |
else if(data_rdy==3 && bit_counter<4 && round_counter==0) |
s1 = 0; |
else if(data_rdy==3 && bit_counter<4 && round_counter>0) |
s1 = 3; |
else |
s1 = 2; |
end |
|
// LUT FF ENABLE MUX |
// LUT FFs are used only at the first four clock cycles of each round |
always@(*) |
begin |
if(data_rdy==3 && bit_counter<4) |
lut_ff_enable = 1; |
else |
lut_ff_enable = 0; |
end |
|
//FIFO FF ENABLE MUX |
always@(*) |
begin |
if(data_rdy==2 || data_rdy==3) |
fifo_ff_enable = 1; |
else |
fifo_ff_enable = 0; |
end |
|
//SHIFTER ENABLES |
// Shifters are enabled when the key is loaded or block cipher is running |
always@(*) |
begin |
if(data_rdy==2 || data_rdy==3) |
shifter_enable1 = 1; |
else |
shifter_enable1 = 0; |
|
if(data_rdy==2 || data_rdy==3) |
shifter_enable2 = 1; |
else |
shifter_enable2 = 0; |
|
end |
|
//Round Counter |
always@(posedge clk) |
begin |
if(data_rdy==3 && bit_counter==63) |
round_counter <= round_counter + 1; |
else if(data_rdy==0) |
round_counter <= 0; |
else |
round_counter <= round_counter; |
end |
|
// The necessary bit of the constant Z is selected by the round counter |
always @(*) |
begin |
if(bit_counter==0) |
z_value = Z[round_counter]; |
else |
z_value = 0; |
end |
|
// The value of c is 1 at the first two cycles of each round only |
always @(*) |
begin |
if(bit_counter==0 || bit_counter==1) |
c = 0; |
else |
c = 1; |
end |
|
// New computed key bit |
assign lut_out = shift_out2 ^ lut_in3 ^ shift_out1 ^ z_value ^ c; |
|
// Output key bit that is connected to the datapath |
assign key_out = shift_out2; |
|
endmodule |
/simon_core/codes/Simon_bit_serial_testbench.v
0,0 → 1,93
`timescale 1ns / 1ps |
|
//////////////////////////////////////////////////////////////////////////////// |
// Team: Virginia Tech Secure Embedded Systems (SES) Lab |
// Implementer: Ege Gulcan |
// |
// Create Date: 19:49:46 11/13/2013 |
// Design Name: top_module |
// Module Name: top_module_test.v |
// Project Name: SIMON |
// Target Device: |
// Tool versions: |
// Description: |
// |
// Verilog Test Fixture created by ISE for module: top_module |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
//////////////////////////////////////////////////////////////////////////////// |
|
module top_module_test; |
|
// Inputs |
reg clk; |
reg data_in; |
reg [1:0] data_rdy; |
|
// Outputs |
wire cipher_out; |
|
// Plaintext and key from the NSA Simon and Speck paper |
reg [127:0] plaintext = 128'h63736564207372656c6c657661727420; |
reg [127:0] key = 128'h0f0e0d0c0b0a09080706050403020100; |
|
integer i; |
|
// Instantiate the Unit Under Test (UUT) |
top_module uut ( |
.clk(clk), |
.data_in(data_in), |
.data_rdy(data_rdy), |
.cipher_out(cipher_out) |
); |
|
initial begin |
// Initialize Inputs |
clk = 0; |
data_in = 0; |
data_rdy = 0; |
|
#110; |
#5; |
//Set data_rdy=1 to load plaintext |
data_rdy=1; |
|
//Loads the plaintext one bit per clock cycle for 128 cycles |
for(i=0;i<128;i = i+1) |
begin |
data_in = plaintext[i]; |
#20; |
end |
|
//Set data_rdy=2 to load key |
data_rdy = 2; |
|
//Loads the key one bit per clock cycle for 128 cycles |
for(i=0;i<128;i = i+1) |
begin |
data_in = key[i]; |
#20; |
end |
//Set data_rdy=0 after loading is done |
data_rdy = 0; |
#20; |
|
//Keep data_rdy=3 while the cipher is running |
data_rdy = 3; |
|
|
end |
|
|
|
always #10 clk = ~clk; |
|
|
|
endmodule |
|
/simon_core/codes/Simon_bit_serial_datapath_FPGA.v
0,0 → 1,225
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Team: Virginia Tech Secure Embedded Systems (SES) Lab |
// Implementer: Ege Gulcan |
// |
// Create Date: 17:21:26 11/13/2013 |
// Design Name: |
// Module Name: simon_datapath_shiftreg |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module simon_datapath_shiftreg(clk,data_in,data_rdy,key_in,cipher_out,round_counter,bit_counter); |
|
input clk,data_in,key_in; |
input [1:0] data_rdy; |
input round_counter; |
output cipher_out; |
output [5:0] bit_counter; |
|
reg [55:0] shifter1; |
reg [63:0] shifter2; |
reg shift_in1,shift_in2; |
wire shift_out1,shift_out2; |
reg shifter_enable1,shifter_enable2; |
|
reg fifo_ff63,fifo_ff62,fifo_ff61,fifo_ff60,fifo_ff59,fifo_ff58,fifo_ff57,fifo_ff56; |
reg lut_ff63,lut_ff62,lut_ff61,lut_ff60,lut_ff59,lut_ff58,lut_ff57,lut_ff56; |
|
reg lut_ff_input,fifo_ff_input; |
reg lut_rol1,lut_rol2,lut_rol8; |
reg s1,s4,s5,s6,s7; |
reg [1:0] s3; |
reg [5:0] bit_counter; |
wire lut_out; |
|
|
|
// Shift Register1 FIFO 56x1 Begin |
// 56x1 Shift register to store the upper word |
always @(posedge clk) |
begin |
if(shifter_enable1) |
begin |
shifter1 <= {shift_in1, shifter1[55:1]}; |
end |
end |
|
assign shift_out1 = shifter1[0]; |
// Shift Register1 End |
|
// Shift Register2 FIFO 64x1 Begin |
// 64x1 Shift register to store the lower word |
always @(posedge clk) |
begin |
if(shifter_enable2) |
begin |
shifter2 <= {shift_in2, shifter2[63:1]}; |
end |
end |
|
assign shift_out2 = shifter2[0]; |
// Shift Register2 End |
|
|
// 8 Flip-Flops to store the most significant 8 bits of the upper word at even rounds |
// Denoted as Shift Register Up (SRU) in Figure 5 |
always@(posedge clk) |
begin |
if(shifter_enable1) |
begin |
fifo_ff63 <= fifo_ff_input; |
fifo_ff62 <= fifo_ff63; |
fifo_ff61 <= fifo_ff62; |
fifo_ff60 <= fifo_ff61; |
fifo_ff59 <= fifo_ff60; |
fifo_ff58 <= fifo_ff59; |
fifo_ff57 <= fifo_ff58; |
fifo_ff56 <= fifo_ff57; |
end |
end |
|
// 8 Flip-Flops to store the most significant 8 bits of the upper word at odd rounds |
// Denoted as Shift Register Down (SRD) in Figure 5 |
always@(posedge clk) |
begin |
lut_ff63 <= lut_ff_input; |
lut_ff62 <= lut_ff63; |
lut_ff61 <= lut_ff62; |
lut_ff60 <= lut_ff61; |
lut_ff59 <= lut_ff60; |
lut_ff58 <= lut_ff59; |
lut_ff57 <= lut_ff58; |
lut_ff56 <= lut_ff57; |
end |
|
// FIFO 64x1 Input MUX |
// Input of the lower FIFO is always the output of the upper FIFO |
always@(*) |
begin |
shift_in2 = shift_out1; |
end |
|
// FIFO 56x1 Input MUX |
// Input of the upper FIFO depends on the select line S1 |
always@(*) |
begin |
if(s1==0) |
shift_in1 = lut_ff56; |
else |
shift_in1 = fifo_ff56; |
end |
|
// FIFO FF Input MUX |
// The input of FIFO_FF can be the input plaintext, output of 56x1 FIFO or the output of LUT |
always@(*) |
begin |
if(s3==0) |
fifo_ff_input = data_in; |
else if(s3==1) |
fifo_ff_input = shift_out1; |
else if(s3==2) |
fifo_ff_input = lut_out; |
else |
fifo_ff_input = 1'bx; // Debugging |
end |
|
// LUT FF Input MUX |
// The input of the LUT_FF is either the output of 56x1 FIFO or the output of LUT |
always@(*) |
begin |
if(s5==0) |
lut_ff_input = shift_out1; |
else |
lut_ff_input = lut_out; |
end |
|
// LUT Input MUX |
always@(*) |
begin |
if(s7==0) |
lut_rol1 = fifo_ff63; |
else |
lut_rol1 = lut_ff63; |
|
if(s4==0) |
lut_rol2 = fifo_ff62; |
else |
lut_rol2 = lut_ff62; |
|
if(s6==0) |
lut_rol8 = fifo_ff56; |
else |
lut_rol8 = lut_ff56; |
end |
|
//Selection MUX |
always@(*) |
begin |
// For the first 8 bits of each even round OR for all the bits after the first 8 bits in odd rounds OR loading the plaintext |
if((round_counter==0 && bit_counter<8)||(round_counter==1 && bit_counter>7)||(data_rdy==1)) |
s1 = 1; |
else |
s1 = 0; |
|
if(data_rdy==1) // Loading plaintext |
s3 = 0; |
else if(round_counter==0) // Even rounds |
s3 = 1; |
else if(round_counter==1) // Odd rounds |
s3 = 2; |
else |
s3 = 1'bx; // For debugging |
|
if(round_counter==0) // Even rounds |
s6 = 0; |
else |
s6 = 1; |
|
s4 = s6; |
s7 = s6; |
s5 = ~s6; |
end |
|
// SHIFTER ENABLES |
// Two shift registers are enabled when the plaintext is being loaded (1) or when the block cipher is running (3) |
always@(*) |
begin |
if(data_rdy==1 || data_rdy==3) |
begin |
shifter_enable1 = 1; |
shifter_enable2 = 1; |
end |
else |
begin |
shifter_enable1 = 0; |
shifter_enable2 = 0; |
end |
end |
|
// The bit_counter value is incremented in each clock cycle when the block cipher is running |
always@(posedge clk) |
begin |
if(data_rdy==0) |
bit_counter <= 0; |
else if(data_rdy==3) |
bit_counter <= bit_counter + 1; |
else |
bit_counter <= bit_counter; |
end |
|
// The new computed value |
assign lut_out = (lut_rol1 & lut_rol8) ^ shift_out2 ^ lut_rol2 ^ key_in; |
|
// The global output that gives the ciphertext value |
assign cipher_out = lut_out; |
endmodule |
/simon_core/codes/Simon_bit_serial_top_module_FPGA.v
0,0 → 1,45
`timescale 1ns / 1ps |
////////////////////////////////////////////////////////////////////////////////// |
// Team: Virginia Tech Secure Embedded Systems (SES) Lab |
// Implementer: Ege Gulcan |
// |
// Create Date: 19:14:37 11/13/2013 |
// Design Name: |
// Module Name: top_module |
// Project Name: |
// Target Devices: |
// Tool versions: |
// Description: |
// |
// Dependencies: |
// |
// Revision: |
// Revision 0.01 - File Created |
// Additional Comments: |
// |
////////////////////////////////////////////////////////////////////////////////// |
module top_module(clk,data_in,data_rdy,cipher_out); |
|
input clk,data_in; |
input [1:0] data_rdy; |
output cipher_out; |
|
wire key; |
wire [5:0] bit_counter; |
wire round_counter_out; |
|
/* |
data_rdy=0 -> Reset, Idle |
data_rdy=1 -> Load Plaintext |
data_rdy=2 -> Load Key |
data_rdy=3 -> Run (keep at 3 while the block cipher is running) |
*/ |
|
simon_datapath_shiftreg datapath(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_in(key), |
. cipher_out(cipher_out), .round_counter(round_counter_out), .bit_counter(bit_counter)); |
|
simon_key_expansion_shiftreg key_exp(.clk(clk), .data_in(data_in), .data_rdy(data_rdy), .key_out(key), .bit_counter(bit_counter), |
.round_counter_out(round_counter_out)); |
|
|
endmodule |
/simon_core/codes/README.txt
0,0 → 1,4
Disclaimer: |
The use of this code is at your own risk. Of course, we do made every effort to ensure |
that the reference files are free of bugs and issues. We also tested the design on FPGAs |
to make sure that it actually works. |