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/trunk/example/example_design_sio.zip

trunk/example/example_design_sio.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/rtl/example_sio_top.vhd =================================================================== --- trunk/rtl/example_sio_top.vhd (nonexistent) +++ trunk/rtl/example_sio_top.vhd (revision 2) @@ -0,0 +1,369 @@ +-- ----------------------------------------------------------------------------- +-- This file is a top level application for conencting the wb_lpc to the sio_logic +-- written by : Istvan Nagy 11.01, 2019 +-- +-- A replacement for a chip like the Microchip SCH3227. +-- The LPC IP has a 32bit wishbone bus, but only lower 8bits used for SIO access, with 8bit LPC cycles. +-- Files from other projects needed: +-- - UART below this module: https://opencores.org/projects/uart16550 +-- For the UART, use the 33MHz compliant version regs file: uart_regs_33m.v +-- In uart_defines.v uncomment the "`define DATA_BUS_WIDTH_8" +-- - PS2 below this module: http://www.opencores.org/projects/ps2/ +-- In the ps2_defines, uncomment `define PS2_AUX to enble the keyboard +-- - LPC slave: https://opencores.org/projects/wb_lpc +-- Use these files: wb_lpc_periph.v, wb_lpc_defines.v, serirq_defines.v, serirq_slave.v +-- Some of the files had references, that needs rewriting to remove relative path: `include "wb_lpc_defines.v" +-- In wb_lpc_periph.v change a line: always @(posedge clk_i or negedge nrst_i) ===> always @(posedge clk_i) +-- - Write your own device-top level file, instantiating/connecting the LPC and SIO. +-- Address range: +-- - COM1: 3F8-3FFh +-- - COM2: 2F8-2FFh +-- - COM3: 3E8-3EFh +-- - COM4: 2E8-2EFh +-- - PS2: 60h AND 64h +-- - post-code: 80h AND 81h +-- - Custom board logic registers: 200h...207h (r/w regs connect in/out outside, ro regs out NC) +-- ----------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + +--entity header ---------------------------------------------------------------- +entity example_sio_top is + Port ( + clk_lpc : in std_logic; + reset_n : in std_logic; + lframe : in std_logic; + lad : inout std_logic_vector(3 downto 0); + serirq : inout std_logic; + parallel_irq : IN std_logic_vector(31 downto 0); + register_0_out : out std_logic_vector(7 downto 0); + register_0_in : in std_logic_vector(7 downto 0); + register_1_out : out std_logic_vector(7 downto 0); + register_1_in : in std_logic_vector(7 downto 0); + register_2_out : out std_logic_vector(7 downto 0); + register_2_in : in std_logic_vector(7 downto 0); + register_3_out : out std_logic_vector(7 downto 0); + register_3_in : in std_logic_vector(7 downto 0); + register_4_out : out std_logic_vector(7 downto 0); + register_4_in : in std_logic_vector(7 downto 0); + register_5_out : out std_logic_vector(7 downto 0); + register_5_in : in std_logic_vector(7 downto 0); + register_6_out : out std_logic_vector(7 downto 0); + register_6_in : in std_logic_vector(7 downto 0); + register_7_out : out std_logic_vector(7 downto 0); + register_7_in : in std_logic_vector(7 downto 0); + port80 : out std_logic_vector(7 downto 0); + port81 : out std_logic_vector(7 downto 0); + serial1_tx: out std_logic; serial1_rx: in std_logic; serial1_rts: out std_logic; serial1_cts: in std_logic; serial1_dtr: out std_logic; serial1_dsr: in std_logic; serial1_ri: in std_logic; serial1_dcd: in std_logic; + serial2_tx: out std_logic; serial2_rx: in std_logic; serial2_rts: out std_logic; serial2_cts: in std_logic; serial2_dtr: out std_logic; serial2_dsr: in std_logic; serial2_ri: in std_logic; serial2_dcd: in std_logic; + serial3_tx: out std_logic; serial3_rx: in std_logic; serial3_rts: out std_logic; serial3_cts: in std_logic; serial3_dtr: out std_logic; serial3_dsr: in std_logic; serial3_ri: in std_logic; serial3_dcd: in std_logic; + serial4_tx: out std_logic; serial4_rx: in std_logic; serial4_rts: out std_logic; serial4_cts: in std_logic; serial4_dtr: out std_logic; serial4_dsr: in std_logic; serial4_ri: in std_logic; serial4_dcd: in std_logic; + ps2_kbd_clk_pad_oe_o: out std_logic; ps2_kbd_clk_pad_o: out std_logic; ps2_kbd_data_pad_oe_o: out std_logic; ps2_kbd_data_pad_o: out std_logic; + ps2_aux_clk_pad_oe_o: out std_logic; ps2_aux_clk_pad_o: out std_logic; ps2_aux_data_pad_oe_o: out std_logic; ps2_aux_data_pad_o: out std_logic; + ps2_kbd_clk_pad_i: in std_logic; ps2_kbd_data_pad_i: in std_logic; ps2_aux_clk_pad_i : in std_logic; ps2_aux_data_pad_i: in std_logic; kb_rstout: out std_logic + ); +end example_sio_top; + + +--architecture start ------------------------------------------------------------ +architecture Behavioral of example_sio_top is + + +-- INTERNAL SIGNALS ------------------------------------------------------------- + SIGNAL dummy0: std_logic; + SIGNAL dummy1: std_logic_VECTOR(6 DOWNTO 0); + SIGNAL xwbm_adr_i : std_logic_vector(31 downto 0); + SIGNAL xwbm_dat_i : std_logic_vector(31 downto 0); + SIGNAL xwbm_sel_i : std_logic_vector(3 downto 0); + SIGNAL xwbm_tga_i : std_logic_vector(1 downto 0); + SIGNAL xwbm_we_i : std_logic; + SIGNAL xwbm_stb_i : std_logic; + SIGNAL xwbm_cyc_i : std_logic; + SIGNAL xwbm_dat_o : std_logic_vector(31 downto 0); + SIGNAL xwbm_ack_o : std_logic; + SIGNAL xwbm_err_o : std_logic; + SIGNAL dma_bs1 : std_logic_vector(2 downto 0); + SIGNAL dma_bs2 : std_logic; + SIGNAL serirq_i : std_logic; + SIGNAL serirq_o : std_logic; + SIGNAL serirq_oe : std_logic; + SIGNAL lad_i : std_logic_vector(3 downto 0); + SIGNAL lad_o : std_logic_vector(3 downto 0); + SIGNAL lad_oe : std_logic; + + + +--------- COMPONENT DECLARATIONS (introducing the IPs) -------------------------- + COMPONENT sio_logic + PORT( + clk : IN std_logic; + reset_n : IN std_logic; + wbm_adr_i : IN std_logic_vector(31 downto 0); + wbm_dat_i : IN std_logic_vector(31 downto 0); + wbm_sel_i : IN std_logic_vector(3 downto 0); + wbm_tga_i : IN std_logic_vector(1 downto 0); + wbm_we_i : IN std_logic; + wbm_stb_i : IN std_logic; + wbm_cyc_i : IN std_logic; + register_0_in : IN std_logic_vector(7 downto 0); + register_1_in : IN std_logic_vector(7 downto 0); + register_2_in : IN std_logic_vector(7 downto 0); + register_3_in : IN std_logic_vector(7 downto 0); + register_4_in : IN std_logic_vector(7 downto 0); + register_5_in : IN std_logic_vector(7 downto 0); + register_6_in : IN std_logic_vector(7 downto 0); + register_7_in : IN std_logic_vector(7 downto 0); + serial1_rx : IN std_logic; + serial1_cts : IN std_logic; + serial1_dsr : IN std_logic; + serial1_ri : IN std_logic; + serial1_dcd : IN std_logic; + serial2_rx : IN std_logic; + serial2_cts : IN std_logic; + serial2_dsr : IN std_logic; + serial2_ri : IN std_logic; + serial2_dcd : IN std_logic; + serial3_rx : IN std_logic; + serial3_cts : IN std_logic; + serial3_dsr : IN std_logic; + serial3_ri : IN std_logic; + serial3_dcd : IN std_logic; + serial4_rx : IN std_logic; + serial4_cts : IN std_logic; + serial4_dsr : IN std_logic; + serial4_ri : IN std_logic; + serial4_dcd : IN std_logic; + ps2_kbd_clk_pad_i : IN std_logic; + ps2_kbd_data_pad_i : IN std_logic; + ps2_aux_clk_pad_i : IN std_logic; + ps2_aux_data_pad_i : IN std_logic; + wbm_dat_o : OUT std_logic_vector(31 downto 0); + wbm_ack_o : OUT std_logic; + wbm_err_o : OUT std_logic; + register_0_out : OUT std_logic_vector(7 downto 0); + register_1_out : OUT std_logic_vector(7 downto 0); + register_2_out : OUT std_logic_vector(7 downto 0); + register_3_out : OUT std_logic_vector(7 downto 0); + register_4_out : OUT std_logic_vector(7 downto 0); + register_5_out : OUT std_logic_vector(7 downto 0); + register_6_out : OUT std_logic_vector(7 downto 0); + register_7_out : OUT std_logic_vector(7 downto 0); + port80 : OUT std_logic_vector(7 downto 0); + port81 : OUT std_logic_vector(7 downto 0); + serial1_tx : OUT std_logic; + serial1_rts : OUT std_logic; + serial1_dtr : OUT std_logic; + serial2_tx : OUT std_logic; + serial2_rts : OUT std_logic; + serial2_dtr : OUT std_logic; + serial3_tx : OUT std_logic; + serial3_rts : OUT std_logic; + serial3_dtr : OUT std_logic; + serial4_tx : OUT std_logic; + serial4_rts : OUT std_logic; + serial4_dtr : OUT std_logic; + --kb_rstout : OUT std_logic; + ps2_kbd_clk_pad_oe_o : OUT std_logic; + ps2_kbd_clk_pad_o : OUT std_logic; + ps2_kbd_data_pad_oe_o : OUT std_logic; + ps2_kbd_data_pad_o : OUT std_logic; + ps2_aux_clk_pad_oe_o : OUT std_logic; + ps2_aux_clk_pad_o : OUT std_logic; + ps2_aux_data_pad_oe_o : OUT std_logic; + ps2_aux_data_pad_o : OUT std_logic + ); + END COMPONENT; + + COMPONENT wb_lpc_periph + PORT( + clk_i : IN std_logic; + nrst_i : IN std_logic; + wbm_dat_i : IN std_logic_vector(31 downto 0); + wbm_ack_i : IN std_logic; + wbm_err_i : IN std_logic; + lframe_i : IN std_logic; + lad_i : IN std_logic_vector(3 downto 0); + wbm_adr_o : OUT std_logic_vector(31 downto 0); + wbm_dat_o : OUT std_logic_vector(31 downto 0); + wbm_sel_o : OUT std_logic_vector(3 downto 0); + wbm_tga_o : OUT std_logic_vector(1 downto 0); + wbm_we_o : OUT std_logic; + wbm_stb_o : OUT std_logic; + wbm_cyc_o : OUT std_logic; + dma_chan_o : OUT std_logic_vector(2 downto 0); + dma_tc_o : OUT std_logic; + lad_o : OUT std_logic_vector(3 downto 0); + lad_oe : OUT std_logic + ); + END COMPONENT; + + + COMPONENT serirq_slave + PORT( + clk_i : IN std_logic; + nrst_i : IN std_logic; + irq_i : IN std_logic_vector(31 downto 0); + serirq_i : IN std_logic; + serirq_o : OUT std_logic; + serirq_oe : OUT std_logic + ); + END COMPONENT; + + +--architecture body start ------------------------------------------------------- +begin + + + +--------- COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------- + Inst_sio_logic: sio_logic PORT MAP( + clk => clk_lpc , + reset_n => reset_n , + wbm_adr_i => xwbm_adr_i, + wbm_dat_i => xwbm_dat_i, + wbm_dat_o => xwbm_dat_o, + wbm_sel_i => xwbm_sel_i, + wbm_tga_i => xwbm_tga_i, + wbm_we_i => xwbm_we_i, + wbm_stb_i => xwbm_stb_i, + wbm_cyc_i => xwbm_cyc_i, + wbm_ack_o => xwbm_ack_o, + wbm_err_o => xwbm_err_o, + register_0_out => register_0_out, + register_0_in => register_0_in, + register_1_out => register_1_out, + register_1_in => register_1_in, + register_2_out => register_2_out, + register_2_in => register_2_in, + register_3_out => register_3_out, + register_3_in => register_3_in, + register_4_out => register_4_out, + register_4_in => register_4_in, + register_5_out => register_5_out, + register_5_in => register_5_in, + register_6_out => register_6_out, + register_6_in => register_6_in, + register_7_out => register_7_out, + register_7_in => register_7_in, + port80 => port80, + port81 => port81, + serial1_tx => serial1_tx, + serial1_rx => serial1_rx, + serial1_rts => serial1_rts, + serial1_cts => serial1_cts, + serial1_dtr => serial1_dtr, + serial1_dsr => serial1_dsr, + serial1_ri => serial1_ri, + serial1_dcd => serial1_dcd, + serial2_tx => serial2_tx, + serial2_rx => serial2_rx, + serial2_rts => serial2_rts, + serial2_cts => serial2_cts, + serial2_dtr => serial2_dtr, + serial2_dsr => serial2_dsr, + serial2_ri => serial2_ri, + serial2_dcd => serial2_dcd, + serial3_tx => serial3_tx, + serial3_rx => serial3_rx, + serial3_rts => serial3_rts, + serial3_cts => serial3_cts, + serial3_dtr => serial3_dtr, + serial3_dsr => serial3_dsr, + serial3_ri => serial3_ri, + serial3_dcd => serial3_dcd, + serial4_tx => serial4_tx, + serial4_rx => serial4_rx, + serial4_rts => serial4_rts, + serial4_cts => serial4_cts, + serial4_dtr => serial4_dtr, + serial4_dsr => serial4_dsr, + serial4_ri => serial4_ri, + serial4_dcd => serial4_dcd, + --kb_rstout => kb_rstout, --missing??? + ps2_kbd_clk_pad_oe_o => ps2_kbd_clk_pad_oe_o, + ps2_kbd_clk_pad_o => ps2_kbd_clk_pad_o, + ps2_kbd_data_pad_oe_o => ps2_kbd_data_pad_oe_o, + ps2_kbd_data_pad_o => ps2_kbd_data_pad_o, + ps2_aux_clk_pad_oe_o => ps2_aux_clk_pad_oe_o, + ps2_aux_clk_pad_o => ps2_aux_clk_pad_o, + ps2_aux_data_pad_oe_o => ps2_aux_data_pad_oe_o, + ps2_aux_data_pad_o => ps2_aux_data_pad_o, + ps2_kbd_clk_pad_i => ps2_kbd_clk_pad_i, + ps2_kbd_data_pad_i => ps2_kbd_data_pad_i, + ps2_aux_clk_pad_i => ps2_aux_clk_pad_i, + ps2_aux_data_pad_i => ps2_aux_data_pad_i + + + ); + + + Inst_wb_lpc_periph: wb_lpc_periph PORT MAP( + clk_i => clk_lpc , + nrst_i => reset_n , + wbm_adr_o => xwbm_adr_i , + wbm_dat_o => xwbm_dat_i , + wbm_dat_i => xwbm_dat_o , + wbm_sel_o => xwbm_sel_i , + wbm_tga_o => xwbm_tga_i , + wbm_we_o => xwbm_we_i , + wbm_stb_o => xwbm_stb_i , + wbm_cyc_o => xwbm_cyc_i , + wbm_ack_i => xwbm_ack_o , + wbm_err_i => xwbm_err_o , + dma_chan_o => dma_bs1, + dma_tc_o => dma_bs2, + lframe_i => lframe , + lad_i => lad_i, + lad_o => lad_o , + lad_oe => lad_oe + ); + + + Inst_serirq_slave: serirq_slave PORT MAP( + clk_i => clk_lpc , + nrst_i => reset_n , + irq_i => parallel_irq , + serirq_o => serirq_o , + serirq_i => serirq_i , + serirq_oe => serirq_oe + ); + + + + +-- local Logic ------------------------------------------------------------------ + + process ( reset_n, lad_oe, lad_o) + begin + if (reset_n='0') then + lad <= "ZZZZ"; + else + if (lad_oe='1') then lad <= lad_o; + else lad <= "ZZZZ"; + end if; + end if; + end process; + lad_i <= lad; + + process ( reset_n, serirq_oe , serirq_o ) + begin + if (reset_n='0') then + serirq <= 'Z'; + else + if (serirq_oe ='1') then serirq <= serirq_o ; + else serirq <= 'Z'; + end if; + end if; + end process; + serirq_i <= serirq; + + + + + +--end file ---------------------------------------------------------------------- +end Behavioral; \ No newline at end of file Index: trunk/rtl/sio_logic.vhd =================================================================== --- trunk/rtl/sio_logic.vhd (nonexistent) +++ trunk/rtl/sio_logic.vhd (revision 2) @@ -0,0 +1,475 @@ +-- Super-I/O Logic Istvan Nagy 2019 09 15 +---------------------------------------------------------------------------------- +-- A multiplexer logic block to create a super-I/O IP compatible with x86 systems. +-- A replacement for a chip like the Microchip SCH3227. +-- The LPC IP has a 32bit wishbone bus, but only lower 8bits used for SIO access, with 8bit LPC cycles. +-- Files from other projects needed: +-- - UART below this module: https://opencores.org/projects/uart16550 +-- For the UART, use the 33MHz compliant version regs file: uart_regs_33m.v +-- In uart_defines.v uncomment the "`define DATA_BUS_WIDTH_8" +-- - PS2 below this module: http://www.opencores.org/projects/ps2/ +-- In the ps2_defines, uncomment `define PS2_AUX to enble the keyboard +-- - LPC slave: https://opencores.org/projects/wb_lpc +-- Use these files: wb_lpc_periph.v, wb_lpc_defines.v, serirq_defines.v, serirq_slave.v +-- Some of the files had references, that needs rewriting to remove relative path: `include "wb_lpc_defines.v" +-- In wb_lpc_periph.v change a line: always @(posedge clk_i or negedge nrst_i) ===> always @(posedge clk_i) +-- - Write your own device-top level file, instantiating/connecting the LPC and SIO. +-- Address range: +-- - COM1: 3F8-3FFh +-- - COM2: 2F8-2FFh +-- - COM3: 3E8-3EFh +-- - COM4: 2E8-2EFh +-- - PS2: 60h AND 64h +-- - post-code: 80h AND 81h +-- - Custom board logic registers: 200h...207h (r/w regs connect in/out outside, ro regs out NC) +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; +--entity header ---------------------------------------------------------------- +entity sio_logic is +Port ( clk : in std_logic; --33.333MHz LPC or PCI-bus-derived clock + reset_n : in std_logic; + wbm_adr_i : in std_logic_vector(31 downto 0); + wbm_dat_i : in std_logic_vector(31 downto 0); + wbm_dat_o : out std_logic_vector(31 downto 0); + wbm_sel_i : in std_logic_vector(3 downto 0); + wbm_tga_i : in std_logic_vector(1 downto 0); + wbm_we_i : in std_logic; + wbm_stb_i : in std_logic; + wbm_cyc_i : in std_logic; + wbm_ack_o : out std_logic; + wbm_err_o : out std_logic; + register_0_out : out std_logic_vector(7 downto 0); + register_0_in : in std_logic_vector(7 downto 0); + register_1_out : out std_logic_vector(7 downto 0); + register_1_in : in std_logic_vector(7 downto 0); + register_2_out : out std_logic_vector(7 downto 0); + register_2_in : in std_logic_vector(7 downto 0); + register_3_out : out std_logic_vector(7 downto 0); + register_3_in : in std_logic_vector(7 downto 0); + register_4_out : out std_logic_vector(7 downto 0); + register_4_in : in std_logic_vector(7 downto 0); + register_5_out : out std_logic_vector(7 downto 0); + register_5_in : in std_logic_vector(7 downto 0); + register_6_out : out std_logic_vector(7 downto 0); + register_6_in : in std_logic_vector(7 downto 0); + register_7_out : out std_logic_vector(7 downto 0); + register_7_in : in std_logic_vector(7 downto 0); + port80 : out std_logic_vector(7 downto 0); + port81 : out std_logic_vector(7 downto 0); + --kb_rstout: out std_logic; + serial1_tx: out std_logic; serial1_rx: in std_logic; serial1_rts: out std_logic; serial1_cts: in std_logic; serial1_dtr: out std_logic; serial1_dsr: in std_logic; serial1_ri: in std_logic; serial1_dcd: in std_logic; + serial2_tx: out std_logic; serial2_rx: in std_logic; serial2_rts: out std_logic; serial2_cts: in std_logic; serial2_dtr: out std_logic; serial2_dsr: in std_logic; serial2_ri: in std_logic; serial2_dcd: in std_logic; + serial3_tx: out std_logic; serial3_rx: in std_logic; serial3_rts: out std_logic; serial3_cts: in std_logic; serial3_dtr: out std_logic; serial3_dsr: in std_logic; serial3_ri: in std_logic; serial3_dcd: in std_logic; + serial4_tx: out std_logic; serial4_rx: in std_logic; serial4_rts: out std_logic; serial4_cts: in std_logic; serial4_dtr: out std_logic; serial4_dsr: in std_logic; serial4_ri: in std_logic; serial4_dcd: in std_logic; + ps2_kbd_clk_pad_oe_o: out std_logic; ps2_kbd_clk_pad_o: out std_logic; ps2_kbd_data_pad_oe_o: out std_logic; ps2_kbd_data_pad_o: out std_logic; + ps2_aux_clk_pad_oe_o: out std_logic; ps2_aux_clk_pad_o: out std_logic; ps2_aux_data_pad_oe_o: out std_logic; ps2_aux_data_pad_o: out std_logic; + ps2_kbd_clk_pad_i: in std_logic; ps2_kbd_data_pad_i: in std_logic; ps2_aux_clk_pad_i : in std_logic; ps2_aux_data_pad_i: in std_logic +); +end sio_logic; +--architecture start ------------------------------------------------------------ +architecture Behavioral of sio_logic is + +--INTERNAL SIGNALS ------------------------------------------------------------- +SIGNAL serial1_wb_adr_i: std_logic_VECTOR(2 downto 0); +SIGNAL serial1_wb_dat_i: std_logic_VECTOR(7 downto 0); +SIGNAL serial1_wb_dat_o: std_logic_VECTOR(7 downto 0); +SIGNAL serial1_wb_we: std_logic; +SIGNAL serial1_wb_stb: std_logic; +SIGNAL serial1_wb_cyc: std_logic; +SIGNAL serial1_wb_ack_o: std_logic; +SIGNAL serial1_wb_sel_i: std_logic_VECTOR(3 downto 0); +SIGNAL serial1_int_o: std_logic; +SIGNAL serial2_wb_adr_i: std_logic_VECTOR(2 downto 0); +SIGNAL serial2_wb_dat_i: std_logic_VECTOR(7 downto 0); +SIGNAL serial2_wb_dat_o: std_logic_VECTOR(7 downto 0); +SIGNAL serial2_wb_we: std_logic; +SIGNAL serial2_wb_stb: std_logic; +SIGNAL serial2_wb_cyc: std_logic; +SIGNAL serial2_wb_ack_o: std_logic; +SIGNAL serial2_wb_sel_i: std_logic_VECTOR(3 downto 0); +SIGNAL serial2_int_o: std_logic; +SIGNAL serial3_wb_adr_i: std_logic_VECTOR(2 downto 0); +SIGNAL serial3_wb_dat_i: std_logic_VECTOR(7 downto 0); +SIGNAL serial3_wb_dat_o: std_logic_VECTOR(7 downto 0); +SIGNAL serial3_wb_we: std_logic; +SIGNAL serial3_wb_stb: std_logic; +SIGNAL serial3_wb_cyc: std_logic; +SIGNAL serial3_wb_ack_o: std_logic; +SIGNAL serial3_wb_sel_i: std_logic_VECTOR(3 downto 0); +SIGNAL serial3_int_o: std_logic; +SIGNAL serial4_wb_adr_i: std_logic_VECTOR(2 downto 0); +SIGNAL serial4_wb_dat_i: std_logic_VECTOR(7 downto 0); +SIGNAL serial4_wb_dat_o: std_logic_VECTOR(7 downto 0); +SIGNAL serial4_wb_we: std_logic; +SIGNAL serial4_wb_stb: std_logic; +SIGNAL serial4_wb_cyc: std_logic; +SIGNAL serial4_wb_ack_o: std_logic; +SIGNAL serial4_wb_sel_i: std_logic_VECTOR(3 downto 0); +SIGNAL serial4_int_o: std_logic; +SIGNAL ps2_wb_cyc: std_logic; +SIGNAL ps2_wb_stb: std_logic; +SIGNAL ps2_wb_we: std_logic; +SIGNAL ps2_wb_sel_i: std_logic_VECTOR(3 downto 0); +SIGNAL ps2_wb_adr_i: std_logic_VECTOR(3 downto 0); +SIGNAL ps2_wb_dat_i: std_logic_VECTOR(31 downto 0); +SIGNAL ps2_wb_dat_o: std_logic_VECTOR(31 downto 0); +SIGNAL ps2_wb_ack_o : std_logic; +SIGNAL ps2_wb_int_o: std_logic; +SIGNAL ps2_wb_intb_o: std_logic; +SIGNAL offset_reg : std_logic_VECTOR(7 downto 0); +SIGNAL device_reg : std_logic_VECTOR(7 downto 0); +SIGNAL reset_activehigh : std_logic; + + + +---------COMPONENT DECLARATIONS (introducing the IPs) ---------------------------- + COMPONENT uart_top + PORT( + wb_clk_i : IN std_logic; + wb_rst_i : IN std_logic; + wb_adr_i : IN std_logic_vector(2 downto 0); + wb_dat_i : IN std_logic_vector(7 downto 0); + wb_we_i : IN std_logic; + wb_stb_i : IN std_logic; + wb_cyc_i : IN std_logic; + wb_sel_i : IN std_logic_vector(3 downto 0); + srx_pad_i : IN std_logic; + cts_pad_i : IN std_logic; + dsr_pad_i : IN std_logic; + ri_pad_i : IN std_logic; + dcd_pad_i : IN std_logic; + wb_dat_o : OUT std_logic_vector(7 downto 0); + wb_ack_o : OUT std_logic; + int_o : OUT std_logic; + stx_pad_o : OUT std_logic; + rts_pad_o : OUT std_logic; + dtr_pad_o : OUT std_logic + ); + END COMPONENT; + COMPONENT ps2_top + PORT( + wb_clk_i : IN std_logic; + wb_rst_i : IN std_logic; + wb_cyc_i : IN std_logic; + wb_stb_i : IN std_logic; + wb_we_i : IN std_logic; + wb_sel_i : IN std_logic_vector(3 downto 0); + wb_adr_i : IN std_logic_vector(3 downto 0); + wb_dat_i : IN std_logic_vector(31 downto 0); + ps2_kbd_clk_pad_i : IN std_logic; + ps2_kbd_data_pad_i : IN std_logic; + ps2_aux_clk_pad_i : IN std_logic; + ps2_aux_data_pad_i : IN std_logic; + wb_dat_o : OUT std_logic_vector(31 downto 0); + wb_ack_o : OUT std_logic; + wb_int_o : OUT std_logic; + --kb_rstout : OUT std_logic; + ps2_kbd_clk_pad_o : OUT std_logic; + ps2_kbd_data_pad_o : OUT std_logic; + ps2_kbd_clk_pad_oe_o : OUT std_logic; + ps2_kbd_data_pad_oe_o : OUT std_logic; + wb_intb_o : OUT std_logic; + ps2_aux_clk_pad_o : OUT std_logic; + ps2_aux_data_pad_o : OUT std_logic; + ps2_aux_clk_pad_oe_o : OUT std_logic; + ps2_aux_data_pad_oe_o : OUT std_logic + ); + END COMPONENT; + +--architecture body start ------------------------------------------------------- +begin +---------COMPONENT INSTALLATIONS (connecting the IPs to local signals) --------- + Inst_uart1_top: uart_top PORT MAP( + wb_clk_i => clk, + wb_rst_i => reset_activehigh, + wb_adr_i => serial1_wb_adr_i(2 downto 0), + wb_dat_i => serial1_wb_dat_i, + wb_dat_o => serial1_wb_dat_o, + wb_we_i => serial1_wb_we, + wb_stb_i => serial1_wb_stb, + wb_cyc_i => serial1_wb_cyc, + wb_ack_o => serial1_wb_ack_o, + wb_sel_i => serial1_wb_sel_i, + int_o => serial1_int_o, + stx_pad_o => serial1_tx, + srx_pad_i => serial1_rx, + rts_pad_o => serial1_rts, + cts_pad_i => serial1_cts, + dtr_pad_o => serial1_dtr, + dsr_pad_i => serial1_dsr, + ri_pad_i => serial1_ri, + dcd_pad_i => serial1_dcd + ); + Inst_uart2_top: uart_top PORT MAP( + wb_clk_i => clk, + wb_rst_i => reset_activehigh, + wb_adr_i => serial2_wb_adr_i(2 downto 0), + wb_dat_i => serial2_wb_dat_i, + wb_dat_o => serial2_wb_dat_o, + wb_we_i => serial2_wb_we, + wb_stb_i => serial2_wb_stb, + wb_cyc_i => serial2_wb_cyc, + wb_ack_o => serial2_wb_ack_o, + wb_sel_i => serial2_wb_sel_i, + int_o => serial2_int_o, + stx_pad_o => serial2_tx, + srx_pad_i => serial2_rx, + rts_pad_o => serial2_rts, + cts_pad_i => serial2_cts, + dtr_pad_o => serial2_dtr, + dsr_pad_i => serial2_dsr, + ri_pad_i => serial2_ri, + dcd_pad_i => serial2_dcd + ); + Inst_uart3_top: uart_top PORT MAP( + wb_clk_i => clk, + wb_rst_i => reset_activehigh, + wb_adr_i => serial3_wb_adr_i(2 downto 0), + wb_dat_i => serial3_wb_dat_i, + wb_dat_o => serial3_wb_dat_o, + wb_we_i => serial3_wb_we, + wb_stb_i => serial3_wb_stb, + wb_cyc_i => serial3_wb_cyc, + wb_ack_o => serial3_wb_ack_o, + wb_sel_i => serial3_wb_sel_i, + int_o => serial3_int_o, + stx_pad_o => serial3_tx, + srx_pad_i => serial3_rx, + rts_pad_o => serial3_rts, + cts_pad_i => serial3_cts, + dtr_pad_o => serial3_dtr, + dsr_pad_i => serial3_dsr, + ri_pad_i => serial3_ri, + dcd_pad_i => serial3_dcd + ); + Inst_uart4_top: uart_top PORT MAP( + wb_clk_i => clk, + wb_rst_i => reset_activehigh, + wb_adr_i => serial4_wb_adr_i(2 downto 0), + wb_dat_i => serial4_wb_dat_i, + wb_dat_o => serial4_wb_dat_o, + wb_we_i => serial4_wb_we, + wb_stb_i => serial4_wb_stb, + wb_cyc_i => serial4_wb_cyc, + wb_ack_o => serial4_wb_ack_o, + wb_sel_i => serial4_wb_sel_i, + int_o => serial4_int_o, + stx_pad_o => serial4_tx, + srx_pad_i => serial4_rx, + rts_pad_o => serial4_rts, + cts_pad_i => serial4_cts, + dtr_pad_o => serial4_dtr, + dsr_pad_i => serial4_dsr, + ri_pad_i => serial4_ri, + dcd_pad_i => serial4_dcd + ); + + + Inst_ps2_top: ps2_top PORT MAP( + wb_clk_i => clk, + wb_rst_i => reset_activehigh, + wb_cyc_i => ps2_wb_cyc, + wb_stb_i => ps2_wb_stb, + wb_we_i => ps2_wb_we, + wb_sel_i => ps2_wb_sel_i, + wb_adr_i => ps2_wb_adr_i, + wb_dat_i => ps2_wb_dat_i, + wb_dat_o => ps2_wb_dat_o, + wb_ack_o => ps2_wb_ack_o, + wb_int_o => ps2_wb_int_o, + --kb_rstout => kb_rstout, + ps2_kbd_clk_pad_i => ps2_kbd_clk_pad_i, + ps2_kbd_data_pad_i => ps2_kbd_data_pad_i, + ps2_kbd_clk_pad_o => ps2_kbd_clk_pad_o, + ps2_kbd_data_pad_o => ps2_kbd_data_pad_o, + ps2_kbd_clk_pad_oe_o => ps2_kbd_clk_pad_oe_o, + ps2_kbd_data_pad_oe_o => ps2_kbd_data_pad_oe_o, + wb_intb_o => ps2_wb_intb_o, + ps2_aux_clk_pad_i => ps2_aux_clk_pad_i, + ps2_aux_data_pad_i => ps2_aux_data_pad_i, + ps2_aux_clk_pad_o => ps2_aux_clk_pad_o, + ps2_aux_data_pad_o => ps2_aux_data_pad_o, + ps2_aux_clk_pad_oe_o => ps2_aux_clk_pad_oe_o, + ps2_aux_data_pad_oe_o => ps2_aux_data_pad_oe_o + ); + +--local Logic -------------------------------------------------------------------- +reset_activehigh <= not reset_n; + + +process ( reset_n, clk, wbm_adr_i, serial1_wb_dat_o, serial2_wb_dat_o, serial3_wb_dat_o, serial4_wb_dat_o, ps2_wb_dat_o, ps2_wb_ack_o, serial1_wb_ack_o, serial2_wb_ack_o, serial3_wb_ack_o, serial4_wb_ack_o, wbm_cyc_i, wbm_we_i, wbm_stb_i, offset_reg, device_reg ) +begin +if (reset_n='0') then + wbm_dat_o <= (others => '0'); + offset_reg <= (others => '0'); + device_reg <= (others => '0'); +else + if (wbm_adr_i(9 downto 3) = "1111111") then --serial1 + wbm_dat_o(7 downto 0) <= serial1_wb_dat_o; wbm_ack_o <= serial1_wb_ack_o; + ps2_wb_cyc <= '0'; serial1_wb_cyc <= wbm_cyc_i; serial2_wb_cyc <= '0'; serial3_wb_cyc <= '0'; serial4_wb_cyc <= '0'; + ps2_wb_we <= '0'; serial1_wb_we <= wbm_we_i; serial2_wb_we <= '0'; serial3_wb_we <= '0'; serial4_wb_we <= '0'; + ps2_wb_stb <= '0'; serial1_wb_stb <= wbm_stb_i; serial2_wb_stb <= '0'; serial3_wb_stb <= '0'; serial4_wb_stb <= '0'; + elsif (wbm_adr_i(9 downto 3) = "1011111") then --serial2 + wbm_dat_o(7 downto 0) <= serial2_wb_dat_o; wbm_ack_o <= serial2_wb_ack_o; + ps2_wb_cyc <= '0'; serial1_wb_cyc <= '0'; serial2_wb_cyc <= wbm_cyc_i; serial3_wb_cyc <= '0'; serial4_wb_cyc <= '0'; + ps2_wb_we <= '0'; serial1_wb_we <= '0'; serial2_wb_we <= wbm_we_i; serial3_wb_we <= '0'; serial4_wb_we <= '0'; + ps2_wb_stb <= '0'; serial1_wb_stb <= '0'; serial2_wb_stb <= wbm_stb_i; serial3_wb_stb <= '0'; serial4_wb_stb <= '0'; + elsif (wbm_adr_i(9 downto 3) = "1111101") then --serial3 + wbm_dat_o(7 downto 0) <= serial3_wb_dat_o; wbm_ack_o <= serial3_wb_ack_o; + ps2_wb_cyc <= '0'; serial1_wb_cyc <= '0'; serial2_wb_cyc <= '0'; serial3_wb_cyc <= wbm_cyc_i; serial4_wb_cyc <= '0'; + ps2_wb_we <= '0'; serial1_wb_we <= '0'; serial2_wb_we <= '0'; serial3_wb_we <= wbm_we_i; serial4_wb_we <= '0'; + ps2_wb_stb <= '0'; serial1_wb_stb <= '0'; serial2_wb_stb <= '0'; serial3_wb_stb <= wbm_stb_i; serial4_wb_stb <= '0'; + elsif (wbm_adr_i(9 downto 3) = "1011101") then --serial4 + wbm_dat_o(7 downto 0) <= serial4_wb_dat_o; wbm_ack_o <= serial4_wb_ack_o; + ps2_wb_cyc <= '0'; serial1_wb_cyc <= '0'; serial2_wb_cyc <= '0'; serial3_wb_cyc <= '0'; serial4_wb_cyc <= wbm_cyc_i; + ps2_wb_we <= '0'; serial1_wb_we <= '0'; serial2_wb_we <= '0'; serial3_wb_we <= '0'; serial4_wb_we <= wbm_we_i; + ps2_wb_stb <= '0'; serial1_wb_stb <= '0'; serial2_wb_stb <= '0'; serial3_wb_stb <= '0'; serial4_wb_stb <= wbm_stb_i; + elsif (wbm_adr_i(12 downto 3) = "0001100000") then --ps2 + wbm_dat_o(7 downto 0) <= ps2_wb_dat_o(31 downto 24); wbm_ack_o <= ps2_wb_ack_o; + ps2_wb_cyc <= wbm_cyc_i; serial1_wb_cyc <= '0'; serial2_wb_cyc <= '0'; serial3_wb_cyc <= '0'; serial4_wb_cyc <= '0'; + ps2_wb_we <= wbm_we_i; serial1_wb_we <= '0'; serial2_wb_we <= '0'; serial3_wb_we <= '0'; serial4_wb_we <= '0'; + ps2_wb_stb <= wbm_stb_i; serial1_wb_stb <= '0'; serial2_wb_stb <= '0'; serial3_wb_stb <= '0'; serial4_wb_stb <= '0'; + elsif (wbm_adr_i(12 downto 3) = "0001100100") then --p2s + wbm_dat_o(7 downto 0) <= ps2_wb_dat_o(31 downto 24); wbm_ack_o <= ps2_wb_ack_o; + ps2_wb_cyc <= wbm_cyc_i; serial1_wb_cyc <= '0'; serial2_wb_cyc <= '0'; serial3_wb_cyc <= '0'; serial4_wb_cyc <= '0'; + ps2_wb_we <= wbm_we_i; serial1_wb_we <= '0'; serial2_wb_we <= '0'; serial3_wb_we <= '0'; serial4_wb_we <= '0'; + ps2_wb_stb <= wbm_stb_i; serial1_wb_stb <= '0'; serial2_wb_stb <= '0'; serial3_wb_stb <= '0'; serial4_wb_stb <= '0'; + else --not serial or ps2 forwarding, decode locally: + + ps2_wb_cyc <= '0'; serial1_wb_cyc <= '0'; serial2_wb_cyc <= '0'; serial3_wb_cyc <= '0'; serial4_wb_cyc <= '0'; + ps2_wb_we <= '0'; serial1_wb_we <= '0'; serial2_wb_we <= '0'; serial3_wb_we <= '0'; serial4_wb_we <= '0'; + ps2_wb_stb <= '0'; serial1_wb_stb <= '0'; serial2_wb_stb <= '0'; serial3_wb_stb <= '0'; serial4_wb_stb <= '0'; + + if (clk'event and clk='1') then + + case ( wbm_adr_i(11 downto 0) ) is + --registers: + when X"200" => + wbm_dat_o(7 downto 0) <= register_0_in(7 downto 0); wbm_ack_o <= '1'; + register_0_out <= wbm_dat_i(7 downto 0); + when X"201" => + wbm_dat_o(7 downto 0) <= register_1_in(7 downto 0); wbm_ack_o <= '1'; + register_1_out <= wbm_dat_i(7 downto 0); + when X"202" => + wbm_dat_o(7 downto 0) <= register_2_in(7 downto 0); wbm_ack_o <= '1'; + register_2_out <= wbm_dat_i(7 downto 0); + when X"203" => + wbm_dat_o(7 downto 0) <= register_3_in(7 downto 0); wbm_ack_o <= '1'; + register_3_out <= wbm_dat_i(7 downto 0); + when X"204" => + wbm_dat_o(7 downto 0) <= register_4_in(7 downto 0); wbm_ack_o <= '1'; + register_4_out <= wbm_dat_i(7 downto 0); + when X"205" => + wbm_dat_o(7 downto 0) <= register_5_in(7 downto 0); wbm_ack_o <= '1'; + register_5_out <= wbm_dat_i(7 downto 0); + when X"206" => + wbm_dat_o(7 downto 0) <= register_6_in(7 downto 0); wbm_ack_o <= '1'; + register_6_out <= wbm_dat_i(7 downto 0); + when X"207" => + wbm_dat_o(7 downto 0) <= register_7_in(7 downto 0); wbm_ack_o <= '1'; + register_7_out <= wbm_dat_i(7 downto 0); + --post code PORT80: + when X"080" => + port80 <= wbm_dat_i(7 downto 0); + wbm_dat_o(7 downto 0) <= offset_reg; wbm_ack_o <= '1'; + when X"081" => + port81 <= wbm_dat_i(7 downto 0); + wbm_dat_o(7 downto 0) <= offset_reg; wbm_ack_o <= '1'; + --sio plug and play logic, for the BIOS/OS to detect the number of ports available. **** + when X"02E" => + if (wbm_we_i='1') then offset_reg <= wbm_dat_i(7 downto 0); end if; + wbm_dat_o(7 downto 0) <= offset_reg; wbm_ack_o <= '1'; + when X"02F" => + if (wbm_we_i='1') then device_reg <= wbm_dat_i(7 downto 0); end if; + wbm_ack_o <= '1'; + if (offset_reg = 7) then + wbm_dat_o(7 downto 0) <= device_reg; + elsif (offset_reg = X"60") then --offset LSB + if (device_reg = 4) then --serial1 + wbm_dat_o(7 downto 0) <= X"F8"; + elsif (device_reg = 3) then --serial2 + wbm_dat_o(7 downto 0) <= X"F8"; + elsif (device_reg = 2) then --serial3 + wbm_dat_o(7 downto 0) <= X"E8"; + elsif (device_reg = 1) then --serial4 + wbm_dat_o(7 downto 0) <= X"E8"; + elsif (device_reg = 6) then --keyboard + wbm_dat_o(7 downto 0) <= X"60"; + elsif (device_reg = 5) then --mouse + wbm_dat_o(7 downto 0) <= X"60"; + else + wbm_dat_o(7 downto 0) <= "00000000"; + end if; + elsif (offset_reg = X"61") then --offset MSB + if (device_reg = 4) then --serial1 + wbm_dat_o(7 downto 0) <= X"03"; + elsif (device_reg = 3) then --serial2 + wbm_dat_o(7 downto 0) <= X"02"; + elsif (device_reg = 2) then --serial3 + wbm_dat_o(7 downto 0) <= X"03"; + elsif (device_reg = 1) then --serial4 + wbm_dat_o(7 downto 0) <= X"02"; + elsif (device_reg = 6) then --keyboard + wbm_dat_o(7 downto 0) <= X"00"; + elsif (device_reg = 5) then --mouse + wbm_dat_o(7 downto 0) <= X"00"; + else + wbm_dat_o(7 downto 0) <= "00000000"; + end if; + elsif (offset_reg = X"70") then --interrupt info + if (device_reg = 4) then --serial1 + wbm_dat_o(7 downto 0) <= X"04"; + elsif (device_reg = 3) then --serial2 + wbm_dat_o(7 downto 0) <= X"03"; + elsif (device_reg = 2) then --serial3 + wbm_dat_o(7 downto 0) <= X"04"; + elsif (device_reg = 1) then --serial4 + wbm_dat_o(7 downto 0) <= X"03"; + elsif (device_reg = 6) then --keyboard + wbm_dat_o(7 downto 0) <= X"01"; + elsif (device_reg = 5) then --mouse + wbm_dat_o(7 downto 0) <= X"0C"; + else + wbm_dat_o(7 downto 0) <= "00000000"; + end if; + end if; + when others => --error + wbm_dat_o <= (others => '0'); wbm_ack_o <= '0'; + --device_reg <= device_reg; port80 <= port80; port81 <= port81; offset_reg <= offset_reg; + --register_0_out <= register_0_out; register_1_out <= register_1_out; register_2_out <= register_2_out; register_3_out <= register_3_out; + --register_4_out <= register_4_out; register_5_out <= register_5_out; register_6_out <= register_6_out; register_7_out <= register_7_out; + end case; + end if; + end if; +end if; +end process; + +ps2_wb_dat_i(31 downto 24) <= wbm_dat_i(7 downto 0); +ps2_wb_dat_i(23 downto 16) <= wbm_dat_i(7 downto 0); +ps2_wb_dat_i(15 downto 8) <= wbm_dat_i(7 downto 0); +ps2_wb_sel_i(3) <= '1'; +ps2_wb_sel_i(2 downto 0) <= "000"; +ps2_wb_adr_i(3 downto 0) <= wbm_adr_i(3 downto 0); +serial1_wb_dat_i <= wbm_dat_i(7 downto 0); +serial1_wb_sel_i <= "1000"; +serial1_wb_adr_i(2 downto 0) <= wbm_adr_i(2 downto 0); +serial2_wb_dat_i <= wbm_dat_i(7 downto 0); +serial2_wb_sel_i <= "1000"; +serial2_wb_adr_i(2 downto 0) <= wbm_adr_i(2 downto 0); +serial3_wb_dat_i <= wbm_dat_i(7 downto 0); +serial3_wb_sel_i <= "1000"; +serial3_wb_adr_i(2 downto 0) <= wbm_adr_i(2 downto 0); +serial4_wb_dat_i <= wbm_dat_i(7 downto 0); +serial4_wb_sel_i <= "1000"; +serial4_wb_adr_i(2 downto 0) <= wbm_adr_i(2 downto 0); + +--end file ---------------------------------------------------------------------- +end Behavioral; + + + + + Index: trunk/rtl/uart_regs_33m.v =================================================================== --- trunk/rtl/uart_regs_33m.v (nonexistent) +++ trunk/rtl/uart_regs_33m.v (revision 2) @@ -0,0 +1,932 @@ +////////////////////////////////////////////////////////////////////// +// 33MHz variant +// Modified version of the original uart_regs.v file from the +// project: https://opencores.org/projects/uart16550 . +// Modified few lines of logic to support standard baud rates +// while running from 33.3333MHz LPC/PCI derived wishbone clock. +// How to use it: replace the original uart_regs.v file inside the +// uart16550 sources folder with this uart_regs_33m.v and rename +// this file to uart_regs.v +////////////////////////////////////////////////////////////////////// +//// //// +//// uart_regs.v //// +//// //// +//// //// +//// This file is part of the "UART 16550 compatible" project //// +//// http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Documentation related to this project: //// +//// - http://www.opencores.org/cores/uart16550/ //// +//// //// +//// Projects compatibility: //// +//// - WISHBONE //// +//// RS232 Protocol //// +//// 16550D uart (mostly supported) //// +//// //// +//// Overview (main Features): //// +//// Registers of the uart 16550 core //// +//// //// +//// Known problems (limits): //// +//// Inserts 1 wait state in all WISHBONE transfers //// +//// //// +//// To Do: //// +//// Nothing or verification. //// +//// //// +//// Author(s): //// +//// - gorban@opencores.org //// +//// - Jacob Gorban //// +//// - Igor Mohor (igorm@opencores.org) //// +//// //// +//// Created: 2001/05/12 //// +//// Last Updated: (See log for the revision history //// +//// //// +//// //// +////////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2000, 2001 Authors //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer. //// +//// //// +//// This source file is free software; you can redistribute it //// +//// and/or modify it under the terms of the GNU Lesser General //// +//// Public License as published by the Free Software Foundation; //// +//// either version 2.1 of the License, or (at your option) any //// +//// later version. //// +//// //// +//// This source is distributed in the hope that it will be //// +//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +//// PURPOSE. See the GNU Lesser General Public License for more //// +//// details. //// +//// //// +//// You should have received a copy of the GNU Lesser General //// +//// Public License along with this source; if not, download it //// +//// from http://www.opencores.org/lgpl.shtml //// +//// //// +////////////////////////////////////////////////////////////////////// +// +// CVS Revision History +// +// $Log: not supported by cvs2svn $ +// Revision 1.41 2004/05/21 11:44:41 tadejm +// Added synchronizer flops for RX input. +// +// Revision 1.40 2003/06/11 16:37:47 gorban +// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended. +// +// Revision 1.39 2002/07/29 21:16:18 gorban +// The uart_defines.v file is included again in sources. +// +// Revision 1.38 2002/07/22 23:02:23 gorban +// Bug Fixes: +// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed. +// Problem reported by Kenny.Tung. +// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers. +// +// Improvements: +// * Made FIFO's as general inferrable memory where possible. +// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx). +// This saves about 1/3 of the Slice count and reduces P&R and synthesis times. +// +// * Added optional baudrate output (baud_o). +// This is identical to BAUDOUT* signal on 16550 chip. +// It outputs 16xbit_clock_rate - the divided clock. +// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use. +// +// Revision 1.37 2001/12/27 13:24:09 mohor +// lsr[7] was not showing overrun errors. +// +// Revision 1.36 2001/12/20 13:25:46 mohor +// rx push changed to be only one cycle wide. +// +// Revision 1.35 2001/12/19 08:03:34 mohor +// Warnings cleared. +// +// +// Revision 1.34 2001/12/19 07:33:54 mohor +// xSynplicityhadtroubles with the comment. +// +// Revision 1.33 2001/12/17 10:14:43 mohor +// Things related to msr register changed. After THRE IRQ occurs, and one +// character is written to the transmit fifo, the detection of the THRE bit in the +// LSR is delayed for one character time. +// +// Revision 1.32 2001/12/14 13:19:24 mohor +// MSR register fixed. +// +// Revision 1.31 2001/12/14 10:06:58 mohor +// After reset modem status register MSR should be reset. +// +// Revision 1.30 2001/12/13 10:09:13 mohor +// thre irq should be cleared only when being source of interrupt. +// +// Revision 1.29 2001/12/12 09:05:46 mohor +// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo). +// +// Revision 1.28 2001/12/10 19:52:41 gorban +// Scratch register added +// +// Revision 1.27 2001/12/06 14:51:04 gorban +// Bug in LSR[0] is fixed. +// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers. +// +// Revision 1.26 2001/12/03 21:44:29 gorban +// Updated specification documentation. +// Added full 32-bit data bus interface, now as default. +// Address is 5-bit wide in 32-bit data bus mode. +// Added wb_sel_i input to the core. It's used in the 32-bit mode. +// Added debug interface with two 32-bit read-only registers in 32-bit mode. +// Bits 5 and 6 of LSR are now only cleared on TX FIFO write. +// My small test bench is modified to work with 32-bit mode. +// +// Revision 1.25 2001/11/28 19:36:39 gorban +// Fixed: timeout and break didn't pay attention to current data format when counting time +// +// Revision 1.24 2001/11/26 21:38:54 gorban +// Lots of fixes: +// Break condition wasn't handled correctly at all. +// LSR bits could lose their values. +// LSR value after reset was wrong. +// Timing of THRE interrupt signal corrected. +// LSR bit 0 timing corrected. +// +// Revision 1.23 2001/11/12 21:57:29 gorban +// fixed more typo bugs +// +// Revision 1.22 2001/11/12 15:02:28 mohor +// lsr1r error fixed. +// +// Revision 1.21 2001/11/12 14:57:27 mohor +// ti_int_pnd error fixed. +// +// Revision 1.20 2001/11/12 14:50:27 mohor +// ti_int_d error fixed. +// +// Revision 1.19 2001/11/10 12:43:21 gorban +// Logic Synthesis bugs fixed. Some other minor changes +// +// Revision 1.18 2001/11/08 14:54:23 mohor +// Comments in Slovene language deleted, few small fixes for better work of +// old tools. IRQs need to be fix. +// +// Revision 1.17 2001/11/07 17:51:52 gorban +// Heavily rewritten interrupt and LSR subsystems. +// Many bugs hopefully squashed. +// +// Revision 1.16 2001/11/02 09:55:16 mohor +// no message +// +// Revision 1.15 2001/10/31 15:19:22 gorban +// Fixes to break and timeout conditions +// +// Revision 1.14 2001/10/29 17:00:46 gorban +// fixed parity sending and tx_fifo resets over- and underrun +// +// Revision 1.13 2001/10/20 09:58:40 gorban +// Small synopsis fixes +// +// Revision 1.12 2001/10/19 16:21:40 gorban +// Changes data_out to be synchronous again as it should have been. +// +// Revision 1.11 2001/10/18 20:35:45 gorban +// small fix +// +// Revision 1.10 2001/08/24 21:01:12 mohor +// Things connected to parity changed. +// Clock devider changed. +// +// Revision 1.9 2001/08/23 16:05:05 mohor +// Stop bit bug fixed. +// Parity bug fixed. +// WISHBONE read cycle bug fixed, +// OE indicator (Overrun Error) bug fixed. +// PE indicator (Parity Error) bug fixed. +// Register read bug fixed. +// +// Revision 1.10 2001/06/23 11:21:48 gorban +// DL made 16-bit long. Fixed transmission/reception bugs. +// +// Revision 1.9 2001/05/31 20:08:01 gorban +// FIFO changes and other corrections. +// +// Revision 1.8 2001/05/29 20:05:04 gorban +// Fixed some bugs and synthesis problems. +// +// Revision 1.7 2001/05/27 17:37:49 gorban +// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file. +// +// Revision 1.6 2001/05/21 19:12:02 gorban +// Corrected some Linter messages. +// +// Revision 1.5 2001/05/17 18:34:18 gorban +// First 'stable' release. Should be sythesizable now. Also added new header. +// +// Revision 1.0 2001-05-17 21:27:11+02 jacob +// Initial revision +// +// + +// synopsys translate_off +`include "timescale.v" +// synopsys translate_on + +`include "uart_defines.v" + +`define UART_DL1 7:0 +`define UART_DL2 15:8 + +module uart_regs (clk, + wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, + +// additional signals + modem_inputs, + stx_pad_o, srx_pad_i, + +`ifdef DATA_BUS_WIDTH_8 +`else +// debug interface signals enabled +ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate, +`endif + rts_pad_o, dtr_pad_o, int_o +`ifdef UART_HAS_BAUDRATE_OUTPUT + , baud_o +`endif + + ); + +input clk; +input wb_rst_i; +input [`UART_ADDR_WIDTH-1:0] wb_addr_i; +input [7:0] wb_dat_i; +output [7:0] wb_dat_o; +input wb_we_i; +input wb_re_i; + +output stx_pad_o; +input srx_pad_i; + +input [3:0] modem_inputs; +output rts_pad_o; +output dtr_pad_o; +output int_o; +`ifdef UART_HAS_BAUDRATE_OUTPUT +output baud_o; +`endif + +`ifdef DATA_BUS_WIDTH_8 +`else +// if 32-bit databus and debug interface are enabled +output [3:0] ier; +output [3:0] iir; +output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +output [4:0] mcr; +output [7:0] lcr; +output [7:0] msr; +output [7:0] lsr; +output [`UART_FIFO_COUNTER_W-1:0] rf_count; +output [`UART_FIFO_COUNTER_W-1:0] tf_count; +output [2:0] tstate; +output [3:0] rstate; + +`endif + +wire [3:0] modem_inputs; +reg enable; +reg slower_enable; +reg [7:0] gate_counter; + + +`ifdef UART_HAS_BAUDRATE_OUTPUT +assign baud_o = enable; // baud_o is actually the enable signal +`endif + + +wire stx_pad_o; // received from transmitter module +wire srx_pad_i; +wire srx_pad; + +reg [7:0] wb_dat_o; + +wire [`UART_ADDR_WIDTH-1:0] wb_addr_i; +wire [7:0] wb_dat_i; + + +reg [3:0] ier; +reg [3:0] iir; +reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored +reg [4:0] mcr; +reg [7:0] lcr; +reg [7:0] msr; +reg [15:0] dl; // 16-(32)-bit divisor latch +reg [7:0] scratch; // UART scratch register +reg start_dlc; // activate dlc on writing to UART_DL1 +reg lsr_mask_d; // delay for lsr_mask condition +reg msi_reset; // reset MSR 4 lower bits indicator +//reg threi_clear; // THRE interrupt clear flag +reg [15:0] dlc; // 16-bit divisor latch counter +reg int_o; + +reg [3:0] trigger_level; // trigger level of the receiver FIFO +reg rx_reset; +reg tx_reset; + +wire dlab; // divisor latch access bit +wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits +wire loopback; // loopback bit (MCR bit 4) +wire cts, dsr, ri, dcd; // effective signals +wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback) +wire rts_pad_o, dtr_pad_o; // modem control outputs + +// LSR bits wires and regs +wire [7:0] lsr; +wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7; +reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r; +wire lsr_mask; // lsr_mask + +// +// ASSINGS +// + +assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r }; + +assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs; +assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]} + : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i}; + +assign dlab = lcr[`UART_LC_DL]; +assign loopback = mcr[4]; + +// assign modem outputs +assign rts_pad_o = mcr[`UART_MC_RTS]; +assign dtr_pad_o = mcr[`UART_MC_DTR]; + +// Interrupt signals +wire rls_int; // receiver line status interrupt +wire rda_int; // receiver data available interrupt +wire ti_int; // timeout indicator interrupt +wire thre_int; // transmitter holding register empty interrupt +wire ms_int; // modem status interrupt + +// FIFO signals +reg tf_push; +reg rf_pop; +wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out; +wire rf_error_bit; // an error (parity or framing) is inside the fifo +wire [`UART_FIFO_COUNTER_W-1:0] rf_count; +wire [`UART_FIFO_COUNTER_W-1:0] tf_count; +wire [2:0] tstate; +wire [3:0] rstate; +wire [9:0] counter_t; + +wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo. +reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle) +reg [7:0] block_value; // One character length minus stop bit + +// Transmitter Instance +wire serial_out; + +uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask); + + // Synchronizing and sampling serial RX input + uart_sync_flops i_uart_sync_flops + ( + .rst_i (wb_rst_i), + .clk_i (clk), + .stage1_rst_i (1'b0), + .stage1_clk_en_i (1'b1), + .async_dat_i (srx_pad_i), + .sync_dat_o (srx_pad) + ); + defparam i_uart_sync_flops.width = 1; + defparam i_uart_sync_flops.init_value = 1'b1; + +// handle loopback +wire serial_in = loopback ? serial_out : srx_pad; +assign stx_pad_o = loopback ? 1'b1 : serial_out; + +// Receiver Instance +uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable, + counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse); + + +// Asynchronous reading here because the outputs are sampled in uart_wb.v file +always @(dl or dlab or ier or iir or scratch + or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading +begin + case (wb_addr_i) + `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3]; + `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier; + `UART_REG_II : wb_dat_o = {4'b1100,iir}; + `UART_REG_LC : wb_dat_o = lcr; + `UART_REG_LS : wb_dat_o = lsr; + `UART_REG_MS : wb_dat_o = msr; + `UART_REG_SR : wb_dat_o = scratch; + default: wb_dat_o = 8'b0; // ?? + endcase // case(wb_addr_i) +end // always @ (dl or dlab or ier or iir or scratch... + + +// rf_pop signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + rf_pop <= #1 0; + else + if (rf_pop) // restore the signal to 0 after one clock cycle + rf_pop <= #1 0; + else + if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab) + rf_pop <= #1 1; // advance read pointer +end + +wire lsr_mask_condition; +wire iir_read; +wire msr_read; +wire fifo_read; +wire fifo_write; + +assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab); +assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab); +assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab); +assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab); +assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab); + +// lsr_mask_d delayed signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + lsr_mask_d <= #1 0; + else // reset bits in the Line Status Register + lsr_mask_d <= #1 lsr_mask_condition; +end + +// lsr_mask is rise detected +assign lsr_mask = lsr_mask_condition && ~lsr_mask_d; + +// msi_reset signal handling +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + msi_reset <= #1 1; + else + if (msi_reset) + msi_reset <= #1 0; + else + if (msr_read) + msi_reset <= #1 1; // reset bits in Modem Status Register +end + + +// +// WRITES AND RESETS // +// +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + lcr <= #1 8'b00000011; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_LC) + lcr <= #1 wb_dat_i; + +// Interrupt Enable Register or UART_DL2 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + ier <= #1 4'b0000; // no interrupts after reset + dl[`UART_DL2] <= #1 8'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_IE) + if (dlab) + begin + dl[`UART_DL2] <= #1 wb_dat_i; + end + else + ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb + + +// FIFO Control Register and rx_reset, tx_reset signals +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) begin + fcr <= #1 2'b11; + rx_reset <= #1 0; + tx_reset <= #1 0; + end else + if (wb_we_i && wb_addr_i==`UART_REG_FC) begin + fcr <= #1 wb_dat_i[7:6]; + rx_reset <= #1 wb_dat_i[1]; + tx_reset <= #1 wb_dat_i[2]; + end else begin + rx_reset <= #1 0; + tx_reset <= #1 0; + end + +// Modem Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + mcr <= #1 5'b0; + else + if (wb_we_i && wb_addr_i==`UART_REG_MC) + mcr <= #1 wb_dat_i[4:0]; + +// Scratch register +// Line Control Register +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + scratch <= #1 0; // 8n1 setting + else + if (wb_we_i && wb_addr_i==`UART_REG_SR) + scratch <= #1 wb_dat_i; + +// TX_FIFO or UART_DL1 +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) + begin + //dl[`UART_DL1] <= #1 8'b0; + dl[`UART_DL1] <= #1 8'b00001100; //reset to 12=9600baud, also enabled * + tf_push <= #1 1'b0; + start_dlc <= #1 1'b0; + end + else + if (wb_we_i && wb_addr_i==`UART_REG_TR) + if (dlab) + begin + dl[`UART_DL1] <= #1 wb_dat_i; + start_dlc <= #1 1'b1; // enable DL counter + tf_push <= #1 1'b0; + end + else + begin + tf_push <= #1 1'b1; + start_dlc <= #1 1'b0; + end // else: !if(dlab) + else + begin + start_dlc <= #1 1'b0; + tf_push <= #1 1'b0; + end // else: !if(dlab) + +// Receiver FIFO trigger level selection logic (asynchronous mux) +always @(fcr) + case (fcr[`UART_FC_TL]) + 2'b00 : trigger_level = 1; + 2'b01 : trigger_level = 4; + 2'b10 : trigger_level = 8; + 2'b11 : trigger_level = 14; + endcase // case(fcr[`UART_FC_TL]) + +// +// STATUS REGISTERS // +// + +// Modem Status Register +reg [3:0] delayed_modem_signals; +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + msr <= #1 0; + delayed_modem_signals[3:0] <= #1 0; + end + else begin + msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 : + msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]); + msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c}; + delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts}; + end +end + + +// Line Status Register + +// activation conditions +assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition +assign lsr1 = rf_overrun; // Receiver overrun error +assign lsr2 = rf_data_out[1]; // parity error bit +assign lsr3 = rf_data_out[0]; // framing error bit +assign lsr4 = rf_data_out[2]; // break error in the character +assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty +assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty +assign lsr7 = rf_error_bit | rf_overrun; + +// lsr bit0 (receiver data available) +reg lsr0_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0_d <= #1 0; + else lsr0_d <= #1 lsr0; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr0r <= #1 0; + else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition + lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted + +// lsr bit 1 (receiver overrun) +reg lsr1_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1_d <= #1 0; + else lsr1_d <= #1 lsr1; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr1r <= #1 0; + else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise + +// lsr bit 2 (parity error) +reg lsr2_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2_d <= #1 0; + else lsr2_d <= #1 lsr2; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr2r <= #1 0; + else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise + +// lsr bit 3 (framing error) +reg lsr3_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3_d <= #1 0; + else lsr3_d <= #1 lsr3; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr3r <= #1 0; + else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise + +// lsr bit 4 (break indicator) +reg lsr4_d; // delayed + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4_d <= #1 0; + else lsr4_d <= #1 lsr4; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr4r <= #1 0; + else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d); + +// lsr bit 5 (transmitter fifo is empty) +reg lsr5_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5_d <= #1 1; + else lsr5_d <= #1 lsr5; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr5r <= #1 1; + else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d); + +// lsr bit 6 (transmitter empty indicator) +reg lsr6_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6_d <= #1 1; + else lsr6_d <= #1 lsr6; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr6r <= #1 1; + else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d); + +// lsr bit 7 (error in fifo) +reg lsr7_d; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7_d <= #1 0; + else lsr7_d <= #1 lsr7; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) lsr7r <= #1 0; + else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d); + + + +// Frequency divider and new enable - NEW CODE +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) begin + dlc <= #1 0; + slower_enable <= #1 1'b0; end + else begin + if (start_dlc | ~ (|dlc)) + dlc <= #1 dl - 1; + else + dlc <= #1 dlc - 1; + if (|dl & ~(|dlc)) // dl>0 & dlc==0 + slower_enable <= #1 1'b1; + else + slower_enable <= #1 1'b0; end +end + + +// GATING LOGIC FOR 33MHZ SUPPORT +// The enable signal should skip more pulses than originally intended, +// 18 times more, as we are running now on higher frequency clock. +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + begin + gate_counter <= 8'b0; + enable <= #1 1'b0; + end + else + begin + if (gate_counter == 17) + enable <= slower_enable; + else + enable <= #1 1'b0; + if (slower_enable) + begin + if (gate_counter == 17) + gate_counter <= 8'b0; + else + gate_counter <= gate_counter +1; + end + end +end + + + +// Delaying THE status for one character cycle after a character is written to an empty fifo. +always @(lcr) + case (lcr[3:0]) + 4'b0000 : block_value = 95; // 6 bits + 4'b0100 : block_value = 103; // 6.5 bits + 4'b0001, 4'b1000 : block_value = 111; // 7 bits + 4'b1100 : block_value = 119; // 7.5 bits + 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits + 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits + 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits + 4'b1111 : block_value = 175; // 11 bits + endcase // case(lcr[3:0]) + +// Counting time of one character minus stop bit +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + block_cnt <= #1 8'd0; + else + if(lsr5r & fifo_write) // THRE bit set & write to fifo occured + block_cnt <= #1 block_value; + else + if (enable & block_cnt != 8'b0) // only work on enable times + block_cnt <= #1 block_cnt - 1; // decrement break counter +end // always of break condition detection + +// Generating THRE status enable signal +assign thre_set_en = ~(|block_cnt); + + +// +// INTERRUPT LOGIC +// + +assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]); +assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level}); +assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE]; +assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]); +assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count); + +reg rls_int_d; +reg thre_int_d; +reg ms_int_d; +reg ti_int_d; +reg rda_int_d; + +// delay lines +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_d <= #1 0; + else rls_int_d <= #1 rls_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_d <= #1 0; + else rda_int_d <= #1 rda_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_d <= #1 0; + else thre_int_d <= #1 thre_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_d <= #1 0; + else ms_int_d <= #1 ms_int; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_d <= #1 0; + else ti_int_d <= #1 ti_int; + +// rise detection signals + +wire rls_int_rise; +wire thre_int_rise; +wire ms_int_rise; +wire ti_int_rise; +wire rda_int_rise; + +assign rda_int_rise = rda_int & ~rda_int_d; +assign rls_int_rise = rls_int & ~rls_int_d; +assign thre_int_rise = thre_int & ~thre_int_d; +assign ms_int_rise = ms_int & ~ms_int_d; +assign ti_int_rise = ti_int & ~ti_int_d; + +// interrupt pending flags +reg rls_int_pnd; +reg rda_int_pnd; +reg thre_int_pnd; +reg ms_int_pnd; +reg ti_int_pnd; + +// interrupt pending flags assignments +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rls_int_pnd <= #1 0; + else + rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition + rls_int_rise ? 1 : // latch condition + rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) rda_int_pnd <= #1 0; + else + rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition + rda_int_rise ? 1 : // latch condition + rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) thre_int_pnd <= #1 0; + else + thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 : + thre_int_rise ? 1 : + thre_int_pnd && ier[`UART_IE_THRE]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ms_int_pnd <= #1 0; + else + ms_int_pnd <= #1 msr_read ? 0 : + ms_int_rise ? 1 : + ms_int_pnd && ier[`UART_IE_MS]; + +always @(posedge clk or posedge wb_rst_i) + if (wb_rst_i) ti_int_pnd <= #1 0; + else + ti_int_pnd <= #1 fifo_read ? 0 : + ti_int_rise ? 1 : + ti_int_pnd && ier[`UART_IE_RDA]; +// end of pending flags + +// INT_O logic +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + int_o <= #1 1'b0; + else + int_o <= #1 + rls_int_pnd ? ~lsr_mask : + rda_int_pnd ? 1 : + ti_int_pnd ? ~fifo_read : + thre_int_pnd ? !(fifo_write & iir_read) : + ms_int_pnd ? ~msr_read : + 0; // if no interrupt are pending +end + + +// Interrupt Identification register +always @(posedge clk or posedge wb_rst_i) +begin + if (wb_rst_i) + iir <= #1 1; + else + if (rls_int_pnd) // interrupt is pending + begin + iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value + iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending) + end else // the sequence of conditions determines priority of interrupt identification + if (rda_int) + begin + iir[`UART_II_II] <= #1 `UART_II_RDA; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ti_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_TI; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (thre_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_THRE; + iir[`UART_II_IP] <= #1 1'b0; + end + else if (ms_int_pnd) + begin + iir[`UART_II_II] <= #1 `UART_II_MS; + iir[`UART_II_IP] <= #1 1'b0; + end else // no interrupt is pending + begin + iir[`UART_II_II] <= #1 0; + iir[`UART_II_IP] <= #1 1'b1; + end +end + +endmodule