OpenCores
URL https://opencores.org/ocsvn/smii/smii/trunk

Subversion Repositories smii

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  • This comparison shows the changes necessary to convert path
    /
    from Rev 6 to Rev 7
    Reverse comparison

Rev 6 → Rev 7

/smii/trunk/rtl/verilog/smii_module_inst.v
65,10 → 65,10
);
 
`ifndef SMII_SYNC_PER_PHY
obufdff obufdff_sync::`i
obufdff obufdff_sync
(
.d(sync),
.pad(sync_pad_o[`i]),
.pad(eth_sync_pad_o),
.clk(eth_clk),
.rst(wb_rst)
);
/smii/trunk/rtl/verilog/smii_module_inst_1.v
19,13 → 19,6
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync2
(
.d(sync),
.pad(sync_pad_o[2]),
.clk(eth_clk),
.rst(wb_rst)
);
eth_top eth_top1
(
.wb_clk_i(wb_clk),
96,6 → 89,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync1
(
.d(sync),
.pad(eth_sync_pad_o[1]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx1
(
.d(tx[1]),
/smii/trunk/rtl/verilog/smii_module_inst_2.v
29,13 → 29,6
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync3
(
.d(sync),
.pad(sync_pad_o[3]),
.clk(eth_clk),
.rst(wb_rst)
);
eth_top eth_top1
(
.wb_clk_i(wb_clk),
106,6 → 99,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync1
(
.d(sync),
.pad(eth_sync_pad_o[1]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx1
(
.d(tx[1]),
190,6 → 190,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync2
(
.d(sync),
.pad(eth_sync_pad_o[2]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx2
(
.d(tx[2]),
/smii/trunk/rtl/verilog/smii_module_inst_3.v
39,13 → 39,6
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync4
(
.d(sync),
.pad(sync_pad_o[4]),
.clk(eth_clk),
.rst(wb_rst)
);
eth_top eth_top1
(
.wb_clk_i(wb_clk),
116,6 → 109,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync1
(
.d(sync),
.pad(eth_sync_pad_o[1]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx1
(
.d(tx[1]),
200,6 → 200,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync2
(
.d(sync),
.pad(eth_sync_pad_o[2]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx2
(
.d(tx[2]),
284,6 → 291,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync3
(
.d(sync),
.pad(eth_sync_pad_o[3]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx3
(
.d(tx[3]),
/smii/trunk/rtl/verilog/smii_module_inst_4.v
49,13 → 49,6
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync5
(
.d(sync),
.pad(sync_pad_o[5]),
.clk(eth_clk),
.rst(wb_rst)
);
eth_top eth_top1
(
.wb_clk_i(wb_clk),
126,6 → 119,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync1
(
.d(sync),
.pad(eth_sync_pad_o[1]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx1
(
.d(tx[1]),
210,6 → 210,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync2
(
.d(sync),
.pad(eth_sync_pad_o[2]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx2
(
.d(tx[2]),
294,6 → 301,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync3
(
.d(sync),
.pad(eth_sync_pad_o[3]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx3
(
.d(tx[3]),
378,6 → 392,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync4
(
.d(sync),
.pad(eth_sync_pad_o[4]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx4
(
.d(tx[4]),
/smii/trunk/rtl/verilog/Makefile
1,22 → 1,22
comp1:
vpp -DSMII=1 smii_module_inst.v > tmp.v
vppp --simple +define+SMII+1 tmp.v > smii_module_inst_1.v
vppp --simple +define+SMII+1 +define+SMII_SYNC_PER_PHY tmp.v > smii_module_inst_1.v
 
comp2:
vpp -DSMII=2 smii_module_inst.v > tmp.v
vppp --simple +define+SMII+2 tmp.v > smii_module_inst_2.v
vppp --simple +define+SMII+2 +define+SMII_SYNC_PER_PHY tmp.v > smii_module_inst_2.v
 
comp3:
vpp -DSMII=3 smii_module_inst.v > tmp.v
vppp --simple +define+SMII+3 tmp.v > smii_module_inst_3.v
vppp --simple +define+SMII+3 +define+SMII_SYNC_PER_PHY tmp.v > smii_module_inst_3.v
 
comp4:
vpp -DSMII=4 smii_module_inst.v > tmp.v
vppp --simple +define+SMII+4 tmp.v > smii_module_inst_4.v
vppp --simple +define+SMII+4 +define+SMII_SYNC_PER_PHY tmp.v > smii_module_inst_4.v
 
comp8:
vpp -DSMII=8 smii_module_inst.v > tmp.v
vppp --simple +define+SMII+8 tmp.v > smii_module_inst_8.v
vppp --simple +define+SMII+8 +define+SMII_SYNC_PER_PHY tmp.v > smii_module_inst_8.v
 
smii:
vppp --simple +define+ACTEL generic_buffers.v smii_sync.v smii_txrx.v | cat copyright.v - > smii_ACTEL.v
/smii/trunk/rtl/verilog/smii_module_inst_8.v
89,13 → 89,6
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync9
(
.d(sync),
.pad(sync_pad_o[9]),
.clk(eth_clk),
.rst(wb_rst)
);
eth_top eth_top1
(
.wb_clk_i(wb_clk),
166,6 → 159,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync1
(
.d(sync),
.pad(eth_sync_pad_o[1]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx1
(
.d(tx[1]),
250,6 → 250,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync2
(
.d(sync),
.pad(eth_sync_pad_o[2]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx2
(
.d(tx[2]),
334,6 → 341,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync3
(
.d(sync),
.pad(eth_sync_pad_o[3]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx3
(
.d(tx[3]),
418,6 → 432,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync4
(
.d(sync),
.pad(eth_sync_pad_o[4]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx4
(
.d(tx[4]),
502,6 → 523,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync5
(
.d(sync),
.pad(eth_sync_pad_o[5]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx5
(
.d(tx[5]),
586,6 → 614,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync6
(
.d(sync),
.pad(eth_sync_pad_o[6]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx6
(
.d(tx[6]),
670,6 → 705,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync7
(
.d(sync),
.pad(eth_sync_pad_o[7]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx7
(
.d(tx[7]),
754,6 → 796,13
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_sync8
(
.d(sync),
.pad(eth_sync_pad_o[8]),
.clk(eth_clk),
.rst(wb_rst)
);
obufdff obufdff_tx8
(
.d(tx[8]),

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