URL
https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk
Subversion Repositories spacewire_light
Compare Revisions
- This comparison shows the changes necessary to convert path
/spacewire_light/trunk/rtl
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/vhdl/spwstream.vhd
11,7 → 11,7
-- |
-- The SpaceWire standard requires that each transceiver use an initial |
-- signalling rate of 10 Mbit/s. This implies that the system clock frequency |
-- must be a multiple of 10 MHz. See the datasheet for further details on |
-- must be a multiple of 10 MHz. See the manual for further details on |
-- bitrates and clocking. |
-- |
|
26,9 → 26,14
-- System clock frequency in Hz. |
-- This must be set to the frequency of "clk". It is used to setup |
-- counters for reset timing, disconnect timeout and to transmit |
-- at 10 Mbit/s during the handshake. |
-- at 10 Mbit/s during the link handshake. |
sysfreq: real; |
|
-- Transmit clock frequency in Hz (only if tximpl = impl_fast). |
-- This must be set to the frequency of "txclk". It is used to |
-- transmit at 10 Mbit/s during the link handshake. |
txclkfreq: real := 0.0; |
|
-- Selection of a receiver front-end implementation. |
rximpl: spw_implementation_type := impl_generic; |
|
67,12 → 72,13
-- Without autostart or linkstart, the link remains in state Ready. |
linkstart: in std_logic; |
|
-- Do not start link (overrides linkstart and autostart) and/or disconnect |
-- if the link is in state Run. |
-- Do not start link (overrides linkstart and autostart) and/or |
-- disconnect a running link. |
linkdis: in std_logic; |
|
-- Scaling factor minus 1, used to scale the system clock into the transmission |
-- signalling rate. The system clock is divided by (unsigned(divcnt) + 1). |
-- Scaling factor minus 1, used to scale the transmit base clock into |
-- the transmission bit rate. The system clock (for impl_generic) or |
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1). |
-- Changing this signal will immediately change the transmission rate. |
-- During link setup, the transmission rate is always 10 Mbit/s. |
txdivcnt: in std_logic_vector(7 downto 0); |
193,8 → 199,12
constant disconnect_time: integer := integer(sysfreq * 850.0e-9); |
|
-- Initial tx clock scaler (10 Mbit). |
type impl_to_real_type is array(spw_implementation_type) of real; |
constant tximpl_to_txclk_freq: impl_to_real_type := |
(impl_generic => sysfreq, impl_fast => txclkfreq); |
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl); |
constant default_divcnt: std_logic_vector(7 downto 0) := |
std_logic_vector(to_unsigned(integer(sysfreq / 10.0e6 - 1.0), 8)); |
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8)); |
|
-- Registers. |
type regs_type is record |
/vhdl/spwxmit_fast.vhd
122,7 → 122,7
-- no problem there. |
-- |
-- This is different when the data stream includes 4-bit tokens. |
-- See the datasheet for an analysis of that case. |
-- See the manual for further comments. |
-- |
-- Implementation guidelines |
-- ------------------------- |
200,6 → 200,7
type token_type is record |
tick: std_ulogic; -- send time code |
fct: std_ulogic; -- send FCT |
fctpiggy: std_ulogic; -- send FCT and N-char |
flag: std_ulogic; -- send EOP or EEP |
char: std_logic_vector(7 downto 0); -- character or time code |
end record; |
220,6 → 221,7
b_token: token_type; |
-- stage C |
c_update: std_ulogic; |
c_busy: std_ulogic; |
c_esc: std_ulogic; |
c_fct: std_ulogic; |
c_bits: std_logic_vector(8 downto 0); |
277,6 → 279,12
end record; |
|
-- Initial state of system clock domain |
constant token_reset: token_type := ( |
tick => '0', |
fct => '0', |
fctpiggy => '0', |
flag => '0', |
char => (others => '0') ); |
constant regs_reset: regs_type := ( |
txenreg => '0', |
txdivreg => (others => '0'), |
285,8 → 293,8
txdivsafe => '0', |
sysflip0 => '0', |
sysflip1 => '0', |
token0 => ( tick => '0', fct => '0', flag => '0', char => (others => '0') ), |
token1 => ( tick => '0', fct => '0', flag => '0', char => (others => '0') ), |
token0 => token_reset, |
token1 => token_reset, |
tokmux => '0', |
txflip0 => "00", |
txflip1 => "00", |
336,7 → 344,7
vtx := rtx; |
v_needtoken := '0'; |
v_havetoken := '0'; |
v_token := ( tick => '0', fct => '0', flag => '0', char => (others => '0') ); |
v_token := token_reset; |
|
-- ---- FAST CLOCK DOMAIN ---- |
|
349,9 → 357,9
-- Stage B: Multiplex tokens from system clock domain. |
-- Update stage B three bit periods after updating stage C |
-- (i.e. in time for the next update of stage C). |
-- Do not update stage B if the last token from stage C was ESC; |
-- stage C already knows what token to put after the ESC. |
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_esc); |
-- Do not update stage B if stage C is indicating that it needs to |
-- send a second token to complete its task. |
vtx.b_update := rtx.txclken and rtx.e_count(0) and (not rtx.c_busy); |
if rtx.b_mux = '0' then |
vtx.b_txflip := rtx.txflip0; |
else |
380,11 → 388,26
-- Stage C: Prepare to transmit EOP, EEP or a data character. |
vtx.c_update := rtx.txclken and rtx.e_count(3); |
if rtx.c_update = '1' then |
-- NULL is broken into two tokens: ESC + FCT |
-- time codes are broken into two tokens: ESC + char |
|
-- NULL is broken into two tokens: ESC + FCT. |
-- Time-codes are broken into two tokens: ESC + char. |
|
-- Enable c_esc on the first pass of a NULL or a time-code. |
vtx.c_esc := (rtx.b_token.tick or (not rtx.b_valid)) and |
(not rtx.c_esc); |
vtx.c_fct := rtx.b_token.fct or (not rtx.b_valid); |
|
-- Enable c_fct on the first pass of an FCT and on |
-- the second pass of a NULL (also the first pass, but c_esc |
-- is stronger than c_fct). |
vtx.c_fct := (rtx.b_token.fct and (not rtx.c_busy)) or |
(not rtx.b_valid); |
|
-- Enable c_busy on the first pass of a NULL or a time-code |
-- or a piggy-backed FCT. This will tell stage B that we are |
-- not done yet. |
vtx.c_busy := (rtx.b_token.tick or (not rtx.b_valid) or |
rtx.b_token.fctpiggy) and (not rtx.c_busy); |
|
if rtx.b_token.flag = '1' then |
if rtx.b_token.char(0) = '0' then |
-- prepare to send EOP |
493,6 → 516,7
vtx.b_mux := '0'; |
vtx.b_valid := '0'; |
vtx.c_update := '0'; |
vtx.c_busy := '1'; |
vtx.c_esc := '1'; -- need to send 2nd part of NULL |
vtx.c_fct := '1'; |
vtx.d_bits := "000000111"; -- ESC = P111 |
584,6 → 608,7
-- prepare to send time code |
v_token.tick := '1'; |
v_token.fct := '0'; |
v_token.fctpiggy := '0'; |
v_token.flag := '0'; |
v_token.char := r.pend_time; |
v_havetoken := '1'; |
590,25 → 615,27
if v_needtoken = '1' then |
v.pend_tick := '0'; |
end if; |
elsif r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then |
-- prepare to send FCT |
v_token.tick := '0'; |
v_token.fct := '1'; |
v_token.flag := '0'; |
v_havetoken := '1'; |
if v_needtoken = '1' then |
v.pend_fct := '0'; |
v.sent_fct := '1'; |
else |
if r.allow_fct = '1' and (xmiti.fct_in = '1' or r.pend_fct = '1') then |
-- prepare to send FCT |
v_token.fct := '1'; |
v_havetoken := '1'; |
if v_needtoken = '1' then |
v.pend_fct := '0'; |
v.sent_fct := '1'; |
end if; |
end if; |
elsif r.allow_char = '1' and r.pend_char = '1' then |
-- prepare to send N-Char |
v_token.tick := '0'; |
v_token.fct := '0'; |
v_token.flag := r.pend_data(8); |
v_token.char := r.pend_data(7 downto 0); |
v_havetoken := '1'; |
if v_needtoken = '1' then |
v.pend_char := '0'; |
if r.allow_char = '1' and r.pend_char = '1' then |
-- prepare to send N-Char |
-- Note: it is possible to send an FCT and an N-Char |
-- together by enabling the fctpiggy flag. |
v_token.fctpiggy := v_token.fct; |
v_token.flag := r.pend_data(8); |
v_token.char := r.pend_data(7 downto 0); |
v_havetoken := '1'; |
if v_needtoken = '1' then |
v.pend_char := '0'; |
end if; |
end if; |
end if; |
|
/vhdl/spwpkg.vhd
232,6 → 232,7
component spwstream is |
generic ( |
sysfreq: real; -- clk freq in Hz |
txclkfreq: real := 0.0; -- txclk freq in Hz |
rximpl: spw_implementation_type := impl_generic; |
rxchunk: integer range 1 to 4 := 1; -- max bits per clk |
tximpl: spw_implementation_type := impl_generic; |
/vhdl/streamtest.vhd
31,6 → 31,9
-- System clock frequency in Hz. |
sysfreq: real; |
|
-- txclk frequency in Hz (if tximpl = impl_fast). |
txclkfreq: real; |
|
-- 2-log of division factor from system clock freq to timecode freq. |
tickdiv: integer range 12 to 24 := 20; |
|
209,6 → 212,7
spwstream_inst: spwstream |
generic map ( |
sysfreq => sysfreq, |
txclkfreq => txclkfreq, |
rximpl => rximpl, |
rxchunk => rxchunk, |
tximpl => tximpl, |