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URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

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  • This comparison shows the changes necessary to convert path 
    /spacewire_light/trunk/syn
    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/spwstream_gr-xc3s1500/spwstream.ucf
5,6 → 5,6
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fastclk" = PERIOD "fastclk" 4 ns ;
 
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "clk" 4 ns ;
TIMESPEC "TS_sys_to_fast" = FROM "clk" TO "fastclk" 4 ns ;
 
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "clk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "clk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;
/spwstream_gr-xc3s1500/Makefile
26,7 → 26,8
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/syncdff.vhd
 
# Device type: Spartan-3 on Pender XC3S1500 board
 
/spwamba_gr-xc3s1500/leon3mp.ucf
22,10 → 22,9
 
# Timing constraints between 200 MHz SpaceWire clock and system clock.
NET "spw_clkl" TNM_NET = "spwclk";
TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 3 ns DATAPATHONLY;
TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 3 ns DATAPATHONLY;
NET "clkm" MAXSKEW = 1 ns;
NET "spw_clkl" MAXSKEW = 1 ns;
TIMESPEC "TS_spwclk_to_clkm" = FROM "spwclk" TO "clkm" 4 ns DATAPATHONLY;
TIMESPEC "TS_clkm_to_spwclk" = FROM "clkm" TO "spwclk" 4 ns DATAPATHONLY;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns;
 
## Input to DCM for 200 MHz SpaceWire clock can not be optimally routed.
PIN "spwclk0.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
/spwamba_gr-xc3s1500/Makefile
5,7 → 5,7
-include .config
 
# Change this to your local GRLIB directory.
GRLIB = /data/leon3/grlib-gpl-1.0.22-b4095
GRLIB = /data/leon3/grlib-gpl-1.1.0-b4104
 
TOP=leon3mp
BOARD=gr-xc3s-1500
37,6 → 37,8
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/syncdff.vhd \
$(RTLDIR)/spwram.vhd \
$(RTLDIR)/spwambapkg.vhd \
$(RTLDIR)/spwamba.vhd \
$(RTLDIR)/spwahbmst.vhd \
/spwamba_gr-xc3s1500/leon3mp.vhd
679,6 → 679,7
ahbi => ahbmi,
ahbo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
tick_in => spw_tick_in,
tick_out => open,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
/streamtest_gr-xc3s1500/streamtest.ucf
5,14 → 5,12
TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns nominal
# 3 ns data path + 1 ns source skew + 1 ns destination skew = 5 ns
# fastclk = 200 MHz = 5 ns nominal = 4 ns data path + 1 ns margin
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
NET "sysclk" MAXSKEW = 1 ns ;
NET "fastclk" MAXSKEW = 1 ns ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;
 
# Board clock
NET "clk" LOC = "aa12" | IOSTANDARD = LVTTL;
/streamtest_gr-xc3s1500/Makefile
27,7 → 27,8
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/syncdff.vhd
 
# For Pender XC3S1500 board
FPGA_TYPE = xc3s1500-fg456-4
55,7 → 56,7
.PHONY : default clean bitfile
 
clean :
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb _xmsgs
$(RM) $(PROJ).xst-script
$(RM) $(PROJ).lso $(PROJ).prj
$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
65,6 → 66,7
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
$(RM) $(PROJ)_bitgen.xwbt usage_statistics_webtalk.html webtalk.log
 
bitfile : $(PROJ).bit
 
/streamtest_gr-xc3s1500/streamtest_top.vhd
240,6 → 240,7
s_linkdisable <= switch(1);
s_senddata <= switch(2);
s_sendtick <= switch(3);
s_txdivcnt(7 downto 4) <= "0000";
s_txdivcnt(3 downto 0) <= switch(7 downto 4);
 
-- Sticky link error LED
/streamtest_digilent-xc3s200/streamtest.xise
51,6 → 51,10
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../rtl/vhdl/syncdff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../rtl/vhdl/streamtest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
/streamtest_digilent-xc3s200/streamtest.ucf
5,11 → 5,12
TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;
 
# Paths between fastclk and sysclk must be constrained to fastclk period.
# fastclk = 200 MHz = 5 ns = 3 ns delay + 2 ns skew
NET "sysclk" TNM_NET = "sysclk" | MAXSKEW = 1 ns;
NET "fastclk" TNM_NET = "fastclk" | MAXSKEW = 1 ns;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;
# fastclk = 200 MHz = 5 ns = 4 ns delay + 1 ns margin
NET "sysclk" TNM_NET = "sysclk" ;
NET "fastclk" TNM_NET = "fastclk" ;
TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;
TIMESPEC "TS_sync" = FROM FFS("*/syncdff_ff1") TO FFS("*/syncdff_ff2") 2 ns ;
 
NET "clk50" LOC = "T9" ;
NET "led(0)" LOC = "K12" | DRIVE = 6 ;
/streamtest_digilent-xc3s200/Makefile
27,7 → 27,8
$(RTLDIR)/spwxmit.vhd \
$(RTLDIR)/spwxmit_fast.vhd \
$(RTLDIR)/spwrecvfront_generic.vhd \
$(RTLDIR)/spwrecvfront_fast.vhd
$(RTLDIR)/spwrecvfront_fast.vhd \
$(RTLDIR)/syncdff.vhd
 
# Device type: Spartan-3 200 on Digilent board
 
53,7 → 54,7
.PHONY : default clean bitfile
 
clean :
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb
$(RM) -rf *~ work dump.xst _ngo 'file graph' xlnx_auto_0_xdb _xmsgs
$(RM) $(PROJ).xst-script
$(RM) $(PROJ).lso $(PROJ).prj
$(RM) $(PROJ).ngc $(PROJ).xst.log $(PROJ).syr $(PROJ).srp $(PROJ).ngr
63,6 → 64,7
$(RM) $(PROJ).ncd $(PROJ).pad $(PROJ).par $(PROJ).xpi $(PROJ)_pad.csv $(PROJ)_pad.txt
$(RM) $(PROJ).bit $(PROJ).bgn $(PROJ).drc
$(RM) $(PROJ).ptwx $(PROJ).unroutes *.xrpt $(PROJ)_summary.xml $(PROJ)_usage.xml $(PROJ)_map.map
$(RM) $(PROJ)_bitgen.xwbt usage_statistics_webtalk.html webtalk.log
 
bitfile : $(PROJ).bit
 
/streamtest_digilent-xc3s200/streamtest_top.vhd
233,6 → 233,7
s_linkstart <= switch(1);
s_linkdisable <= switch(2);
s_senddata <= switch(3);
s_txdivcnt(7 downto 4) <= "0000";
s_txdivcnt(3 downto 0) <= switch(7 downto 4);
 
-- Sticky link error LED

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